.EDU
Subject: Re: Making Encoded Bits Human Readable
"IBM Mainframe Assembler List" wrote on
02/08/2022 11:23:03 AM:
> I use instructions for what they do, not for their motivation or
> nomenclature.
I would never begrudge another programmer their choices in getting
their
"IBM Mainframe Assembler List" wrote on
02/08/2022 01:05:09 PM:
> Should not that be LA R5,0(,RG) ???
>
> And... where can I find one of those machines? :-)
No. But, yes, it's a typo.
LA R5,16
Sincerely,
Dave Clark
--
int.ext: 91078
direct: (937) 531-6378
home: (937) 751-
Should not that be LA R5,0(,RG) ???
And... where can I find one of those machines? :-)
On 2/8/2022 12:58, Dave Clark wrote:
"IBM Mainframe Assembler List" wrote on
02/08/2022 11:23:03 AM:
I use instructions for what they do, not for their motivation or
nomenclature.
I would n
"IBM Mainframe Assembler List" wrote on
02/08/2022 11:23:03 AM:
> I use instructions for what they do, not for their motivation or
> nomenclature.
I would never begrudge another programmer their choices in getting
their job done. Then again, I love it when I look at someone else's co
t: Tuesday, February 8, 2022 10:44 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Making Encoded Bits Human Readable
>
> On Feb 7, 2022, at 23:10:49, Bob Raicer wrote:
> >
> > Just for fun, here is yet one more variation on Peter's scheme, using
> > onl
[0014e0e4a59b-dmarc-requ...@listserv.uga.edu]
Sent: Tuesday, February 8, 2022 10:44 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
On Feb 7, 2022, at 23:10:49, Bob Raicer wrote:
>
> Just for fun, here is yet one more variation on Peter's scheme, u
"IBM Mainframe Assembler List" wrote on
02/08/2022 10:44:06 AM:
> A pedant insisted (here? lately?) that LA should be used only with
> operands referring to storage addresses.
That is now my motto ever since I was told about the LHI and AHI
instructions. I even created an SHI macro to
On Feb 7, 2022, at 23:10:49, Bob Raicer wrote:
>
> Just for fun, here is yet one more variation on Peter's scheme, using
> only S/360 instructions. In the comments, YY and ZZ represent the two
> bit pairs of interest, lower case x represents bits or bytes of unknown
> value. Bit strings are encl
Just for fun, here is yet one more variation on Peter's scheme, using
only S/360 instructions. In the comments, YY and ZZ represent the two
bit pairs of interest, lower case x represents bits or bytes of unknown
value. Bit strings are enclosed in square brackets. Bytes are separated
by undersco
Making Peter's approach even more old school, use R14 and R15
instead of R0 and R1, and do the character conversion stuff
with Load Address instead of Add Halfword Immediate.
ICM R14,B'1000',BYTE Put the byte into bits 0-7
SRDL R14,30 Move BYTE.0-1 to reg 14.30-
(Snip)
I don't remember why the OP wanted to make a value range of 0-3
human-readable as 1-4.
(End Snip)
I think it was the display of the VSAM SHAREOPTION after the extraction of
the encoded equivalent from the catalog.
Mike Kerford-Byrnes
OK. Let's go through the code one instruction at a time.
I1 LLGC R0,BYTE Low order byte of R0
* contains byte of interest.
*
* Bits 56-59 contain the two
* ad
"IBM Mainframe Assembler List" wrote on
02/05/2022 08:25:37 AM:
> The lowest-tech approach using only two regs (no 64-bit regs, no z/Arch
> instructions, no 6-byte instructions even) that came to mind was this:
>
> ICM 0,B'1000',BYTE Put the byte into bits 0-7
> SRDL 0,30
"IBM Mainframe Assembler List" wrote on
02/05/2022 08:25:37 AM:
> I don't remember why the OP wanted to make a value range of 0-3
> human-readable as 1-4.
VSAM ShareOptions are displayed as 1 to 4 but stored in the
catalog as 0 to 3. That is why. ;-)
Sincerely,
Dave Clark
--
in
On Feb 5, 2022, at 06:25:37, Peter Relson wrote:
> ...
> I don't remember why the OP wanted to make a value range of 0-3
> human-readable as 1-4. ...
>
Do you remember why the count field in SS instructions is
Similarly biased to a human-readable 1-256?
--
gil
The lowest-tech approach using only two regs (no 64-bit regs, no z/Arch
instructions, no 6-byte instructions even) that came to mind was this:
ICM 0,B'1000',BYTE Put the byte into bits 0-7
SRDL 0,30 Move BYTE.0-1 to reg 0.30-31,
*
[dlcl...@winsupplyinc.com]
Sent: Friday, February 4, 2022 12:26 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
"IBM Mainframe Assembler List" wrote on
02/04/2022 12:11:53 PM:
> Instruction 3 doesn't affect R0, so it still has the 4 leftmost
"IBM Mainframe Assembler List" wrote on
02/04/2022 12:11:53 PM:
> Instruction 3 doesn't affect R0, so it still has the 4 leftmost bits
> from instruction 2. Instruction 4 removes the left two bits, leaving
> only the right two bits.
In that case, those are the wrong two bits that would
of Dave Clark [dlcl...@winsupplyinc.com]
Sent: Friday, February 4, 2022 10:05 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
"IBM Mainframe Assembler List" wrote on
02/03/2022 06:49:33 PM:
> Here is another possibility that uses instructions
Clark [dlcl...@winsupplyinc.com]
Sent: Friday, February 4, 2022 10:51 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
David L Clark/it/crp/WinWholesale wrote on 02/04/2022 10:05:30 AM:
> OK, let's examine this. I follow what lines 1 to 3 will do. But
David L Clark/it/crp/WinWholesale wrote on 02/04/2022 10:05:30 AM:
> OK, let's examine this. I follow what lines 1 to 3 will do. But
> it doesn't seem that line 4 will do what I need. The reason I am
> confused is because the PoPs manual says that line 3, in this case,
> will not change the
"IBM Mainframe Assembler List" wrote on
02/03/2022 06:49:33 PM:
> Here is another possibility that uses instructions which have been
> available since the publication of the original z/Architecture
> Principles of Operation in December 2000. It is only one
> instruction longer (and four instruct
Here is another possibility that uses instructions which have been
available since the publication of the original z/Architecture
Principles of Operation in December 2000. It is only one
instruction longer (and four instruction bytes longer) than the
scheme offered by Dan Greiner, although not as
One other option that generates a few bytes less code:
IC 1,BYTE
RISBGZ 0,1,54,55,2
RISBGZ 1,1,62,63,-4
OR 0,1
AHI 0,C'11'
This puts the results in the rightmost two bytes of general register 0.
No sexy instructions, but this code provides the output characters
complete with a space, and uses only one register:
LLC 1,BYTE
SRL 1,4
MHI 1,3
LA 1,TABLE(1)
MVC RESULT,0(1)
TABLE DC C'1 11 21 31 42 12 22 32 43 13 23 33 44 14 24 34
"IBM Mainframe Assembler List" wrote on
02/01/2022 04:40:19 AM:
> To be fair we have to consider that Dave stored the results
That's correct. but, I wasn't storing the two values next to each
other. I left a space in between. So you need two instructions to store
the results instea
ary 1, 2022 2:49 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
Seymour,
where is ALI documented? or is that a typo and you ment AHI?
Martin
UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
To be fair we have to consider that Dave stored the results
So:
Dave had 38 with storing results
Dan is IMHO 32 with storing results
Mine is 26 with storing results
LLC R0,BYTE
SRDL R0,6
SRL R1,6
SLDL R0,8
AHI R0,C"11"
Tony,
sorry - I did not read to the end.
Yours is the shortest (24 bytes - all should have new machines)
But the table is pretty long
Martin
Ref: Your note of Tue, 1 Feb 2022 10:40:19 +0100
Martin Truebner writes:
>
> LLC R0,BYTE
> SRDL R0,6
> SRL R1,6
> SLDL R0,8
> AHI R0,C"11"
> STH R0,RESULT
>
> But HLASM complains:
> ** ASMA320W Immediate field operand may have incorrect sign or magnitude
>
> only a sev 4
That's because C'11' is
To be fair we have to consider that Dave stored the results
So:
Dave had 38 with storing results
Dan is IMHO 32 with storing results
Mine is 26 with storing results
LLC R0,BYTE
SRDL R0,6
SRL R1,6
SLDL R0,8
AHI R0,C"11"
STH R0,RESULT
But HLASM complains:
** ASMA320W Immediate field oper
Seymour,
where is ALI documented? or is that a typo and you ment AHI?
Martin
Tony,
Your code only decodes the first two bits
Martin
Subject: Re: Making Encoded Bits Human Readable
Caution! This message was sent from outside your organization.
On Mon, 31 Jan 2022 at 15:55, Dave Clark wrote:
> Good deal. I replaced the following 104 bytes of machine code...
...
> ...with the following 38 bytes of machin
On Mon, 31 Jan 2022 at 15:55, Dave Clark wrote:
> Good deal. I replaced the following 104 bytes of machine code...
...
> ...with the following 38 bytes of machine code. Thanks.
Here's a different approach, though if you are primarily looking to
economize on code bytes, it may n
2022 7:40 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
Perhaps that train has left the station?
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Seymour J Metz
Sent: Monday, Janua
___
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Dave Clark [dlcl...@winsupplyinc.com]
Sent: Monday, January 31, 2022 2:31 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Making Encoded Bits Human Readable
I have two pairs of encoded bits in the hi
Perhaps that train has left the station?
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Seymour J Metz
Sent: Monday, January 31, 2022 4:27 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human
p://mason.gmu.edu/~smetz3
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Paul Gilmartin [0014e0e4a59b-dmarc-requ...@listserv.uga.edu]
Sent: Monday, January 31, 2022 2:52 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making En
ROTATE THEN INSERT SELECTED BITS (RISBG) was added as a part of the
general-instructions-extension facility coincident with the introduction of the
z10 in 2008. As I recall, most operating systems are now level set at or above
the z10, so there's a pretty good chance the instruction will be avai
Elegant...and now we're down to 24 bytes of machine code!
Dan, is RISBGZ one of the instructions added to speed up Java garbage
collection?
Mike Shaw
MVS/QuickRef Support Group
Chicago-Soft, Ltd.
On Mon, Jan 31, 2022 at 4:08 PM Dan Greiner wrote:
> The following code snippet does the trick, l
The following code snippet does the trick, leaving the results in general
registers 0 and 1.
LLC 0,BYTE
RISBGZ 1,0,62,63,-4
SRL 0,6
AHI 0,C'1'(or CA'1' for results in ASCII)
AHI 1,C'1' (or CA'1' for results in ASCII)
(I consider ROTATE THEN INSERT SELECTED BITS to be the sexiest
Good deal. I replaced the following 104 bytes of machine code...
IF RECBUF+108,(ON,TM),B'1100'
MVI CWORK,C'4'
ELSE
IF RECBUF+108,(ON,TM),B'1000'
MVI CWORK,C'3'
ELSE
IF RECBUF+108,(ON,TM),B'0100'
MVI CWORK,C'2'
ELSE
MVI CWORK,C'1'
ENDIF
ENDIF
ENDIF
Gil,
that was a bit too short an answer.
I intended it to mean yes, you should surely use IPM to preserve program
mask.
Having said that, the solution you suggested is far superior.
So better forget SPM and IPM altogether ;-)
BTW: the closest thing to shift-and-mask is probably RISBG with a zer
"IBM Mainframe Assembler List" wrote on
01/31/2022 03:13:25 PM:
> On Jan 31, 2022, at 13:03:32, Farley, Peter x23353 wrote:
> >
> > Gil, that is clever as all get out. Thanks for the idea, though I
> don't have any immediate use for it myself. That's one to file in
> the ASM tools bag,
> >
>
Gil,
you surely should!
Abe
===
Op 31/01/2022 om 21:13 schreef Paul Gilmartin:
> On Jan 31, 2022, at 13:03:32, Farley, Peter x23353 wrote:
>> Gil, that is clever as all get out. Thanks for the idea, though I don't
>> have any immediate use for it myself. That's one to file in the ASM tools
On Jan 31, 2022, at 13:03:32, Farley, Peter x23353 wrote:
>
> Gil, that is clever as all get out. Thanks for the idea, though I don't have
> any immediate use for it myself. That's one to file in the ASM tools bag,
>
You're welcome. Except I forgot there's no shift-and-mask instruction.
O
2:52 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Making Encoded Bits Human Readable
On Jan 31, 2022, at 12:31:15, Dave Clark wrote:
>
>I have two pairs of encoded bits in the high order of a binary
> byte. These two pairs (values of 0 to 3, each) actually represent the
"IBM Mainframe Assembler List" wrote on
01/31/2022 02:52:25 PM:
> I'm thinking:
> Isolate a bit-pair with shift-and-mask
> then AHI C'1'
I'm not familiar with shift-and-mask. It is not in my PoPs
manual.
Sincerely,
Dave Clark
--
int.ext: 91078
direct: (937) 531-6378
home:
Dave,
you might consider to use SPM to set the CC in the PSW from the two bits.
Then you can use a series of BC instructions to select the desired
subsequent action...
Does that make sense without a coded example ?
If not, I'll cobble something together for you ...
Abe
===
Op 31/01/2022 om 2
On Jan 31, 2022, at 12:31:15, Dave Clark wrote:
>
>I have two pairs of encoded bits in the high order of a binary
> byte. These two pairs (values of 0 to 3, each) actually represent the
> numbers 1 to 4 in each case. Now, I know that I could do this the hard
> (long?) way by bit-testi
I have two pairs of encoded bits in the high order of a binary
byte. These two pairs (values of 0 to 3, each) actually represent the
numbers 1 to 4 in each case. Now, I know that I could do this the hard
(long?) way by bit-testing these and come up with the human-readable zoned
equiva
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