Re: Instructions by Machine

We're actually using OPTABLE(Z12). Honestly, I'd rather the assembler fail than have a customer get some kind of program exception because they didn't have the right hardware (or feature). I can justify Z12 easily so that's why we have it set in the configuration. *Mark* On Wed, May 15,

Re: Instructions by Machine

e may decide to bump the architecture up in the HLASM config, but I'll probably be retired by then. *Mark Hammack* On Wed, May 15, 2024 at 9:28 AM Peter Relson wrote: > Mike Shaw wrote > > > > This _gold_ for ISVs writing code that must execute on many different z > > models

Re: Relative branching instructions info

Something like this would have answered the question I had a few weeks ago :-). So one up-vote from me. *Mark Hammack* On Thu, May 9, 2024 at 11:04 AM Jonathan Scott wrote: > I have for some years had a comprehensive list of all opcodes > supported by HLASM showing the range of OP

Re: OPCODE tables

A few years back (few being relative), when z/Architecture was first introduced, we wound up doing exactly what Dan suggests. We had one module that did a lot of data manipulation and created another module to do the same processing using 64 bit architecture.I remember dual-pathing one piece of

Re: OPCODE tables

ructions. This came to a head the other day when one of our other developers used an instruction that assumed (according to the latest PoOps) a doubleword boundary but his (very) outdated, private copy didn't say anything about it (honestly, it probably did, he just missed it). *Mark Hammack* On Th

Re: OPCODE tables

Thanks! That's pretty handy :-). *Mark* On Wed, Mar 20, 2024 at 4:35 PM Tony Harminc wrote: > On Wed, 20 Mar 2024 at 17:12, Mark Hammack wrote: > > > Is there a list somewhere (other than OPTABLE LIST) that shows which > > instructions were added at each hardware level?

OPCODE tables

Is there a list somewhere (other than OPTABLE LIST) that shows which instructions were added at each hardware level? I thought PoP used to have something similar but I don't see anything back to Revision 7 (oldest copy I have). *Mark Hammack*

Re: ASMA057E Undefined operation code SR 15,15

the arguments (,). *Mark* On Tue, Nov 14, 2023 at 3:30 PM João Reginato wrote: > Mark > yes, it worked but why? > I still need the entire instruction in SETCs > > João Reginato > (61) 9911-55500 > > > Em ter., 14 de nov. de 2023 às 18:27, Mark Hammack > > es

Re: ASMA057E Undefined operation code SR 15,15

This worked but may not be what you need: MACRO ZERO SETC 'SR' SETC ' ,' , MEND *Mark* On Tue, Nov 14, 2023 at 3:20 PM Willy Jensen wrote: > Would a sublisted SETC do, where P(1) is the instruction and P(2) is the > register? > > -Oprindelig

Re: ASMA057E Undefined operation code SR 15,15

I've always had a LCLC in my macros. Never tried it without. *Mark* On Tue, Nov 14, 2023 at 2:28 PM João Reginato wrote: > hi > I can't see the error on this simple code. > Can anyone help me pls? > > TIA > João Reginato > (+55 61) 9911-55500 > > > Active Usings: None > > Loc Object

Constants in MVI/CLI instructions

I came across something working on a new (to me) assembler program. The program was written many years ago and the programmer used C'Y' and C'N' as flags. Sometime later, another programmer added: YES EQU X'FF' NO EQU X'00' For some "new" flags that were added (there are external

Re: Assembler theology question

In this specific case (and others like it), I'd probably use the latter case as well (although I have done both). However, even for just a line or two, I much prefer using the former syntax (I also tend to use R14, R15 to traverse control blocks until I get to the end). Then again, I'm not sure

Re: Jump vs. Branch

; http://mason.gmu.edu/~smetz3 > > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com] > Sent: Friday, March 4, 2022 4:28 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subje

Re: Jump vs. Branch

report > it? > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com] > Sent: Friday, March 4, 2022 3:16 P

Re: Jump vs. Branch

report > it? > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com] > Sent: Friday, Mar

Re: Jump vs. Branch

t; From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com] > Sent: Friday, March 4, 2022 3:58 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Jump vs. Branch > > Using BRANCH, LABEL would need to be within +4k (x

Re: Jump vs. Branch

384 or something like that? > > J label would be subject to the same issues as B label. > > Or am I missing the point? > > Charles > > > -Original Message- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] > On Behalf Of Mark Hamm

Re: Jump vs. Branch

Agreed wholeheartedly. However, I ran into a situation recently that MIGHT have been caught using branch rather than jump. It involved copy/paste from one subroutine to another and not changing the JUMP address. In this case, if a BC had been used, the program would have received a compile

Re: Branch-and-Link nomenclature question

Think I've always used the "KISS" nomenclature -- "Then you call a subroutine". Maybe it comes from BASIC/Fortran/C/Cobol/etc, but unless you're worried about the mechanics, call works (to my way of thinking). Mark Hammack Systemware, Inc, On Thu, Feb 10, 2022 at 10:04

Re: Base-less macros

ovember 30, 2021 5:39 AM > > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > > Subject: Re: Base-less macros > > > > Steve Smith wrote: > >> And there are other bizarre ways to return without > >> restoring R14, which is not actually required by documented convention

Re: Base-less macros

__ > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com] > Sent: Tuesday, November 30, 2021 12:43 PM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Base-less macros > > Couldn't do

Re: Base-less macros

sage- > From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] > On Behalf Of Mark Hammack > Sent: Tuesday, November 30, 2021 7:54 AM > To: ASSEMBLER-LIST@LISTSERV.UGA.EDU > Subject: Re: Base-less macros > > In our case, the caller doesn't "know" whet

Re: Base-less macros

r 'SA' should be > enough. > > > -- > Shmuel (Seymour J.) Metz > http://mason.gmu.edu/~smetz3 > > > From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on > behalf of Mark Hammack [mark.hamm...@gmail.com]

Re: Base-less macros

On Tue, Nov 30, 2021 at 10:10 AM Martin Ward wrote: > On 30/11/2021 15:53, Mark Hammack wrote: > > using the high half of R14 may be an option. ... > > Does anyone still remember the problems caused by clever > programmers using the top 8 bits of a 24 bit address to store data >

Re: Base-less macros

g R14, which is not actually required by documented conventions. > > Only restoring of AR14 and the high half of R14 are required (for > non-AMODE 64 cases), in general. > (Although I would guess that there are many violations of preserving the > high half of R14). > Some interfaces

Re: Base-less macros

So an interesting dilemma: I have a macro that switches between a regular (24/31 bit style) save area and an extended (64 bit "F4SA") save area. Before saving the registers, I am checking whether the current save area is old (24/31 bit) or new (64 bit) save area. The original code used CLC

Re: Base-less macros

So yes, typically a branch table for return codes is going to be in the order of 6 (0,4,8,12,16,20) and anything else would be handled by the "you shouldn't be here" case. 95% of the time CIJE 15,0,RC0ROUTINE/CIJE 15,4,RC4ROUTINE/etc. would work just fine (I like that idea, especially when

Re: Base-less macros

macro (IMO). Also, my intent was to hide a lot of the branch table weaknesses. From a LOOONG time ago, the original IBM C compiler implemented branch tables for switch/case. Steve, I need to investigate BAS. Thought about BAL but guess I never "equated" the two. *Mark Hammack* Systemwa

Re: Base-less macros

the literals out of the 4k 'base'. The way I took care of *most* of the issue was to go with immediate, long displacement or relative instructions as much as possible which all but eliminated the need for an LTORG or at least reduced the need for multiple LTORGs in the program. *Mark Hammack

Re: ASMPUT question

Thank you for the explanation! I'll forgo the use of ASMPUT and pursue a different solution for the issue. Respectfully, *Mark Hammack* Senior z/OS Developer Systemware, Inc. mark.hamm...@gmail.com 214-478-0955 (c) On Thu, Nov 18, 2021 at 3:49 AM Jonathan Scott wrote: > Mark Hammack wr

ASMPUT question

king into that. Thanks for the feedback, *Mark Hammack* Senior z/OS Developer Systemware, Inc. mark.hamm...@gmail.com 214-478-0955 (c)

Re: Macro to set a bit string

I will say that mine specifically does not support register notation so TBIT may have some extra overhead for that. *Mark* On Thu, May 20, 2021 at 10:47 AM Mark Hammack wrote: > Just a guess but your TBIT macro looks like it does the same thing as one > of mine...if so, it probabl

Re: Macro to set a bit string

Just a guess but your TBIT macro looks like it does the same thing as one of mine...if so, it probably uses SETB to build the mask for a single TM instruction. Not sure you're going to get much better performance than that. *Mark* On Thu, May 20, 2021 at 10:34 AM Charles Mills wrote: > I

Re: Add 1, Subtract 1

+1 on this. Readability/maintainability is much more important than relative instruction speed on modern systems. *Mark* On Wed, Mar 10, 2021 at 6:56 PM Charles Mills wrote: > 1. "Instruction speed" is not exactly a concept anymore due to pipelining. > An instruction can take literally zero

Re: EQU * considered harmful

In 1985 (first MF assembler gig, I had been doing PC programming before that), we were using Assembler H on MVS/XA (as I recall). Our shop standard was to use EQU * for labels and ALWAYS code a a label on a branch in open code, even if it was just skipping a single instruction. Macros were

Re: Pu

Here's the direct link: http://publibfi.boulder.ibm.com/epubs/pdf/dz9zr010.pdf *Mark* On Wed, Jan 31, 2018 at 2:19 PM, Seymour J Metz wrote: > I sometimes add references to Wikipedia articles and would like to know > whether there is a URL for a current z Principles of

Re: Pu

How about: https://www-03.ibm.com/systems/z/os/zos/library/bkserv/v2r2pdf/#zarchpops *Mark* On Wed, Jan 31, 2018 at 2:19 PM, Seymour J Metz wrote: > I sometimes add references to Wikipedia articles and would like to know > whether there is a URL for a current z Principles of

Re: Fair comparison C vs HLASM

Thought I'd throw my $.02 in. In the mid 80's I was on the decision team that transitioned from Z80 assembler to C. Why? It was easier to train 30 people in C than it was to train them in 8086 assembler. At the time, the rest of the shop was primarily using Assembler-H. A couple of years

Re: *+n branches

something about adding another entry in the symbol table but who cares :-). MARK HAMMACK mark.hamm...@gmail.com 214-478-0955 K2MLH On Thu, Jul 2, 2015 at 3:21 PM, Dougie Lawson dl1...@gmail.com wrote: What's the point? You've got a fully fledged assembler, why not give the DS 0H a sensible

Re: *+n branches

From what I've seen, the blank line is there, but SDSF doesn't honor carriage control (some online report viewers honor CC while others don't). Print it out and the blanks lines should be there. MARK HAMMACK mark.hamm...@gmail.com 214-478-0955 K2MLH On Fri, Jul 3, 2015 at 12:42 PM, Paul

Re: What's the difference between...

Not really the answer you are looking for, but why not: Long1 DS CL1504 binary data (1 field of 1504 characters) The assembler should take that and doesn't really care what data you put in the field. Or you could try: Long1 DS 1504B (1504 1 byte values treated as one

Re: RX Operands?

Looking at the Object code, wouldn't that be a 'descriptor' of #MS_TEMP1 -- blank index register (0), Base register (r13), and offset (152)? Mark On Sun, Jun 30, 2013 at 11:04 AM, Paul Gilmartin paulgboul...@aim.com wrote: Looking, for the first time, at the pseudo assembly listing produced by

Re: MVC with 2nd operand length

of a missing terminator (i.e. something other than a x'00' as the terminator). It's easily addressed (stick the expected terminator in the last character of the sending field), but just something I encountered today. Thanks again, Mark Hammack On Wed, May 16, 2012 at 4:14 PM, Paul Gilmartin

Typechecking for 64 bit data

fullword of a 64 bit register(s), I would think the TYPECHECK would accept this notation and complain if I had specified the 31 bit registers. Is anyone using TYPECHECK to successfully catch issues earlier in the process? Mark Hammack Senior Developer Systemware, Inc.

Re: Typechecking for 64 bit data

it. Thanks again, Mark Hammack On Mon, Aug 8, 2011 at 11:10 AM, David Bond david-b...@comcast.net wrote: On Mon, 8 Aug 2011 10:35:00 -0500, Mark Hammack wrote: Ex: R1 EQU 1,GR31 RW1 EQU 1,GR64 ... PTR DS AD ... L R1,PTR= hoped

Re: ISPCMDTB

As an aside, IBM added the ability to have multiple levels of command tables 'logically appended' to ISPCMDS. That way, you can add commands without affecting the 'defaults'. Well worth the effort. IIRC, it takes an IPL (that may have changed, we set it up about 12 years ago). Good luck! Mark

Macro question -- register pair

generates L 14+1,AREA) and REG1SETC 'X' X SETA X+1 REG2SETC 'X' (sets REG2 to '15' for example which works, but needs the extra SETA) Anyway, what I'm wondering is if anyone has come up with a better solution. Thanks for looking, Mark Hammack Senior Technical Specialist

Re: Thoughts on enhancements to HLASM or other z a ssembler‏

as annoying :-). Mark Hammack 2010/10/27 john gilmore john_w_gilm...@msn.com I( think Mr Hammack is saying that before there was |label DCCA'text' support available he used |label DCX'hexadecimal string for ASCII characters instead, and that the ISPF colorization for CA

Re: Sample code to read a PDS member using BPAM

I also recommend the ISPF manualshttp://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/Shelves/ISPZPM61from IBM. Especially the ISPF Services and Edit and Edit Macros books. Good luck, Mark On Wed, Oct 13, 2010 at 8:24 AM, Paul Gilmartin paulgboul...@aim.comwrote: On Oct 13, 2010, at 05:38,

Re: CDS and alignment question

doesn't look at hardcoded offsets, just generated base/offset (S-con). I am still not sure whether the actual data MUST be on a true doubleword boundary or if it would work on a fullword boundary. Guess it's time for an experiment. Thanks again, Mark Hammack Senior Technical Specialist