Re: [casper] Fwd: Request for a sample bof file

Thank you, Jason. I'll you know how it goes. B.t.w., this is the beginning of development for the DSN Transient Observatory about which Kara Kundert spoke at the last workshop. The hardware for Goldstone is still being assembled but we now have a test set-up in the lab. We will be happy

[casper] Shared BRAM yellow block

Hi all, We are using multiple shared bram yellow blocks in our FX correlator design (ska-sa software library, Xilinx 11.4 tools, Linux, Roach 2, KatADC, 150MHz FPGA clock — eventually 300 MHz). We want to store some gain/scaling and other coefficients in this memory and read from the memory

Re: [casper] Shared BRAM yellow block

Hi Nimish, If the time required to load the coefficients is not critical, you could consider using explicit dual port BRAMs with one fo the ports connected to a shared register for data and a shared register for address. This may give you more control in meeting timing. We've also been

Re: [casper] Shared BRAM yellow block

Hi Nimish We have been making a lot of changes to the ROACH2 infrastructure in the last few weeks. This includes fixes that improve timing scores considerably (software registers were being connected so that the FPGA clock was registering the value instead of the EPB clock and the EPB clock

Re: [casper] Shared BRAM yellow block

Hi Glen. We've also been experimenting with adding TIG (timing ignore) statements to the timing constraint file so that things like shared registers are not constrained to meet timing, since it shouldn't make much difference. This is not yet commonly done though. I would be very nervous