[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu accepted this revision. zixuan-wu added a comment. This revision is now accepted and ready to land. LGTM if nobody objects. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added a comment. ping? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D156363: [Driver] -###: exit with code 1 if hasErrorOccurred

zixuan-wu added a comment. Herald added a subscriber: sunshaoce. I am afraid there is also error at clang/test/Driver/as-options.s when default triple is 'riscv32-unknown-elf' Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156363/new/

[PATCH] D149017: [RISCV] Rewrite all found class-based subroutines to functions

zixuan-wu added a comment. Is it going to commit? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149017/new/ https://reviews.llvm.org/D149017 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D156363: [Driver] -###: exit with code 1 if hasErrorOccurred

zixuan-wu added inline comments. Comment at: clang/test/Driver/debug-options.c:245 // // RUN: %clang -### -c -gsplit-dwarf -g -gno-pubnames %s 2>&1 | FileCheck -check-prefix=NOPUB %s // Here should add not or specify the target with x86 because it fails when

[PATCH] D154588: [CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32'

zixuan-wu added inline comments. Comment at: llvm/test/CodeGen/CSKY/intrinsic.ll:21 +entry: + %ntz = call i32 @llvm.cttz.i32(i32 %x, i1 1) + ret i32 %ntz I think we can also test the condition that the second argument is zero. CHANGES SINCE LAST ACTION

[PATCH] D154588: [CSKY] Optimize implementation of intrinsic 'llvm.cttz.i32'

zixuan-wu added inline comments. Comment at: clang/test/CodeGen/CSKY/csky-builtins.c:1 +// RUN: %clang_cc1 -triple csky -emit-llvm -o - %s | FileCheck %s + benshi001 wrote: > This file is pure test, has nothing to do with `llvm.cttz`, just to avoid > another

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:66 return CSR_XLEN_F32_Interrupt_SaveList; return CSR_Interrupt_SaveList; } Here also need adjust for rve. Repository: rG LLVM Github Monorepo CHANGES

[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:908 static const MCPhysReg CSRegs[] = { RISCV::X1, /* ra */ RISCV::X5, RISCV::X6, RISCV::X7, /* t0-t2 */ Hi, @wangpc it's hidden bug

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. In D153674#4461195 , @sammccall wrote: > Sorry about the delay, and thanks for the `.i`. > > It took me a while to work out what was going on, but it looks like it's just > a bug where GCC forgets to automatic-move. > Fixed in

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. In D153674#4455357 , @sammccall wrote: > Hi, sorry about that - are you able to provide a full log, or link to a > failing bot? > That error message doesn't show where in the LLVM code the error occurs. It can pass with gcc 8.

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. Hi, there is a compiling error introduced recently as like following when files under clang/lib/Analysis/FlowSensitive/ are being compiled such as TypeErasedDataflowAnalysis.cpp and Transfer.cpp. Does anybody meet also? > from /usr/include/c++/7/functional:60, >

[PATCH] D151397: [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub

zixuan-wu added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1734 + __RISCV_VXRM_RDN = 2, + __RISCV_VXRM_ROD = 3, +}; I am wondering if we need a dynamic mode enum which representing using current vxrm value? Repository: rG LLVM

[PATCH] D152570: [clang] Apply -fmacro-prefix-map to anonymous tags in template arguments

zixuan-wu added a comment. Hi, Comment at: clang/test/CodeGenCXX/macro-prefix-map-lambda.cpp:11 + auto *s = lambdatest([](){}); +// CHECK: @"__PRETTY_FUNCTION__._Z10lambdatestIZ4mainE3$_0EDaOT_" = private unnamed_addr constant [{{[0-9]+}} x i8] c"auto lambdatest(f &&) [f =

[PATCH] D153111: [clang][Serialization][RISCV] Increase the number of reserved predefined type IDs

zixuan-wu added a comment. I also caught this issue. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D153111/new/ https://reviews.llvm.org/D153111 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D142388: [clang] Add builtin_nondeterministic_value

zixuan-wu added inline comments. Comment at: clang/test/CodeGen/builtins-nondeterministic-value.c:26 +// CHECK-LABEL: entry +// CHECK: [[A:%.*]] = alloca double, align 8 +// CHECK: store double [[X:%.*]], ptr [[A]], align 8 ManuelJBrito wrote: > zixuan-wu wrote:

[PATCH] D142388: [clang] Add builtin_nondeterministic_value

zixuan-wu added inline comments. Comment at: clang/test/CodeGen/builtins-nondeterministic-value.c:26 +// CHECK-LABEL: entry +// CHECK: [[A:%.*]] = alloca double, align 8 +// CHECK: store double [[X:%.*]], ptr [[A]], align 8 hi, @ManuelJBrito , because double is

[PATCH] D148206: [clang] Do not crash after suggesting typo correction to constexpr if condition

zixuan-wu added inline comments. Comment at: clang/test/SemaCXX/invalid-if-constexpr.cpp:7 +} +void a() { if constexpr (__adl_swap<>) {}} // expected-error{{use of undeclared identifier '__adl_swap'; did you mean '__sync_swap'?}} \ + //

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu abandoned this revision. zixuan-wu added a comment. Herald added subscribers: jobnoorman, luke. As this issue is solved at https://reviews.llvm.org/D148124, abandon this revision. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129824/new/ https://reviews.llvm.org/D129824

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

zixuan-wu added a comment. Thx. It has solved the issue D129824 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___

[PATCH] D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension

zixuan-wu added a comment. In D141899#4065375 , @nikic wrote: > In D141899#4061237 , @zixuan-wu > wrote: > >> With considering >> https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility I >>

[PATCH] D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension

zixuan-wu added a comment. With considering https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility I think we need make consensus to choose one option from following 2 options. 1. Remove X86amx type in IR totally. (what I am doing now) 2. Without removing X86amx type in IR, just

[PATCH] D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension

zixuan-wu added a comment. In D141899#4058173 , @LuoYuanke wrote: > @zixuan-wu, changing x86_amx would break our internal code. May I know the > motivation to change the type? The background is at https://reviews.llvm.org/D135202. No more motivation,

[PATCH] D137838: [Support] Move TargetParsers to new component

zixuan-wu added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:10 +/// \file +/// This header is deprecated in favour of `llvm/Support/RISCVISAInfo.h`. +/// I think there is a typo that should be 'in favour of

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. Ping.. Do we still prefer to specify target triple explicitly to make a check? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129824/new/ https://reviews.llvm.org/D129824 ___ cfe-commits mailing list

[PATCH] D136239: [testcase] [OpenMP] Fix the testcase error of check-all when DCLANG_DEFAULT_OPENMP_RUNTIME is not libomp

This revision was automatically updated to reflect the committed changes. Closed by commit rG55c2137939d8: [testcase][OpenMP] Fix the testcase error of check-all when… (authored by zixuan-wu). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D136239: [testcase] [OpenMP] Fix the testcase error of check-all when DCLANG_DEFAULT_OPENMP_RUNTIME is not libomp

zixuan-wu created this revision. zixuan-wu added reviewers: jdoerfert, MaskRay. Herald added subscribers: StephenFan, arphaman, guansong, yaxunl. Herald added a project: All. zixuan-wu requested review of this revision. Herald added subscribers: cfe-commits, sstefan1. Herald added a project:

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:411 // implemented such that the stack will always be 16 byte aligned. unsigned LibCallFrameSize = alignTo((STI.getXLen() / 8) * LibCallRegs, 16);

[PATCH] D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string

zixuan-wu added a comment. In D116735#3429850 , @craig.topper wrote: > I'm seeing a regression on 401.bzip2 and possibly 471.astar. And I'm not > seeing large improvements on 471.omnetpp or 483.xalancbmk. LGTM. But do you still get regression on spec?

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:106 +for (size_t Reg = RISCV::X16; Reg <= RISCV::X31; Reg++) + markSuperRegs(Reserved, Reg); + I am wondering whether we need construct another new RegisterClass

[PATCH] D134454: [Driver][Distro] Fix ArchLinux sysroot detection

zixuan-wu added a comment. It's fine for CSKY to use config file. I only have 2 points. 1. I agree sysroot should be separated from GCC because sysroot is not dependent to GCC and there is even not gcc when we use llvm runtime. This rule should also apply to multilib logic. Sysroot can detect

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added a comment. In D121445#3824657 , @MaskRay wrote: > mips computed sysroot from GCCInstallation very early in 2013 > rG08450bd55ccdc4aee4f5f73cde97e25b3c4ce5b9 > and >

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. AFAIK, --target is clang-specific and transparent for compiler user in RV side. -m is also undefined or less used by RV user. It just uses -march to specify 32 or 64 mode and extensions. Is the convention specified in RV Spec? CHANGES SINCE LAST ACTION

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu marked an inline comment as not done. zixuan-wu added a comment. ping... CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129824/new/ https://reviews.llvm.org/D129824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added inline comments. Comment at: clang/test/Driver/riscv-arch.c:410 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-TARGET %s +// RUN: %clang --target=riscv32-unknown-elf -mcpu=sifive-s21 -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. In D129824#3706654 , @asb wrote: > @zixuan-wu we discussed this a bit in the last community sync call > . > One aspect that makes this patch a

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. In D129824#3699911 , @kito-cheng wrote: > Just realized the problem is trying to fixed the default value of `-mabi=`, > currently `clang -target riscv32-elf -march=rv64gc > -mabi=lp64d`/`riscv32-elf-clang -march=rv64gc

[PATCH] D63329: Allow static linking of libc++ on Linux, just like -static-libstdc++

zixuan-wu added a comment. Herald added a subscriber: MaskRay. Herald added a project: All. Is this going to continue? And also if we use libunwind to handle EH, then it uses dladdr function which need link libdl. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D93138: Add initial support for multilibs in Baremetal toolchain.

zixuan-wu added inline comments. Comment at: clang/lib/Driver/ToolChains/BareMetal.cpp:177 if (!getDriver().SysRoot.empty()) -return getDriver().SysRoot; +return getDriver().SysRoot + SelectedMultilib.osSuffix(); abidh wrote: > zixuan-wu wrote: > >

[PATCH] D93138: Add initial support for multilibs in Baremetal toolchain.

zixuan-wu added inline comments. Herald added subscribers: pcwang-thead, luke957, StephenFan, MaskRay, arichardson. Herald added a project: All. Comment at: clang/lib/Driver/ToolChains/BareMetal.cpp:177 if (!getDriver().SysRoot.empty()) -return getDriver().SysRoot; +

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. In D129824#3670586 , @reames wrote: > This was very briefly discussed at today's sync up call. We were running > short on time, so we didn't get a chance to talk through it, but there did > seem to be a consensus that

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu updated this revision to Diff 445690. zixuan-wu added a comment. Remove unnecessary include header. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129824/new/ https://reviews.llvm.org/D129824 Files: clang/lib/Driver/Driver.cpp clang/test/Driver/riscv-abi.c

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added inline comments. Comment at: clang/lib/Driver/Driver.cpp:660 + +if (RVArch == llvm::Triple::riscv64 && +ArchName.startswith_insensitive("rv32")) eopXD wrote: > Do we need to throw error (or warning) when these two (`RVArch` and >

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu added a comment. In D129824#3653895 , @jrtc27 wrote: > Does GCC allow this or not? Because this strikes me as a bad idea at first > sight… GCC can deduce from -mcpu but not -mabi. > riscv64-unknown-linux-gnu-gcc a.c -mabi=ilp32 > cc1: error:

[PATCH] D54214: [RISCV] Set triple based on -march flag

zixuan-wu added a comment. Herald added subscribers: sunshaoce, pcwang-thead, eopXD, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, MaskRay, arichardson. Herald added a project: All. In D54214#1737255 , @simoncook wrote: >

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu created this revision. zixuan-wu added reviewers: simoncook, lenary, asb. Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult,

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

This revision was automatically updated to reflect the committed changes. Closed by commit rG563cc3fda9a2: [Clang][CSKY] Add support about CSKYABIInfo (authored by zixuan-wu). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126451/new/

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu updated this revision to Diff 432820. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126451/new/ https://reviews.llvm.org/D126451 Files: clang/lib/CodeGen/TargetInfo.cpp clang/test/CodeGen/CSKY/csky-abi.c clang/test/CodeGen/CSKY/csky-hard-abi.c

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu added a comment. BTW, I have run llvm-test-suite, it passed. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126451/new/ https://reviews.llvm.org/D126451 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu added inline comments. Comment at: clang/lib/CodeGen/TargetInfo.cpp:11708 + case llvm::Triple::csky: { +bool IsSoftFloat = !getTarget().hasFeature("hard-float-abi"); +bool hasFP64 = getTarget().hasFeature("fpuv2_df") || DavidSpickett wrote: >

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu added a comment. In D126451#3539656 , @rengolin wrote: > This looks good to me, but wait to make sure others see it, too. > > My reasons are: it is largely similar to RISCV implementation, it seems to > follow what I expected of the ABI (which

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu added a comment. In D126451#3539512 , @DavidSpickett wrote: > Can you reupload with more context? See > https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface > > I doubt I'll be able to give any in depth review but

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu updated this revision to Diff 432228. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D126451/new/ https://reviews.llvm.org/D126451 Files: clang/lib/CodeGen/TargetInfo.cpp clang/test/CodeGen/CSKY/csky-abi.c clang/test/CodeGen/CSKY/csky-hard-abi.c Index:

[PATCH] D126451: [Clang][CSKY] Add support about CSKYABIInfo

zixuan-wu created this revision. zixuan-wu added reviewers: rengolin, DavidSpickett. Herald added a project: All. zixuan-wu requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. According to the CSKY ABIv2 document

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

This revision was automatically updated to reflect the committed changes. Closed by commit rGdca37af061fb: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different (authored by zixuan-wu). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu added a comment. Gentle pin.. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124977/new/ https://reviews.llvm.org/D124977 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu updated this revision to Diff 428585. zixuan-wu added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124977/new/ https://reviews.llvm.org/D124977 Files: clang/test/CodeGen/c-strings.c clang/test/Sema/builtin-alloca-with-align.c Index:

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu added inline comments. Comment at: clang/test/Sema/builtin-alloca-with-align.c:32 void test8(void) { +#if defined(__csky__) __builtin_alloca_with_align(sizeof(__INT64_TYPE__), __alignof__(__INT64_TYPE__)); // expected-warning {{second argument to

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu added a comment. Could anybody else have a review or nominate a reviewer? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124977/new/ https://reviews.llvm.org/D124977 ___ cfe-commits mailing

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu added inline comments. Comment at: clang/test/Sema/builtin-alloca-with-align.c:32 void test8(void) { +#if defined(__csky__) __builtin_alloca_with_align(sizeof(__INT64_TYPE__), __alignof__(__INT64_TYPE__)); // expected-warning {{second argument to

[PATCH] D124977: [NFC][Clang] Modify expect of fail test or XFAIL because CSKY align is different

zixuan-wu created this revision. zixuan-wu added reviewers: majnemer, kparzysz, ddunbar. Herald added a project: All. zixuan-wu requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. CSKY is always in 4-byte align, no matter it's long long type.

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added a comment. In D121445#3431569 , @dyung wrote: > Hi, one of the tests you added. csky-toolchain.c seems to be failing on a > Windows build bot, and from a quick look, it appears to be a path separator > issue. Can you take a look? > >

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG97e496054a37: [Clang][CSKY] Add the CSKY target and compiler driver (authored by zixuan-wu). Changed prior to commit:

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added a comment. In D121445#3416518 , @rengolin wrote: > There is also a test error: > > TEST 'Clang :: Driver/csky-toolchain.c' FAILED > > ... >

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu updated this revision to Diff 419076. zixuan-wu added a comment. Herald added subscribers: StephenFan, dexonsmith, MaskRay. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121445/new/ https://reviews.llvm.org/D121445 Files: clang/lib/Basic/CMakeLists.txt

[PATCH] D122089: [CUDA] Add getTargetFeatures for the NVPTX toolchain

zixuan-wu added inline comments. Comment at: clang/lib/Driver/ToolChains/Cuda.cpp:648 +#define CASE_CUDA_VERSION(CUDA_VER, PTX_VER) \ + case CudaVersion::CUDA_##CUDA_VER: \ +PtxFeature = "+ptx"

[PATCH] D122089: [CUDA] Add getTargetFeatures for the NVPTX toolchain

zixuan-wu added inline comments. Comment at: clang/lib/Driver/ToolChains/Cuda.cpp:648 +#define CASE_CUDA_VERSION(CUDA_VER, PTX_VER) \ + case CudaVersion::CUDA_##CUDA_VER: \ +PtxFeature = "+ptx"

[PATCH] D122160: [clang][extract-api] Refactor ExtractAPI and improve docs

zixuan-wu added inline comments. Comment at: clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp:159 + switch (Language) { + case Language::C: +return "c"; It's same name as `Language` variable above, and it cause compile error. @zixuw Maybe the

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added a comment. In D121445#3388842 , @rengolin wrote: > I'm surprised these tests are passing for you. Perhaps you're not building or > running them all. > > To make sure you're running your tests, you need to build both clang and llvm >

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added a comment. I have updated the patch. Any more comments? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121445/new/ https://reviews.llvm.org/D121445 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu updated this revision to Diff 415006. zixuan-wu added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D121445/new/ https://reviews.llvm.org/D121445 Files:

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added inline comments. Comment at: clang/test/Driver/csky-arch.c:26 + +// RUN: %clang -target csky-unknown-elf -march=csky -### %s \ +// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=CSKY %s rengolin wrote: > I don't think this is doing what you

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu added inline comments. Comment at: clang/lib/Basic/Targets/CSKY.cpp:43 + Builder.defineMacro("__CSKYABI__", ABI == "abiv2" ? "2" : "1"); + Builder.defineMacro("__cskyabi__", ABI == "abiv2" ? "2" : "1"); + DavidSpickett wrote: > Any need to handle

[PATCH] D121445: [Clang][CSKY] Add the CSKY target and compiler driver

zixuan-wu created this revision. zixuan-wu added reviewers: rengolin, kito.cheng, rsmith, asb, DavidSpickett, kaz7. Herald added subscribers: krytarowski, mgorny. Herald added a project: All. zixuan-wu requested review of this revision. Herald added a project: clang. Herald added a subscriber:

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added a comment. Sorry for the wrong action of commandeer, @pcwang-thead will still be the author. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401 ___

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu added a comment. It's difficult to run llvm-test-suite in ilp32e abi in Linux. Because there are no workable environment such as runtime and kernel for ilp32e in GNU series tools. And we can not run llvm-test-suite in baremental environment(NOT linux but elf triple). So I have a

[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

zixuan-wu commandeered this revision. zixuan-wu added a reviewer: pcwang-thead. zixuan-wu added a comment. In D70401#3250049 , @khchen wrote: > 2. Have you try to run llvm-test-suite with rv32e config on qemu? It's difficult to run llvm-test-suite in

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3224329 , @jrtc27 wrote: > In D115921#3224324 , @zixuan-wu > wrote: > >> In D115921#3224284 , @jrtc27 wrote: >> >>> but also with

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:48 {"v", RISCVExtensionVersion{0, 10}}, +//{"v", RISCVExtensionVersion{0, 7}}, {"zba", RISCVExtensionVersion{1, 0}}, jrtc27 wrote: > Don't do this This nit will be

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3224284 , @jrtc27 wrote: > but also with RISC-V extensions not being changed once ratified any more > (changes mean new extensions entirely, not new versions) I don't think so. Or why is there version in RISC-V

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. ping... CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Could abandon it due to D108189 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 396148. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch-version.c

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:33 + bool operator!=(const RISCVExtensionVersion ) const { +return !operator==(Version); + } craig.topper wrote: > Use `!(*this == Version)` Good taste.

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 396147. zixuan-wu edited the summary of this revision. zixuan-wu added a comment. Address all comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3206156 , @jrtc27 wrote: > Do not bring back V draft 0.7. It is gone, it will never be supported again > by LLVM under that name. The standard extension namespace is reserved for > ratified extensions and

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 395803. zixuan-wu edited the summary of this revision. zixuan-wu added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp

[PATCH] D115923: [RISCV][Don't Commit] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu abandoned this revision. zixuan-wu added a comment. Only need review D115921 . Just abandon it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115923/new/ https://reviews.llvm.org/D115923

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3201346 , @luismarques wrote: >> enable 'm' extension with passing mattr=+m After this patch, it would be >> -mattr=+m2p0. > > It's not obvious to me that support for extension versions should mean or has > to

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu created this revision. zixuan-wu added reviewers: asb, craig.topper, kito-cheng, luismarques, apazos, jrtc27, Jim, akuegel. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, armkevincheng, eric-k256, vkmr, frasercrmck, jdoerfert, evandro, sameer.abuasal,

[PATCH] D115923: [RISCV][Don't Commit] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu created this revision. zixuan-wu added reviewers: asb, craig.topper, kito-cheng, luismarques, apazos, jrtc27, Jim, akuegel, jhenderson, MaskRay, sjarus. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, sameer.abuasal, s.egerton,

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Hi, @Jim. What time is P extension going to upstream to community since it's been no update for some months? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a subscriber: pcwang-thead. zixuan-wu added a comment. In D70401#3175266 , @khchen wrote: >> Is it (D70401 ) good enough to solve or >> complete rv32e issue? > > It need to > > 1. disallow ilp32e ABI with

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a comment. In D70401#3172750 , @khchen wrote: > In D70401#3172457 , @zixuan-wu wrote: > >> Hi, all. Why is it not continued? > > Sorry, I have to work on other tasks so stop the rv32e implementation

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Hi, all. Why is it not continued? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D70401/new/ https://reviews.llvm.org/D70401

[PATCH] D112921: [clang] Enable sized deallocation by default in C++14 onwards

zixuan-wu added a comment. Is this going to be reviewed again or committed? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112921/new/ https://reviews.llvm.org/D112921 ___ cfe-commits mailing list

[PATCH] D8467: C++14: Disable sized deallocation by default due to ABI breakage

zixuan-wu added a comment. In D8467#3125313 , @tstellar wrote: > In D8467#3095610 , @zixuan-wu wrote: > >> Hi, I am wondering could -fsized-deallocation this be enabled by default >> nowadays in 2021? > > Were you

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957. Hi, @kito-cheng as your this patch unify the extension handing in one same place by new infra, are you going to support the multiple extension version in next step? Repository: rG LLVM Github Monorepo CHANGES SINCE

[PATCH] D8467: C++14: Disable sized deallocation by default due to ABI breakage

zixuan-wu added a comment. Herald added a subscriber: dang. Hi, I am wondering could -fsized-deallocation this be enabled by default nowadays in 2021? Repository: rL LLVM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D8467/new/ https://reviews.llvm.org/D8467

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp:107 + for (auto Feature : RISCVFeatureKV) { +if (FeatureBits[Feature.Value] && +llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) If

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