for that?
Are there any hardware errata related to that feature?
I think that MSI delivery is more efficient and "sexy" than the traditional
delivery via IO-APIC (although everything is integrated).
Also, is there a way to override that default in a mainboard configuration?
Thank you.
--
An
should be
shrdw %bx, %ax
?
I believe that the original value of %ax would be shifted out and replaced with
the value of %bx. So, 0xbbbb. Same as %bx.
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I found a really old document about AMD-8131 chipset which seems like something
that later morphed into the APIC component of the southbrdiges and in that
document they discuss APIC -> HT mapping quite extensively. I wonder what went
wrong later on.
In this copy of the document it's on page 67
haps there is some problem with chipset
> configuration. Please check the HT specs and try to sort out the MT3 setup.
>
I've just got this working on my AMD hardware too.
I had to use the same HT encoding for the Delivery Mode / Message Type bits as
with IO-APIC.
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On 09/10/2016 13:02, Andriy Gapon wrote:
> On 08/10/2016 23:04, Andriy Gapon wrote:
>> On 08/10/2016 20:35, Rudolf Marek wrote:
>>> Andriy Gapon wrote:
> [...]
>>> This has to do about Hypertransportspecification. Please have a look to
>>>
>>> Ta
On 08/10/2016 23:04, Andriy Gapon wrote:
> On 08/10/2016 20:35, Rudolf Marek wrote:
>> Andriy Gapon wrote:
[...]
>> This has to do about Hypertransportspecification. Please have a look to
>>
>> Table 103. x86 Interrupt Request Packet Format (HT spec version 1.1)
>
for an
FSB (=MSI, I guess) interrupt mode and set the delivery mode in the same fashion
as I would for an MSI interrupt. The results were exactly the same as what I am
getting when setting IO-APIC redirection mode to NMI.
If you were able to get this stuff to work on a similar hardware, then I would
appreciate your advice.
Thank you very much!
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you very much!
On Wed, Sep 26, 2012 at 10:49 PM, Andriy Gapon a...@freebsd.org wrote:
Guys,
It's been quite a while since I worked with any coreboot tools.
I see that a lot has changed...
I am posting a trivial FreeBSD-related patch here, but I am ready to follow
the
proper way if you
\
- -Werror-implicit-function-declaration -ansi $(SVNDEF) \
+ -Werror-implicit-function-declaration -ansi $(VERSION) \
-I/usr/local/include
LDFLAGS += -L/usr/local/lib
LIBS = -lz
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on 06/06/2011 19:49 Marc Jones said the following:
Updated.
Thank you. That page is a very convenient place to get links to the specs.
BTW, looks like SB800 BDG was missed:
support.amd.com/us/Embedded_TechDocs/45483.pdf
On Sun, Jun 5, 2011 at 3:26 AM, Andriy Gapon a...@icyb.net.ua wrote
Looks like the docs page http://www.coreboot.org/Datasheets#AMD_4 can be
updated:
http://support.amd.com/us/psearch/Pages/psearch.aspx?type=2.2%3B2.3product=2.7.4.3.5.3.2contentType=Tech+Doc+Embeddedostype=keywords=items=20
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on 17/10/2010 19:37 Idwer Vollering said the following:
Update support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com mailto:vid...@gmail.com
BTW: http://www.freebsd.org/cgi/cvsweb.cgi/ports/sysutils/superiotool/
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levels of ifdefs within flashrom sources becomes more and more
difficult to read and understand.
BTW:
http://sourceforge.net/projects/mk-configure/
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!
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bridge
(handled by its SPI controller)? Or is it a more generic mechanism?
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on 16/07/2010 16:29 Qing Pei Wang said the following:
i think the spi chips are wired to both south bridge and super I/O.
On my mobo they are definitely wired to Super I/O only.
That doesn't preclude, of course, Super I/O being wired to SB :-)
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on 14/07/2010 23:25 Peter Stuge said the following:
Andriy Gapon wrote:
In this context I would really appreciate unabridged version of
ITE IT8718F-S specification.
Maybe you already know this, but I would not expect the superio to be
involved very much in the dualbios mechanism - at most
In this context I would really appreciate unabridged version of ITE IT8718F-S
specification.
If someone could somehow share it, it would be terrific.
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on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
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on 09/04/2010 15:42 Carl-Daniel Hailfinger said the following:
On 09.04.2010 14:35, Andriy Gapon wrote:
on 09/04/2010 15:18 Carl-Daniel Hailfinger said the following:
By the way, some of us have good contacts at ITE, so we can ask ITE for
details about the undocumented registers
interest that time.
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on 28/11/2009 07:24 Peter Stuge said the following:
Andriy Gapon wrote:
Please review the following patch that adds FreeBSD support to msrtool.
MSR values are obtained via /dev/cpuctl ioctl interface.
Signed-off-by: Andriy Gapon a...@icyb.net.ua
I made some small changes, _open
Please review the following patch.
It changes a few bash-specific constructs to more portable syntax specified by
POSIX. After the change the script keeps working with bash interpreter and can
also be interpreted by FreeBSD /bin/sh.
Signed-off-by: Andriy Gapon a...@icyb.net.ua
Index
Please review the following patch that adds FreeBSD support to msrtool.
MSR values are obtained via /dev/cpuctl ioctl interface.
Signed-off-by: Andriy Gapon a...@icyb.net.ua
Index: msrtool.c
===
--- msrtool.c (revision 4776
,IBS
This is how FreeBSD MCA code reported the machine check:
MCA: CPU 5 UNCOR PCC OVER DTLB L1 error
MCA: Address 0x80e5c8000
My guess of possible FreeBSD code issue: 4K mappings are not flushed when
corresponding PDE is updated from pointing to PT to pointing to a 2M page.
Thank you.
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commands.
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Are there any guidelines or code for setting up DRAM ECC mode in memory
controller
of AMD Family 10h processors?
I mean beyond what BKDG has to say on that.
Thank you!
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Yu Ning, thank you very much again.
BTW, an unrelated question:
Generating OPCODES... done
does this line mean that no opcodes at all were generated?
I wonder why that could be.
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into error at offset 45056.
Yu Ning, thank you for the very enlightening explanation!
I wonder what the following means (on my machine):
0x54: 0x (FREG0)
Flash region of size 0?
BTW:
0x50: 0x0a0b (FRAP)
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http
on 30/01/2009 02:39 Carl-Daniel Hailfinger said the following:
On 29.01.2009 13:45, Andriy Gapon wrote:
Sorry for top posting.
flashrom stopped working for me on intel DG33TL motherboard since I
reported success.
In the quoted older message below you can find what flashrom reported
on 30/01/2009 11:43 Stefan Reinauer said the following:
On 29.01.2009 13:45 Uhr, Andriy Gapon wrote:
Sorry for top posting.
flashrom stopped working for me on intel DG33TL motherboard since I
reported success.
In the quoted older message below you can find what flashrom reported
then, here
... ich_spi_read_page: offset=0, number=256, buf=0x800e0
Invalid OPCODE 0x03
Error readingdone.
Exit 255
on 14/11/2008 17:46 Andriy Gapon said the following:
on 14/11/2008 17:19 Carl-Daniel Hailfinger said the following:
On 14.11.2008 15:38, Andriy Gapon wrote:
Below is output of flashrom -V. It couldn't find
semaphoring software has been put in
place to ensure that
all threads/processors are ready for the C2 state when the read to
this register occurs.
/quote
The subsequent byte registers are LV3, LV4, LV5 and for mobile version
LV6 intended for entering C3, C4, C5 and C6 states.
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Andriy Gapon
INSTALL=install
PREFIX=/usr/local
creating Makefile... done
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a similar flash chip, you can try to force read your chip. Run:
flashrom -f -r -c similar_supported_flash_chip filename
Note: flashrom can never write when the flash chip isn't found
automatically.
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on 14/11/2008 17:19 Carl-Daniel Hailfinger said the following:
On 14.11.2008 15:38, Andriy Gapon wrote:
Below is output of flashrom -V. It couldn't find the flash chip. This
is ICH9 (G33) chipset.
There is one WARNING and one FAILED messages.
A few hours ago I posted a patch
on 30/10/2008 11:16 Andriy Gapon said the following:
It seems that romcc with -mcpu=p3 -O produces incorrect code for
cpu/x86/16bit/reset16.inc. -mpcu=p2 -O does work fine.
I will try to provide more hard data later but it looks like the
following code is compiled into an (slightly
Add support for W83977EF Super-IO chip.
This is based on w83977tf code and on earlier support for this chip in
superiotool.
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
---
As trivial change as it was I still managed to make a couple of mistakes
(not all files renamed, one old resource
.
.section .reset
.code16
.globl reset_vector
reset_vector:
.byte 0xe9
.int _start - ( . + 2 )
. = 0x8;
.code32
Jump seems to be off by -4 bytes.
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solution here. It is debatable how
coreboot should set PAM register, and it is not right to make SeaBIOS
too hardware dependent.
Maybe coreboot could somehow export functions for setting access to
option ROM space (aka legacy memory segments) and SeaBIOS could call them.
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on 30/10/2008 16:34 Myles Watson said the following:
-Original Message-
From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED]
On Behalf Of Andriy Gapon
Sent: Thursday, October 30, 2008 8:25 AM
To: Coreboot
Subject: [coreboot] coreboot.v2+seabios on 440bx: option roms not found
on 30/10/2008 16:52 Myles Watson said the following:
-Original Message-
From: Andriy Gapon [mailto:[EMAIL PROTECTED]
Sent: Thursday, October 30, 2008 8:43 AM
To: Myles Watson
Cc: 'Coreboot'
Subject: Re: [coreboot] coreboot.v2+seabios on 440bx: option roms not
found
on 30/10/2008
on 30/10/2008 17:46 Uwe Hermann said the following:
On Wed, Oct 29, 2008 at 03:14:46PM +0200, Andriy Gapon wrote:
Allow nvramtool to build and work on FreeBSD.
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
Thanks, r3709, with some changes though.
Thanks a lot!
The patch you posted
patch soon :-)
on 24/10/2008 18:53 Andriy Gapon said the following:
Was the following a revelation only to me or is it a generally obscure
knowledge?
PIIX4 documentation says that bit 2 of PCI config register 0xCB (of
function 0) enables access to CMOS memory bank2 via IO ports 0x72 and
0x73
Allow nvramtool to build and work on FreeBSD.
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
---
Again this is done using the same technique as for flashrom and superiotool.
Tested on FreeBSD 7.
BTW, any news on official release of flashrom?
--
Andriy Gapon
Index: cmos_lowlevel.c
allow superiotool to compile and work on FreeBSD
using the same approach as earlier flashrom port
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
---
This is tested on FreeBSD 7, dump for W83977EF/EG that I sent previously
was obtained using this patch.
It seems that this approach can also
on 20/10/2008 00:06 Uwe Hermann said the following:
On Fri, Oct 17, 2008 at 06:26:52PM +0300, Andriy Gapon wrote:
Add register definitions for W83627HF based on publicly available
specification and local testing.
Also tweak a little bit algorithm for (internal) device id calculation:
chips
on 28/10/2008 17:56 Idwer Vollering said the following:
2008/10/28, Andriy Gapon [EMAIL PROTECTED] mailto:[EMAIL PROTECTED]:
allow superiotool to compile and work on FreeBSD
using the same approach as earlier flashrom port
Signed-off-by: Andriy Gapon [EMAIL PROTECTED
Add (basic) support for W83977EF Super-IO chip.
This is based on w83977tf code and on earlier support for this chip in
superiotool.
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
---
This was done by copy'n'paste of w83977tf, substitution of w83977tf with
w83977ef, and then some chip
contain some data, e.g. 83 06
seems to be 0x683, ID of my Pentium III CPU.
When bit 2 of 0xCB is zero, then 0x72/0x73 ports seem to provide access
to regular CMOS just like 0x70/0x71.
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on 20/10/2008 00:06 Uwe Hermann said the following:
On Fri, Oct 17, 2008 at 06:26:52PM +0300, Andriy Gapon wrote:
Add register definitions for W83627HF based on publicly available
specification and local testing.
Also tweak a little bit algorithm for (internal) device id calculation:
chips from
W83627HF/GF family
have the same device id but revisions 0xFx.
Signed-off-by: Andriy Gapon [EMAIL PROTECTED]
---
What about this patch (in addition to my previous question/rant)?
Please note that the last line of the patch simply fixes the comment
about internal device id composition (upper half
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on 29/09/2008 20:25 Marc Jones said the following:
Andriy Gapon wrote:
on 26/09/2008 20:02 Marc Jones said the following:
This patch fixes the it8712f keyboard issues and should also fix any
general keyboard init issues with other SIOs.
Marc
Guys,
you might find this useful:
http
/gmane.comp.emulators.qemu/30106
[register 20h there should be changed to register 59h]
P.S.
bochs is really good, BTW, but qemu's speed is fascinating.
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that this was included into bochs code.
Maybe this is something that we would qemu to support as well.
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/mailman/listinfo/coreboot
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chipset bios
...
}
if ((*walk) == 0 || ((*walk) 0x3ff) != 0) {
printf(Flash image seems to be a legacy BIOS. Disabling
checks.\n);
...
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