Dear Jonathan,
Am Freitag, den 25.03.2016, 04:38 +0100 schrieb Jonathan Neuschäfer:
> Below is a link to my GSoC project proposal draft[1]. In essence it's
> about porting coreboot to a non-emulated board with a RISC-V CPU. If you
> have any comments, please go ahead and add them to the
Dear coreboot folks,
please make sure to rebuild the utility cbmem with commit 08e920e5
(util/cbmem: Scale time stamp values correctly) [1]. There was a
regression present for some months, causing the resulting time stamps
to be in milliseconds instead of microseconds.
Most of us probably
Dear Stefan,
Am Sonntag, den 13.03.2016, 22:27 -0700 schrieb Stefan Reinauer:
> On 03/12/2016 01:51 PM, Paul Menzel wrote:
> > does Coverity still check the coreboot code base or have there been
> > changes? It’d be great to get it going again and to have the errors
&g
Dear coreboot folks,
neither in the coreboot Wiki [1] nor the repository I was able to find
a list of the members of the so called coreboot leadership. Stefan’s
blog post from May 2015 [2] lists the people below.
1. Stefan Reinauer
2. Ronald Minnich
3. Marc Jones
4. Patrick Georgi
5. Aaron
Dear coreboot folks,
does Coverity still check the coreboot code base or have there been
changes? It’d be great to get it going again and to have the errors
fixed in code that is currently committed.
Thanks,
paul
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coreboot
Dear coreboot folks,
Am Donnerstag, den 10.03.2016, 19:24 -0600 schrieb REACTS:
> The QEMU x86_64 Q35 fails verification for branch master as of
> commit
>
> The following tests failed:
> BOOT_FAILURE
>
> Commits since last successful test:
> c7a1a3e northbridge/i945/gma: Re-enable NVRAM
Dear coreboot folks,
Am Donnerstag, den 10.03.2016, 19:30 -0600 schrieb REACTS:
> The ASUS KFSN4-DRE (K8) fails verification for branch master as of
> commit c7a1a3e994135bb405662e2f52d0b22efa899c3d
>
> The following tests failed:
> BOOT_FAILURE
>
> Commits since last successful test:
>
Dear coreboot folks,
There are patches up for review [1], creating a new memtest86plus
project [2].
Martin, as you are the author, could you please give a little bit more
information?
The last Memtest86+ release seems to be from 2013, and looking at your
change sets there are a lot of patches
Dear coreboot folks,
just a short thank you to Timothy Pearson from Raptor Engineering [1]
for implementing auxiliary channel PS/2 device presence detection in
coreboot [2] in commit 448e3863 (drivers/pc80: Add PS/2 mouse presence
detect).
As a result it was easy to adapt it for the Nuvoton
Dear coreboot folks,
thanks to Timothy Pearson’s patch set #13159 (southbridge/amd/sb700:
Set HPET min tick value to RPR recommendation) [1] I became aware of
the Kconfig option `HPET_MIN_TICKS`.
It looks like quite some boards (southbridges) don’t set it and it then
gets set to 0 in
Dear Zheng,
Thank you very much!
Am Sonntag, den 24.01.2016, 07:28 + schrieb Zheng Bao:
> Hi, Paul,
> I made a timestamp log by the following steps.
> 1. Build coreboot with check "Create a table of timestamps collected
> during boot ". Run coreboot.
> 2. build cbmem on target machine.
>
Dear coreboot users,
to rule out that the longer boot time issue with GCC 5 is related to
AGESA, could users of an AGESA board please make an upload of the
latest state with CBMEM time stamp collection enabled to board status?
Please run with `make V=1` and maybe even upload that log or attach
Dear coreboot folks,
Am Sonntag, den 10.01.2016, 13:40 +0100 schrieb Paul Menzel:
> on the ASRock E350M1, I lately noticed that the SeaBIOS banner takes
> longer to appear. And looking at the logs board status [1], the time
> stamps stored in CBMEM confirm this.
>
> ```
>
Dear coreboot folks,
on the ASRock E350M1, I lately noticed that the SeaBIOS banner takes
longer to appear. And looking at the logs board status [1], the time
stamps stored in CBMEM confirm this.
```
$ grep 1st asrock/e350m1/4.2-*/*/coreboot_timestamps.txt
Dear coreboot folks,
change set #12804 [1] proposes the following addition to the file
`Documentation/gerrit_guidelines.md`.
239 +* When bringing in a patch from another git repo, update the original
240 +git/gerrit tags by prepending the lines with 'Original-'. Marking
241 +the
Dear coreboot administrators,
www.coreboot.org and coreboot.org redirect to tracker.coreboot.org.
Thanks,
Paul
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Dear Łukasz,
Am Mittwoch, den 25.11.2015, 23:33 + schrieb Łukasz Dobrowolski:
> I would like to port coreboot to one of my laptops (ThinkPad X140e
> and X120e). Both of them have AMD APU-s.
Awesome! Welcome to coreboot!
> I would be grateful if somebody could take a look at attachments
Dear coreboot folks,
I pushed change set I379e4b1e1b1725648c6231bc6954ac3cc655a596
(mainboard: Remove empty mainboard.c files) [1] for review.
```
mainboard: Remove empty mainboard.c files
All the deleted mainboard files contain no code besides some print
statements denoting, that the init is
Dear coreboot folks,
just a late notice, that – thanks to the work of Kyösti Mälkki – as of
commit 68825740 (asrock/e350m1: Add ACPI S3 support) suspend to RAM and
resume works now on the ASRock E350M1!
I successfully tested it under Debian 8.2 with the Linux kernel 4.2. If
somebody wants to
Dear coreboot folks,
Am Donnerstag, den 29.10.2015, 12:55 -0600 schrieb Martin Roth:
> As the community has grown, so has the need to formalize some of the
> guidelines that the community lives by. When the community was small,
> it was easy to communicate these things just from one person to
>
Dear coreboot folks,
Jonathan Kollasch pushed the port of Sun Ultra 40 M2 for review. Help
reviewing that AMD board is much appreciated.
The “base“ change set is #12304 [1].
Thanks,
Paul
[1] http://review.coreboot.org/12304
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Dear Aaron,
thank you for the quick reply.
Am Montag, den 28.09.2015, 09:38 -0500 schrieb Aaron Durbin:
> On Sun, Sep 27, 2015 at 2:54 PM, Paul Menzel wrote:
> > building a coreboot image for the ASRock E350M1 with the attached
> > config, having code coverage enabled, I a
Dear coreboot folks,
building a coreboot image for the ASRock E350M1 with the attached
config, having code coverage enabled, I am unable to run the utility
`cbmem`.
```
$ sudo util/cbmem/cbmem -V -l
Looking for coreboot table at 0 1048576 bytes.
Mapping 1MB of physical memory at 0x0 (requested
Dear coreboot folks,
Am Donnerstag, den 10.09.2015, 16:25 -0700 schrieb Julius Werner:
> I'd bet it's just a single large allocation somewhere. You can try adding
>
> CFLAGS_ramstage += -Wstack-usage=1024
>
> somewhere in coreboot/Makefile.inc and then clean+rebuild your code while
> passing
Dear Maxime,
Am Sonntag, den 06.09.2015, 16:20 +0200 schrieb Maxime de Roucy:
> On a pcengines apu1 when I tried to leave coreinfo (press ESC) I get a
> "General Protection Fault Exception".
>
> I attached my .config file of coreinfo (it's the default
> configuration) and the console output
Dear coreboot folks,
Am Donnerstag, den 10.09.2015, 22:14 +0200 schrieb Carl-Daniel Hailfinger:
> The venue still has 7 very affordable single/double rooms available!
Would somebody share a double room to reduce the costs a little? If
yes, please contact me.
Thanks,
Paul
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Dear coreboot folks,
the coreboot meeting 2015 is taking place soon from October 9th to 11th
[1].
Reading so much about SerialICE [2] and never having really used it,
would there be one of the experts be willing to do some kind of
workshop. That’d be really awesome!
I am looking forward to
Dear coreboot folks,
following Patrick to test devices with the Firmware Test Suite [1], I
built fwts V15.08.00-7-g9ddce1f from the their Git repository [2] and
ran it on the ASRock E350M1 with coreboot [3] and SeaBIOS.
The first tests failing are the MTRR tests.
```
mtrr: MTRR tests.
Dear coreboot,
this week the Gerrit review score -2 was discussed again in
#coreb...@irc.freenode.net.
Several times, during the last two years, a review score of -2 was
given and dealing with it caused a lot of discussion and friction.
This thread is not about the usefulness of -2. Currently
Dear coreboot folks,
with a coreboot image built from commit 11f1d31d (buildgcc: Deal with
gmp on 32bit Cygwin on 64bit host) [1] for the ASRock E350M1 removing
`fallback/payload` leaves an empty file behind and trying to add a file
with the same name again fails, as cbfstool says it’s already
Dear Matthias,
Am Mittwoch, den 05.08.2015, 21:03 +0200 schrieb Matthias Apitz:
I have some (yes, some) Acer C720 Chromebooks which are rooted to
enter SeaBIOS to boot any OS from USB or SSD. This works fine, in
general.
I have one particular USB key, which says on attach to a FreeBSD
Dear Kroms,
Am Montag, den 13.07.2015, 09:43 +0200 schrieb kr...@posteo.be:
[…]
There are two more things two do.
1. Contact the Linux i915 folks and ask them, if the module is able
to detect the configuration itself and does not rely on the
firmware or if there is a way to
Dear Kroms,
Am Sonntag, den 12.07.2015, 22:17 +0200 schrieb kr...@posteo.be:
Thank you! Unfortunately, it also does not contain the Git
revision.
#define COREBOOT_ORIGIN_GIT_REVISION Unknown
I dont´t know if you noticed that Francis wrote in this thread on Sun
Jul 5
Dear Libreboot folks,
Am Sonntag, den 05.07.2015, 09:42 +0200 schrieb Paul Menzel:
Am Samstag, den 04.07.2015, 11:11 +0200 schrieb kr...@posteo.be:
[…]
the payload - I dont know to get or find it.
It is GRUB. Unfortunately, I do not see GRUB’s debug messages in
CBMEM.
Could you please
Dear Kroms,
I am sorry for the long delay.
Am Sonntag, den 05.07.2015, 17:05 +0200 schrieb kr...@posteo.be:
It might be in the revision file in CBFS.
build/cbfstool build/coreboot.rom extract -n revision -f revision.txt
Please find attached the revision.txt.
Thank you!
Am Samstag, den 11.07.2015, 08:00 -0500 schrieb Aaron Durbin:
On Sat, Jul 11, 2015 at 4:34 AM, Paul Menzel wrote:
[…]
With the latest changes we they are measured relatively to system
start.
$ more
asrock/e350m1/4.0-10270-gbd1499d/2015-07-10T13\:23\:53Z/coreboot_timestamps.txt
12
Dear YongGon,
welcome to coreboot and thank you for your message!
Am Mittwoch, den 08.07.2015, 20:47 +0900 schrieb YongGon Kim:
[…]
I have uploaded detailed information using board_status.sh
Following is link for the information.
Dear Kroms,
Am Samstag, den 04.07.2015, 11:11 +0200 schrieb kr...@posteo.be:
I used a pre-compiled libreboot ROM image for flashing my T400:
t400_8mb_ukqwerty_vesafb.rom
(source: http://mirrors.mit.edu/libreboot/20150518/rom/)
I attached most of the requested information, I hope I
Dear Kroms,
Am Freitag, den 03.07.2015, 16:27 +0200 schrieb kr...@posteo.be:
I allready contacted Francis from libreboot and he forwared me to
this list, because it seems to be an issue regarding coreboot.
welcome and thank you for writing a message to the mailing list.
I have flashed a
Dear coreboot folks,
if the CBMEM console is disabled in coreboot and only enabled in
SeaBIOS, currently SeaBIOS does not write any messages to the CBMEM
console (SeaBIOS commit f24eb2f85 (build: CONFIG_VGA_FIXUP_ASM should
depend on CONFIG_BUILD_VGABIOS)).
$ more src/fw/coreboot.c
[…]
Dear Ron,
Am Sonntag, den 28.06.2015, 15:50 + schrieb ron minnich:
So, can someone remind me, is there no native graphics for the T60? I
could have sworn we got there last time we met. Or even in Berlin.
as already discussed in #coreb...@irc.freenode.net, there are two
variants of the
Dear Tyler,
Am Freitag, den 19.06.2015, 20:58 -0700 schrieb Tyler Parks:
I'm using Fedora 20 x86_64, along with freshly pulled Coreboot source,
and trying to compile Coreboot for QEMU.
Welcome to coreboot!
However I get a make error that says CBFS files located outside
itself. I haven't
Dear coreboot folks,
Am Donnerstag, den 26.02.2015, 17:23 +0200 schrieb Emilian Bold:
I was trying to duplicate a coreboot build back in November and I noticed I
couldn't get my ROM file to be identical to the one I found online.
It seems that coreboot doesn't have reproducible builds yet.
Dear Michael,
Am Donnerstag, den 28.05.2015, 02:39 +0200 schrieb Michael Gerlach:
I've done that for revision I used and latest HEAD for both, x201 and
x230..
Thank you very much!
commit d46ebfbac6ad8bf3a38639c00f6874ebf4c563d5
Author: Michael Gerlach n...@terminal21.de
Dear Michael,
Am Mittwoch, den 27.05.2015, 18:22 +0200 schrieb Michael Gerlach:
[…]
Awesome that you got it to work!
For debug and documentation reasons i will attach the working config,
vgabios, pxe rom image (with disabled BANNER_TIMEOUT), the final cbmem
boot log, the old vgabios which
Dear Michael,
Am Dienstag, den 26.05.2015, 21:12 +0200 schrieb Michael Gerlach:
This is actually what i have and as i already wrote in another mail i
got the image via:
echo 1 /sys/devices/pci\:00/\:00\:02.0/rom
cp /sys/devices/pci\:00/\:00\:02.0/rom vgabios.bin
On
Dear Michael,
Am Samstag, den 23.05.2015, 04:28 +0200 schrieb Michael Gerlach:
Uhm - I do not explicitly compressed it. I just added it to config..
Extracted it via
echo 1 /sys/devices/pci\:00/\:00\:02.0/rom
cp /sys/devices/pci\:00/\:00\:02.0/rom vgabios.bin
How to
Dear Juan,
Am Montag, den 18.05.2015, 21:05 + schrieb black...@crimson.ua.edu:
This is my first time writing to the email list to ask for some help
or insights about my problems building Coreboot. I apologize if I make
some mistakes while attempting to communicate.
Welcome to coreboot!
Dear coreboot folks,
Timothy, congratulations again on making a coreboot port for the ASUS
KGPE-D16 and therefore completing your third coreboot port! That’s
really amazing!
Am Mittwoch, den 29.04.2015, 22:46 +0100 schrieb The Gluglug:
You should crowd-fund the $35,000 figure, there are lots
Dear coreboot folks,
change set #10208 [1] is currently blocked as there are doubts if that
is the real name.
Signed-off-by: Pi Van Den Cirkel opdecir...@gmail.com
The development guidelines of coreboot contain the following sentence
[2].
You have to use your real name in the Signed-off-by
Dear coreboot folks,
Am Montag, den 04.05.2015, 23:47 -0500 schrieb REACTS:
The QEMU x86_64 Q35 fails verification as of commit
8ccdeaeb207031eea3881511acfaf3e949678f74
The following tests failed:
CBMEM_TIMESTAMP_ACCESS_FAILURE
CBMEM_OBJECT_TABLE_TRUNCATED
Commits since last
Dear coreboot folks,
commit f780c40f (CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE
for cbfstool) [1] adds a description to the Kconfig variable
`CBFS_SIZE`, which makes it, I think, visible in the Kconfig menu (`make
menuconfig`).
[…]
│
Dear Gerd, dear Greg,
sorry for the late reply.
Am Dienstag, den 21.04.2015, 11:31 -0400 schrieb Gregg Levine:
On Tue, Apr 21, 2015 at 11:21 AM, Gerd Hoffmann kra...@redhat.com wrote:
On Di, 2015-04-21 at 02:24 -0500, Raptor Engineering Automated Test Stand
wrote:
The QEMU x86_64 Q35
Dear coreboot folks,
currently there are three change sets up for review adding new Lenovo
laptops based on the Intel GM45 chipset [1][2][3]. Most of them are very
similar to the Lenovo X200, which is already in our tree.
One of the major differences between the Lenovo T* models is the HDA
verb
Dear sibu,
Am Montag, den 27.04.2015, 20:25 +0100 schrieb sibu:
I am new to this list.
welcome!
I am trying to learn how to compile coreboot. My host has these:
---cpu: AMD64 3 cores
---OS: linux (BLFS) linux-3.10.32, ( pure 64-bit ), gcc-4.8.1. IASL (
downloaded as
Dear Rajashaker
welcome to coreboot!
Am Donnerstag, den 23.04.2015, 11:03 +0800 schrieb rajashaker Goud:
I can see the CONFIG_COLLECT_TIMESTAMPS macro in the source of coreboot,
but am unable to get the clear picture of it.
if you select this option, build a coreboot based image and boot
Dear coreboot folks,
looking at the time stamps of the Intel Haswell device Google Panther,
which Matt DeVillier thankfully uploaded to the board status repository
[1], it looks odd that it took around a quarter of a second, from after
the SeaBIOS payload was decompressed to starting the
Dear coreboot folks,
commit a7d92441 (timestamps: You can never have enough of them!) [1]
added new time stamps. So please rebuild the utility `cbmem` so that the
output does not contain any *unknown* strings [2].
Or on my ASRock E350M1 with 4.0-9470-g72645bb [3]
With old cbmem:
12 entries
a waste of time.
It could be argued that GRUB2 is not GRUB, but I don't think GRUB2
is an improvement.
A lot has changed! ;-) There is also test suite (`make check`) and I
haven’t had any problems for over three or four years. You should give
it another try.
Paul Menzel wrote:
in my
Dear Alexandru,
Am Montag, den 06.04.2015, 23:09 -0700 schrieb Alexandru Gagniuc:
On Monday, April 06, 2015 11:22:18 PM Paul Menzel wrote:
Am Montag, den 06.04.2015, 14:07 -0700 schrieb Alexandru Gagniuc:
On Monday, April 06, 2015 10:46:32 PM Paul Menzel wrote:
Am Donnerstag, den
Dear Matt, dear Duncan,
Am Donnerstag, den 09.04.2015, 18:11 -0500 schrieb Matt DeVillier:
On 4/9/2015 1:21 PM, Duncan Laurie wrote:
[I got a bounce when sending this so trying again]
I think you should be able to alter the behavior with the 0xf2 and 0xf4
registers in the LDN4 block.
Dear Ajoy,
welcome to coreboot!
Am Dienstag, den 07.04.2015, 20:56 +0530 schrieb Ajoy Das:
I am running coreboot on qemu with the following sequence.
coreboot - seabios - GRUB - kernel.
The kernel booting hangs at *All ACPI Tables successfully acquired*
coreboot-4.0
Please give us
Dear Tim,
Am Montag, den 06.04.2015, 12:55 -0400 schrieb Tim Vrakas:
Hello! This is my first time doing anything with coreboot, so please
forgive my newbie mistakes.
welcome to coreboot!
I am working to add support for my motherboard (Asus Q87T) to coreboot.
Here are the basic specs:
Dear Alexandru,
Am Donnerstag, den 26.03.2015, 11:54 -0700 schrieb Alexandru Gagniuc:
On Thursday, March 26, 2015 07:53:04 AM Paul Menzel wrote:
The file is now 578K big and in CBFS the compressed size is a little
over 200 KB.
I never understood how grub2 can do less than seabios
[CC’ing coreboot, GRUB, SeaBIOS, Syslinux project and Linux kernel]
Am Montag, den 16.03.2015, 11:38 +0100 schrieb Kay Sievers:
On Mon, Mar 16, 2015 at 11:29 AM, Umut Tezduyar Lindskog wrote:
I would like to pass the time it was spent in bootloader to systemd.
Is there a kernel command line
Dear Alexandru,
Am Montag, den 06.04.2015, 14:07 -0700 schrieb Alexandru Gagniuc:
On Monday, April 06, 2015 10:46:32 PM Paul Menzel wrote:
Am Donnerstag, den 26.03.2015, 11:54 -0700 schrieb Alexandru Gagniuc:
On Thursday, March 26, 2015 07:53:04 AM Paul Menzel wrote:
The file is now
Dear Iru,
welcome to coreboot!
Am Donnerstag, den 26.03.2015, 09:33 +0800 schrieb Iru Cai:
I tried to use GRUB2 as a payload when building coreboot for ThinkPad X201,
but it's too big to fit into the rom. The GRUB2 coreboot image without
modules is 2.8M and 800K after compressing, it's
Dear Kushagra,
Am Mittwoch, den 25.03.2015, 19:26 -0700 schrieb mrnuke via coreboot:
On Thursday, March 26, 2015 07:43:26 AM Kushagra Kumar wrote:
Which is the best Linux based os to be worked on with coreboot?
Fedora
as Ron replied, as we have the coreboot toolchain (`make crossgcc`) it
Dear Kushagra,
only by chance I looked at the untitled attachment, which contains your
GSoC 2015 application.
I think you need to use the Melange(?) Web interface to turn in your
application.
Thanks and good luck,
Paul
PS: You wrote a lot of messages to the mailing list in the last days.
Dear Kevin,
Am Donnerstag, den 12.03.2015, 23:08 -0700 schrieb Kevin Paul Herbert:
Not sure how I missed this, unless util/abuild does not rebuild it.
native graphics is not selected by default. Next time change set #5957
[1] should be rebased on top to get it build tested.
Thanks,
Paul
Dear coreboot folks,
thanks to (mainly) Kyösti’s awesome work, CBMEM console [1] is now
enabled by default in the master branch.
So, if you distribute coreboot based firmware and have not enabled these
two options yet, please publish new images from latest master and upload
the board status.
Am Donnerstag, den 12.03.2015, 05:55 -0700 schrieb Milton Krutt:
Thanks Paul.
so, software RAID is fine too?
What about hardware based ones?
Sorry, I have no idea if there are boards with a hardware RAID supported
by coreboot.
As you wrote small, I suggest the ASRock E350M1 [1] or the
Am Freitag, den 13.03.2015, 00:05 -0500 schrieb Alexandru Gagniuc:
On Friday, March 13, 2015 12:42:38 AM ron minnich wrote:
On Thu, Mar 12, 2015 at 3:48 PM Paul Menzel wrote:
As this is an Intel device [1] and I am waiting for an AMD based laptop,
I’d say no. ;-)
I'm not sure AMD
Dear Milton,
Am Mittwoch, den 11.03.2015, 17:12 -0700 schrieb Milton Krutt:
Hi, can anyone suggest me a motherboard that is
suitable to set up a small backup server, say 10TB,
using some flavour of RAID (and running coreboot of
course) ?
so, software RAID is fine too?
As you wrote small, I
Dear Anthony,
Am Donnerstag, den 12.03.2015, 15:27 -0700 schrieb Anthony Martin:
I have a few questions about the samus device and I figure this
is the best place to ask.
a link to that device would be nice for those not knowing the
development names by heart.
if BOARD_GOOGLE_SAMUS
Dear coreboot folks,
trying to build a normal/fallback image [1] for the Lenovo T60 fails
with the following error.
$ make
fatal: Repository '/src/nvidia-cbootimage.git' existiert nicht.
Klonen von '/src/nvidia-cbootimage.git' in Submodul-Pfad
'util/nvidia/cbootimage'
Dear Felix, dear Varad,
Varad, welcome to coreboot!
Am Freitag, den 06.03.2015, 21:50 +0100 schrieb Felix Held:
I dumped the BIOS binary for a Radeon GPU and am trying to make sense of it
using the atombios kernel header [1] - are there any resources on ATOMBIOS
internals I can use? I
Dear David,
Am Dienstag, den 03.03.2015, 19:42 +0100 schrieb David Englund:
Is this board supported?
the board ASUS F2A85M PRO [1] is currently not supported as can be seen
in our board status page [2] or the folder `src/mainboard/asus/` of the
coreboot repository.
There was a report in the
Am Dienstag, den 03.03.2015, 00:06 -0600 schrieb Alexandru Gagniuc:
[…]
And once that's settled, we can start migrating all files to concise notices,
while keeping the exact same information we had before.
Unfortunately this never happened despite the fact it was “decided” on
in the past
Am Freitag, den 27.02.2015, 12:20 +0100 schrieb Carl-Daniel Hailfinger:
On 19.02.2015 00:14, Carl-Daniel Hailfinger wrote:
The selection of target systems should include:
1. at least one x86 laptop without an active ME (present but inactive
would be OK)
2. at least one x86 laptop which
Am Donnerstag, den 26.02.2015, 22:15 +0100 schrieb Patrick Georgi:
2015-02-26 21:56 GMT+01:00 Aaron Durbin adur...@chromium.org:
I reproduced the error. I was trying to figure out how to debug it. I
entered into the util/crossgcc/build-armv7-a-eabi-gcc directory and
typed make. Everything
Dear coreboot folks,
Am Sonntag, den 08.09.2013, 15:27 +0100 schrieb Mark Mc:
Unfortunately it wont compile the rom without crossgcc compiling for both
platforms, my crossgcc-build.log ends with and appears to have no other
failures than:
cc1: fatal error: .vis: No such file or directory
Dear Timothy,
thanks again for improving the support for the ASUS KFSN4-DRE and being
so responsive. It’s a great example for how to work with upstream!
You uploaded the board status output [1] with commit 8057285 [2].
Thanks!
But, it looks like a lot of information is missing from the
Dear Timothy,
Am Mittwoch, den 11.02.2015, 11:41 -0600 schrieb Timothy Pearson:
I have recently updated the coreboot ACPI autogeneration code to
generate valid processor _PSS objects when more than 10 cores are
installed in one system.
Unfortunately this required a rather large update
Dear John,
Am Freitag, den 14.11.2014, 11:44 + schrieb John Lewis:
I've modified the board-status script to have as few external
dependencies as possible, be a self-extracting, self-running binary.
and removed the time-stamp to keep the number initial commits down. Feel
free to tell
Dear Wen,
welcome to coreboot!
Am Donnerstag, den 22.01.2015, 23:34 -0500 schrieb Wen Wang:
Has anybody tried to launch GRUB2 by SeaBIOS as a payload (not grub2 on
MBR)? I am hoping to see grub2 on SeaBIOS boot menu.
Yes, I did. You can press F12 (or the configured key) and select the
Am Donnerstag, den 15.01.2015, 16:08 -0800 schrieb David Hendricks:
On Thu, Jan 15, 2015 at 3:34 PM, Paul Menzel wrote:
Issues which are closed now will almost certainly remain that way.
Should those be referenced in the source code then?
Probably not, but at some point it just
Dear coreboot folks,
Am Mittwoch, den 14.01.2015, 22:53 +0100 schrieb Paul Menzel:
on the Lenovo X60s, running coreboot with SeaBIOS as payload, adding the
two lines below to GRUB’s configuration in `/etc/default/grub`
GRUB_GFXMODE=1024x768
GRUB_GFXPAYLOAD_LINUX=keep
Am Mittwoch, den 14.01.2015, 15:17 -0800 schrieb David Hendricks:
On Wed, Jan 14, 2015 at 2:11 PM, Paul Menzel wrote:
looking at change set #8214 [1], it adds a comment with a reference to
the Chromium bug tracker at code.google.com.
http://crosbug.com/p/29117
Unfortunately
Dear coreboot folks,
on the Lenovo X60s, running coreboot with SeaBIOS as payload, adding the
two lines below to GRUB’s configuration in `/etc/default/grub`
GRUB_GFXMODE=1024x768
GRUB_GFXPAYLOAD_LINUX=keep
and running `update-grub`, which updates GRUB 2.02~beta2-20 (Debian
Dear coreboot folks,
looking at change set #8214 [1], it adds a comment with a reference to
the Chromium bug tracker at code.google.com.
http://crosbug.com/p/29117
Unfortunately access to view that is denied to me.
Looking at some of the items already in the upstream tree, most of them
Am Dienstag, den 06.01.2015, 12:30 +0100 schrieb Michał Masłowski:
Does somebody have a coreboot log from serial or USB for cold boot and
resume, please? I am unable to get one right now, because the docking
station is not here.
I have logs from EHCI debug: normal boot and resume from
Am Sonntag, den 04.01.2015, 12:44 +0100 schrieb Michał Masłowski:
On the i945 based Lenovo X60, running `cbmem -l` (or any other option)
works fine. Suspending and resuming the system, running any `cbmem`
commands does *not* work anymore.
Running cbmem -Vl on my X60t shows that the first
Dear coreboot folks,
first of all I wish everyone a happy new year!
On the i945 based Lenovo X60, running `cbmem -l` (or any other option)
works fine. Suspending and resuming the system, running any `cbmem`
commands does *not* work anymore.
$ sudo pm-suspend
$ sudo cbmem -l
Dear Prannoy,
Am Donnerstag, den 18.12.2014, 19:46 +0530 schrieb Prannoy Pilligundla:
I am Prannoy currently pursuing undergrad in India. I am competent in C,
Java and Python. I have experience of working in Assembly on x86
processors. I have been using Linux since last two years. I
Dear Alexandre,
Am Mittwoch, den 29.10.2014, 04:43 +0100 schrieb Garreau, Alexandre:
I noticed some Fn+key present with previous BIOS still are unimplemented
with coreboot in Lenovo Thinkpad X60T: Fn+Space (zoom?), Fn+F9 (eject??),
Fn+PgUp (ThinkLed??), Fn+Print (“SysRq”), Fn+Pause (“Break”).
Dear Alex,
Am Montag, den 20.10.2014, 15:49 +0800 schrieb alex...@mxic.com.tw:
Please help to update the new Macronix SPI Flash support
in the ~coreboot/src/driver/spi/macronix.c .
thanks a lot for your contribution. Idwer Vollering submitted it for
code review [1] and, after
Dear anonymous,
Am Freitag, den 24.10.2014, 07:59 + schrieb corebootlap...@yopmail.com:
Which $300 to $500 laptop would be the topmost pick for CoreBoot
compatibility?
first, please note that the official spelling of coreboot is all
lowercase. (At least never CamelCase.)
I need CoreBoot
Dear anonymous,
Am Freitag, den 24.10.2014, 07:59 + schrieb corebootlap...@yopmail.com:
[…]
As long as I'm here I may as well ask about miniITX too. If the laptop
is too problematic then that's another way I can go. What's the most
compatible miniITX on the market?
I’d recommend the
TLDR; Upgrading the drive firmware to 070H solved the issue.
Am Samstag, den 20.09.2014, 02:12 +0200 schrieb Peter Stuge:
Paul Menzel wrote:
Changelog for 070H:
..
* Resolved a power-up timing issue that could result in a drive
hang, resulting in an inability to communicate
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