Mimicked from flashrom.c, see patch.
Signed-off-by: Idwer vid...@gmail.com
Index: README
===
--- README (revision 3854)
+++ README (working copy)
@@ -21,7 +21,7 @@
Usage
-
- $ flashrom [-rwvEVfh] [-c chipname] [-s
2009/5/13 Uwe Hermann u...@hermann-uwe.de
On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Thanks, r499.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
2009/5/13 Uwe Hermann u...@hermann-uwe.de
On Wed, May 13, 2009 at 12:05:32PM +0200, Carl-Daniel Hailfinger wrote:
Acked-by: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
Thanks, r499.
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
2009/5/22 Urja Rannikko urja...@gmail.com
Hello all,
First thanks to Uwe for nic3com support and to Mats Erik (IIRC) for helping
with (or atleast pointing out the lack of) 3C905B support - i just tested a
SST 29EE010 on an 3C905B-TXNM that had been useless for a while - works :)
Anyways,
2009/6/2 Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net
On 15.05.2009 01:29, Idwer Vollering wrote:
Index: nic3com.c
===
--- nic3com.c (revision 501)
+++ nic3com.c (working copy)
@@ -51,6 +51,9
: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Make FreeBSD's gmake happy.
Signed-off-by: Idwer Vollering vid...@gmail.com
Index: board_enable.c
===
--- board_enable.c (revision 568)
+++ board_enable.c
r.ma...@assembler.cz
+ * Copyright (C) 2010 Idwer Vollering vid...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
2010/4/12 Keith Hui buu...@gmail.com
This patch adds preliminary and untested ACPI support to Intel
440BX/82371EB
(e.g. ASUS P2B and its variants/similar boards).
It focuses on an/the ASUS P2B which comes with three ram slots, hence the
change to src/northbridge/intel/i440bx/raminit.c.
Is the three or four DIMM choice committed ? Because I don't see it in
Kconfig:
http://tracker.coreboot.org/trac/coreboot/browser/trunk/src/mainboard/asus/p2b/Kconfig
Found it: http://tracker.coreboot.org/trac/coreboot/changeset/5204
It looks like changing Kconfig for the P2B was overlooked
...@assembler.cz
+ * Copyright (C) 2010 Idwer Vollering vid...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your
2010/5/14 Keith Hui buu...@gmail.com
The original patch was unclean as pork (didn't apply cleanly). Please
use this one instead.
Thanks Joseph.
And edit your board's romstage similar to patch below:
Index: src/mainboard/asus/p2b-ls/romstage.c
2010/5/14 Keith Hui buu...@gmail.com
BTW enable CAR and try again.
Like this (note that it doesn't boot my asus p2b, rev 1.04):
svn diff src/mainboard/asus/p2b/Kconfig
Index: src/mainboard/asus/p2b/Kconfig
===
---
2010/5/16 Keith Hui buu...@gmail.com
A number of cleanups for 440BX raminit code.
Resolves a number of TODOs items within, and clarified a number of other
TODOs.
Change register_values[] from long to u8 (byte). For what we are doing
this is sufficient and makes it only 1/4 the size.
Remove
2010/8/30 Andreas Schultz aschu...@tpip.net
Hi,
Here is a series of patches wich improve i855 support and a new board
with that chipset.
The board boots successfully with Seabios into Linux!
Nice work. Can you show the output from the console (serial output) ?
Off topic: I'm asking this
APIC_CLUSTER: 0 init
start_eip=0xc000, offset=0x0010, code_size=0x005b
Initializing CPU #0
CPU: vendor Intel device f29
CPU: family 0f, model 02, stepping 09
POST: 0x60
Enabling cache
Andreas
Idwer
On Tue, 2010-08-31 at 02:41 +0200, Idwer Vollering wrote:
2010/8/30 Andreas
2010/9/18 Uwe Hermann u...@hermann-uwe.de
See patch.
This fix is brought to you by SerialICE(tm), thanks!
Tested on hardware with an identical southbridge (ASUS P2B rev 1.04),
booting doesn't seem to be affected.
Acked-by: Idwer Vollering vid...@gmail.com
Uwe.
--
http://hermann-uwe.de
2010/10/6 Uwe Hermann u...@hermann-uwe.de
See patch.
Here is a fix for building on 32-bit platforms:
Index: src/northbridge/intel/i440bx/raminit.c
===
--- src/northbridge/intel/i440bx/raminit.c (revision 5917)
+++
2010/10/7 Stefan Reinauer stefan.reina...@coresystems.de
On 10/6/10 2:27 PM, Idwer Vollering wrote:
2010/10/6 Uwe Hermann u...@hermann-uwe.de
See patch.
Here is a fix for building on 32-bit platforms:
Index: src/northbridge/intel/i440bx/raminit.c
Acking the second patch (v4_remove_c_includes_i82371eb_2.patch):
Acked-by: Idwer Vollering vid...@gmail.com
else converting the QEMU target to CAR seems like the other option.
That won't work as far as I've heard (QEMU limitations).
Uwe.
--
http://hermann-uwe.de | http://sigrok.org
http
If it does:
Acked-by: Idwer Vollering vid...@gmail.com
Index: mainboard/gigabyte/ga-6bxe/romstage.c
===
--- mainboard/gigabyte/ga-6bxe/romstage.c (revision 5929)
+++ mainboard/gigabyte/ga-6bxe/romstage.c (working copy
2010/10/12 Keith Hui buu...@gmail.com
Guys,
Hi Keith,
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
unknown CPU. I believe it will happen with any Slot 1 440BX boards
that supports model_6bx CPUs.
Can you confirm that this changeset caused the regression:
Update support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com
---
FreeBSD support already existed but doesn't compile without errors on my
fbsd 8.1 machine:
$ gmake
gcc -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing
-Werror-implicit-function-declaration -ansi
Add support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com
---
I took the liberty to copy MSR code from flashrom's hwaccess.h.
Patch was written using FreeBSD 8.1, earlier versions might or might not
work.
Index: inteltool.h
2010/10/18 Warren Turkal w...@penguintechs.org
On Sunday, October 17, 2010 09:37:27 am Idwer Vollering wrote:
Update support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com
Updated patch attached.
Signed-off-by: Idwer Vollering vid...@gmail.com
A few questions:
* Would
2010/10/18 Warren Turkal w...@penguintechs.org
On Sunday, October 17, 2010 09:37:31 am Idwer Vollering wrote:
Add support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com
Updated patch attached.
Signed-off-by: Idwer Vollering vid...@gmail.com
In inteltool.h:
* Can you
2010/10/18 Andriy Gapon a...@icyb.net.ua
on 17/10/2010 19:37 Idwer Vollering said the following:
Update support for FreeBSD.
Signed-off-by: Idwer Vollering vid...@gmail.com mailto:
vid...@gmail.com
BTW: http://www.freebsd.org/cgi/cvsweb.cgi/ports/sysutils/superiotool/
I know of its
2010/11/9 Qing Pei Wang wangqing...@gmail.com
see the patch
Nack. Please don't change this, or this will happen (demonstrated using
FreeBSD 8.1 + libpci 3.1.7 + gmake-3.81):
$ gmake clean gmake
rm -f superiotool *.o
gcc -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing
Forwarding this to the list, for reference/proof:
-- Forwarded message --
From: Andreas Schultz aschu...@tpip.net
Date: 2010/8/31
Subject: Re: [coreboot] [PATCH 0/3] i855 support
To: Idwer Vollering vid...@gmail.com
Hi,
Attached is the serial output and the configuration i used
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5.
Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo
2010/11/28 Uwe Hermann u...@hermann-uwe.de
On Sat, Nov 27, 2010 at 12:02:46PM +0100, Tobias Diedrich wrote:
Add acpi_is_wakeup_early to i82371eb and P2B.
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi
2010/11/29 Joseph Smith j...@settoplinux.org
On Sun, 28 Nov 2010 01:19:18 +0100, Idwer Vollering vid...@gmail.com
wrote:
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5.
Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6
2010/12/21 Keith Hui buu...@gmail.com:
As promised. Attached is my fix:
Copy/paste:
Index: src/northbridge/intel/i440bx/raminit.c
===
--- src/northbridge/intel/i440bx/raminit.c (revision 6205)
+++
2010/12/26 Stefan Reinauer stefan.reina...@coresystems.de
See patch
Nice. Can you extend it so the serial port number, #define DEBUG_PORT
PORT_SERIAL1, in $seabios_dir/src/output.c is shared with
CONFIG_CONSOLE_SERIAL_COM1 in coreboot's .config, and so on for COM2..4 ?
Dito for #define
2011/1/8 Roger rogerx@gmail.com
On Fri, Jan 07, 2011 at 10:45:40PM +0200, Jouni Mettälä wrote:
Hi
Parts of original patch are already in coreboot. This version made
cache
work in my board now. It might need work so it doesn't break others.
Here
is part of serial capture.
2011/3/2 Keith Hui buu...@gmail.com
---
First, Mysterious breakage on experimental i82371eb ACPI stuff
Rudolf, Idwer, and anyone that tried doing ACPI for the ASUS P2B
series of boards:
I'm seeing mysterious compiler breakge after updating my local copy to
r6424. I copied that from P2B to
2011/3/10 Peter James messageforpe...@gmail.com
Just wondering if any further progress has been made to the intel 82855
chipset which as far as I can tell is in a WIP status. Has anyone been able
to get this working successfully?
Apparently not/not really. What board images have you tried
2011/3/29 Georgi, Patrick patrick.geo...@secunet.com:
Am Dienstag, den 29.03.2011, 16:22 +0530 schrieb sharib khan:
sharib/coreboot]$ make menuconfig
Makefile, line 23: Missing dependency operator
Makefile, line 25: Need an operator
Error expanding embedded variable.
Could anyone tell what
/deskpro_en_sff_p600
emulation/qemu-x86
gigabyte/ga-6bxc
gigabyte/ga-6bxe
msi/ms6119
msi/ms6147
msi/ms6156
nokia/ip530
soyo/sy-6ba-plus-iii
tyan/s1846
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
2011/4/1 Stefan Reinauer stefan.reina...@coreboot.org:
* Idwer Vollering vid...@gmail.com [110401 20:29]:
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
===
--- src
V2.
Signed-off-by: Idwer Vollering vid...@gmail.com
---
Index: src/southbridge/intel/i82371eb/Makefile.inc
===
--- src/southbridge/intel/i82371eb/Makefile.inc (revision 6474)
+++ src/southbridge/intel/i82371eb/Makefile.inc (working
2011/4/5 James Wall scouter...@gmail.com:
Hello all,
What is the status of the i865 memory controller?
That chipset as a whole is (currently) unsupported, however plans to
support it are there.
RAM init is work in progress, another developer and I have a total of
three i865 boards. Since RAM
2011/4/6 James Wall scouter...@gmail.com:
I will look at the source code then for more ideas and to help understand
the code then. thanks for the information.
If you want to help porting, can you produce a serialice log (and send
it to Josephd and me, offlist) ? See the website,
2011/4/1 Keith Hui buu...@gmail.com:
ping?
Adds support for initializing registered SDRAM modules on Intel 440BX
northbridge.
Drops unneeded romcc-inspired programming tricks.
Only set nbxecc flags (see 440BX datasheet, page 3-16) when a non-ECC
module has been detected
in a row via SPD;
2011/4/18 Peter Stuge pe...@stuge.se:
Marek wrote:
What about the DB_PORT programming header?
http://hardforum.com/showthread.php?t=1598236
Maybe! Can you trace the connections from the port to the flash
chips?
Is the dual BIOS stored on the MX25L1606EM2I-12G chip?
GIGABYTE boards that
2011/4/20 David Bein d.b...@f5.com:
Hello Idwer,
Hello David,
Thank you very much for the assistance. I assume
that something like: nvramtool -c 0 will force the
newly booted bios to re-compute the checksum on the cmos?
I assume you want to save the current contents with nvramtool -b
2011/4/22 Schenk, John josch...@uncc.edu:
Could anyone help in identifying the Phoenix BIOS Chip on the motherboard?
It looks like the chip is just below the lower right corner of the
cardbus frame: http://www.techex.biz/ebaybiz/pics/Motherboards/MBD-00544_02.jpg
The objective is to replace
2011/5/16 Scott Duplichan sc...@notabs.org:
If you happen to want to test windows xp setup
using a standard setup CD, windows will not find the drives because
it has no AHCI support. The standard solution is the F6 floppy method
of adding an AHCI driver, but lack of floppy support on new
2011/5/27 Cui Lei neverforget_2...@163.com:
I had the same error, just install the lastest binutils, try again.
Quote: If you have compiler or binutils trouble, REPRODUCE WITH
coreboot/util/crossgcc and then send a log to the mailing list
i try to do a build Of core boot and I get this after
2011/6/19 dove - railing doverail...@gmail.com:
I have phoned Australia and spoke to an expert in Procon.com.au about 2
times and corresponded via email. Procon.com.au are wanting several hundred
dollars whether it's my font or theirs. This is not affordable. I don't
know why vga bios is
2011/8/2 dove - railing doverail...@gmail.com:
If I said I am prepared to pay for it, what are you going to charge for
doing this project?
Sorry, I have no idea what (amount of money) to charge, nor how much
work it will be.
Others can most likely provide a better/more satisfying answer.
Idwer
2011/8/15 dove - railing doverail...@gmail.com:
Please tell if you interested in doing this project, leaving aside the money
issues.
Please use reply to all, thanks in advance.
Idwer
Regards
Meeku
On Sun, Aug 14, 2011 at 6:49 PM, Idwer Vollering vid...@gmail.com wrote:
2011/8/2 dove
2011/10/5 Alp Eren Köse alperenk...@buyutech.com.tr:
Anyone has an idea?
Another question is I can't find my mainboard vendor Axiomtek in Mainboard
Vendor selection list in menuconfig as expectedly, but all the chips and
chipset of it seem to be supported as I see them in coreboot website. Is
2011/10/10 Alp Eren Köse alperenk...@buyutech.com.tr:
As written on the subject 'make crossgcc' fails as following:
Skipping GDB as requested by command line
Building IASL 20110623 ... failed
make[1]: *** [build-without-gdb] Error 1
make: *** [crossgcc] Error 2
Anyone knows why?
and the
Comments inline:
2011/10/17 Idwer Vollering vid...@gmail.com
2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr
Hi all,
I can't get serial output from the board I am trying to put coreboot on,
so I am not able to go any further to see whats going on..
The board has a Winbond
2011/10/17 Alp Eren Köse alperenk...@buyutech.com.tr
Hi all,
I can't get serial output from the board I am trying to put coreboot on, so
I am not able to go any further to see whats going on..
The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e.
It is likely that you need
2011/10/18 Alp Eren Köse alperenk...@buyutech.com.tr
Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e
Register dump:
idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f
val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff
def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00
CR24
2011/12/30 Prakash Punnoor prak...@punnoor.de:
Hi,
I am trying to build coreboot with SeaBios (for a new mainboard I am trying
to port). Initially the build system complained about a broken LD, so I
built make crossgcc -j1 (iasl compile fails in parallel mode, btw)
Oh? Wasn't that fixed..
Or: how to start a multicore (hyperthreading) processor as if it were
a singlecore (non-hyperthreading) processor.
Would it be necessary to configure APIC/IPI in serialice' mainboard
specific code?
See these message [1] [2] [3].
This is the output from two processors with hyperthreading disabled
patch is totally untested, but I expect it to work.
A big THANK YOU goes to Idwer Vollering who tested a dozen iterations of
this code until I had figured out the very surprising and unique
properties of the SerialICE protocol.
Another big THANK YOU goes to Ron Minnich who sent a mail titled
Op 28 maart 2012 14:52 heeft ali hagigat hagigat...@gmail.com het
volgende geschreven:
- Forwarded message --
From: ali hagigat hagigat...@gmail.com
Date: Wed, Mar 28, 2012 at 4:58 PM
Subject: Re: [coreboot] porting Coreboot to a new motherboard
To: Kyösti Mälkki
Op 30 maart 2012 18:59 heeft Marc Dunivan mduni...@hawk.iit.edu het
volgende geschreven:
I have and old HP Pavillion with an Asus M2N68-LA Narra 2 mother board.
Coreboot hasn't been ported to it. Not asking for it either.
I just want to know the northbridge and southbridge it has.
2012/5/23 martin.m...@mic.com.tw:
Hello all,
I check out coreboot and build and run persimmon project via menuconfig,
Are you using a payload? If so, which one are you using?
Mainborad: AMD
Mainboard Model: Persimon
FlashSize: 4MB
But it always show 0x00 on my PCI debug card.
2012/6/6 Ross McDonald ross0mcdon...@gmail.com:
Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq NC6320.
The board vendor is HP. It is a
HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M southbridge and i945
northbridge). The CPU is an Intel Core 2 Duo T5600. It has a
2012/6/25 Tomi Leppänen tomppel...@gmail.com:
Hi,
I have a Gigabyte GA-6BXE (Rev 2.1) motherboard with coreboot (built last
week, I think). My processor is Intel Pentium III 550 and I have 786 MiB of
RAM (actually 1 GiB but the motherboard can't see a part of it). It works
just fine when I
2012/7/6 Michael Büchler mbuechle...@gmail.com:
On Fri, 2012-07-06 at 13:10 +0200, Michael Büchler wrote:
I'm trying to run coreboot on an ASUS A8V-E Deluxe. It stops with a
SIGILL after saying the following (tail of the log I got over serial):
I was able to get around this by using gcc-4.4.6
2012/7/2 Sven Schnelle sv...@stackframe.org:
Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net writes:
[adding coreboot mailing list to CC]
Am 29.06.2012 16:49 schrieb Stefan Monnier:
You do know that all Thinkpad T60/X60 can replace the BIOS with coreboot?
No, I didn't, that would
2012/7/8 Peter Stuge pe...@stuge.se:
Idwer Vollering wrote:
I have a X60 (1707-CTO / 1707YAU) that won't boot Linux (it
segfaults while booting either a 32- or 64-bit kernel/distribution)
at all, with ACPI enabled.
What does the failed boot look like? Maybe you could try netconsole
2012/7/9 ron minnich rminn...@gmail.com:
On Sat, Jul 7, 2012 at 6:24 PM, Idwer Vollering vid...@gmail.com wrote:
netconsole won't - afaik - work because IP (UDP) isn't
functional/loaded at the time of the crash..
hi, did not check this, but you did not used to need IP or any kind up
2012/7/14 Motiejus Jakštys desired@gmail.com:
On Fri, Jul 13, 2012 at 10:43 AM, Motiejus Jakštys
desired@gmail.com wrote:
On Thu, Jul 12, 2012 at 1:26 PM, Tomasz Ostaszewski
ostaszewski.tom...@gmail.com wrote:
Hi Peter, Motiejus,
Tried to ask on the flashrom mailing list but to
2012/7/15 David Griffith d...@661.org:
Would it be worthwhile, at least as an learning experience, to port Coreboot
to the Thinkpad T42?
My advice is to make i855 work on a desktop machine first.
lspci of a thinkpad t42:
http://www.linuxquestions.org/hcl/showproduct.php/product/3047/cat/all
2012/7/26 wx fred...@hotmail.com:
How can get 3rd party bins like mrc.bin for SandyBridge/Ivybridge ?
Besides having the possibility to extract mrc.bin with cbfstool, you
can 'download' at least one mrc.bin from the blobs repository:
git clone http://review.coreboot.org/p/blobs.git
Folder
CC: flash...@flashrom.org
2012/9/15 Keith Hui buu...@gmail.com:
Hi all,
I'm back. With a new laptop.
I'm now rocking a Lenovo x230 tablet, dual-booting Windows 7 and
Fuduntu, both 64-bit. Knowing the last time I contributed to coreboot
it was the good old 440BX when life was much simpler,
2012/10/15 Hristo Venev mustrum...@gmail.com:
Is it a gcc bug or is it a coreboot bug?
Actually it is a binutils 'bug'. You should run 'make crossgcc' (and
remove .xcompile) in the top directory, where you run 'make
menuconfig'.
--
coreboot mailing list: coreboot@coreboot.org
2012/10/15 Hristo Venev mustrum...@gmail.com:
Binutils bug or feature?
Rather a distribution feature.
http://www.coreboot.org/Development_Guidelines#Required_Toolchain --
Linux distributions usually modify their compilers in ways
incompatible with coreboot. If in doubt, use our toolchain.
--
Please reply with reply to all, thanks.
2012/10/15 Hristo Venev mustrum...@gmail.com:
Fixed it by using my linux distribution's toolchain but specifying -march=i686
Probable reason: some instructions enabled by default by gcc but not enabled
at
early stages of booting.
Hm, I suppose that
2012/11/1 jeroenkrabben...@fastmail.fm:
Thank you for this tip.
I followed the instructions (make crossgcc), but got stuck while building gcc
on a 'bus error' of genautomata.
Details (total of 3):
1. Output of make crossgcc:
Indus ~ # cd /usr/src/coreboot/
Indus coreboot # make
2012/11/1 jeroenkrabben...@fastmail.fm:
Thx for replying.
I switch to this email address, trying not to pollute the mailing list.
Please keep coreboot@ in the To: or CC field, others can't help you
when you don't use reply-to-all.
I think is not a hardware problem, as the error occurs on
2012/12/18 David Hubbard david.c.hubbard+coreb...@gmail.com:
Hi all,
On Mon, Dec 17, 2012 at 6:40 AM, Bernhard Urban lew...@gmail.com wrote:
On Mon, Dec 17, 2012 at 2:33 PM, darkdefe...@gmail.com wrote:
Rudolf Marek writes:
Maybe it is slowly time to prepare a patch, I think I will need
2013/2/26 Francisco Otero Martínez de Al girot...@yahoo.es:
I didn't flash nothing yet.
Please advise me if it is safe to load coreboot on this motherboard.
Quoting the logfile: Found chipset NVIDIA MCP61
MCP61 is not in this list:
http://www.coreboot.org/Supported_Chipsets_and_Devices so the
2013/4/6 Marc Jones marcj...@gmail.com:
Hi Ward,
I think that the H8QGI has fairly good support (the one SMP late init bug
noted). I didn't look at the details, but similar boards should be a easy
port. The supermicro boards will often have the pads for the debug header
for when the going
2013/4/11 Pradish M P, ERS, HCLTech pradis...@hcl.com:
Dear coreboot folks
i downloaded the latest source code form coreboot.org , when i tried to build
the cross compiler
using the command make crossgcc
it gives the following error
root@test-VirtualBox:~/coreboot# make crossgcc
2013/5/14 Bin X z2...@outlook.com:
I apologize if it does not make sense at all since this is my first attempt
to flash a bios with unmatched bios ID.
I was trying to flash bios on a Itona TC2331 to get rid of the limitation
they put on of any IDE HDD and USB HDD can’t be larger than 64mb.
2013/6/25 Gerd Hoffmann kra...@redhat.com:
Hi,
Two little issues with T60:
First, the keyboard doesn't work on cold boots.
http://www.coreboot.org/SeaBIOS#Other_Configuration_items
You have to create the file etc/ps2-keyboard-spinup:
$ ./encodeint.py ps2-keyboard-spinup 2000
$ hexdump
2013/8/27 matti christensen mat...@iki.fi
/mc
matti christensen
---keep-IT-simple---
No one can, or will, help you when you don't include any information at all.
Which linux distribution are you using?
Did you run 'make crossgcc' ?
coreboot supports three [1] epia-m boards, which one do you
2013/10/29 Haywood-Evans Matthew mahev...@qinetiq.com:
Hi,
I am presently looking at trying to get Coreboot up and running on an
ASUS F2A85-M system. I am however running into some issues.
Using a bus pirate and flashrom I first backed up the original bios,
then erased the chip and restored
Oops, let's send it to the list as well.
2013/11/25 ron minnich rminn...@gmail.com:
Folks, I'm looking for a very small board with the following:
- x86_64, preferably with virtualization capability
- 4-8 G or so of memory
- intel e1000 or rtl8139 gige
- coreboot not required, but strongly
2013/12/13 陈军根 c...@bolod.net:
Dear all:
I run coreboot in ASUS F2A85-MLE CPU is A10-5800k, kingston ddr3
1600(kvr1600d3n9/4g),coreboot halt at assertion Failed:file
'src/vendorcode/amd/agesa/f15tn/proc/mem/main/mmexcludedimm.c',line 236. I
don't know how to do, can anyone help me?
Forwarding the reply where 陈军根 c...@bolod.net informed me of his
findings, see below.
-- Forwarded message --
From: 陈军根 c...@bolod.net
Date: 2013/12/17
Subject: Re: [coreboot] coreboot on amd A85 can't work
To: Idwer Vollering vid...@gmail.com
Idwer:
the vendor(ASUS) EFI
2014-01-30 Darmawan Salihun darmawan.sali...@gmail.com:
Is this where to clone it from:
http://review.coreboot.org/coreboot.git
You can find cloning instructions, and how to contribute/push changes,
on this wiki page: http://www.coreboot.org/Git
HTH,
Idwer
--
coreboot mailing list:
Compiling for 8MB however works just fine.
Error output:
Created CBFS image (capacity = 4193256 bytes)
E: Could not add [build/coreboot_hudson_romsig.bin, 16 bytes (0
KB)@0xffc2]; too big?
E: Failed to add 'build/coreboot_hudson_romsig.bin' into ROM image.
make: *** [build/coreboot.pre1]
2014-02-07 Andy Pont andy.p...@sdcsystems.com:
Hello!
Hello!
I am trying to setup a build environment on 64bit CentOS 6.5 platform to be
able to build coreboot. I have cloned the coreboot sources from git and
have run the following commands:
make crossgcc -- to build the cross
2014-02-09 20:05 GMT+01:00 Andy Pont andy.p...@sdcsystems.com:
Hello Idwer,
8
I have noticed that whenever I call make it gives a warning about not having
a compiler for aarch64-elf and also complains about not having an IASL
compiler and suggesting that I install the one that comes with
Adding seabios at seabios dot org to the recipients.
2014-02-10 0:47 GMT+01:00 Andy Pont andy.p...@sdcsystems.com:
Hello!
Apparently CentOS installs, or will install, a really old version of
iasl; here you'll see that they (still) use
iasl-20090123-3.1.el6.x86_64:
2014-02-04 22:36 GMT+01:00 Rudolf Marek r.ma...@assembler.cz:
Perfect thank you for this whole procedure. This is what I obtain:
My rom (with my vga bios):
coreboot-4.0-5394-gba6b07e Thu Jan 30 19:48:58 CET 2014 starting...
BSP Family_Model: 00610f31
cpu_init_detectedx =
Thank you for this information. Please indicate the compatible
processor on the motherboard page.
See this list:
http://en.wikipedia.org/wiki/List_of_AMD_Accelerated_Processing_Unit_microprocessors#Virgo_-_.22Trinity.22_.282012.2C_32_nm.29
I'll add it to the board's wiki page.
--
coreboot
2014-02-17 6:56 GMT+01:00 Anthony Ross anthonyross...@gmail.com:
Hello Folks
Well Im a bit confused on how to use the IRC provided for the list
members. It seems just silent for hours, no responses at all. Could someone
provide help?
Quiet? Are you sure you joined the right channel :) ?
2014-02-20 9:38 GMT+01:00 Justin Roylance justin.royla...@gmail.com:
the flashrom utility in Kubuntu says no chipset found and no EEPROM/flash
device found.
The version that Kubuntu ships could very well be outdated. (dist-)upgrade
your installation and/or see
2014-03-12 11:23 GMT+01:00 yu chyuan fu fuh0...@gmail.com:
Hi All
I am a novice with coreboot. I successfully build coreboot.rom follow
www.coreboot.org.
Now i want to burn it to flash chips. I tried using the vendors provide
flash utility write to flash chips, it's can write success.
The
2014-04-03 17:07 GMT+02:00 Dominic Walden domi...@dwalden.co.uk:
Hi all,
I understand the f2a85-m is working with coreboot. Does anyone know if
the Limited Edition version will also work, or whether it will
require some work?
See these posts:
2014-04-05 15:48 GMT+02:00 Luc Verhaegen l...@skynet.be:
On Sat, Apr 05, 2014 at 03:20:08PM +0200, Rudolf Marek wrote:
Hi all,
I think there is OpenRadeonBios. The problem is that thhe AtomBIOS
bytecode is vendor specific blob, which cannot be in principle released
by AMD because it is
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