Hi Meeku,
dove - railing wrote:
> I am prepared to offer 200 euros to any software engineer/s who
> is/are able to alter the BIOS fonts to a font that I prefer.
First, coreboot is not a BIOS modding forum. There are at least a few
actual BIOS modding forums, where you would be swamped with respon
Oskar Enoksson wrote:
> Checking out the version just after my commit 2010-08-20 compiles
> and seems to boot, but depending on how much debugging messages I
> choose in "make menuconfig" I get different problems such as just
> one of my two CPU's initializing, or just strange lockups. In
> general
Scott Duplichan wrote:
> ]the bootblock doesn't correctly set up ROM mapping correctly.
>
> That is a good point about rom mapping. According to the 8111
> document, only the top 64KB is decoded by default. Simnow confirms
> this, and won't boot the DL145 G1coreboot image.
Good find.
> If I man
Lundie wrote:
> I have rolled and flashed a coreboot rom to the above motherboard, and
> after a reboot (soft) my video bios flashed up a few times and I
> sucessfully made the SeaBIOS prompt. However since then I have not had
> video.
..
> The specs of the machine are: 768mb ( 3 x 256mb pc133
Hi Roman,
Roman B. wrote:
> I would like to have my motherboad supported. Technical data as
> asked on the wiki follows.
>
> 1. Motherboad, chipset and CPU
> ASUS P5GD1-VM
> Northbridge: Intel 915 Graphics Memory Controller Hub (GMCH)
Not exactly supported I think, so adding support for your boa
Hi,
Oskar Enoksson wrote:
> I'm trying to upload a patch. It seems that for some reason
> "gerrit" requires a "signed-off-by" line in every single local
> commit in order to push it to the remote location.
More background at
http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure
> I'
Stefan Reinauer wrote:
>> Building IASL 20110623 ... failed
>> make[1]: *** [build-without-gdb] Error 1
>> make: *** [crossgcc] Error 2
>
> Sounds like $(CC) is not set for some reason?
I spent some time debugging this when I first encountered it but I
don't know how simple the solution is. CC ind
Kerry Sheh wrote:
> commit 42acf3ccf042ecf596df8d149ad66512e81a8fc8
> Author: Kerry Sheh
> Date: Mon Oct 10 19:19:46 2011 +0800
>
> mainboard: complete the sb800 devicetree even device is off
>
> sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
> enable_dev() f
Thomas Gstädtner wrote:
> As a "end-user" I'd really prefer a possibility to participate in this
> issue;
You would send a patch.
> I think it is not possible for the few active devs to maintain
> every mainboard all the time and make sure to note it in git.
This was never the idea. It is obvio
mopz0506 mopz0506 wrote:
> the new url is : http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf
> the new url is: http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf
I've updated all URLs for SB7x0. Thanks.
//Peter
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coreboot mailing list: coreboot@coreboot.org
http://www.cor
mopz0506 mopz0506 wrote:
> Yes it works now.
>
> Even though ASRock put this "Always Power On" feature under
> "SouthBridge Configuration" menu item (mislead me very much),
> it actually controlled by SIO, NUVOTON NCT5572D.
>
> I think the E350M1 + coreboot is perfect for me now. so nice to
> ge
QingPei Wang wrote:
> the superio part should placed under the LCP bridge.
> for your mainboard,
> it should under
> "device pci 1f.0 on end # LPC bridge
> "
The "end" on this line goes after the newly introduced chip block.
> add the superio things like:
> "
> device pc
mopz0506 mopz0506 wrote:
> What I do is just enable the E350M1 Winbound ACPI device in
> devicetree.cb.
> just change the "off" to "on" and everything works fine.
Aha! No code changes needed?
> Is it OK to attach the patch in this mail list?
Normally everything goes via Gerrit, but because you
Kyösti Mälkki wrote:
> Some trouble here, local abuild completes patchsets, but Jenkins
> doesnt.
>
> http://review.coreboot.org/302
This has been verified now. Dunno what you fixed?
> http://review.coreboot.org/303
>
> Here the patchset Parent(s) got set properly, but dependency to
> E7505 is
Hi,
Bao, Zheng wrote:
> We are building a build machine, which is connect the AMD network
> with a firewall. We need to provide the IP address and port(29418)
> of coreboot.org to access the git server. It doesn't work yet.
>
> I am wondering if the OpenID needs extra website address and port
> t
Peter Stuge wrote:
> The Gerrit server communicates directly with your OpenID provider,
To clarify, this is in addition to you communicating with the Gerrit
web interface and you communicating with the OpenID provider's web
interface.
> so you do not have to consider this part in t
Hi,
Bao, Zheng wrote:
> I tried to change my username for accessing the repository.
I do not think that your username can be changed in the web
interface, but maybe Patrick can help if you send him an email
directly, with the new username you would like to have.
//Peter
--
coreboot mailing li
Alp Eren Köse wrote:
> > > But unfortunately I needed a windoz machine to extract the CMC binary,
> > > you can use the CBROM utility like this:
> > > C:\> CBROM32_195.EXE vendor_bios.bin /TOPHOLE:FFFD extract
> > I'd say you can do the same with dd(1), no?
> >
> Oh yes of course, that's very l
Toki Tahmid wrote:
> I'm interested in knowing if my Intel D865PERL board is supported
> by coreboot.
No.
//Peter
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Toki Tahmid wrote:
> ... A little more detail, please...?
There's no more to say.. Noone has implemented coreboot for the
board, and the significant components on the board are not otherwise
supported by coreboot.
The components are very old and there exists no public documentation
for them, as i
Hi Nils!
Are you subscribed to the coreboot mailing list? I only got your
email direct, so I guess not. I'm including the list in Cc.
Nils wrote:
> I found a bug in msrtool.
> On AMD Geode GX2 the reading of MSR registers above 0x7FFF gives
> an error.
> For MSR register 0x8000 the error
fivefr...@lavabit.com wrote:
> http://www.asrock.com/mb/overview.asp?model=p4i65gv
>
> 1. My current motherboard:
>
> Vendor: ASRock
> Name: P4i65GV
> CPU: Intel Pentium 4 1.60GHz (Socket 478, Prescott)
> Northbridge: Intel® 865GV
> Southbridge: Intel® ICH5
See previous thread about exact same p
Matias Jose Seco wrote:
> builded on the native laptop through Gentoo installed on USB, from an
> amd64 (march=native) version:
Was your gcc and binutils built with USE=vanilla? If not, it is
completely possible that your toolchain produced a broken image.
I've had this happen with some gcc versio
Denis 'GNUtoo' Carikli wrote:
> it now works better:
> with pci=nocrs the radeon card initialize and kdm+Xorg works somehow
> I've now the screen flickering problem at high resolutions(starting at
> 1024x768, 800x600 is fine).
>
> if the problem can't be fixed, would buying an nvidia nv50 wor
Fred . wrote:
> $ lspci|grep EHCI|cut -f1 -d' '
> 00:1a.7
> 00:1d.7
>
> $ sudo lspci -vs 00:1a.7
> 00:1a.7 USB Controller: Intel Corporation 82801JI (ICH10 Family) USB2
> EHCI Controller #2 (prog-if 20 [EHCI])
> Subsystem: Giga-byte Technology GA-EP45-DS5 Motherboard
> Flags: bus maste
Wolfgang Kamp - datakamp wrote:
> I have attached the coreboot log file.
Attached zip file was 0 bytes. It is possible that the mailing list
is stripping non-text attachments.
Please either save the boot log as a .txt file and attach that
uncompressed (text/plain mimetype) or put it somewhere on
ali hagigat wrote:
> I am working with Pentium III, Intel GMCH, 82815 and Intel ICH2, 82801.
>
> I managed to initialize DRAM controller to recognize the first 640 K
> of the memory correctly in the real mode.
>
> When i switch to the protected mode, CPU writes to the first 64K only.
> Every othe
Kyösti Mälkki wrote:
> Could someone explain the need for five (5) different versions of
> root_complex, which appears to be just a logical container with
> no real hw to control?
No need. People have copypasted without abstracting.
> Could you not have just one drivers/generic/root_complex?
So
Hi,
Mathias Krause wrote:
> Some keyboards take pretty long to respond to a reset command,
I've pushed this to Gerrit.
> Since I was unable to download the git tree (why is it HTTP only,
> btw?)
You can also access the Git repo using SSH. Please do that. You'll
need to create a user in Gerrit
Hi all!
During the 28th Chaos Communication Congress [1] which starts today
there is an unusually high concentration of coreboot developers and
enthusiasts in Berlin, so this is a nice opportunity to have dinner
together, and perhaps chat a bit or two about firmware!
After reviewing the schedule
Peter Stuge wrote:
> 28th Chaos Communication Congress [1]
> fahrplan [2]
> dolores [3]
[1] http://events.ccc.de/congress/2011/wiki/Welcome
[2] http://events.ccc.de/congress/2011/Fahrplan/
[3] http://www.dolores-online.de/index_mitte.html
//Peter
--
coreboot mailing list:
Nils wrote:
> >> Is that a caching problem introduced by tiny bootblock?
> >> What is needed to get it right?
> >Probably MTRRs. With tinybootblock, these are set at slightly
> >different times.
> >GX2 uses Cache-As-RAM, right? That affects MTRRs, too (as CAR is a
> >"special" MTRR setup)
>
> Cor
Hi Brian,
Brian Luckau wrote:
> I have an elf netowrk bootable image for linux that was created
> with mkelfImage. How can I extract the file to view its contents
> (which kernel modules were included in the file, etc. )
The image may or may not include initrd, if yes it will quite likely
be com
Brian Luckau wrote:
> root@admin cache]# readelf -a Compute.ebi
..
> Program Headers:
> Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
> NOTE 0xd4 0x 0x 0x000a4 0x000a4 RWE 0
> LOAD 0x000178 0x0001 0x0001 0x01288 0x0552
Stefan Reinauer wrote:
> > I understand what you're saying, yet I've gotten my hands on two
> > boards with the aforementioned chipsets and a lot of goodies on
> > them, so I thought to give it a go before spending €€€ for an
> > already supported board (which would obviously be much easier)
>
> T
Josh Stump wrote:
> I have a Lenovo T60 Type 8743-GZU. From experience I know that with the
> stock BIOS if I put in 4Gb of RAM I can only utilze 3Gb even with a 64bit
> OS installed. Is this a limitation of the stock BIOS that coreboot can
> overcome or is this simply a chipset limitation and ev
Peter Stuge wrote:
> then run dd if=coreboot.rom of=top64k.bin bs=1 \
> skip=$[sizeof(coreboot.rom) - 0x1] count=64k
Insert one step here:
then run dd if=coreboot.rom bs=1 \
skip=$[sizeof(coreboot.rom) - 0x1] count=64k | hexdump
# and verify that the complete range is filled w
ron minnich wrote:
> >> It's almost certainly impossible to get coreboot going on your T60.
> >
> > I believe Sven's port is working!
>
> on x60, good news. But T60?
Yes, also. Sven is using it on his machine already. It needed some
more work besides the X60, but it works for him.
//Peter
--
ron minnich wrote:
> > Yes, also. Sven is using it on his machine already. It needed some
> > more work besides the X60, but it works for him.
>
> I am in awe of these accomplishments! Geez, I go away for just a
> little while and these great things happen :-)
Sven is doing a great job with the T
Kim C. Callis wrote:
> Is there a way to check under knoppix the specs on the motherboard
> to see if this machine is a viable candidate for coreboot
> replacement?
Start with lspci
//Peter
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Kerry Sheh wrote:
> AGESA F15: AMD family15 AGESA code
..
> 733 files changed, 257251 insertions(+), 0 deletions(-)
A quarter million lines of code. Maybe a new patch bomb record.
//Peter
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Carl-Daniel Hailfinger wrote:
> I'd be really glad if somebody can bring a Thinkpad which has
> working VGA out, preferably at a resolution a beamer can work with.
Yeah, I've mentioned a few times that I will bring one.
//Peter
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http://www.coreboo
Prakash Punnoor wrote:
> Yay, I think I solved this problem.
Nice work!
> - seabios payload: no gfx output, but postcode is F8
Focus on this. What is the serial output from coreboot and SeaBIOS?
> - grub2 payload, coreboot initialized option ROM: infinte reset loop
> (but now "warm start" and
Prakash Punnoor wrote:
> >> - seabios payload: no gfx output, but postcode is F8
> >
> > Focus on this. What is the serial output from coreboot and SeaBIOS?
>
> That's the thing: I don't have a serial port on this mainboard, that's
> why I had to do painful post code debugging...
Maybe you can u
Paul Menzel wrote:
> But not knowing for sure the reasons people stay away from coreboot
> development this is of course just a suggestion and a guess.
I for one think they are good ideas, and I hope that they will be
mentioned during the talk!
//Peter
pgpgHXJGXGgn7.pgp
Description: PGP signat
ali hagigat wrote:
> I have developed the assembly code by myself and I am sure that it is
> OK as I have written a simple code in assembly which initializes RAM,
> serial port and hard disk.
How did you verify that your code works?
//Peter
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coreboot mailing list: coreboot@coreboot.org
http:
ali hagigat wrote:
> I can verify that by the assembly code i have. writing to any
> memory location and reading that. Also I tested it by ram_check()
> in Coreboot. Both are correct.
This is not a very good memory test. Try running memtest86. It should
be possible as long as you have set up seria
ali hagigat wrote:
> I received filo by the Coreboot site, and libpayload was made
> successfully but making filo stops with the following error:
>
> /root/bios/coreboot/payloads/filo> make
> Found Libpayload
> /root/bios/coreboot/payloads/filo/build/libpayload/lib/libpayload.a.
> CC build/
ali hagigat wrote:
> cd payloads/libpayload/
> /root/bios/coreboot/payloads/libpayload> make defconfig
> /root/bios/coreboot/payloads/libpayload> make
> /root/bios/coreboot/payloads/libpayload> make DESTDIR=../filo/build install
> /root/bios/coreboot/payloads/libpayload> cd ../filo
> /root/bios/cor
ali hagigat wrote:
> Stage: loading fallback/coreboot_ram @ 0x10 (180224 bytes), entry @
> 0x10
> Stage: done loading.
> Jumping to image.
..
> When it wants to do a jump inside cbfs_and_run_core(), the processor
> halts some how.
RAM is not initialized correctly.
//Peter
--
coreboot
ali hagigat wrote:
> The managers of this project even do not accept their own mistakes.
> Now FILO can not be compiled and when i report it as the README of the
> filo is saying, the manager emails me and tells me that you are not a
> programmer!!
I'm not a manager. I'm a contributor in an open s
Ivan Shmakov wrote:
> >> I wonder, did anyone try Coreboot and SeaBIOS on Gigabyte's
> >> GA-M52S-S3P?
>
> > The nvidia chipset is the biggest challenge. I don't know how close
> > it is to the nvida support in coreboot.
>
> I seem to be quite lucky in this respect, as I've just found
Hi Tom,
Tom Gundersen wrote:
> I'd like to know if my motherboard is supported, or alternatively if
> there is anything I could do to help it become supported.
..
> CPU: Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz (Type 0, Family 6,
> Model 15, Stepping 11)
This is fine.
> Chipset: Intel P35 /
Hi,
Tom Gundersen wrote:
> On Wed, Feb 8, 2012 at 6:55 PM, Peter Stuge wrote:
> > Expect to spend perhaps a year on reverse engineering the factory BIOS
> > and porting coreboot to the board.
>
> Thanks for the info. I guess that's a bit more than what I would be
>
Kyösti Mälkki wrote:
> I don't recall the following Intel document being advertised on the
> list, at least recently.
>
> http://download.intel.com/design/intarch/papers/323246.pdf
Thanks for the link! Svante's thesis has a bit more detail, and the
Intel doc has references to BWG and MRC which as
Hi Jan,
Jan Berce wrote:
> I have seen your tutorial for gethering information
Where was that exactly?
> I have attached all other files and I hope they will be some help
> to you in your progress.
No, it's just noise, and we should work to change any tutorial that
suggests otherwise. Helpful
green wrote:
> Now I am surprised about the claim on the main page that coreboot
> supports "over 230 different mainboards". That seems to be false...?
Things might work even if they have not been tested. And other things
might need more work before they work. Of course it would be nice to
have m
Oliver Schinagl wrote:
> I was pointed to this one: A25L032-F
> http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085
>
> (There's also a Q version, which I don't think is what I'd want).
Correct. Q is a WSON package which does not fit at all. Make sure you
buy farnell nr. 190
David Hillman wrote:
> It looks like I am missing something to properly initialize memory
> to get correct SPD info. Maybe SMBUS isn't working properly?
I think SMBUS is OK and memory init too. Here's the diff between your
two logs with some comments, but there may be more relevant stuff
than wha
Oliver Schinagl wrote:
> I noticed an intersting hack on the coreboot wiki:
> http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash
>
> It lists a neat trick to double stack two spi flash modules to make
> testing/developping/flashing coreboot easier. However there's no
> schematic or other i
Hi Kostas,
Kostas Gounaris wrote:
> I could not find this model on the supported list,
So your mainboard is not supported.
> but I can see that the chipsets (945PL/IHC7) are! Is it possible to
> support my MB
Sure it is. You need to spend some time on studying coreboot and the
other mainboard
Noé Rubinstein wrote:
> Did you try to "make clean" before re-making with the new gcc?
I recommend rm -rf build instead of make clean. I'm not sure if
make clean will in fact do a complete clean.
In any case we should run make clean or rm -rf build automatically
as part of make crossgcc.
//Pete
Peter Stuge wrote:
> In any case we should run make clean or rm -rf build automatically
> as part of make crossgcc.
The clean-for-update target is a dependency for crossgcc, so the
build dir "should" have been cleaned out. I don't know if it is
complete? Help?
//Peter
--
Christian wrote:
> I currently working on a Igel Thin Client 3210.
> The board is very closer to bcom/winnetp680.
> CN700 northbridge
> VT8237R southbridge
> W83679HF SuperIO
> A try with this tree did not work.
What CPU do you have? Is CN700 usable exclusively with C7? What
generation C7 do you h
Kyösti Mälkki wrote:
> commit bdab48d3f13d117bd1100be616837e6d1dbb55fc
> Author: Kyösti Mälkki
> Date: Mon Mar 5 09:25:12 2012 +0200
>
> Fix address of IDT in real-mode entry
Was this tested not to cause regression?
//Peter
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http://www.cor
Fred . wrote:
> Intel provides a Linux-ready Firmware Kit
This is well-known in the community since many years.
If you want to contribute then please *USE* the software and either
just report results, or even better send fixes for any problems which
are found.
As you know, you can do limited tes
Oliver Schinagl wrote:
> Well My electrical engineering knowledge does not reach as far that I would
> know where to connect what :) I can read a schematic and solder based on
> that, but those pictures from the wiki that I linked,
> http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash has
Oliver Schinagl wrote:
>> I guess whoever made the PCB can publish source and gerbers so that
>> others can order the same board if they want.
> That would be probably the best idea to start with. I've been staring at
> the foto of the pvb for a while, and did notice as you said, only one pin
> i
Oliver Schinagl wrote:
> Pin 1, 'chip select enable' is an inverted? pin. enables and
> disables device operation. When chip select is high, the device is
> de-selected and the serial data pins are at 'high impedance'.
Correct.
> So if I understand all this correctly, the chip can be
> connected
Hi,
Niklas Cholmkvist wrote:
> is there any rss or atom feed for commits or any other
> contributions made on gerrit?
You can get RSS for merged commits via gitweb:
http://review.coreboot.org/gitweb?p=coreboot.git
Links are at the bottom of the page.
It doesn't look like Gerrit has an RSS feed
HighlyCaffeinated wrote:
> unable to build with the crossgcc toolchain.
> I sidestepped by loading 10.10 on an unused machine (which appears
> to have been successful), but thought it should be mentioned. Logs
> available for the interested parties.
Yes, logs are neccessary for any action to be ta
Carl-Daniel Hailfinger wrote:
> Tools which would help developers, usable .. with current hardware.
I think the best way is to put them on the Talk:GSoC wiki page. Ie.
not on the GSoC page itself, but on the discussion page for that
page.
> - Flash ICE device with SPI support.
> - Flash ICE devi
Hi Svetoslav,
Svetoslav Trochev wrote:
> I know the theory how those things are working, but I have zero
> experience. Do you think I can be useful even if it is outside the
> GSoC program?
For sure you can. And right now it's still only March, so if you have
spent some time on these things you m
Marc Jones wrote:
> coreboot was not selected to participate in GSoC 2012. This is
> disappointing new for the project. I do not know why we were not
> selected this year. I will attend the post selection meeting to see
> what we can do to improve our chances of selection next year.
I'd love to he
Oliver Schinagl wrote:
> I've attached a more or less 'complete' render
Please just send the .pcb so that I can open it. Also, the schematic
is not very clear.
//Peter
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HighlyCaffeinated wrote:
> One thing I have noticed - at least on my board - is that I cannot
> flash the ROM when I have booted from Coreboot.
Please send flashrom -V output.
//Peter
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Oliver Schinagl wrote:
> I just received this in my wrong inbox and after going through the mail
> headers I found why:
>
> X-Amavis-Alert: BAD HEADER SECTION, Non-encoded 8-bit data (char C3 hex):
> From: Ky\303\266sti M\303\244lkki (k[...]
>
> Is this something wrong in gerrit's setup and
Georgi, Patrick wrote:
> Errors in mails to the list aren't gerrit's fault, but mine.
Oh! I thought the hook was from gerrit. Then it may be easy to fix!
//Peter
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ali hagigat wrote:
> Besides I checked RAM by ramcheck() function of Coreboot.
This means nothing.
> I will test it finally by memtest().
Do two instances of testing, one with memtest86, one with memtest86+.
> But i am believing that the problem is some where else.
Yes this is obvious to eve
HighlyCaffeinated wrote:
> Two files attached. In fromregboot.txt the machine was booted to
> the factory BIOS, the chips swapped, and flashrom-V executed. The
> second fromcoreboot.txt was booted from Coreboot and the same
> command run.
Thanks! In both cases the flash chip is detected correctly
Jonathan Bennett wrote:
> cpuSetAMDMSR FIXME! CPU Version unknown or not supported!
That's pretty clear. I suggest to boot with factory BIOS, check the
exact parameters of the CPU, look at the code which is being run, and
look for relevant documentation for your CPU in the scope of that
code.
If
Stefan Reinauer wrote:
> ... and always include IP checksumming in romstage.
> It's generally useful and our upcoming port needs it.
I don't know.. Why add code which in most cases isn't being used.
We've created a fairly elaborate and powerful build system
specifically to avoid this, and
Oliver Schinagl wrote:
> Unfortunately I have had little feedback so far. But here's a small
> update.
Thanks for the update.
I did look at your previous board but needed more time to really look
closely.
> I have finally received my SO8 memory modules and those babies are
> small.
Oh it's not
Paul Geraedts wrote:
> My hardware target is the Papilio platform in general [1];
I have one as well, can try to help test.
> All current Papilio implementations (to which I count the OLS) rely
> on UART over USB.
They rely on UART, not USB. FPGA on OLS as well as Papilio has no
idea that there
Paul Geraedts wrote:
> > The OLS is not a good fit for installation into e.g. a laptop. This
> > is one of the use cases for a QiProg; it's intended to be soldered
> > into the target system, on top of, or very near, the flash chip.
>
> Can you please post a reference to this QiProg device? I woul
Paul Geraedts wrote:
> My hardware target is the Papilio platform in general
For the SPI flash emulator, suggest use IS61WV20488BLL-10TLI.
//Peter
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Kiran Patil wrote:
> To make this project true "Open Compute Project", this Coreboot
> BIOS software on Motherboard is essential.
>
> I request you to consider using Coreboot (www.coreboot.org) as BIOS
> for Server and Storage motherboards used in Open Compute Project.
Note that BIOS refers to a
Stefan Reinauer wrote:
> Fill out ChromeOS specific coreboot table extensions
>
> ChromeOS uses two extensions to the coreboot table:
> - ChromeOS specific GPIO description for onboard switches
> - position of verified boot area in nvram
..
> +++ b/src/include/boot/coreboot_tab
ron minnich wrote:
> > Maybe it should be made clear also in the names that these tags are
> > chromeos specific?
>
> I don't think we should. I am hoping that some other vendor will
> figure out how neat these things are and use them too.
It's good to collaborate on design rather than just run w
Paul Geraedts wrote:
> >> I will try to make my VHDL cores so they will be compatible with
> >> both types of boards. I plan to start with UART over USB support
> >> for the currently available Papilio boards.
> >
> > UART is stoneage idiotic useless. It's 2012, so please aim higher.
>
> Yet anoth
Hi,
Thanks for your effort on the code!
Stefan Reinauer wrote:
> commit 1c810f17a1a3e9c5433e9eee4a18175d64698be2
> Author: Stefan Reinauer
> Date: Tue Apr 3 16:17:11 2012 -0700
>
> Fixes and Sandybridge support for lapic cpu init
>
> - preprocessor macros should not use defined(CONFI
ron minnich wrote:
> What I'm thinking to do is submit a commit for this tool in its
> nascent state and let people take a look. Or, share the code, which
> may be better.
I think it's a good approach. I would like having separate
repositories for our tools, but for now adding one more is
not maki
Ken Phillis Jr wrote:
> Just another board support request...
This is not really something compatible with the coreboot community
development model. If you need the board supported you have to do it
yourself.
//Peter
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Luc Verhaegen wrote:
> > the following patch was just integrated into master:
> >
> > Add the memory reference code binary for sandybridge chipsets
> >
> > Reviewed-By: Peter Stuge at Mon Apr 16 01:12:57 2012,
> > giving +2
>
> ?
For the first
Hi.
xdrudis wrote:
> Sorry for the rant, it's not aimed at any particular person,
> just to blobs which I don't think should get into coreboot.
I'm afraid you seem quite disconnected from the reality of PC
firmware in the industry. If you haven't already read Svante's
thesis on the topic then I
Paul Menzel wrote:
> Where the flash chips are given away, at the coreboot or
> Flashrom booth or at the sponsor’s booth does not matter
> much.
Note there will not be a flashrom booth at LinuxTag this year. We'll
of course try to answer flashrom questions in the coreboot booth as
best we can! :)
Luc Verhaegen wrote:
> > I still believe that we the coreboot community can create more
> > innovative init code, as we have done for a decade already, but
> > someone has to do it. So far I don't know of significant effort to
> > create Sandy Bridge/Ivy Bridge memory controller init, but if one
>
ake a SVN diff patch.
Looks good!
> > signed-off-by : Bingxun Shi <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
> Index: winbond.c
> ===
> --- winbond.c (Revision 3051)
> +++ winbond.c (Arbeitsk
On Fri, Jan 18, 2008 at 04:08:58PM +0100, [EMAIL PROTECTED] wrote:
> -See http://snapshots.linuxbios.org/
> +See http://tracker.coreboot.org/
snapshots in the tracker?
> -unsigned long write_linuxbios_table(
> +unsigned long write_coreboot_table(
Really?
> - /* Create cm
On Fri, Jan 18, 2008 at 05:31:45PM +0100, Stefan Reinauer wrote:
> I will also update v3. Not sure whether we should touch v1 in this
> way?
I think v1 should be completely unchanged. It's neither active nor
supported so I don't think it should have the current name.
//Peter
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