Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH v7 2/2] drm: rcar-du: Add RZ/G2L DSI driver
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Fri, Sep 16, 2022 at 09:48:07AM +0100, Biju Das wrote:
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC.
> It
> > current
Since qxl_io_reset(qdev) will be called immediately
after qxl_ring_create() been called,
and parameter like notify_on_prod will be set to default value.
So the call to qxl_ring_init_hdr() before becomes meaningless.
Signed-off-by: Zongmin Zhou
Suggested-by: Ming Xie
---
drivers/gpu/drm/qxl/qxl_cm
From: ye xingchen
Return the value ttm_pool_alloc() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
---
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/
On Tue, 20 Sep 2022, William Tseng wrote:
> This is a workaround for HDMI 1.4 sink which has a CEA mode with higher vic
> than what is defined in CEA-861-D.
>
> As an example, a HDMI 1.4 sink has the video format 2560x1080p to be
> displayed and the video format is indicated by both SVD (with vic
From: ye xingchen
Return the value atomctrl_initialize_mc_reg_table_v2_2() directly instead
of storing it in another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
---
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c | 4 +---
1 file changed, 1 insertion(+),
From: ye xingchen
Return the value append_vbios_pptable() directly instead of storing it in
another redundant variable.
Reported-by: Zeal Robot
Signed-off-by: ye xingchen
---
.../gpu/drm/amd/pm/powerplay/hwmgr/vega12_processpptables.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
This is a workaround for HDMI 1.4 sink which has a CEA mode with higher vic
than what is defined in CEA-861-D.
As an example, a HDMI 1.4 sink has the video format 2560x1080p to be
displayed and the video format is indicated by both SVD (with vic 90 and
picture aspect ratio 64:27) and DTD. When co
From: Minghao Chi
The implementation of strscpy() is more robust and safer.
That's now the recommended way to copy NUL terminated strings.
Signed-off-by: Minghao Chi
---
v1->v2
using DRIVER_NAME instead of "DW-HDMI".
drivers/gpu/drm/bridge/synopsys/dw-hdmi-ahb-audio.c | 6 +++---
1 file chang
kernel-doc warns that a function name in a comment does not match the
code's function name, so correct that.
../drivers/gpu/drm/drm_atomic_helper.c:802: warning: expecting prototype for
drm_atomic_helper_check_wb_connector_state(). Prototype was for
drm_atomic_helper_check_wb_encoder_state() ins
Hi Luis,
On Mon, 9 May 2022 13:38:28 -0700
Luis Chamberlain wrote:
> On Mon, May 09, 2022 at 06:23:35PM +0200, Mauro Carvalho Chehab wrote:
> > Currently, kernel/module annotates module dependencies when
> > request_symbol is used, but it doesn't cover more complex inter-driver
> > dependencies
Hi CK,
We can use [1] in mt8186. Please ignore this PATCH.
Thanks,
Allen
[1]
http://lists.infradead.org/pipermail/linux-mediatek/2022-August/046713.html
On 9/19/22 11:01, Allen-KH Cheng wrote:
> Hi CK,
>
> We will test this fix on the mt8186/mt8183.
> Maybe our fix is not necessary.
>
> I app
On Mon, 19 Sep 2022 05:13:18 -0700, Jani Nikula wrote:
>
> On Mon, 19 Sep 2022, Badal Nilawar wrote:
> > For MTL SAMedia updated relevant functions and places in the code to get
> > Media C6 residency.
> >
> > v2: Fixed review comments (Ashutosh)
> >
> > Cc: Vinay Belgaumkar
> > Cc: Ashutosh Dixi
Thanks, the patch applied against 6.0-rc6 kernel worked and the amdgpu module
loaded and works on my Radeon R7 250 (Cape Verde) GPU.
Arthur Marsh.
On 20 September 2022 2:03:54 am ACST, Alex Deucher
wrote:
>On Sun, Sep 18, 2022 at 8:09 AM root wrote:
>>
>> Hi, I recently experienced lock-ups
Please run this patch through checkpatch.pl, as it shows
12 warnings with it. Use these command line options:
"--strict --show-types".
Inlined:
On 2022-09-13 16:40, Andrey Grodzovsky wrote:
> Given many entities competing for same run queue on
> the same scheduler and unacceptably long wait time
On Mon, Sep 19, 2022 at 1:43 PM Isabella Basso wrote:
> >> +* "(K)TAP version XX" should be the first line on all (sub)tests
> >> as per
> >> +*
> >> https://www.kernel.org/doc/html/latest/dev-tools/ktap.html#version-lines
> >> +* but actually isn't, as it currently depen
On Fri, Sep 16, 2022 at 01:48:23PM -0700, Ashutosh Dixit wrote:
> From: Chris Wilson
>
> If attempting to perform a GT reset takes long than 5 seconds (including
> resetting the display for gen3/4), then we declare all hope lost and
> discard all user work and wedge the device to prevent further
Hi!
Unfortunately the use-after-free issue still happens on the 6.0-rc5 kernel.
The issue became hard to repeat. I spent the whole day at the computer
when use-after-free again happened, I was playing the game Tiny Tina's
Wonderlands.
Therefore, forget about repeatability. It remains only to hope f
Hi Tom
On 9/19/22 14:27, Tom Rix wrote:
> There are several copies of CalculateRemoteSurfaceFlipDelay.
> Reduce to one instance.
>
> Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
Just a minor comment below.
> ---
> .../dc/dml/dcn20/display_mode_vba_20.c| 4 +-
> .../dc/dml/dcn20/
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4c9ca5b1597e3222177ba2a94658f78fa5ef4f58 Add linux-next specific
files for 20220919
Error/Warning reports:
https://lore.kernel.org/linux-doc/202209200314.tchs7q2y-...@intel.com
https
Hi Tom,
On 9/18/22 23:37, Tom Rix wrote:
> There are several copies of CalculateTwait.
> Reduce to one instance and change local variable name to match common usage.
>
> Signed-off-by: Tom Rix
Reviewed-by: Maíra Canal
Although, it would be nice to put this function on the
display_mode_vba.h f
Hi Tom
Nice to see this patch coming to the DML! Some small nits inline.
On 9/17/22 15:37, Tom Rix wrote:
> Mimimize the function signature by passing a pointer and an index instead
> of passing several elements of the pointer.
>
> The dml2x,dml3x families uses the same algorithm. Remove the du
On Mon, Sep 19, 2022 at 03:46:47PM -0700, Matt Roper wrote:
> On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> > Updated the CAGF functions to get actual resolved frequency of
> > 3D and SAMedia
> >
> > Bspec: 66300
> >
> > Cc: Vinay Belgaumkar
> > Cc: Ashutosh Dixit
> > Signed-
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> Updated the CAGF functions to get actual resolved frequency of
> 3D and SAMedia
>
> Bspec: 66300
>
> Cc: Vinay Belgaumkar
> Cc: Ashutosh Dixit
> Signed-off-by: Badal Nilawar
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++
> -Original Message-
> From: Sean Anderson
> Sent: Monday, September 19, 2022 5:24 PM
> To: Oleksij Rempel ; Pengutronix Kernel Team
> ; linux-...@vger.kernel.org; linux-arm-kernel
> ; Vinod Koul ;
> dmaeng...@vger.kernel.org
> Cc: Sumit Semwal ; Christian König
> ; Linux Kernel Mailing
MTL once again changes the multicast register types and steering
details. Key changes from past platforms:
* The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
according to the MTL subplatform and cannot be read from fuse
registers.
* The MCR steering register (and its b
On Xe_HP the fault registers are now in a multicast register range.
However as part of the GAM these registers follow special rules and we
need only read from the "primary" GAM's instance to get the information
we need. So a single intel_gt_mcr_read_any() (which will automatically
steer to the pri
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
he
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 4
Rather than using the same _MMIO() macro to define MCR registers as
singleton registers, let's use a new MCR_REG() macro to make it clear
that these registers are special and should be handled accordingly. For
now MCR_REG() will still generate an i915_reg_t with the given offset,
but we'll change
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper
---
drivers/gpu
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 424 +++---
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 259 insertions(+), 169 deletions(-)
di
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give u
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by: Matt Roper
---
Starting in Xe_HP, several registers our driver works with have been
converted from singleton registers into replicated registers with
multicast behavior. Although the registers are still located at the
same MMIO offsets as on previous platforms, let's duplicate the register
definitions in prepara
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered). There are some registers that transitioned from
singleton behavior to multicast during the gen7 -> gen8 transition;
let's duplicate the reg
We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond. In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix
On Fri, Sep 16, 2022 at 11:18 AM Jagan Teki wrote:
>
> This series supports common bridge support for Samsung MIPI DSIM
> which is used in Exynos and i.MX8MM SoC's.
>
> Previous v4 can be available here [1], repo on linux-next [2] and
> Engicam i.Core MX8M Mini SoM boot log [3].
>
> The final brid
On Fri, Sep 16, 2022 at 02:17:30PM -0700, Jeff Johnson wrote:
> On 9/16/2022 1:00 PM, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > The DisplayPort controller's hot-plug mechanism is based on pinmuxing a
> > physical signal no a GPIO pin into the controller. This is not always
>
> nit
On Sat, Sep 17, 2022 at 06:03:27PM +0100, Krzysztof Kozlowski wrote:
> On 16/09/2022 21:00, Bjorn Andersson wrote:
> > From: Bjorn Andersson
> >
> > Add compatibles for the DisplayPort and Embedded DisplayPort blocks in
> > Qualcomm SDM845 and SC8280XP platforms.
> >
> > Signed-off-by: Bjorn And
On Sun, Sep 18, 2022 at 11:36 PM Dan Carpenter wrote:
>
> The ->ring_idx_mask variable is a u64 so static checkers, Smatch in
> this case, complain if the BIT() is not also a u64.
>
> drivers/gpu/drm/virtio/virtgpu_ioctl.c:50 virtio_gpu_fence_event_create()
> warn: should '(1 << ring_idx)' be a 64
Hi, Janusz,
> Am 09/09/2022 um 12:18 PM schrieb Janusz Krzysztofik
> :
>
> Hi Isabella,
>
> On Monday, 29 August 2022 02:09:19 CEST Isabella Basso wrote:
>> This adds functions for both executing the tests as well as parsing (K)TAP
>> kmsg output, as per the KTAP spec [1].
>>
>> [1] https://ww
Hi, David
> Am 01/09/2022 um 3:37 AM schrieb 'David Gow' via KUnit Development
> :
>
> On Mon, Aug 29, 2022 at 8:10 AM Isabella Basso wrote:
>>
>> This adds functions for both executing the tests as well as parsing (K)TAP
>> kmsg output, as per the KTAP spec [1].
>>
>> [1] https://www.kernel.
On 9/19/22 15:43, Maxime Ripard wrote:
Hi,
Hello Maxime,
On Sun, Sep 18, 2022 at 02:56:00PM +0200, Marek Vasut wrote:
On 8/1/22 15:11, Marek Vasut wrote:
Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and
adjust DSI input frequency calculations such that they expect t
There are several copies of CalculateRemoteSurfaceFlipDelay.
Reduce to one instance.
Signed-off-by: Tom Rix
---
.../dc/dml/dcn20/display_mode_vba_20.c| 4 +-
.../dc/dml/dcn20/display_mode_vba_20v2.c | 40 +--
.../dc/dml/dcn21/display_mode_vba_21.c| 40 +-
On 19-09-2022 22:19, Andi Shyti wrote:
Hi Badal,
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia
can you please use the imperative form? "Update" and not
"Updated".
Ok.
Besides I don't really un
Hi Nathan,
Thank you for the patch.
On Tue, Sep 13, 2022 at 01:56:00PM -0700, Nathan Huckleberry wrote:
> The mode_valid field in drm_connector_helper_funcs is expected to be of
> type
> enum drm_mode_status (* mode_valid) (struct drm_connector *connector,
> s
Add HDMI audio support for mt8195
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
index 39e07a6dd490..bb7593ea4c86 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8
Add the DPI1 hdmi path support in mtk dpi driver
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 630a4e301ef6..91212b7610e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -15
Add a flag to indicate support for frame colorimetry.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 30407603d693..9fe086e2cd7c 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/
Some phys, such as mt8195, needs to have a configure callback defined.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c
b/drivers/phy/mediatek/phy-mtk-hdmi.c
index d4bd419abc3c..af46472237e0 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/medi
Add dpi support to enable the HDMI path.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 72049a530ae1..27f029ca760b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.
In order to share register with a dedicated ddc driver, set the hdmi
compatible to syscon.
Signed-off-by: Guillaume Ranquet
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
index abb231a06
Add a flag to indicate support for cec.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index bfcca6f8b839..86653ebaacfd 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/m
Adds hdmi and hdmi-ddc support for mt8195.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index 008ec69da67b..f1ef6c8ae2b8 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -24,6 +24,8 @
Add basic support for the mediatek hdmi phy on MT8195 SoC
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
index bb7593ea4c86..0157acdce56c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8195_hdmi.c
+++ b/drivers/
Create a common "framework" that can be used to add support for
different hdmi IPs within the mediatek range of products.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index d4d193f60271..008ec69da67b 100644
--- a/drivers/gpu
Add dt-binding documentation of dpi for MediaTek MT8195 SoC.
Signed-off-by: Guillaume Ranquet
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 5bb23e97cf33..2c7ecef54986 100644
--- a/D
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, move to a syscon.
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c
b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 3196189429bc..5cd05d4fe1a9 100644
--- a/drivers/
Add mt8195 SoC bindings for hdmi and hdmi-ddc
Make port1 optional for mt8195 as it only supports HDMI tx for now.
Requires a ddc-i2c-bus phandle.
Requires a power-domains phandle.
Signed-off-by: Guillaume Ranquet
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yam
Add a compatible for the HDMI PHY on MT8195
Signed-off-by: Guillaume Ranquet
diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
index 0d94950b84ca..71c75a11e189 100644
--- a/Documentation/devicetree/bindings/p
Add a flag to indicate support for an external connector
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 86653ebaacfd..30407603d693 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/g
From: Pablo Sun
Add the clock gate definition for the DPI1 hardware
in VDOSYS1.
The parent clock "hdmi_txpll" is already defined in
`mt8195.dtsi`.
Signed-off-by: Pablo Sun
Signed-off-by: Guillaume Ranquet
diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c
b/drivers/clk/mediatek/clk-mt8195-
From: Pablo Sun
Expand dt-bindings slot for VDOSYS1 of MT8195.
This clock is required by the DPI1 hardware
and is a downstream of the HDMI pixel clock.
Signed-off-by: Pablo Sun
Signed-off-by: Guillaume Ranquet
Reviewed-by: Mattijs Korpershoek
diff --git a/include/dt-bindings/clock/mt8195-clk
and the dpi/drm_drv adjustements to
support hdmi.
Based on next-20220919
Signed-off-by: Guillaume Ranquet
---
Guillaume Ranquet (15):
dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible
dt-bindings: display: mediatek: add MT8195 hdmi bindings
drm/mediatek: hdmi: use a sysc
Hi Biju,
Thank you for the patch.
On Fri, Sep 16, 2022 at 09:48:07AM +0100, Biju Das wrote:
> This driver supports the MIPI DSI encoder found in the RZ/G2L
> SoC. It currently supports DSI video mode only.
>
> Signed-off-by: Biju Das
> Acked-by: Sam Ravnborg
> ---
> v6->v7:
> * Added rzg2l_mi
Hi Badal,
On Mon, Sep 19, 2022 at 05:29:05PM +0530, Badal Nilawar wrote:
> Updated the CAGF functions to get actual resolved frequency of
> 3D and SAMedia
can you please use the imperative form? "Update" and not
"Updated".
Besides I don't really understand what you did from the
commit, can you p
On Sun, Sep 18, 2022 at 8:09 AM root wrote:
>
> Hi, I recently experienced lock-ups that only responded to magic sysreq
> reboots when the amdgpu module was loading on my pc (Athlon II X4 640 CPU,
> with Radeon R7 250 - Cape Verde).
>
> .config has:
>
> CONFIG_DRM_AMDGPU=m
> CONFIG_DRM_AMDGPU_SI=y
[AMD Official Use Only - General]
> I think the proper fix is to set it to:
> build_coefficients(&coeff, TRANSFER_FUNCTION_SRGB);
I agree, default arg should be TRANSFER_FUNCTION_SRGB.
Even though it's a change in behaviour, previous behaviour was wrong.
Ideally it would be based on input TF, but
On Mon, Sep 19, 2022 at 2:44 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 06.09.22 um 21:57 schrieb Hamza Mahfooz:
> > Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use
> > drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs
> > struct.
>
> drm_atomic_helper_dirtyfb()
Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for
Gen11+. Therefore ensure perf_limit_reasons sysfs/debugfs files are created
only for Gen11+. Otherwise on Gen < 5 accessing these files results in the
following oops:
<1> [88.829420] BUG: unable to handle page fault for address:
Pushed, Thanks!
Andi
On Fri, Sep 16, 2022 at 11:24:01AM +0200, Janusz Krzysztofik wrote:
> i915_perf assumes that it can use the i915_gem_context reference to
> protect its i915->gem.contexts.list iteration. However, this requires
> that we do not remove the context from the list until after we d
Add the relevant AMD developers to comment.
On Mon, Sep 19, 2022 at 12:05 PM Alex Deucher wrote:
>
> On Mon, Sep 19, 2022 at 3:19 AM Zeng Heng wrote:
> >
> > Fix below compile warning when open enum-conversion
> > option check:
> >
> > drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_ga
On Mon, Sep 19, 2022 at 3:19 AM Zeng Heng wrote:
>
> Fix below compile warning when open enum-conversion
> option check:
>
> drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:
> In function ‘apply_degamma_for_user_regamma’:
> drivers/gpu/drm/amd/amdgpu/../display/modules/color/colo
On Mon, Sep 19, 2022 at 06:29:41PM +0300, Laurent Pinchart wrote:
> On Sun, Jul 17, 2022 at 07:44:49PM +0200, Sam Ravnborg wrote:
> > When atomic_check() is defined, then mode_fixup() is ignored,
> > so it had no effect that drm_bridge_funcs.mode_fixup was assigned.
> > Embed the original implement
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:58:00PM +0200, Sam Ravnborg wrote:
> All users are converted over to drm_bridge_funcs.atomic_check()
> so it is safe to drop the mode_fixup support.
>
> Update the comment for atomic_check with relevant parts from mode_fixup.
>
> Signe
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:59PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default im
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:58PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
> The driver implements the state operations, so no other changes
> are required for the replacement.
>
>
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:57:57PM +0200, Sam Ravnborg wrote:
> The implementation of drm_bridge_funcs.mode_fixup is optional
> so there is no need to provide an empty implementation.
> Drop mtk_hdmi_bridge_mode_fixup() so the driver no longer uses the
> deprecate
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:49PM +0200, Sam Ravnborg wrote:
> When atomic_check() is defined, then mode_fixup() is ignored,
> so it had no effect that drm_bridge_funcs.mode_fixup was assigned.
> Embed the original implementation in the caller and drop the functi
> -Original Message-
> From: Das, Nirmoy
> Sent: Monday, September 19, 2022 8:33 PM
> To: intel-...@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Auld, Matthew
> ; Gupta, Anshuman
> Subject: [PATCH] drm/i915: Do not dereference NULL bo->resource
>
> bo->resource could b
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:48PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default im
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:47PM +0200, Sam Ravnborg wrote:
> Replace the deprecated drm_bridge_funcs.mode_fixup() with
> drm_bridge_funcs.atomic_check().
>
> drm_bridge_funcs.atomic_check() requires the atomic state operations,
> update these to the default im
On 15/09/2022 17:03, Thomas Zimmermann wrote:
G200ER does not seem to support 24 bpp, so force the console to
use 32 bpp. The problem was introduced, when commit 73f54d5d9682
("drm/mgag200: Remove special case for G200SE with <2 MiB") changed
the preferred color depth from 32 bit to 24 bit.
A se
On 9/7/22 2:24 PM, Matt Roper wrote:
Intel hardware allows some preemption settings to be controlled either
by the kernel-mode driver exclusively, or placed under control of the
user-mode drivers; on Linux we always select the userspace control
option. The various registers involved in this a
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:46PM +0200, Sam Ravnborg wrote:
> There are no users left of drm_bridge_chain_mode_fixup() and we
> do not want to have this function available, so drop it.
>
> Signed-off-by: Sam Ravnborg
> Reviewed-by: Maxime Ripard
> Cc: Laurent
On 2022-09-14 15:26, Anup K Parikh wrote:
On Wed, Sep 14, 2022 at 10:24:36AM -0400, Andrey Grodzovsky wrote:
On 2022-09-14 06:36, Anup K Parikh wrote:
Fix two warnings during doc build which also results in corresponding
additions in generated docs
Warnings Fixed:
1. include/drm/gpu_schedule
Hi Sam,
Thank you for the patch.
On Sun, Jul 17, 2022 at 07:44:45PM +0200, Sam Ravnborg wrote:
> The mode_valid implementation had a call to
> drm_bridge_chain_mode_fixup() which would be wrong as the mode_valid is
> not allowed to change anything - only to validate the mode.
>
> As the next bri
Hi Sam,
Thank you for the patch, and sorry for the review delay. The series only
recently jumped to the top of my inbox.
On Sun, Jul 17, 2022 at 07:44:43PM +0200, Sam Ravnborg wrote:
> The atomic variants of enable/disable in drm_bridge_funcs are the
> preferred operations - introduce these.
>
>
bo->resource could be NULL hence add a NULL check for
bo->resource before dereferencing it.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/6850
Fixes: ad74457a6b5a96 ("drm/i915/dgfx: Release mmap on rpm suspend")
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.
Hi Thomas,
On Fri, Sep 16, 2022 at 01:31:25PM +0200, Thomas Zimmermann wrote:
> Am 16.09.22 um 13:06 schrieb Laurent Pinchart:
> > On Fri, Sep 09, 2022 at 12:59:45PM +0200, Thomas Zimmermann wrote:
> >> Provide drm_univeral_plane_alloc(), which allocated an initializes a
> >> plane. Code for non-a
Hi Geert,
On Mon, Sep 19, 2022 at 09:58:01AM +0200, Geert Uytterhoeven wrote:
> Hi Stephen,
>
> On Mon, Sep 19, 2022 at 3:07 AM Stephen Rothwell
> wrote:
> > Today's linux-next merge of the drm tree got a conflict in:
> >
> > drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
> >
Hi,
On Sun, Sep 18, 2022 at 02:56:00PM +0200, Marek Vasut wrote:
> On 8/1/22 15:11, Marek Vasut wrote:
> > Fill in hs_rate and lp_rate to struct mipi_dsi_device for this bridge and
> > adjust DSI input frequency calculations such that they expect the DSI host
> > to configure HS clock according to
The Nanote UMPC-01 is a mini laptop with a 1200x1920 portrait screen
mounted in a landscape oriented clamshell case. Add a quirk for this.
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/drm
Il 19/09/22 10:40, Hsin-Yi Wang ha scritto:
On Mon, Sep 19, 2022 at 4:39 PM Nícolas F. R. A. Prado
wrote:
As the comment right before the mtk_dsi_stop() call advises,
mtk_dsi_stop() should only be called after
mtk_drm_crtc_atomic_disable(). That's because that function calls
drm_crtc_wait_one_
On Mon, 19 Sept 2022 at 12:48, Laurent Pinchart
wrote:
>
> Hi Rob,
>
> Thank you for the patch.
>
> On Mon, Sep 19, 2022 at 12:20:09PM +0200, Robert Foss wrote:
> > Revert this patch since it depends on devicetree functionality that
> > previously has been reverted in the below commit.
> >
> > com
On Mon, Sep 19, 2022 at 8:06 AM Christian König
wrote:
>
> That check must now come after grabing the spinlock, not before.
>
> Signed-off-by: Christian König
> Fixes: b96fb1e724ae ("dma-buf: dma_fence_wait must enable signaling")
Acked-by: Alex Deucher
> ---
> drivers/dma-buf/dma-fence.c | 6
Add register constants for the framebuffer scanout addresses and
update the related helper functions. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 28
drivers/gpu/drm/udl/udl_proto.h | 8
2 files changed,
Add constants for the various commands that the driver can send to
the device and update the respective helper functions. No functional
changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_drv.h | 10 --
drivers/gpu/drm/udl/udl_modeset.c | 16 +---
driv
Add constants for the registers the contain various display-mode
parameters and update the mode-setting function. No functional
changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/udl/udl_modeset.c | 102 ++
drivers/gpu/drm/udl/udl_proto.h | 15 +
2 f
Add drm_dev_enter() and drm_dev_exit() to the various modesetting
functions that interact with the device. After hot-unplugging the
device, these functions will return early. So far, the udl driver
relied on USB interfaces to handle unplugging of the device.
Signed-off-by: Thomas Zimmermann
---
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