Add support for DisplayPort to the bridge, which entails the following:
- Get and use an interrupt for HPD;
- Properly clear all status bits in the interrupt handler;
Signed-off-by: John Ripple
---
V1 -> V2: Cleaned up coding style and addressed review comments
V2 -> V3:
- Removed unused HPD IRQs
The AM62x SoC features 2 OLDI TXes each, which makes it possible to
connect them in dual-link or cloned single-link OLDI display modes. This
series enables OLDI support on AM62X[1].
[1]: https://www.ti.com/product/AM625
Aradhya Bhatia (2):
arm64: dts: ti: k3-am62: Add support for AM625 OLDI IO
From: Aradhya Bhatia
Add TI DSS OLDI-IO control registers for AM625 DSS. This is a region of
12 32bit registers found in the TI AM625 CTRL_MMR0 register space[0].
They are used to control the characteristics of the OLDI DATA/CLK IO as
needed by the DSS display controller node.
[0]: https://www.t
Documentation/process/deprecated.rst recommends against the use of kmalloc
with dynamic size calculations due to the risk of overflow and smaller
allocation being made than the caller was expecting. This could lead to
buffer overflow in code similar to the memcpy in
amdgpu_dm_plane_add_modifier().
On 9/12/25 3:06 PM, Bagas Sanjaya wrote:
> Commit 6cc44e9618f03f ("drm: Add directive to format code in comment")
> fixes original Sphinx indentation warning as introduced in
> 471920ce25d50b ("drm/gpuvm: Add locking helpers"), by means of using
> code-block:: directive. It semantically conflicts w
From: Boris Brezillon
The new uAPI lets user space query the KM driver for the available
priorities a job can be given at submit time. These are managed through
the notion of a context, for which we also provide new creation and
destruction ioctls.
Reviewed-by: Steven Price
Signed-off-by: Boris
On Tue, Sep 09, 2025 at 09:21:33AM +0200, Neil Armstrong wrote:
> On 08/09/2025 23:24, Dmitry Baryshkov wrote:
> > On Mon, Sep 08, 2025 at 03:04:21PM +0200, Neil Armstrong wrote:
> > > The QMP USB3/DP Combo PHY hosts an USB3 phy and a DP PHY on top
> > > of a combo glue to route either lanes to the
Hi Andre,
Am Donnerstag, dem 04.09.2025 um 00:29 +0100 schrieb Andre Przywara:
> Hi,
>
> the Allwinner A523/A527/T527 family of SoCs feature a Vivante
> "VIP9000"(?) NPU, though it seems to be disabled on many SKUs.
> See https://linux-sunxi.org/A523#Family_of_sun55iw3 for a table, the
> row labe
To support following DisplayPort (DP) mode over the Type-C PHY, rename
USB-specific functions and ops to clearly separate them from common or
DP-related logic.
This is a preparatory cleanup to enable USB + DP dual mode.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Xiangxu Yin
---
drivers/phy/q
Implement DMA heap for protected DMA-buf allocation in the TEE
subsystem.
Protected memory refers to memory buffers behind a hardware enforced
firewall. It is not accessible to the kernel during normal circumstances
but rather only accessible to certain hardware IPs or CPUs executing in
higher or
On 2025-09-11 13:21, Melissa Wen wrote:
> Don't update DC stream color components during atomic check. The driver
> will continue validating the new CRTC color state but will not change DC
> stream color components. The DC stream color state will only be
> programmed at commit time in the `atomi
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The sysirq has "intpol-controller" as node name, but being this an
interrupt controller, it needs to be named "interrupt-controller"
as per what the bindings (correctly) expect.
This commit brings no functional changes, but fixes a dtbs_c
On Thu, Sep 11, 2025 at 10:26:08PM +0900, Alexandre Courbot wrote:
> On Thu Sep 11, 2025 at 9:46 PM JST, Danilo Krummrich wrote:
[..]
> >> By keeping the initialization in the GPU, we can keep the GSP object
> >> architecture-independent, and I think it makes sense from a design point
> >> of view
On Tue, 09 Sep 2025 13:36:23 +
Alice Ryhl wrote:
> Instead of manually deferring cleanup of vm_bos, use the new GPUVM
> infrastructure for doing so.
>
> To avoid manual management of vm_bo refcounts, the panthor_vma_link()
> and panthor_vma_unlink() methods are changed to get and put a vm_bo
MediaTek MT8196 has Mali-G925-Immortalis GPU. panthor drm driver gained
support for it recently.
Signed-off-by: Chia-I Wu
---
v2: update commit message
---
Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetre
Hi,
>As I said, maybe the problem is fixed now, but at the same time there
>is something nice about the interrupt type only being specified in one
>place. ...and IIRC the device tree validator gets upset if you don't
>specify the interrupt type there, so removing it from the source code
>seems ni
On 9/12/25 19:20, David Hildenbrand wrote:
> On 12.09.25 06:49, Balbir Singh wrote:
>> On 9/11/25 22:52, David Hildenbrand wrote:
>>> On 11.09.25 14:49, Balbir Singh wrote:
On 9/11/25 21:45, David Hildenbrand wrote:
> On 08.09.25 02:04, Balbir Singh wrote:
>> Add routines to support al
On Fri, Sep 12, 2025 at 11:38 AM Nicolas Frattaroli
wrote:
> diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.h
> b/drivers/gpu/drm/panthor/panthor_devfreq.h
> index
> a891cb5fdc34636444f141e10f5d45828fc35b51..94c9768d5d038c4ba8516929edb565a1f13443fb
> 100644
> --- a/drivers/gpu/drm/pantho
Agh! Sorry for the spam, I should have double checked the code before writing
this as I realized the reason I didn't implement this. Correct me if I'm wrong
here since it's the first time I've interacted very much with this API in the
kernel but: it seems like the reference counting for dma_buf obj
On 10/09/2025 16:54, Harry Wentland wrote:
On 2025-06-18 11:19, Melissa Wen wrote:
From: Rodrigo Siqueira
As part of the effort of stopping using raw edid, this commit move the
copy of the edid in DC to a dedicated function that will allow the usage
of drm_edid in the next steps.
Signed-o
On Thu, 11 Sep 2025 12:09:54 -0300, Ariel D'Alessandro wrote:
> Currently, users of Mediatek OD (display overdrive) DT bindings set
> mediatek,gce-client-reg node property, which is missing from the DT schema.
>
> For example, device tree arch/arm64/boot/dts/mediatek/mt8173.dtsi is
> causing the
On Fri, Sep 12, 2025 at 02:14:18PM -0400, Frank Li wrote:
> Convert megachips-stdp-ge-b850v3-fw.txt to yaml format.
>
> Additional changes:
> - Only keep one example.
>
> Signed-off-by: Frank Li
> ---
> .../megachips,stdp2690-ge-b850v3-fw.yaml | 105 ++
> .../megachips-
…though, I just realized immediately after sending that response to you that I
mentioned that this type is reference counted in the commit message - but I
never actually added an implementation for AlwaysRefCounted. So, that's at
least one additional thing I will make sure to add. Similarly though,
On Fri, 2025-09-12 at 10:25 +0200, Christian König wrote:
> On 12.09.25 00:57, Lyude Paul wrote:
> > In order to implement the gem export callback, we need a type to represent
> > struct dma_buf. So - this commit introduces a set of stub bindings for
> > dma_buf. These bindings provide a ref-counte
On 9/13/25 04:27, Danilo Krummrich wrote:
On 9/12/25 3:06 PM, Bagas Sanjaya wrote:
Commit 6cc44e9618f03f ("drm: Add directive to format code in comment")
fixes original Sphinx indentation warning as introduced in
471920ce25d50b ("drm/gpuvm: Add locking helpers"), by means of using
code-block:: d
Hello fbdev maintainers/developers,
This is a 31-day syzbot report for the fbdev subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/fbdev
During the period, 2 new issues were detected and 0 were fixed.
In total, 6 issues are still open and 27 have
On Thu, Aug 28, 2025 at 04:01:29PM +0200, Janne Grunau wrote:
> After discussion with the devicetree maintainers we agreed to not extend
> lists with the generic compatible "apple,i2c" anymore [1]. Use
> "apple,t8103-i2c" as fallback compatible as it is the SoC the driver
> and bindings were writte
Hi,
On Fri, Sep 12, 2025 at 12:25 PM John Ripple wrote:
>
> @@ -153,6 +164,8 @@
> * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
> * @comms_enabled: If true then communication over the aux channel is
> enabled.
> * @comms_mutex: Protects modification of comms_en
On Fri, Sep 12, 2025 at 09:57:47PM +0300, Marius Vlad wrote:
> On Fri, Sep 12, 2025 at 05:31:17PM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Sep 11, 2025 at 08:34:48PM +0300, Marius Vlad wrote:
> > > > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > > > b/drivers/gpu/drm/msm/d
On 9/12/25 6:06 AM, Bagas Sanjaya wrote:
> Commit 6cc44e9618f03f ("drm: Add directive to format code in comment")
> fixes original Sphinx indentation warning as introduced in
> 471920ce25d50b ("drm/gpuvm: Add locking helpers"), by means of using
> code-block:: directive. It semantically conflict
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
The display related IPs in MT8183 are flexible and support being
interconnected with different instances of DDP IPs forming a full
Display Data Path that ends with an actual display output, which
is board specific.
Add a common graph in t
When the initial drivers were submitted, some of the timing was hard coded and
did not allow for any MIPI-DSI panel to be attached.
In general, panels or bridges can only be supported if MIPI-DSI lanes were 4.
If the number of lanes were 3,2,1, the math no longer works out.
A new API was created f
On 9/12/2025 9:43 AM, Colin Ian King wrote:
> There is a spelling mistake in a xe_gt_err error message. Fix it.
>
> Signed-off-by: Colin Ian King
Reviewed-by: Michal Wajdeczko
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Fix the pinctrl node names to adhere to the bindings, as the main
pin node is supposed to be named like "uart0-pins" and the pinmux
node named like "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
.../boot
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
The jpeg decoder main node is under the soc bus but currently has
no ranges or reg specified, while the children do, and this is
wrong in multiple aspects.
The very same is also valid for the jpeg encoder node.
Rename the decoder and enc
On 9/12/2025 4:46 PM, Konrad Dybcio wrote:
> On 9/12/25 4:15 AM, Xiangxu Yin wrote:
>> On 9/12/2025 9:24 AM, Dmitry Baryshkov wrote:
>>> On Thu, Sep 11, 2025 at 10:55:01PM +0800, Xiangxu Yin wrote:
Introduce QCS615 hardware-specific configuration for DP PHY mode,
including register offs
On Fri, Sep 12, 2025 at 05:17:56PM +0200, Maxime Ripard wrote:
> Hi,
Hi Maxime,
>
> On Thu, Sep 11, 2025 at 04:07:33PM +0300, Marius Vlad wrote:
> > diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
> > index 45b42f14a750..74fe925c69a2 100644
> > --- a/drivers/video/hdmi.c
> > +++ b/drivers
Hello,
On Thu, Aug 28, 2025 at 04:01:39PM +0200, Janne Grunau wrote:
> The PWM controller on Apple's M2 Pro/Max SoCs behaves in the same way as
> on previous M1 and M2 SoCs. Add its per SoC compatible.
>
> At the same time fix the order of existing entries. The sort order logic
> is having SoC nu
On Fri, 12 Sep 2025 08:43:30 +0100, Colin Ian King wrote:
> There is a spelling mistake in a xe_gt_err error message. Fix it.
>
>
Merged to drm-xe-next, thanks!
[1/1] drm/xe/guc: Fix spelling mistake "sheduling" -> "scheduling"
commit: 9e0b0fd5311ef68638abcd05306233b367c6b407
--
Lucas De
Add support for DisplayPort to the bridge, which entails the following:
- Get and use an interrupt for HPD;
- Properly clear all status bits in the interrupt handler;
Signed-off-by: John Ripple
---
V1 -> V2: Cleaned up coding style and addressed review comments
V2 -> V3:
- Removed unused HPD IRQs
On Fri, Sep 12, 2025 at 05:31:17PM +0200, Maxime Ripard wrote:
> Hi,
>
> On Thu, Sep 11, 2025 at 08:34:48PM +0300, Marius Vlad wrote:
> > > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > > b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > > index ca400924d4ee..4b87f4f78d38 100644
> > > >
On Thu, Sep 11, 2025 at 04:07:35PM +0300, Marius Vlad wrote:
> This would please the compiler to have a enum transformation from one to
> another even though the values are the same. It should also make things
> obvious that we use different enums.
>
> Signed-off-by: Marius Vlad
> ---
> .../gpu/
Add innolux,n133hse-ea1 13.3" TFT LCD panel and nlt,nl12880bc20-spwg-24
12.1" WXGA (1280 x 800) LVDS TFT LCD panel.
Signed-off-by: Frank Li
---
.../devicetree/bindings/display/panel/panel-simple.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/
The MT8196 SoC uses an embedded MCU to control frequencies and power of
the GPU. This controller is referred to as "GPUEB".
It communicates to the application processor, among other ways, through
a mailbox.
The mailbox exposes one interrupt, which appears to only be fired when a
response is recei
On some devices, devfreq is not controlled directly by DT OPPs and the
common clock framework, but through an external devfreq driver. To
permit this type of usage, add the concept of devfreq providers.
Devfreq providers for panthor register themselves with panthor as a
provider. panthor then gets
On the MediaTek MT8196 SoC, the GPU has its power and frequency
dynamically controlled by an embedded special-purpose MCU. This MCU is
in charge of powering up the GPU silicon. It also provides us with a
list of available OPPs at runtime, and is fully in control of all the
regulator and clock fiddl
The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB",
acting as glue logic to control power and frequency of the Mali GPU.
This MCU runs special-purpose firmware for this use, and the main
application processor communicates with it through a mailbox.
Add a binding that describes
As it stands, panthor keeps a cached current frequency value for when it
wants to retrieve it. This doesn't work well for when things might
switch frequency without panthor's knowledge.
Instead, implement the get_cur_freq operation, and expose it through a
helper function to the rest of panthor.
The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
control the power and frequency of the GPU.
It lets us omit the OPP tables from the device tree, as those can now be
enumerated at runtime from the MCU.
Add the mediatek,mt8196-mali compatible, and a performance-domains
property
Convert megachips-stdp-ge-b850v3-fw.txt to yaml format.
Additional changes:
- Only keep one example.
Signed-off-by: Frank Li
---
.../megachips,stdp2690-ge-b850v3-fw.yaml | 105 ++
.../megachips-stdp-ge-b850v3-fw.txt | 91 ---
2 files changed, 105
On 9/12/25 04:43, Greg KH wrote:
> On Mon, Sep 08, 2025 at 02:01:34PM -0700, Mukesh R wrote:
>> On 9/6/25 04:36, Greg KH wrote:
>>> On Fri, Sep 05, 2025 at 06:09:52PM -0700, Mukesh Rathor wrote:
With CONFIG_HYPERV and CONFIG_HYPERV_VMBUS separated, change CONFIG_HYPERV
to bool from trista
On Fri, Sep 12, 2025 at 08:03:01PM +0800, Xiangxu Yin wrote:
>
> On 9/12/2025 6:32 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 11, 2025 at 10:55:08PM +0800, Xiangxu Yin wrote:
> >> Introduce mutual exclusion between USB and DP PHY modes to prevent
> >> simultaneous activation.
> > Describe the pro
On 11.09.2025 10:30, Steven Price wrote:
> On 10/09/2025 17:50, Boris Brezillon wrote:
> > On Wed, 10 Sep 2025 16:56:43 +0100
> > Steven Price wrote:
> >
> >> On 10/09/2025 16:52, Boris Brezillon wrote:
> >>> On Wed, 10 Sep 2025 16:42:32 +0100
> >>> Steven Price wrote:
> >>>
> > +int panfrost
On Fri, Sep 12, 2025 at 3:59 AM Nicolas Frattaroli
wrote:
>
> On Friday, 12 September 2025 06:48:17 Central European Summer Time Chia-I Wu
> wrote:
> > On Fri, Sep 5, 2025 at 3:24 AM Nicolas Frattaroli
> > wrote:
> > >
> > > The MT8196 SoC uses an embedded MCU to control frequencies and power of
Hi Raphael,
thanks for this patch.
On Thu, Jul 17, 2025 at 09:15:34PM +0200, Raphael Gallais-Pou wrote:
> The display subsystem represent how IPs are interacting together and
> have nothing to do within the SoC node.
>
> Extract it from the SoC node and let IPs nodes in the Soc node.
>
> Severa
On Thu, Sep 11, 2025 at 10:55:04PM +0800, Xiangxu Yin wrote:
> Introduce DisplayPort PHY configuration routines for QCS615, including
> aux channel setup, lane control, voltage swing tuning, clock config and
> calibration. These callbacks are registered via qmp_phy_cfg to enable DP
> mode on USB/DP
On Thu, Sep 11, 2025 at 04:07:36PM +0300, Marius Vlad wrote:
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c
> b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 61cab32e213a..15820e6ba057 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -1057,7 +1057,7
On Fri, Sep 12, 2025 at 04:58:45PM +0800, Damon Ding wrote:
> The analogix_dp_unbind() should be balanced with analogix_dp_bind().
> There are no bridge enabling and panel preparing in analogix_dp_bind(),
> so it should be reasonable to remove the bridge disabing and panel
> unpreparing in analogix
The usefulness of /sys/kernel/debug/dri/bridges is limited as it only shows
bridges between drm_bridge_add() and drm_bridge_remove(). However
refcounted bridges can stay allocated for a long time after
drm_bridge_remove(), and a memory leak due to a missing drm_bridge_put()
would not be visible in
Between drm_bridge_add() and drm_bridge_remove() bridges are registered to
the DRM core via the global bridge_list and visible in
/sys/kernel/debug/dri/bridges. However between drm_bridge_remove() and the
last drm_bridge_put() memory is still allocated even though the bridge is
not registered, i.e.
This series shows removed bridges to the global /dri/bridges file.
Removed bridges are bridges after drm_bridges_remove() but before they are
eventually freed on the last drm_bridge_put().
This is part of the work towards removal of bridges from a still existing
DRM pipeline without use-after-free
Hi,
On Fri, Sep 12, 2025 at 6:07 AM Amirreza Zarrabi
wrote:
>
> This patch series introduces a Trusted Execution Environment (TEE)
> driver for Qualcomm TEE (QTEE). QTEE enables Trusted Applications (TAs)
> and services to run securely. It uses an object-based interface, where
> each service is a
Hi Dave, Simona,
Pull for v6.18, as described below.
The following changes since commit 3cf6147f2b51a569761e1ef010efbd891e3a3a15:
soc: qcom: use no-UBWC config for MSM8956/76 (2025-08-25 14:01:26 -0700)
are available in the Git repository at:
https://gitlab.freedesktop.org/drm/msm.git tags
On Fri, Sep 12, 2025 at 8:48 AM Thorsten Blum wrote:
>
> Hi Alex,
>
> On 9. Sep 2025, at 17:35, Alex Deucher wrote:
> > Applied. Thanks!
> >
> > On Tue, Sep 9, 2025 at 11:29 AM Thorsten Blum
> > wrote:
> >>
> >> Replace kmalloc() followed by copy_from_user() with memdup_user() to
> >> improve a
Hi,
On Thu, Sep 11, 2025 at 08:34:48PM +0300, Marius Vlad wrote:
> > > diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > index ca400924d4ee..4b87f4f78d38 100644
> > > --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> > > +++ b/drivers/gpu/drm/msm/d
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Fix the pinctrl node names to adhere to the bindings, as the main
pin node is supposed to be named like "uart0-pins" and the pinmux
node named like "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
.../medi
Hi,
On Fri, Sep 12, 2025 at 6:11 AM Zhijian Yan
wrote:
>
> Signed-off-by: Zhijian Yan
> ---
> drivers/gpu/drm/panel/panel-edp.c | 1 +
> 1 file changed, 1 insertion(+)
Please provide the EDID in the commit message. See nearly all recent
commits to this file. Thanks!
-Doug
Convert the limited MIPI clock calculations to a full range of settings
based on math including H/W limitation validation.
Since the required DSI division setting must be specified from external
sources before calculations, expose a new API to set it.
Signed-off-by: Chris Brandt
Signed-off-by: hi
Hello Raphael,
Thanks for this patch.
On Thu, Jul 17, 2025 at 09:15:33PM +0200, Raphael Gallais-Pou wrote:
> Enhance the probing sequence by using the ports property of the
> display-subsystem node.
>
> That done, it becomes possible to handle the display-substem node
> outside of the soc node w
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
There is no need to specify #address-cells and #size-cells in a
node that has only one non-addressable subnode, and this is the
case of the flash@0 node in this devicetree, as it has only one
"partitions" subnode.
Remove those to suppress
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Move the VBAT supply to mt8195-cherry-tomato-{r1,r2} as this power
supply is named like that only for the Realtek RT5682i codec.
Signed-off-by: AngeloGioacchino Del Regno
Applied, thanks
---
arch/arm64/boot/dts/mediatek/mt8195-che
On 25/07/2025 16:57, Lukas Zapolskas wrote:
From: Adrián Larumbe
The sampler aggregates counter and set requests coming from userspace
and mediates interactions with the FW interface, to ensure that user
sessions cannot override the global configuration.
From the top-level interface, the samp
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
This devicetree contained only the SoC compatible but lacked the
machine specific one: add a "mediatek,mt8516-pumpkin" compatible
to the list to fix dtbs_check warnings.
Fixes: 9983822c8cf9 ("arm64: dts: mediatek: add pumpkin board dts")
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
All of the MT6360 regulator nodes were wrong and would not probe
because the regulator names are supposed to be lower case, but
they are upper case in this devicetree.
Change all nodes to be lower case to get working regulators.
Fixes: 9
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Add the missing DBVDD and LDO1-IN power supplies to the codec
node as both RT5682i and RT5682s require those.
This commit only fixes a dtbs_check warning but doesn't produce
any functional changes because the VIO18 LDO is already powered
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Not all of the kukui machines have got a real DSI panel, infact,
some of those have got a DSI to eDP bridge instead: this means
that the address and size cells are necessary in the first case
but unnecessary in the latter.
Instead of addi
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
Being this an interrupt controller, the binding forbids to use
interrupts-extended and wants an `interrupts` property instead.
Since this interrupt controller's parent is on the GPIO controller
set it as interrupt-parent and change interr
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
Change the latch-ck value from 0x14 to 4: as only bits [0-3] are
actually used, the final value that gets written to the register
field for DAT_LATCH_CK_SEL is just 0x4.
This also fixes dtbs_check warnings.
Fixes: 5a65dcccf483 ("arm64: d
On 24/07/2025 10:39, AngeloGioacchino Del Regno wrote:
The binding wants the node to be named "i2c-number", alternatively
"i2c@address", but those are named "i2c-gpio-number" instead.
Rename those to i2c-0, i2c-1 to adhere to the binding and suppress
dtbs_check warnings.
Signed-off-by: Angel
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The PCIe TPHY is under the soc bus, which provides MMIO, and all
nodes under that must use the bus, otherwise those would clearly
be out of place.
Add ranges to the PCIe tphy and assign the address to the main
node to silence a dtbs_check
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
Add pinctrl nodes for the MicroSD slot on mmc1 and SDIO Controller
on mmc2 and assign those to the respective controller nodes.
This makes sure that all of the pins are muxed in the right state
and with the right pullup/down(s) before tryi
Add DisplayPort controller for Qualcomm SM6150 SoC.
SM6150 shares the same configuration as SM8350, its hardware capabilities
differ about HBR3. Explicitly listing it ensures clarity and avoids
potential issues if SM8350 support evolves in the future.
Signed-off-by: Xiangxu Yin
---
Documentation
On Thu, Sep 11, 2025 at 12:09:52PM -0300, Ariel D'Alessandro wrote:
> Convert the existing text-based DT bindings for Marvell 8897/8997
> (sd8897/sd8997) bluetooth devices controller to a DT schema.
>
> While here:
>
> * bindings for "usb1286,204e" (USB interface) are dropped from the DT
> sche
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
All of the I2C nodes in this devicetree has a bogus "id" property,
which was probably specifying the I2C bus number.
This property was never parsed and never used - and besides, it
also gives dtbs_check warnings: remove it from all i2c no
On 25/07/2025 12:56, Fei Shao wrote:
On Thu, Jul 24, 2025 at 5:48 PM AngeloGioacchino Del Regno
wrote:
Change the pinctrl node names to adhere to the binding: the main
nodes are now named like "uart0-pins" and the children "pins-bus".
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-
On 25/07/2025 12:52, Fei Shao wrote:
On Thu, Jul 24, 2025 at 5:49 PM AngeloGioacchino Del Regno
wrote:
The "M4U" IOMMU requires a handle to the infracfg to switch to
the 4gb/pae addressing mode: add it.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Fei Shao
Applied thanks
On 9/12/25 2:33 AM, Chuanyu Tseng wrote:
Introduce a DRM interface for DRM clients to further restrict the
VRR Range within the panel supported VRR range on a per-commit
basis.
The goal is to give DRM client the ability to do frame-doubling/
ramping themselves, or to set lower static refresh rat
From: Boris Brezillon
A JM context describes user-requested priorities for the JM queues.
Context creation leads to the initialization of scheduling entities of
the same priority for all the device's job slots.
Until context creation and destruction are exposed to UM, all issued
jobs shall be b
From: Boris Brezillon
Minor revision of the driver must be bumped because this expands the
uAPI. On top of that, let UM know about the available priorities so that
they can create contexts with legal priority values.
Signed-off-by: Boris Brezillon
Signed-off-by: Adrián Larumbe
---
drivers/gpu
On 12/09/2025 10:27, Chen-Yu Tsai wrote:
>>> +properties:
>>> + compatible:
>>> +oneOf:
>>> + - enum:
>>> + - mediatek,mt8173-mdp-rdma
>>> + - mediatek,mt8173-mdp-rsz
>>> + - mediatek,mt8173-mdp-wdma
>>> + - mediatek,mt8173-mdp-wrot
>>
>> Why there is n
On 12/09/2025 11:00, AngeloGioacchino Del Regno wrote:
> Il 04/08/25 11:02, AngeloGioacchino Del Regno ha scritto:
>> Il 24/07/25 11:14, Krzysztof Kozlowski ha scritto:
>>> On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The dual and triple core jpeg encoder and decoder (respectively)
>
From: Boris Brezillon
For DebugFS builds, create a filesystem knob that, for every single open
file of the Panfrost DRM device, shows its command name information and
PID (when applicable), and all of its existing JM contexts.
For every context, show the DRM scheduler priority value of all of it
This patch series brings the notion of JM contexts into Panfrost.
UM will be able to create contexts, get a handle for them and attach
it to a job submission. Contexts describe basic HW resource assignment
to jobs, but at the moment that includes priorities only.
There's a MR for a Mesa commit ser
Commit 6cc44e9618f03f ("drm: Add directive to format code in comment")
fixes original Sphinx indentation warning as introduced in
471920ce25d50b ("drm/gpuvm: Add locking helpers"), by means of using
code-block:: directive. It semantically conflicts with earlier
bb324f85f72284 ("drm/gpuvm: Wrap drm_
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The node names for "pmic", "regulators", "rtc", and "keys" are
dictated by the PMIC MFD binding: change those to adhere to it.
Fixes: aef783f3e0ca ("arm64: dts: mediatek: Add MT6331 PMIC devicetree")
Signed-off-by: AngeloGioacchino Del Re
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
Add a compatible for the General Purpose Timer (GPT) found on the
MediaTek Helio X10 MT6795 SoC which is fully compatible with the
one found in MT6577.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Matthias Brugger
---
D
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
Both clocks and clock-names are missing (a lot of) entries: add
all the used audio clocks and their description and also fix the
example node.
You forgot to fix the example node.
Matthias
Signed-off-by: AngeloGioacchino Del Regno
-
On 24/07/2025 10:38, AngeloGioacchino Del Regno wrote:
The GCE Mailbox needs only one clock and the clock-names can be
used only by the driver (which, for instance, does not use it),
and this is true for all of the currently supported MediaTek SoCs.
Stop requiring to specify clock-names on al
On Tue, Sep 09, 2025 at 01:21:19PM +0200, Konrad Dybcio wrote:
> On 9/9/25 1:16 PM, Dmitry Baryshkov wrote:
> > On Tue, Sep 09, 2025 at 09:14:49AM +0200, Neil Armstrong wrote:
> >> On 08/09/2025 23:14, Dmitry Baryshkov wrote:
> >>> On Mon, Sep 08, 2025 at 03:04:20PM +0200, Neil Armstrong wrote:
> >
On Fri, Sep 12, 2025 at 07:54:31PM +0800, Xiangxu Yin wrote:
>
> On 9/12/2025 7:46 PM, Dmitry Baryshkov wrote:
> > On Fri, Sep 12, 2025 at 07:39:16PM +0800, Xiangxu Yin wrote:
> >> Add DisplayPort controller for Qualcomm SM6150 SoC.
> >> SM6150 shares the same configuration as SM8350, its hardware
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