https://bugs.freedesktop.org/show_bug.cgi?id=108577
Michel Dänzer changed:
What|Removed |Added
CC||harry.wentl...@amd.com,
On Fri, 26 Oct 2018 at 11:27, Daniel Vetter wrote:
>
> On Fri, Oct 26, 2018 at 11:05:50AM +0100, Emil Velikov wrote:
> > From: Emil Velikov
> >
> > Earlier commit updated the vgem driver to improve the topology, by
> > passing a platform device as parent to drm_dev_init(). Shortly
> > afterwords
On Fri, Oct 26, 2018 at 9:43 PM Priit Laes wrote:
>
> On Fri, Oct 26, 2018 at 08:13:39PM +0530, Jagan Teki wrote:
> > Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
> > LCD panel. Add panel driver for it.
> >
> > Signed-off-by: Jagan Teki
> > Tested-by: Jagan Teki
> > ---
> >
The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
on the one on A31.
Add A64 compatible and append A31 compatible as fallback.
Signed-off-by: Jagan Teki
---
Changes for v3:
- none
Changes for v2:
- new patch
Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt | 2 +-
1
Current driver is calculating hbp maximum value by subtracting
hsync_start with hdisplay which is front porch value, but the
hbp refers to back porch.
Back porch value is calculating by subtracting htotal with
hsync_end as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB
bridge panel, which is available on same PCB with 24-bit RGB interface.
So, this patch adds DSI specific binding details on existing
dt-bindings file.
Signed-off-by: Jagan Teki
---
Changes for v3:
- Use existing binding doc and
Hi Linus,
Please pull these VLA removal changes for v4.20-rc1. This turns on "-Wvla"
globally now that the last few trees with their VLA removals have landed
(crypto, block, net, and powerpc). Arnd mentioned that there may be a
couple more VLAs hiding in hard-to-find randconfigs, but nothing big
On Thu, Oct 18, 2018 at 12:35 AM Icenowy Zheng wrote:
>
> This patchset brings the support for Analogix ANX6345 RGB-(e)DP bridge,
> which is used by some Allwinner A64 laptops, such as Pinebook and Olimex
> TERES-I.
>
> It reuses some definitions from the ANX78xx driver that already exists
> in
Current driver is calculating hfp maximum value by subtracting
htotal with hsync_end which is front back value, but the
hpp refers to front porch.
Front porch value is calculating by subtracting hsync_start with
hdisplay as per drm_mode timings, and BSP code from BPI-M64-bsp
is eventually
Short transfer write support for DCS and Generic transfer types
share similar way to process command sequence in DSI block so
add generic write 2 param transfer type macro so-that the panels
which are requesting similar transfer type may process properly.
Signed-off-by: Jagan Teki
Tested-by:
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add dt-bingings for it.
Signed-off-by: Jagan Teki
---
Changes for v3:
- new patch
Changes for v2:
- none
.../display/panel/techstar,ts8550b.txt| 20 +++
1 file changed, 20 insertions(+)
create mode
This patch add support for Bananapi S070WV20-CT16 DSI panel to
BPI-M64 board.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC1 as DVDD supply
- PD6 gpio for reset pin
- PD5 gpio for backlight enable pin
- PD7 gpio for backlight vdd supply
Signed-off-by: Jagan Teki
TCON DRQ set bits for non-burst DSI mode can computed via
horizontal front porch instead of front porch + sync timings.
BSP code form BPI-M64-bsp is computing TCON DRQ set bits
for non-burts as
(in linux-sunxi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
=> panel->lcd_ht -
Increase the hfp packet overhead with another 10 bytes, the extra
10 bytes(which is hblk packet overhead) is adding for hfp packet
overhead since hfp depends on hblk.
This is truely as per BSP code from BPI-M64-bsp.
The real computation from BSP is
(in
The horizontal and vertical back porch calculation in BSP
code is simply following the Linux drm comment diagram, in
include/drm/drm_modes.h which is
[hv]back porch = [hv]total - [hv]sync_end
BSP code form BPI-M64-bsp is calculating vertical back porch as
(from
On Sat, Oct 27, 2018 at 03:25:29PM +0530, Jagan Teki wrote:
> On Fri, Oct 26, 2018 at 9:43 PM Priit Laes wrote:
> >
> > On Fri, Oct 26, 2018 at 08:13:39PM +0530, Jagan Teki wrote:
> > > Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
> > > LCD panel. Add panel driver for it.
> > >
> >
Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.
BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
tmp =
Add 10 bytes packet overhead for hblk where blank is set using
a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes)
This is according to BSP code from BPI-M64-bsp
(in drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
dsi_hblk = (ht-hspw)*dsi_pixel_bits[format]/8-(4+4+2);
Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
panel which can be used to connect via DSI port on BPI-M64 board,
so add a driver for it.
The same panel PCB comes with parallel RBG which is supported via
panel-simple driver with "bananapi,s070wv20-ct16" compatible.
BSP
hblk is adding line with all porch timing values, or timings
values from htotal without sync time.
Current driver is subtracting htotal with hsa, but the hsa
is bounded with packet overhead. For real hblk calculation
needed by subtracting htotal with back and front porch values
and BSP code
Amarula A64-Relic board by default bound with Techstar TS8550B
MIPI-DSI panel, add support for it.
DSI panel connected via board DSI port with,
- DC1SW as AVDD supply
- DCDC2 as DVDD supply
- DCDC1 as VCC-DSI supply
- PD24 gpio for reset pin
- PD23 gpio for backlight enable pin
Signed-off-by:
Some NKM PLLs doesn't work well when their output clock rate is set below
certain rate.
So, add support for minimal rate for relevant PLLs.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
Tested-by: Jagan Teki
---
Changes for v3:
- collect Stephen Ack
- add tested credit
Changes for v2:
-
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock(CLK_DSI_SCLK)
So, alter has_mod_clk bool via driver data for respective
SoC's compatible.
Signed-off-by: Jagan Teki
Tested-by: Jagan Teki
---
Changes for v3:
- add tested credit
Changes for
Some NKM PLLs, frequency can be set above PLL working range.
Add a constraint for maximum supported rate. This way, drivers can
specify which is maximum allowed rate for PLL.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
Tested-by: Jagan Teki
---
Changes for v3:
- collect Stephen Ack
- add
Video start delay can be computed by subtracting total vertical
timing with front porch timing and with adding 1 delay line for TCON.
BSP code form BPI-M64-bsp is computing video start delay as
(in linux-sunxi/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)
u32 vfp = panel->lcd_vt
Some boards have VCC-DSI pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
MIPI DSI driver.
Signed-off-by: Jagan Teki
Tested-by: Jagan Teki
---
Changes for v3:
- new patch
Changes for v2:
- none
On Fri, Oct 26, 2018 at 08:13:39PM +0530, Jagan Teki wrote:
> Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
> LCD panel. Add panel driver for it.
>
> Signed-off-by: Jagan Teki
> Tested-by: Jagan Teki
> ---
> Changes for v3:
> - new patch
> Changes for v2:
> - none
>
>
Manual noted to use PLL_MIPI rate 500MHz to 1.4GHz,
but lowering the min rate by 300MHz can result proper
working nkms divider with the help of desired dclock
rate from panel driver.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
Tested-by: Jagan Teki
---
Changes for v3:
- collect Stephen
The MIPI DSI controller on Allwinner A64 is similar to
Allwinner A31 without support of DSI mod clock.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Tested-by: Jagan Teki
---
Changes for v3:
- add tested credit
Changes for v2:
- none
The A64 has a MIPI-DSI block which is similar to A31
without mod clock.
So, add dsi node with A64 compatible, dphy node with
A31 compatible and finally connect dsi to tcon0 to
make proper DSI pipeline.
Signed-off-by: Jagan Teki
Tested-by: Jagan Teki
---
Changes for v3:
- add
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI
LCD panel. Add panel driver for it.
Signed-off-by: Jagan Teki
Tested-by: Jagan Teki
---
Changes for v3:
- new patch
Changes for v2:
- none
drivers/gpu/drm/panel/Kconfig | 9 +
drivers/gpu/drm/panel/Makefile
DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.
Signed-off-by: Jagan Teki
Acked-by: Stephen Boyd
Tested-by: Jagan Teki
---
Changes for v3:
- collect Stephen Ack
- add tested credit
Changes for v2:
- none
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
1 file changed, 1
This series fixed the issues related to work DSI on 2-lane panel
which is reported on previous version[1].
Few comments from previous version still in discussion, but I just
send this version just to group all working changes together.
anyway I will fix in this in next version if any.
PLL_MIPI
https://bugs.freedesktop.org/show_bug.cgi?id=108096
--- Comment #18 from Michel Dänzer ---
Andrey, can you work with Dieter to figure out where the error is coming from?
E.g. by attaching patches adding debugging printks.
--
You are receiving this mail because:
You are the assignee for the
https://bugs.freedesktop.org/show_bug.cgi?id=108585
--- Comment #1 from Michel Dänzer ---
There were no amdgpu driver changes between rc8 and final... Are you sure this
is 100% reproducible with the latter and not reproducible with the former? If
so, can you bisect?
--
You are receiving this
https://bugs.freedesktop.org/show_bug.cgi?id=108487
--- Comment #6 from Pekka Paalanen ---
I removed the misleading bit from the title, because lack of
EGL_ANDROID_native_fence_sync will not stop weston.
--
You are receiving this mail because:
You are the assignee for the
https://bugs.freedesktop.org/show_bug.cgi?id=108487
Pekka Paalanen changed:
What|Removed |Added
Summary|Wayland compositors are |Wayland compositors are
https://bugs.freedesktop.org/show_bug.cgi?id=108585
Bug ID: 108585
Summary: *ERROR* hw_init of IP block failed -22
Product: DRI
Version: unspecified
Hardware: PowerPC
OS: Linux (All)
Status: NEW
To avoid the execution of link integrity check when the HDCP is
already disabled, cancel the delayed work for link integrity check
before disabling the HDCP.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This series defines the HDCP2.2 authentication messages at drm header
along with intel specific HDCP2.2 registers. And introduces a
structure intel_hdcp to wrap all hdcp related variables into it.
Out of these patches 4 were previously reviewed at
https://patchwork.freedesktop.org/series/38254/
Considering significant number of HDCP specific variables, it will
be clean to have separate struct for HDCP.
New structure called intel_hdcp is added within intel_connector.
v2:
struct hdcp statically allocated. [Sean Paul]
enable and disable function parameters are retained.[Sean Paul]
v3:
This patch adds HDCP register definitions for HDMI and DP HDCP
adaptations.
HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h,
where as HDCP2.2 register offsets in DPCD offsets are defined at
drm_dp_helper.h.
v2:
bit_field definitions are replaced by macros. [Tomas and Jani]
Intel HDCP2.2 registers are defined with addr offsets and bit details.
v2:
Replaced the arith calc with _PICK [Sean Paul]
v3:
No changes.
v4:
%s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma]
v5:
Added parentheses for the parameters of macro.
v6:
No changes
v7:
No changes
Signed-off-by:
This patch defines the hdcp2.2 protocol messages for authentication.
v2:
bit_fields are removed. Instead bitmasking used. [Tomas and Jani]
prefix HDCP_2_2_ is added to the macros. [Tomas]
v3:
No Changes.
v4:
Style and spellings are fixed [Uma]
v5:
Fix for macros.
v6:
comment for Type
As a policy, this change considers all I915 programming failures and
HW failures as ERRORS. Where as all HDCP failures due to the sink is
considered as DEBUG logs.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 18 +-
1 file changed, 9 insertions(+), 9
On Fri, Oct 26, 2018 at 08:13:37PM +0530, Jagan Teki wrote:
> Bananapi S070WV20-CT16 ICN6211 is 800x480, 4-lane MIPI-DSI to RGB bridge
> panel which can be used to connect via DSI port on BPI-M64 board,
> so add a driver for it.
>
> The same panel PCB comes with parallel RBG which is supported
On Fri, Oct 26, 2018 at 08:13:35PM +0530, Jagan Teki wrote:
> Some boards have VCC-DSI pin connected to voltage regulator which may
> not be turned on by default.
>
> Add support for such boards by adding voltage regulator handling code to
> MIPI DSI driver.
>
> Signed-off-by: Jagan Teki
>
This patch adds a new API to clean up the scheduler job resources. This
is primarliy needed in cases the job was created but was not queued to
the scheduler queue. Additionally with this change, the layer which
creates the scheduler job also gets to free up the job's resources and
this entails
On Fri, Oct 26, 2018 at 08:13:34PM +0530, Jagan Teki wrote:
> Unlike hblk, the vblk timings should follow an equation to compute
> the desired value for lane 4 devices and rest of devices it would be 0.
>
> BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
> (in
On Fri, Oct 26, 2018 at 08:13:33PM +0530, Jagan Teki wrote:
> Increase the hfp packet overhead with another 10 bytes, the extra
> 10 bytes(which is hblk packet overhead) is adding for hfp packet
> overhead since hfp depends on hblk.
>
> This is truely as per BSP code from BPI-M64-bsp.
> The real
On Fri, Oct 26, 2018 at 08:13:31PM +0530, Jagan Teki wrote:
> Add 10 bytes packet overhead for hblk where blank is set using
> a blanking packet like (4 bytes + 4 bytes + payload + 2 bytes)
>
> This is according to BSP code from BPI-M64-bsp
> (in
On Fri, Oct 26, 2018 at 08:13:25PM +0530, Jagan Teki wrote:
> Short transfer write support for DCS and Generic transfer types
> share similar way to process command sequence in DSI block so
> add generic write 2 param transfer type macro so-that the panels
> which are requesting similar transfer
On Mon, Oct 29, 2018 at 11:11:16AM +0800, CK Hu wrote:
> Hi,Daniel:
>
> On Fri, 2018-10-26 at 12:21 +0200, Daniel Vetter wrote:
> > On Fri, Oct 26, 2018 at 03:22:03PM +0800, CK Hu wrote:
> > > After adding dma_dev in struct drm_device and
> > > drm_gem_cma_dumb_create_no_kmap(),
On Fri, Oct 26, 2018 at 08:13:19PM +0530, Jagan Teki wrote:
> This series fixed the issues related to work DSI on 2-lane panel
> which is reported on previous version[1].
>
> Few comments from previous version still in discussion, but I just
> send this version just to group all working changes
On 26.10.2018 00:21, Douglas Anderson wrote:
> As far as I can tell the bindings that were added in commit
> 9c04400f7ea6 ("dt-bindings: drm/panel: Document Innolux TV123WAM panel
> bindings") weren't actually for Innolux TV123WAM but were actually for
> Innolux P120ZDG-BF1.
>
> As far as I can
On Mon, 29 Oct 2018 10:03:01 +0100
Daniel Vetter wrote:
> On Mon, Oct 29, 2018 at 09:41:36AM +0100, Boris Brezillon wrote:
> > On Mon, 29 Oct 2018 09:06:40 +0100
> > Daniel Vetter wrote:
> >
> > > On Fri, Oct 26, 2018 at 06:10:03PM +0300, Ville Syrjälä wrote:
> > > > On Fri, Oct 26, 2018
On Thu, Oct 25, 2018 at 09:21:31PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:43 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:32PM +0530, Jagan Teki wrote:
> > > A64 manual say PLL_MIPI rates are 500MHz to 1.4GHz, but
> > > using minimum 500MHz can't release the
On Sun, Oct 28, 2018 at 09:46:43PM +0100, Noralf Trønnes wrote:
>
> Den 28.10.2018 21.21, skrev David Lechner:
> > On 10/26/2018 05:38 PM, Noralf Trønnes wrote:
> > > Den 17.10.2018 15.04, skrev Noralf Trønnes:
> > > > This move makes tinydrm useful for more drivers. tinydrm doesn't need
> > > >
On 26.10.2018 00:21, Douglas Anderson wrote:
> Let's solve the mystery of commit bf1178c98930 ("drm/bridge:
> ti-sn65dsi86: Add mystery delay to enable()"). Specifically the
> reason we needed that mystery delay is that we weren't paying
> attention to HPD.
>
> Looking at the datasheet for the
On Mon, Oct 29, 2018 at 09:41:36AM +0100, Boris Brezillon wrote:
> On Mon, 29 Oct 2018 09:06:40 +0100
> Daniel Vetter wrote:
>
> > On Fri, Oct 26, 2018 at 06:10:03PM +0300, Ville Syrjälä wrote:
> > > On Fri, Oct 26, 2018 at 04:52:33PM +0200, Boris Brezillon wrote:
> > > > On Fri, 26 Oct 2018
On Thu, Oct 25, 2018 at 06:51:14PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:40 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:34PM +0530, Jagan Teki wrote:
> > > The A64 has a MIPI-DSI block which is similar to A31
> > > without mod clock.
> > >
> > > So, add dsi
On Thu, Oct 25, 2018 at 06:22:51PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:39 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:33PM +0530, Jagan Teki wrote:
> > > The MIPI DSI PHY HDMI controller on Allwinner A64 is similar
> > > on the one on A31.
> > >
> > > Add A64
On Thu, Oct 25, 2018 at 04:32:06PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:36 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:24PM +0530, Jagan Teki wrote:
> > > The MIPI DSI controller on Allwinner A64 is similar to
> > > Allwinner A31 without support of DSI mod
On Thu, Oct 25, 2018 at 04:25:59PM +0530, Jagan Teki wrote:
> On Wed, Oct 24, 2018 at 11:34 PM Maxime Ripard
> wrote:
> >
> > On Tue, Oct 23, 2018 at 09:20:22PM +0530, Jagan Teki wrote:
> > > Some NKM PLLs doesn't work well when their output clock rate is set below
> > > certain rate.
> > >
> > >
On Mon, 29 Oct 2018 09:06:40 +0100
Daniel Vetter wrote:
> On Fri, Oct 26, 2018 at 06:10:03PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 26, 2018 at 04:52:33PM +0200, Boris Brezillon wrote:
> > > On Fri, 26 Oct 2018 16:26:03 +0200
> > > Daniel Vetter wrote:
> > >
> > > > On Fri, Oct 26,
On Fri, 26 Oct 2018 17:34:15 +
"Kazlauskas, Nicholas" wrote:
> On 10/26/18 10:53 AM, Ville Syrjälä wrote:
> > On Fri, Oct 26, 2018 at 02:49:31PM +, Kazlauskas, Nicholas wrote:
> >> On 10/26/18 7:37 AM, Pekka Paalanen wrote:
> >>> Hi,
> >>>
> >>> where is the documentation that
On Fri, Oct 26, 2018 at 06:10:03PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 26, 2018 at 04:52:33PM +0200, Boris Brezillon wrote:
> > On Fri, 26 Oct 2018 16:26:03 +0200
> > Daniel Vetter wrote:
> >
> > > On Fri, Oct 26, 2018 at 3:57 PM Boris Brezillon
> > > wrote:
> > > >
> > > > On Fri, 26 Oct
On Fri, Oct 26, 2018 at 07:05:12PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Trivial fix to a spelling mistake of the error access name EACCESS,
> rename to EACCES
>
> Signed-off-by: Colin Ian King
Thanks for your patch, applied to drm-misc-next.
-Daniel
> ---
>
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