On 21-10-22, 17:49, Arnd Bergmann wrote:
> diff --git a/drivers/cpufreq/sa1110-cpufreq.c
> b/drivers/cpufreq/sa1110-cpufreq.c
> index 1a83c8678a63..bb7f591a8b05 100644
> --- a/drivers/cpufreq/sa1110-cpufreq.c
> +++ b/drivers/cpufreq/sa1110-cpufreq.c
> @@ -344,14 +344,8 @@ static int __init
On Tue, 25 Oct 2022 at 12:21, John Hubbard wrote:
>
> On 10/24/22 05:43, Oded Gabbay wrote:
>
> Hi Oded,
>
> The patches make sense to me. I'm still just reading through and looking
> for minor issues, but at a high level it seems to match what the LPC
> discussions pointed to.
>
> >> What's your
On 10/24/22 05:43, Oded Gabbay wrote:
Hi Oded,
The patches make sense to me. I'm still just reading through and looking
for minor issues, but at a high level it seems to match what the LPC
discussions pointed to.
What's your opinion on the long-term prospect of DRM vs accel? I assume
that
Enable VP9 inner racing mode
We send lat trans buffer to the core when trigger lat to work, instead of
waiting for the lat decode done.
It can be reduce decoder latency.
Signed-off-by: Mingjia Zhang
---
Changes from v3:
- CTS/GTS test pass
- Fluster result: Ran 275/303 tests successfully
Hi Dave, Daniel,
The following changes since commit 9abf2313adc1ca1b6180c508c25f22f9395cc780:
Linux 6.1-rc1 (2022-10-16 15:36:24 -0700)
are available in the Git repository at:
git://linuxtv.org/pinchartl/media.git tags/drm-next-20221025
for you to fetch changes up to
On 9/24/2022 9:11 AM, Jacek Lawrynowicz wrote:
VPU stands for Versatile Processing Unit and it's a CPU-integrated
inference accelerator for Computer Vision and Deep Learning
applications.
The VPU device consist of following componensts:
- Buttress - provides CPU to VPU integration,
GuC will set the min/max frequencies to theoretical max on
ATS-M. This will break kernel ABI, so limit min/max frequency
to RP0(platform max) instead.
Also modify the SLPC selftest to update the min frequency
when we have a server part so that we can iterate between
platform min and max.
v2:
Hi Dave,
A few fixes for the v6.1 cycle. Summary below.
The following changes since commit e8b595f7b058c7909e410f3e0736d95e8f909d01:
drm/msm/hdmi: make hdmi_phy_8996 OF clk provider (2022-09-18 09:38:07 -0700)
are available in the Git repository at:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed,
with separate partitioning in WOPCM for the root GT GuC and the media
GT GuC. The size of WOPCM is 4MB with the lower 2MB reserved for the
media GT and the upper 2MB for the root GT.
Given that MTL has
On 10/24/2022 2:46 PM, John Harrison wrote:
On 10/24/2022 14:39, Ceraolo Spurio, Daniele wrote:
On 10/24/2022 2:33 PM, John Harrison wrote:
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed
On 10/24/2022 14:39, Ceraolo Spurio, Daniele wrote:
On 10/24/2022 2:33 PM, John Harrison wrote:
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed
with
separate partitioning in WOPCM for GCD/GT GuC
On 10/24/2022 2:33 PM, John Harrison wrote:
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
of WOPCM is 4MB with
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
From: Aravind Iddamsetty
With MTL standalone media architecture the wopcm layout has changed with
separate partitioning in WOPCM for GCD/GT GuC and SA Media GuC. The size
of WOPCM is 4MB with lower 2MB for SA Media and upper 2MB for GCD/GT.
The currently default Round-Robin GPU scheduling can result in starvation
of entities which have a large number of jobs, over entities which have
a very small number of jobs (single digit).
This can be illustrated in the following diagram, where jobs are
alphabetized to show their chronological
https://bugzilla.kernel.org/show_bug.cgi?id=216119
--- Comment #47 from Harald Judt (h.j...@gmx.at) ---
I have tried attachment 303055 and
https://patchwork.kernel.org/project/dri-devel/patch/20221020103755.24058-2-tzimmerm...@suse.de/
together with attachment 303064, but unfortunately it made no
On 10/21/2022 17:10, Daniele Ceraolo Spurio wrote:
Our current FW loading process is the same for all FWs:
- Pin FW to GGTT at the start of the ggtt->uc_fw node
- Load the FW
- Unpin
This worked because we didn't have a case where 2 FWs would be loaded on
the same GGTT at the same time. On
On Tue, Sep 27, 2022 at 01:04:52PM +0200, Hans de Goede wrote:
> So to fix this we need to make acpi_video_get_backlight_type()
> return native on the Acer Chromebook Spin 713.
Isn't the issue broader than that? Unless the platform is Windows 8 or
later, we'll *always* (outside of some corner
Hi,
On Fri, Oct 21, 2022 at 2:18 PM Abhinav Kumar wrote:
>
> Hi Doug
>
> On 10/21/2022 1:07 PM, Douglas Anderson wrote:
> > If we fail to get a valid panel ID in drm_edid_get_panel_id() we'd
> > like to see the EDID that was read so we have a chance of
> > understanding what's wrong. There's
On 10/21/2022 5:10 PM, Daniele Ceraolo Spurio wrote:
The render and media GuCs share the same interrupt enable register, so
we can no longer disable interrupts when we disable communication for
one of the GuCs as this would impact the other GuC. Instead, we keep the
interrupts always enabled
From: Don Hiatt
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake,
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency
From: Badal Nilawar
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6
On Sun, Oct 23, 2022 at 06:07:47PM +0200, Ondrej Jirman wrote:
> lcdsel_grf_reg is defined as u32, so "< 0" comaprison is always false,
> which breaks VOP selection on eg. RK3399. Compare against 0.
>
Sorry about that. I can confirm this works for me on the rk3566 (specifically
the Anbernic
From: Kees Cook
Implement a robust overflows_type() macro to test if a variable or
constant value would overflow another variable or type. This can be
used as a constant expression for static_assert() (which requires a
constant expression[1][2]) when used on constant values. This must be
Yeah, it was just spelling typos. I'll add your RB to it and repost.
I cannot push to drm-misc-next, but hope someone will pick it up.
Regards,
Luben
On 2022-10-24 14:42, Christian König wrote:
> I've seen that one, but couldn't figure out what was actually changed
> between the two.
>
> If
On Mon, Oct 24, 2022 at 12:13:13PM -0700, Ashutosh Dixit wrote:
> From: Badal Nilawar
>
> Add support for C6 residency and C state type for MTL SAMedia. Also add
> mtl_drpc.
>
> v2: Fixed review comments (Ashutosh)
> v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
>
On Mon, Oct 24, 2022 at 12:16:28PM -0700, Dixit, Ashutosh wrote:
> On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
> >
>
> Hi Rodrigo,
>
> > On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > > From: Badal Nilawar
> > >
> > > Add support for C6 residency and C state
On 10/21/2022 10:26 PM, Dixit, Ashutosh wrote:
On Fri, 21 Oct 2022 18:38:57 -0700, Belgaumkar, Vinay wrote:
On 10/20/2022 3:57 PM, Dixit, Ashutosh wrote:
On Tue, 18 Oct 2022 11:30:31 -0700, Vinay Belgaumkar wrote:
Hi Vinay,
diff --git a/drivers/gpu/drm/i915/gt/selftest_slpc.c
On 10/21/22 00:33, Dmitry Osipenko wrote:
> The drm_client_buffer_delete() wasn't switched to unlocked GEM vunmapping
> by accident when rest of drm_client code transitioned to the unlocked
> variants of the vmapping functions. Make drm_client_buffer_delete() use
> the unlocked variant. This fixes
This reverts commit 55eea8ef98641f6e1e1c202bd3a49a57c1dd4059.
This quirk is now handled in the DRM core, so we can drop all of
the internal code that was added to handle it.
Signed-off-by: Hamza Mahfooz
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 35 ---
1 file changed,
Since, the quirk is handled in the DRM core now, we can use that value
instead of the internal value.
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 +--
2 files changed, 11
The LG 27GP950 and LG 27GN950 have visible display corruption when
trying to use 10bpc modes. So, to fix this, cap their maximum DSC
target bitrate to 15bpp.
Suggested-by: Roman Li
Signed-off-by: Hamza Mahfooz
---
drivers/gpu/drm/drm_edid.c | 12
include/drm/drm_connector.h | 6
On 10/20/22 02:12, max...@cerno.tech wrote:
A significant number of RaspberryPi drivers using the firmware don't
have a phandle to it, so end up scanning the device tree to find a node
with the firmware compatible.
That code is duplicated everywhere, so let's introduce a helper instead.
On Fri, 21 Oct 2022 09:35:32 -0700, Rodrigo Vivi wrote:
>
Hi Rodrigo,
> On Wed, Oct 19, 2022 at 04:37:21PM -0700, Ashutosh Dixit wrote:
> > From: Badal Nilawar
> >
> > Add support for C6 residency and C state type for MTL SAMedia. Also add
> > mtl_drpc.
>
> I believe this patch deserves a slip
From: Badal Nilawar
Update CAGF functions for MTL to get actual resolved frequency of 3D and
SAMedia.
v2: Update MTL_MIRROR_TARGET_WP1 position/formatting (MattR)
Move MTL branches in cagf functions to top (MattR)
Fix commit message (Andi)
v3: Added comment about registers not needing
From: Don Hiatt
On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.
v2:
- Fixed review comments(Ashutosh)
- Added function intel_rps_read_rpstat_fw to read RPSTAT without
forcewake,
From: Badal Nilawar
Add support for C6 residency and C state type for MTL SAMedia. Also add
mtl_drpc.
v2: Fixed review comments (Ashutosh)
v3: Sort registers and fix whitespace errors in intel_gt_regs.h (Matt R)
Remove MTL_CC_SHIFT (Ashutosh)
Adapt to RC6 residency register code
Previously RC6 residency functions directly accepted RC6 residency register
MMIO offsets (there are four RC6 residency registers). This worked but
required an assumption on the residency register layout so was not future
proof.
Therefore change RC6 residency functions to accept RC6 residency
This series includes the code changes to get CAGF, RC State and C6
Residency of MTL.
v3: Included "Use GEN12 RPSTAT register" patch
v4:
- Rebased
- Dropped "Use GEN12 RPSTAT register" patch from this series
going to send separate series for it
v5:
- Included "drm/i915/gt: Change RC6
Instead of masks/shifts settle on REG_FIELD_GET as the standard way to
extract reg fields. This allows future patches touching this code to also
consistently use REG_FIELD_GET and friends.
Suggested-by: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Reviewed-by: Rodrigo Vivi
---
I've seen that one, but couldn't figure out what was actually changed
between the two.
If you just fixed a typo feel free to add my R-B to this one as well.
Christian.
Am 24.10.22 um 19:25 schrieb Luben Tuikov:
Hi Christian,
Can you add an R-B to V1 of this patch, as the v1 is what I'd like
On 10/24/22 18:29, Jason A. Donenfeld wrote:
With char becoming unsigned by default, and with `char` alone being
ambiguous and based on architecture, signed chars need to be marked
explicitly as such. This fixes warnings like:
drivers/video/fbdev/sis/init301.c:3549 SiS_GetCRT2Data301() warn:
On 24.10.2022 18.58, Ville Syrjälä wrote:
On Mon, Oct 24, 2022 at 08:48:15AM -0700, Rob Clark wrote:
On Mon, Oct 24, 2022 at 5:43 AM wrote:
Hi,
I've discussing the idea for the past year to add an IGT test suite that
all well-behaved KMS drivers must pass.
The main idea behind it comes
On Tue, 25 Oct 2022, Akihiko Odaki wrote:
> That aside, the first patch in this series can be applied without the
> later patches so you may have a look at it. It's fine if you don't merge
> it though since it does not fix really a pragmatic bug as its message says.
I think it's problematic
Arnd Bergmann writes:
> From: Arnd Bergmann
>
> After the removal of the unused board files, I went through the
> omap1 code to look for code that no longer has any callers
> and remove that.
>
> In particular, support for the omap7xx/omap8xx family is now
> completely unused, so I'm only
On Mon, Oct 24, 2022 at 03:33:37PM +0300, Jani Nikula wrote:
> Having the EDID override debugfs directly update the EDID property is
> problematic. The update is partial only. The driver has no way of
> knowing it's been updated. Mode list is not updated. It's an
> inconsistent state.
>
> Detach
On Mon, Oct 24, 2022 at 6:21 PM Jeffrey Hugo wrote:
>
> On 10/22/2022 3:46 PM, Oded Gabbay wrote:
> > The accelerator devices are exposed to user-space using a dedicated
> > major. In addition, they are represented in /dev with new, dedicated
> > device char names: /dev/accel/accel*. This is done
Hi Christian,
Can you add an R-B to V1 of this patch, as the v1 is what I'd like pushed.
I sent it right after this one.
Regards,
Luben
On 2022-10-24 06:42, Christian König wrote:
> Am 22.10.22 um 03:09 schrieb Luben Tuikov:
>> The currently default Round-Robin GPU scheduling can result in
Applied. Thanks!
Alex
On Mon, Oct 24, 2022 at 11:41 AM Takashi Iwai wrote:
>
> This patch adds the support for the notification of HD-audio hotplug
> via the already existing drm_audio_component framework to radeon
> driver. This allows us more reliable hotplug notification and ELD
> transfer
Applied. Thanks!
Alex
On Mon, Oct 24, 2022 at 9:17 AM Joaquín Ignacio Aramendía
wrote:
>
> This file was split in commit 5d945cbcd4b16a29d6470a80dfb19738f9a4319f
> ("drm/amd/display: Create a file dedicated to planes") and the logic in
> dm_plane_format_mod_supported() function got changed by
Waitboost (when SLPC is enabled) results in a H2G message. This can result
in thousands of messages during a stress test and fill up an already full
CTB. There is no need to request for boost if min softlimit is equal or
greater than it.
v2: Add the tracing back, and check requested freq
in the
On Mon, Oct 24, 2022 at 3:33 AM Thomas Zimmermann wrote:
>
> Hi
>
> Am 24.10.22 um 08:20 schrieb Quan, Evan:
> > [AMD Official Use Only - General]
> >
> > Reviewed-by: Evan Quan
> >
> >> -Original Message-
> >> From: amd-gfx On Behalf Of Alex
> >> Deucher
> >> Sent: Thursday, October
On 24/10/2022 19:12, Rob Clark wrote:
On Mon, Oct 24, 2022 at 8:14 AM Dmitry Baryshkov
wrote:
The function a6xx_create_address_space() is mostly a copy of
adreno_iommu_create_address_space() with added quirk setting. Reuse the
original function to do the work, while introducing the wrapper to
Add gcc-bus clock required for the SDM845 DPU device tree node. This
change was made in the commit 111c52854102 ("arm64: dts: qcom: sdm845:
move bus clock to mdp node for sdm845 target"), but was not reflected in
the schema.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
In order to make the schema more readable, split dpu-qcm2290 into the DPU
and MDSS parts, each one describing just a single device binding.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-qcm2290.yaml | 148 --
In order to make the schema more readable, split dpu-sc7280 into the DPU
and MDSS parts, each one describing just a single device binding.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7280.yaml | 162 --
In order to make the schema more readable, split dpu-msm8998 into the DPU
and MDSS parts, each one describing just a single device binding.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/qcom,msm8998-dpu.yaml | 95 +++
...pu-msm8998.yaml =>
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm
SM8250 platform.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/mdss-common.yaml | 4 +-
.../bindings/display/msm/qcom,sm8250-dpu.yaml | 92 +
Add interconnects required for the SDM845 MDSS device tree node. This
change was made in the commit c8c61c09e38b ("arm64: dts: qcom: sdm845:
Add interconnects property for display"), but was not reflected in the
schema.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
Move properties common to all DPU DT nodes to the dpu-common.yaml.
Note, this removes description of individual DPU port@ nodes. However
such definitions add no additional value. The reg values do not
correspond to hardware INTF indices. The driver discovers and binds
these ports not paying any
In order to make the schema more readable, split dpu-sc7180 into the DPU
and MDSS parts, each one describing just a single device binding.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sc7180.yaml | 158 --
Move properties common to all MDSS DT nodes to the mdss-common.yaml.
This extends qcom,msm8998-mdss schema to allow interconnect nodes, which
will be added later, once msm8998 gains interconnect support.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
In order to make the schema more readable, split dpu-sdm845 into the DPU
and MDSS parts, each one describing just a single device binding.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../bindings/display/msm/dpu-sdm845.yaml | 148 --
Add missing device nodes (DSI, PHYs, DP/eDP) to the existing MDSS
schemas.
Reviewed-by: Rob Herring
Signed-off-by: Dmitry Baryshkov
---
.../display/msm/qcom,msm8998-mdss.yaml| 153 +
.../display/msm/qcom,qcm2290-mdss.yaml| 81 +
Split Mobile Display SubSystem (MDSS) root node bindings to the separate
yaml file. Changes to the existing (txt) schema:
- Added optional "vbif_nrt_phys" region used by msm8996
- Made "bus" and "vsync" clocks optional (they are not used by some
platforms)
- Added optional resets property
Create separate YAML schema for MDSS devicesd$ (both for MDP5 and DPU
devices). Cleanup DPU schema files, so that they do not contain schema
for both MDSS and DPU nodes. Apply misc small fixes to the DPU schema
afterwards. Add schema for the MDSS and DPU on sm8250 platform.
Soft dependency on [1]
On Wed, Oct 19, 2022 at 05:32:13PM +0800, allen wrote:
> From: allen chen
>
> Add properties to restrict dp output data-lanes and clock.
>
> Signed-off-by: Pin-Yen Lin
> Signed-off-by: Allen Chen
> ---
> .../bindings/display/bridge/ite,it6505.yaml | 89 +--
> 1 file
With char becoming unsigned by default, and with `char` alone being
ambiguous and based on architecture, signed chars need to be marked
explicitly as such. This fixes warnings like:
drivers/video/fbdev/sis/init301.c:3549 SiS_GetCRT2Data301() warn:
On 10/22/2022 12:22 PM, Dixit, Ashutosh wrote:
On Sat, 22 Oct 2022 10:56:03 -0700, Belgaumkar, Vinay wrote:
Hi Vinay,
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index fc23c562d9b2..32e1f5dde5bb 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++
On Mon, Oct 24, 2022 at 8:14 AM Dmitry Baryshkov
wrote:
>
> The function a6xx_create_address_space() is mostly a copy of
> adreno_iommu_create_address_space() with added quirk setting. Reuse the
> original function to do the work, while introducing the wrapper to set
> the quirk.
>
>
On Mon, Oct 24, 2022 at 03:33:44PM +0300, Jani Nikula wrote:
> Convert to drm_kms_dbg/drm_err where possible, and reference the
> connector using [CONNECTOR:%d:%s]. Pass connectors around a bit more to
> enable this. Where this is not possible, unify the rest of the debugs to
> DRM_DEBUG_KMS.
>
>
On Mon, Oct 24, 2022 at 03:33:42PM +0300, Jani Nikula wrote:
> Conform to device specific logging.
>
> v2: Include [CONNECTOR:%d:%s] (Ville)
>
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/drm_edid_load.c | 12
> 1 file changed, 8
On Mon, Oct 24, 2022 at 08:48:15AM -0700, Rob Clark wrote:
> On Mon, Oct 24, 2022 at 5:43 AM wrote:
> >
> > Hi,
> >
> > I've discussing the idea for the past year to add an IGT test suite that
> > all well-behaved KMS drivers must pass.
> >
> > The main idea behind it comes from v4l2-compliance
On Mon, Oct 24, 2022 at 5:43 AM wrote:
>
> Hi,
>
> I've discussing the idea for the past year to add an IGT test suite that
> all well-behaved KMS drivers must pass.
>
> The main idea behind it comes from v4l2-compliance and cec-compliance,
> that are being used to validate that the drivers are
On Fri, 21 Oct 2022 at 15:24, Matti Vaittinen wrote:
>
> On 10/21/22 16:18, Matti Vaittinen wrote:
> > Simplify using devm_regulator_bulk_get_enable()
> >
> > Signed-off-by: Matti Vaittinen
> > Reviewed-by: Robert Foss
>
> Robert, I did slightly modify the return from probe when using the
>
This patch adds the support for the notification of HD-audio hotplug
via the already existing drm_audio_component framework to radeon
driver. This allows us more reliable hotplug notification and ELD
transfer without accessing HD-audio bus; it's more efficient, and more
importantly, it works
Use drm_connector's helpers enable_hpd and disable_hpd to enable and
disable HPD automatically by the means of drm_kms_helper_poll_*
functions. As the drm_bridge_connector_enable_hpd() and
drm_bridge_connector_disable_hpd() functions are now unused, replace
them with stubs to ease driver
Intruct two drm_connector_helper_funcs: enable_hpd() and disable_hpd().
They are called by drm_kms_helper_poll_enable() and
drm_kms_helper_poll_disable() (and thus drm_kms_helper_poll_init() and
drm_kms_helper_poll_fini()) respectively.
This allows drivers to rely on drm_kms_helper_poll for
The functionality of drm_bridge_connector_enable_hpd() and
drm_bridge_connector_disable_hpd() is provided automatically by the
drm_kms_poll helpers. Stop calling these functions manually.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/omapdrm/omap_drv.c | 41 --
The functionality of drm_bridge_connector_enable_hpd() and
drm_bridge_connector_disable_hpd() is provided automatically by the
drm_kms_poll helpers. Stop calling these functions manually.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/hdmi.c | 2 --
1 file changed, 2 deletions(-)
The functionality of drm_bridge_connector_enable_hpd() and
drm_bridge_connector_disable_hpd() is provided automatically by the
drm_kms_poll helpers. Stop calling these functions manually.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/imx/dcss/dcss-dev.c | 4
Now as all drivers stopped calling drm_bridge_connector_enable_hpd() and
drm_bridge_connector_disable_hpd() it is safe to remove them complelely.
Rename our internal helpers to remove the underscore prefix.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_bridge_connector.c | 33
Merge drm_kms_helper_poll_disable() and drm_kms_helper_poll_fini() code
into a common helper function.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/drm_probe_helper.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git
>From all the drivers using drm_bridge_connector only iMX/dcss and OMAP
DRM driver do a proper work of calling
drm_bridge_connector_en/disable_hpd() in right places. Rather than
teaching each and every driver how to properly handle
drm_bridge_connector's HPD, make that automatic.
Add two
Applied. Thanks!
Alex
On Mon, Oct 24, 2022 at 11:20 AM Nathan Chancellor wrote:
>
> Clang warns:
>
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c:686:3: error: variable 'data' is
> uninitialized when used here [-Werror,-Wuninitialized]
> data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
The rest of the code expects that master's device drvdata is the
struct msm_drm_private instance. Do not override the mdp5's drvdata.
Fixes: 6874f48bb8b0 ("drm/msm: make mdp5/dpu devices master components")
Signed-off-by: Dmitry Baryshkov
---
Abhinav, Rob, please pick this for -fixes.
This is
On 12/10/2022 15:02, Vinod Polimera wrote:
Update crtc retrieval from dpu_enc to dpu_enc connector state,
since new links get set as part of the dpu enc virt mode set.
The dpu_enc->crtc cache is no more needed, hence cleaning it as
part of this change.
Signed-off-by: Vinod Polimera
---
On 10/22/2022 3:46 PM, Oded Gabbay wrote:
The accelerator devices are exposed to user-space using a dedicated
major. In addition, they are represented in /dev with new, dedicated
device char names: /dev/accel/accel*. This is done to make sure any
user-space software that tries to open a graphic
Clang warns:
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c:686:3: error: variable 'data' is
uninitialized when used here [-Werror,-Wuninitialized]
data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
^~~~
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c:674:10: note: initialize the
Applied. Thanks!
Alex
On Sat, Oct 22, 2022 at 2:06 AM wangjianli wrote:
>
> Delete the redundant word 'the'.
>
> Signed-off-by: wangjianli
> ---
> drivers/gpu/drm/radeon/radeon_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
After the msm_iommu instance is created, the IOMMU domain is completely
handled inside the msm_iommu code. Move the iommu_domain_alloc() call
into the msm_iommu_new() to simplify callers code.
Reported-by: kernel test robot
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Fixed the
The function a6xx_create_address_space() is mostly a copy of
adreno_iommu_create_address_space() with added quirk setting. Reuse the
original function to do the work, while introducing the wrapper to set
the quirk.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 31
On Sat, Oct 22, 2022 at 2:02 AM wangjianli wrote:
>
> Delete the redundant word 'the'.
>
> Signed-off-by: wangjianli
Applied. Thanks!
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Mon, Oct 24, 2022 at 03:33:30PM +0300, Jani Nikula wrote:
> The connector->override_edid flag is strictly for EDID override debugfs
> management, and drivers have no business using it.
>
> The check for override_edid was added in commit 301906290553 ("drm/i915:
> Ignore TMDS clock limit for
Hi,
On 10/24/22 16:45, Rafael J. Wysocki wrote:
> On Mon, Oct 24, 2022 at 4:32 PM Hans de Goede wrote:
>>
>> Hi,
>>
>> On 10/24/22 16:12, Dmitry Osipenko wrote:
>>> Chromebooks don't have backlight in ACPI table, they suppose to use
>>> native backlight in this case. Check presence of the CrOS
On Mon, Oct 24, 2022 at 10:41 AM Oded Gabbay wrote:
>
> On Mon, Oct 24, 2022 at 4:55 PM Alex Deucher wrote:
> >
> > On Sat, Oct 22, 2022 at 5:46 PM Oded Gabbay wrote:
> > >
> > > In the last couple of months we had a discussion [1] about creating a new
> > > subsystem for compute accelerator
On 10/24/2022 1:52 AM, Dave Airlie wrote:
On Mon, 24 Oct 2022 at 17:23, Oded Gabbay wrote:
On Sun, Oct 23, 2022 at 3:40 PM Greg Kroah-Hartman
wrote:
On Sun, Oct 23, 2022 at 12:46:21AM +0300, Oded Gabbay wrote:
The accelerator devices will be exposed to the user space with a new,
dedicated
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