Re: [PATCH 4/5] drm/radeon: Don't register Thunderbolt eGPU with vga_switcheroo

On Fri, Feb 24, 2017 at 2:19 PM, Lukas Wunner wrote: > An external Thunderbolt GPU can neither drive the laptop's panel nor be > powered off by the platform, so there's no point in registering it with > vga_switcheroo. In fact, when the external GPU is runtime suspended, >

[PATCH 1/3] drm/msm: Remove msm_debugfs_cleanup()

Move the contents of msm_debugfs_cleanup() to msm_drm_uninit() to free up the drm_driver->debugfs_cleanup callback. Also remove the mdp_kms_funcs->debugfs_cleanup callback which has no users. Cc: robdcl...@gmail.com Signed-off-by: Noralf Trønnes ---

[PATCH 2/3] drm/debugfs: Remove the drm_driver.debugfs_cleanup callback

Remove the .debugfs_cleanup() callback now that all the users are gone. Signed-off-by: Noralf Trønnes --- drivers/gpu/drm/drm_debugfs.c | 5 - include/drm/drm_drv.h | 1 - 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/drm_debugfs.c

[PATCH 3/3] drm/qxl: Remove qxl_debugfs_remove_files()

drm_debugfs_cleanup() now removes all minor->debugfs_list entries automatically, so it's not necessary to call drm_debugfs_remove_files(). Cc: airl...@linux.ie Cc: kra...@redhat.com Signed-off-by: Noralf Trønnes --- drivers/gpu/drm/qxl/qxl_debugfs.c | 13 -

[PATCH 0/3] drm: debugfs: Remove all files automatically on cleanup part 2

This is a follow up that removes the drm_driver.debugfs_cleanup callback. Tegra is the only remaining user of drm_debugfs_remove_files(). Note: Patches are only compile tested. Noralf. Noralf Trønnes (3): drm/msm: Remove msm_debugfs_cleanup() drm/debugfs: Remove the

[Bug 99974] Pinned memory is extremely slow on Dolphin

https://bugs.freedesktop.org/show_bug.cgi?id=99974 --- Comment #1 from Marek Olšák --- Has it ever been fast? Even with a different GPU? -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing

Re: RFC: late drm pull requests and other topics

On Tue, Mar 7, 2017 at 10:56 AM, Alex Deucher wrote: > On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter wrote: >> Hi all, >> >> In the 4.11 drm pull request Linus raised a few things that we need to >> discuss: >> >> Late driver/enabling pull requests >>

[Bug 194731] drm general protection fault in drm_atomic_init

https://bugzilla.kernel.org/show_bug.cgi?id=194731 --- Comment #7 from Janpieter Sollie (janpieter.sol...@dommel.be) --- hello, I have some other news about this bug (if anyone is still interested): I rewrote the amdgpu-pro driver, as the amdgpu driver seems more complex, and I took one step

[PATCH 12/15] drm/sun4i: tcon: multiply the vtotal when not in interlace

It appears that the total vertical resolution needs to be doubled when we're not in interlaced. Make sure that is the case. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

[PATCH 14/15] ARM: sun5i: a10s: Add the HDMI controller node

The A10s has an HDMI controller connected to the second TCON channel. Add it to our DT. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s.dtsi | 34 - arch/arm/boot/dts/sun5i.dtsi | 1 +- 2 files changed, 35

[PATCH 13/15] drm/sun4i: Add HDMI support

The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI controller. That HDMI controller is able to do audio and CEC, but those have been left out for now. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/Makefile | 5 +-

[PATCH 15/15] ARM: sun5i: a10s-olinuxino: Enable HDMI

The A10s Olinuxino has an HDMI connector. Make sure we can use it. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 12 1 file changed, 12 insertions(+), 0 deletions(-) diff --git

[PATCH 2/15] clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate

The clocks might need to modify their parent clocks. In order to make that possible, give them access to the parent clock being evaluated, and to a pointer to the parent rate so that they can modify it if needed. Signed-off-by: Maxime Ripard ---

[PATCH 9/15] drm/sun4i: tcon: Pass the encoder to the mode set functions

The mode set function need some changes based on which encoder is being used. Make sure we can differentiate between our encoders by passing the encoder structure asking for the mode set. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_rgb.c | 2

Re: [PATCH 3/4] drm/exynos/decon5433: fix vblank event handling

Thanks for fixing it. Andrzej, DECON_CRFMID register is new to me. Where did you refer this register description from? I couldn't find this register in datasheet I have for Exynos5433. Below are a little bit trivial comments. 2017년 02월 23일 01:05에 Andrzej Hajda 이(가) 쓴 글: > Current

[PATCH 6/15] dt-bindings: display: sun4i: Add HDMI display bindings

One of the possible output of the display pipeline, on the SoCs that have it, is the HDMI controller. Add a binding for it. Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 21 +++- 1 file changed, 21

[PATCH 0/15] drm: sun4i: Add support for the HDMI controller

Hi, Here is an attempt at getting the HDMI controller running. This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s, A20, A31). This driver only supports for now the A10s because it was an easy target, being very close to the A13 that is already supported by our DRM

[PATCH 1/15] clk: divider: Make divider_round_rate take the parent clock

So far, divider_round_rate only considers the parent clock returned by clk_hw_get_parent. This works fine on clocks that have a single parents, this doesn't work on muxes, since we will only consider the first parent, while other parents may totally be able to provide a better combination.

[PATCH 8/15] drm/sun4i: tcon: Add channel debug

While all functions have debug logs, the channel enable and disable are not logged. Make sure this is the case. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 1 file changed, 4 insertions(+), 0 deletions(-) diff --git

[PATCH 7/15] dt-bindings: display: sun4i: Add allwinner, tcon-channel property

The Allwinner Timings Controller has two, mutually exclusive, channels. When the binding has been introduced, it was assumed that there would be only a single user per channel in the system. While this is likely for the channel 0 which only connects to LCD displays, it turns out that the channel

[PATCH 5/15] clk: sunxi-ng: sun5i: Export video PLLs

The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun5i.h | 6 -- include/dt-bindings/clock/sun5i-ccu.h | 3 +++ 2 files changed, 7

[PATCH 10/15] drm/sun4i: tcon: Switch mux on only for composite

Even though that mux is undocumented, it seems like it needs to be set to 1 when using composite, and 0 when using HDMI. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git

[PATCH 4/15] clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT

The current code only rely on the parent to change its rate in the case where CLK_SET_RATE_PARENT is set. However, some clock rates might be obtained only through a modification of the parent and the clock divider. Just rely on the round rate of the clocks to give us the best computation that

[PATCH 3/15] clk: sunxi-ng: div: Switch to divider_round_rate

divider_round_rate already evaluates changing the parent rate if CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's just use it. Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu_div.c | 25 ++--- 1 file changed,

[PATCH 11/15] drm/sun4i: tcon: Fix tcon channel 1 backporch calculation

It seems like what's called a backporch in the datasheet is actually the backporch plus the sync period. Fix that in our driver. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff

Re: [PATCH] drm/exynos/decon5433: implement frame counter

2017년 03월 02일 17:35에 Andrzej Hajda 이(가) 쓴 글: > Decon in Exynos5433 has frame counter, it can be used to implement > get_vblank_counter callback. > > Signed-off-by: Andrzej Hajda > --- > Hi Inki, > > The patch is based on my last patches, maybe to make it clear I will

Re: [Intel-gfx] [PATCH v1] drm/i915/bxt: use NULL for GPIO connection ID

On Tue, Mar 07, 2017 at 12:48:26PM +0200, Andy Shevchenko wrote: > On Sun, 2017-02-26 at 22:45 +0100, Daniel Vetter wrote: > > On Tue, Feb 21, 2017 at 06:52:24PM +0200, Andy Shevchenko wrote: > > > On Tue, 2017-02-21 at 18:26 +0200, Jani Nikula wrote: > > > > On Tue, 21 Feb 2017, Andy Shevchenko

Re: [PATCH 4/4] drm/exynos/decon5433: signal frame done interrupt at VSYNC

2017년 02월 23일 01:05에 Andrzej Hajda 이(가) 쓴 글: > DECON in case of video mode generates interrupt by default at start > of vertical back porch. As this interrupt is used to generate VBLANK > events more optimal point is start of vertical front porch. > > Signed-off-by: Andrzej Hajda

Re: [PATCH 3/4] drm/exynos/decon5433: fix vblank event handling

On 07.03.2017 10:12, Inki Dae wrote: > Thanks for fixing it. > > Andrzej, > DECON_CRFMID register is new to me. Where did you refer this register > description from? I couldn't find this register in datasheet I have for > Exynos5433. I have found it in android sources. > > Below are a little

Re: [PATCH v7 5/6] drm/i915: enable scrambling

On Fri, 2017-03-03 at 21:58 +0530, Shashank Sharma wrote: > Geminilake platform sports a native HDMI 2.0 controller, and is > capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec > mendates scrambling for these higher clocks, for reduced RF footprint. > > This patch checks if the monitor

[Bug 93687] ppc64el:Gallium / clover fails to compile

https://bugs.freedesktop.org/show_bug.cgi?id=93687 Andreas Boll changed: What|Removed |Added Resolution|NOTOURBUG |DUPLICATE

Re: [PATCH 1/15] clk: divider: Make divider_round_rate take the parent clock

On 03/07, Maxime Ripard wrote: > So far, divider_round_rate only considers the parent clock returned by > clk_hw_get_parent. > > This works fine on clocks that have a single parents, this doesn't work on > muxes, since we will only consider the first parent, while other parents > may totally be

[Bug 100058] amdgpu/dpm: NULL pointer dereference

https://bugs.freedesktop.org/show_bug.cgi?id=100058 --- Comment #7 from Adam Wolk --- Regarding the display flicking on/off (the effect feels like changing resolution - the way it goes out and back). This is completely mitigated by running DRI_PRIME=1 glxgears hence why I

Re: [Intel-gfx] Implementing Miracast

On 07/03/17 05:00, Daniel Kasak wrote: Any news on this? I'm also interested :) Dan Hmm, good question! I will ping internally and see if we are ready to release something as an RFC. Martin ___ dri-devel mailing list

Re: RFC: late drm pull requests and other topics

On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter wrote: > Hi all, > > In the 4.11 drm pull request Linus raised a few things that we need to > discuss: > > Late driver/enabling pull requests > -- > > Imo this isn't as one-sided as Linus made it

Re: RFC: late drm pull requests and other topics

On Tue, Mar 07, 2017 at 01:11:43AM +0100, Daniel Vetter wrote: > Hi all, > > In the 4.11 drm pull request Linus raised a few things that we need to > discuss: > > Late driver/enabling pull requests > -- > > Imo this isn't as one-sided as Linus made it sound,

[Bug 100058] amdgpu/dpm: NULL pointer dereference

https://bugs.freedesktop.org/show_bug.cgi?id=100058 --- Comment #8 from Alex Deucher --- Do the patches in bug 99387 help? -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list

[Bug 99387] Kernel 4.9: Kaveri + Hainan choked on boot using amdgpu

https://bugs.freedesktop.org/show_bug.cgi?id=99387 Alex Deucher changed: What|Removed |Added Resolution|--- |FIXED

Re: [PATCH 1/6] doc: Explain light-handed markup preference a bit better

On Thu, Mar 02, 2017 at 04:16:33PM +0100, Daniel Vetter wrote: > We already had a super-short blurb, but worth extending it I think: > We're still pretty far away from anything like a consensus, but > there's clearly a lot of people who prefer an as-light as possible > approach to converting

[PATCH 1/4] drm/msm: Fix wrong pointer check in a5xx_destroy

Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH 0/4] drm/msm: Fixes for 4.11

Hey Rob, here are a handful of things that might be fixable for 4.11 but if not consider them for -next. Jordan Jordan Crouse (4): drm/msm: Fix wrong pointer check in a5xx_destroy drm/msm: Don't increase priv->num_aspaces until we know that it fits drm/msm: Pass interrupt status to

[PATCH 4/4] drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR section while maintaining backwards compatibility for tools that only understand 32 bit iovas. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_rd.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[PATCH 2/4] drm/msm: Don't increase priv->num_aspaces until we know that it fits

priv->num_aspaces is increased and then checked to see if it still fits in the priv->aspace array. If it doesn't, we warn and exit but priv->num_aspaces remains incremented. Don't incremement the count until we know that it fits in the array. Signed-off-by: Jordan Crouse

[PATCH 02/11] drm/msm: Improve the zap shader

Simply the code, use snprintf correct and make sure that we memset the rest of the segment if the memory size in the ELF file is larger than the file size. Signed-off-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 +-

[PATCH 04/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the user sets 'hint' to non-zero it means that they want a IOVA for the GEM object instead of a mmap() offset. Return the iova in the 'offset' member. Signed-off-by: Jordan Crouse ---

[v2] [PATCH 00/11] drm/msm: A5XX preemption

Here is v2 of the preemption series - Changes: * Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov) * Removed preemption worker and fixed atomics (Thanks Stephen Boyd) * Various fixes and improvements based on testing Thanks! Jordan Jordan Crouse (11): drm/msm: Make sure to

[PATCH] gpu: host1x: Fix syncpt array index check

The index overflow check in host1x_syncpt_get was incorrect, and would return a pointer past the syncpt array if the syncpt index given was the total number of syncpts. Fix this. Signed-off-by: Mikko Perttunen --- drivers/gpu/host1x/syncpt.c | 6 +++--- 1 file changed, 3

Re: [PATCH 0/2] Documentation/EDID fixes

On Mon, 06 Mar 2017, Javi Merino wrote: > I found these two minor issues while building an EDID. I'm not sure > whether the second patch (Add O= to support) is upstream material, but > I'm sending it just in case. I'm not opposed to fixing existing issues like this, but

[PATCH v3 1/6] drm: bridge: dw-hdmi: Extract PHY interrupt setup to a function

From: Laurent Pinchart In preparation for adding PHY operations to handle RX SENSE and HPD, group all the PHY interrupt setup code in a single location and extract it to a separate function. Signed-off-by: Laurent Pinchart

Re: RFC: late drm pull requests and other topics

On Tue, 07 Mar 2017, Daniel Vetter wrote: > Hi all, > > In the 4.11 drm pull request Linus raised a few things that we need to > discuss: > > Late driver/enabling pull requests > -- > > Imo this isn't as one-sided as Linus made it sound, we've had

[PATCH v3 6/6] drm: bridge: dw-hdmi: Move HPD handling to PHY operations

The HDMI TX controller support HPD and RXSENSE signaling from the PHY via it's STAT0 PHY interface, but some vendor PHYs can manage these signals independently from the controller, thus these STAT0 handling should be moved to PHY specific operations and become optional. The existing STAT0 HPD and

[PATCH v3 4/6] drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

Some display pipelines can only provide non-RBG input pixels to the HDMI TX Controller, this patch takes the pixel format from the plat_data if provided. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 322 +-

Re: RFC: late drm pull requests and other topics

On Tue, 07 Mar 2017, Sean Paul wrote: > On Tue, Mar 07, 2017 at 01:11:43AM +0100, Daniel Vetter wrote: >> Linus shitting on dri-devel >> --- >> > IMO, the best approach is to do exactly what danvet did last time: > praise the contributor for their

Re: [PATCH 1/6] doc: Explain light-handed markup preference a bit better

On Tue, 7 Mar 2017 17:40:35 +0100 Daniel Vetter wrote: > Jon, can you pls pick this one up, or want me to resend stand-alone? I got it; I should get both applied before too long. jon ___ dri-devel mailing list

[PATCH v3 2/6] media: uapi: Add RGB and YUV bus formats for Synopsys HDMI TX Controller

In order to describe the RGB and YUB bus formats used to feed the Synopsys DesignWare HDMI TX Controller, add missing formats to the list of Bus Formats. Documentation for these formats is added in a separate patch. Signed-off-by: Neil Armstrong ---

[PATCH v3 5/6] drm: bridge: dw-hdmi: Add Documentation on supported input formats

This patch adds a new DRM documentation entry and links to the input format table added in the dw_hdmi header. Signed-off-by: Neil Armstrong --- Documentation/gpu/dw-hdmi.rst | 15 +++ Documentation/gpu/index.rst | 1 + 2 files changed, 16 insertions(+)

[PATCH v3 3/6] documentation: media: Add documentation for new RGB and YUV bus formats

Add documentation for added Bus Formats to describe RGB and YUS formats used as input to the Synopsys DesignWare HDMI TX Controller. Signed-off-by: Neil Armstrong --- Documentation/media/uapi/v4l/subdev-formats.rst | 4992 ++- 1 file changed, 3963

[PATCH v3 0/6] drm: bridge: dw-hdmi: Add support for Custom PHYs

The Amlogic GX SoCs implements a Synopsys DesignWare HDMI TX Controller in combination with a very custom PHY. Thanks to Laurent Pinchart's changes, the HW report the following : Detected HDMI TX controller v2.01a with HDCP (Vendor PHY) The following differs from common PHY integration as

[PATCH 08/11] drm/msm: Support multiple ringbuffers

Add the infrastructure to support the idea of multiple ringbuffers. Assign each ringbuffer an id and use that as an index for the various ring specific operations. The biggest delta is to support legacy fences. Each fence gets its own sequence number but the legacy functions expect to use a

[PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

We should be detaching the MMU before destroying the address space. To do this cleanly, the detach has to happen in adreno_gpu_cleanup() because it needs access to structs in adreno_gpu.c. Plus it is better symmetry to have the attach and detach at the same code level. Signed-off-by: Jordan

[PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

We use a global ringbuffer size and block size for all targets and at least for 5XX preemption we need to know the value the RB_CNTL in several locations so it makes sense to caculate it once and use it everywhere. The only monkey wrench is that we need to disable the RPTR shadow for A430 targets

[PATCH 11/11] drm/msm: Implement preemption for A5XX targets

Implement preemption for A5XX targets - this allows multiple ringbuffers for different priorities with automatic preemption of a lower priority ringbuffer if a higher one is ready. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/Makefile | 1 +

[PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

Add a shadow pointer to track the current command being written into the ring. Don't commit it as 'cur' until the command is submitted. Because 'cur' is used to construct the software copy of the wptr this ensures that somebody peeking in on the ring doesn't assume that a command is inflight while

[PATCH 03/11] drm/msm: Remove idle function hook

There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 -

[PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse ---

[PATCH 07/11] drm/msm: Remove memptrs->wptr

memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 2 files changed, 4 deletions(-) diff --git

[PATCH 5/6] drm/msm: gpu: Use OPP tables if we can

If a OPP table is defined for the GPU device in the device tree use that in lieu of the downstream style GPU frequency table. If we do use the downstream table convert it to a OPP table so that we can take advantage of the OPP lookup facilities later. Signed-off-by: Jordan Crouse

[PATCH 6/6] msm/drm: gpu: Dynamically locate the clocks from the device tree

Instead of using a fixed list of clock names use the clock-names list in the device tree to discover and get the list of clocks that we need. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_gpu.c | 76 ++-

[PATCH 2/6] drm/msm: Reference count address spaces

There are reasons for a memory object to outlive the file descriptor that created it and so the address space that a buffer object is attached to must also outlive the file descriptor. Reference count the address space so that it can remain viable until all the objects have released their

[PATCH 4/6] drm/msm: Hard code the GPU "slow frequency"

Some A3XX and A4XX GPU targets required that the GPU clock be programmed to a non zero value when it was disabled so 27Mhz was chosen as the "invalid" frequency. Even though newer targets do not have the same clock restrictions we still write 27Mhz on clock disable and expect the clock subsystem

[PATCH 3/6] drm/msm: Add MSM_PARAM_GMEM_BASE

User space needs to know where the GMEM whole starts so that they can set up the addressing correctly. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++ include/uapi/drm/msm_drm.h | 1 + 2 files changed, 4 insertions(+) diff

[PATCH 0/6] drm/msm: New features for 4.12

Hey Rob - here are a handful of new features and more extensive bug fixes that might be suitable for 4.12. Of note is the reference count for address spaces which is a pre-requisite for per-instance pagetables and the move to OPP tables which is a stepping stone for all sorts of clock related

[PATCH 1/6] drm/msm: Don't allow zero sized buffer objects

Zero sized buffer objects tend to make various bits of the GEM infrastructure complain: WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 drm_mm_insert_node_generic+0x258/0x2f0 Modules linked in: CPU: 1 PID: 2323 Comm: drm-api-test Tainted: GW 4.9.0-rc4-00906-g693af44 #213

[PATCH 2/6] drm/msm: Pass the MMU domain index in struct msm_file_private

Pass the index of the MMU domain in struct msm_file_private instead of assuming gpu->id throughout the submit path. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_drv.c| 2 ++ drivers/gpu/drm/msm/msm_drv.h| 6 +-

[PATCH 1/6] drm/msm: Enable 64 bit mode by default

A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers and the microcode use 64 bit virtual addressing in either case but the upper 32 bits are ignored if the GPU is in 32 bit mode. There is no performance disadvantage to remaining in 64 bit mode even if we are only generating 32 bit

[PATCH 4/6] drm/msm: Use TTBR1 for kernel side GPU buffer objects

Use a TTBR1 pagetable for the GPU IOMMU domain and map all the GPU kernel side buffer objects into that range. This will make it easier to switch out TTBR0 for per-process pagetables. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18

[PATCH 3/6] drm/msm: Make separate iommu function tables for v1 and v2 MMUs

Since we have the infrastructure for IOMMU function tables it makes sense to use it to differentiate between v1 and v2 targets. It adds a bit more infrastructure but it also gives us the freedom to expand on each flavor (especially v2) for things like dynamic domains. Signed-off-by: Jordan Crouse

[PATCH 0/6] drm/msm: Add per-instance pagetables

Using the framework described here https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html This implements per-instance pagetables for the GPU driver creating an individual pagetable for each file descriptor (so not strictly per-process but in practice we can't share buffers

[PATCH 6/6] drm/msm: a5xx: Support per-instance pagetables

Support per-instance pagetables for 5XX targets. Per-instance pagetables allow each open DRM instance to have its own VM memory space to prevent accidently or maliciously copying or overwriting buffers from other instances. It also opens the door for SVM since any given CPU side address can be

[PATCH 5/6] drm/msm: Support dynamic IOMMU domains

Dynamic IOMMU domains allow multiple pagetables to be attached to the same IOMMU device. These can be used by smart devices like the GPU that can switch the pagetable dynamically between DRM instances. Add support for dynamic IOMMU domains if they are enabled and supported by your friendly

[Bug 100104] Gallium-9 hitting LLVM assert when trying to start EVE-Online

https://bugs.freedesktop.org/show_bug.cgi?id=100104 Bug ID: 100104 Summary: Gallium-9 hitting LLVM assert when trying to start EVE-Online Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All)

Re: [PATCH v3 3/4] drm/imx: don't wait for vblank and stop calling cleanup_planes in commit_tail

Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel: > drm_atomic_helper_cleanup_planes only calls the cleanup_fb plane > helpers, which we don't implement as a CMA framebuffer based driver. > There is no reason to wait for vblanks in commit_tail only to do nothing > afterwards. > >

Re: [PATCH v3 4/4] drm/imx: add deferred plane disabling

Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel: > The DP (display processor) channel disable code tried to busy wait for > the DP sync flow end interrupt status bit when disabling the partial > plane without a full modeset. That never worked reliably, and it was > disabled

[Bug 100071] [Regression] Tomb Raider: TressFX broken with recent LLVM

https://bugs.freedesktop.org/show_bug.cgi?id=100071 --- Comment #2 from Marek Olšák --- Not sure but this might help: https://reviews.llvm.org/D30717 -- You are receiving this mail because: You are the assignee for the bug.___

Re: [PATCH v10 3/3] arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board

On Wed, Feb 22, 2017 at 10:09:54AM +0900, Hoegeun Kwon wrote: > From: Hyungwon Hwang > > This patch add the panel device tree node for S6E3HA2 display > controller to TM2 dts. > > Signed-off-by: Hyungwon Hwang > Signed-off-by: Andrzej Hajda

Re: [Intel-gfx] [PATCH v1] drm/i915/bxt: use NULL for GPIO connection ID

On Sun, 2017-02-26 at 22:45 +0100, Daniel Vetter wrote: > On Tue, Feb 21, 2017 at 06:52:24PM +0200, Andy Shevchenko wrote: > > On Tue, 2017-02-21 at 18:26 +0200, Jani Nikula wrote: > > > On Tue, 21 Feb 2017, Andy Shevchenko > > l.co > > > m> wrote: > > > > The

Re: [PATCH v3 4/6] drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

Hi Neil, On 07-03-2017 16:42, Neil Armstrong wrote: > Some display pipelines can only provide non-RBG input pixels to the HDMI TX > Controller, this patch takes the pixel format from the plat_data if provided. > > Signed-off-by: Neil Armstrong > --- >

Re: [PATCH v3 6/6] drm: bridge: dw-hdmi: Move HPD handling to PHY operations

Hi Neil, On 07-03-2017 16:42, Neil Armstrong wrote: > The HDMI TX controller support HPD and RXSENSE signaling from the PHY > via it's STAT0 PHY interface, but some vendor PHYs can manage these > signals independently from the controller, thus these STAT0 handling > should be moved to PHY

Re: linux-next: manual merge of the sunxi tree with the drm-misc tree

On Tue, Mar 7, 2017 at 7:59 AM, Stephen Rothwell wrote: > Hi all, > > Today's linux-next merge of the sunxi tree got a conflict in: > > drivers/gpu/drm/sun4i/sun4i_drv.c > > between commit: > > 50480a78e282 ("drm: sun4i: use vblank hooks in struct drm_crtc_funcs") > >

Re: [PATCH 0/2] Documentation/EDID fixes

On Tue, Mar 07, 2017 at 06:16:51PM +0200, Jani Nikula wrote: > On Mon, 06 Mar 2017, Javi Merino wrote: > > I found these two minor issues while building an EDID. I'm not sure > > whether the second patch (Add O= to support) is upstream material, but > > I'm sending it

Re: [linux-sunxi] [PATCH 5/15] clk: sunxi-ng: sun5i: Export video PLLs

Hi Maxime, On Tue, Mar 7, 2017 at 7:56 PM, Maxime Ripard wrote: > The video PLLs are used directly by the HDMI controller. Export them so > that we can use them in our DT node. > > Signed-off-by: Maxime Ripard > --- >

Re: [PATCH 12/15] drm/sun4i: tcon: multiply the vtotal when not in interlace

Hi, On Tue, Mar 7, 2017 at 4:56 PM, Maxime Ripard wrote: > It appears that the total vertical resolution needs to be doubled when > we're not in interlaced. Make sure that is the case. This is true for both channels, though we handle them differently. > >

Re: [PATCH v3 1/6] drm: bridge: dw-hdmi: Extract PHY interrupt setup to a function

Hi Neil, On 07-03-2017 16:42, Neil Armstrong wrote: > From: Laurent Pinchart > > In preparation for adding PHY operations to handle RX SENSE and HPD, > group all the PHY interrupt setup code in a single location and extract > it to a separate function.

Re: [PATCH 6/6] drm/msm: a5xx: Support per-instance pagetables

On Tue, Mar 07, 2017 at 10:14:20AM -0700, Jordan Crouse wrote: > Support per-instance pagetables for 5XX targets. Per-instance > pagetables allow each open DRM instance to have its own VM memory > space to prevent accidently or maliciously copying or overwriting > buffers from other instances. It

Re: [PATCH 00/19] drm: debugfs: Remove all files automatically on cleanup

On Mon, Jan 30, 2017 at 10:10:15AM +0100, Thierry Reding wrote: > On Mon, Jan 30, 2017 at 10:03:44AM +0100, Daniel Vetter wrote: > > On Mon, Jan 30, 2017 at 09:58:48AM +0100, Thierry Reding wrote: > > > On Fri, Jan 27, 2017 at 03:05:46PM +0100, Daniel Vetter wrote: > > > > On Fri, Jan 27, 2017 at

Re: [PATCH v4 1/7] drm: Add DRM support for tiny LCD displays

On Sat, Feb 11, 2017 at 07:48:52PM +0100, Noralf Trønnes wrote: > +const struct file_operations tinydrm_fops = { > + .owner = THIS_MODULE, > + .open = drm_open, > + .release= drm_release, > + .unlocked_ioctl = drm_ioctl, > +#ifdef CONFIG_COMPAT > +

[Bug 100089] Space Run rendering prolems

https://bugs.freedesktop.org/show_bug.cgi?id=100089 LunarG changed: What|Removed |Added QA Contact|intel-3d-bugs@lists.freedes |dri-devel@lists.freedesktop

[Bug 100095] [Regression] Volumetric lighting result in white surface

https://bugs.freedesktop.org/show_bug.cgi?id=100095 --- Comment #1 from Marek Olšák --- Not sure but this might help: https://reviews.llvm.org/D30717 -- You are receiving this mail because: You are the assignee for the bug.___

Re: [PATCH 3/4] drm/exynos/decon5433: fix vblank event handling

2017년 03월 07일 18:58에 Andrzej Hajda 이(가) 쓴 글: > On 07.03.2017 10:12, Inki Dae wrote: >> Thanks for fixing it. >> >> Andrzej, >> DECON_CRFMID register is new to me. Where did you refer this register >> description from? I couldn't find this register in datasheet I have for >> Exynos5433. > > I

linux-next: build failure after merge of the rcu tree

Hi Paul, After merging the rcu tree, today's linux-next build (x86_64 allmodconfig) failed like this: In file included from include/linux/resource_ext.h:19:0, from include/linux/pci.h:32, from include/drm/drmP.h:50, from

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