On 5/17/2023 4:53 PM, Abhinav Kumar wrote:
On 5/14/2023 10:06 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:39, Abhinav Kumar
wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF
There are two tiers of pending flush control, main controller and
individual hardware block. Currently only the main controller of
flush mask is reset to 0 but leave out some individual pending flush
mask of particular hardware block keep previous value at
clear_pending_flush(). Reset all
From: Abhinav Kumar
Add DSC 1.2 hardware blocks to the catalog with necessary sub-block and
feature flag information. Each display compression engine (DCE) contains
dual DSC encoders so both share same base address but with its own
different sub block address.
changes in v4:
-- delete
Unset DSC_ACTIVE bit at dpu_hw_ctl_reset_intf_cfg_v1(),
dpu_encoder_unprep_dsc() and dpu_encoder_dsc_pipe_clr() functions
to tear down DSC data path if DSC data path was setup previous.
Changes in V10:
-- pass ctl directly instead of dpu_enc to dsc_pipe_cfg()
-- move both dpu_encoder_unprep_dsc()
Add support for DSC 1.2 by providing the necessary hooks to program
the DPU DSC 1.2 encoder.
Changes in v3:
-- fixed kernel test rebot report that "__iomem *off" is declared but not
used at dpu_hw_dsc_config_1_2()
-- unrolling thresh loops
Changes in v4:
-- delete DPU_DSC_HW_REV_1_1
-- delete
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine was moved to INTF with the help of the flush mechanism.
Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
dpu_hw_pp_setup_dsc() and
Disabling the crossbar mux between DSC and PINGPONG currently
requires a bogus enum dpu_pingpong value to be passed when calling
dsc_bind_pingpong_blk() with enable=false, even though the register
value written is independent of the current PINGPONG block. Replace
that `bool enable` parameter
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires
both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be
executed to complete DSC configuration if DSC hardware block is present.
Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions
to the
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same time to make it
consistent with the location
On Thu, May 18, 2023 at 7:29 PM Fabio Estevam wrote:
>
> Hi Adam,
>
> On Thu, May 18, 2023 at 8:06 PM Adam Ford wrote:
> >
> > This series fixes the blanking pack size and the PMS calculation. It then
> > adds support to allows the DSIM to dynamically DPHY clocks, and support
> > non-burst mode
Writeback was the last user of dpu_encoder_phys_ops's atomic_check()
callback. As the code was moved to the dpu_writeback.c, the callback
becomes unused. Drop it now.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ---
The writeback backend of the dpu_encoder is the only user of the
dpu_encoder_phys_ops::atomic_check() callback. Move corresponding code
to the DPU's drm_writeback_connector implementation (dpu_writeback.c)
and drop corresponding callback code.
Dependency chanin:
-
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.
Signed-off-by: Dmitry Baryshkov
---
.../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 54
Fix a wrong error return by dropping an error return.
When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
then only what we have to is to free ctx->raw_edid so that driver removing
can work correctly - it's not an error case.
Signed-off-by: Inki Dae
---
On 5/18/2023 3:37 PM, Dmitry Baryshkov wrote:
On Fri, 19 May 2023 at 01:17, Jessica Zhang wrote:
On 5/17/2023 5:19 PM, Dmitry Baryshkov wrote:
On 16/05/2023 23:20, Jessica Zhang wrote:
Add support for the 1080x2340 Visionox R66451 AMOLED DSI panel that
comes with the Qualcomm HDK8350
Hi Adam,
On Thu, May 18, 2023 at 8:06 PM Adam Ford wrote:
>
> This series fixes the blanking pack size and the PMS calculation. It then
> adds support to allows the DSIM to dynamically DPHY clocks, and support
> non-burst mode while allowing the removal of the hard-coded clock values
> for the
Remove intf_idx and wb_idx fields from struct dpu_encoder_phys and
struct dpu_enc_phys_init_params. Set the hw_intf and hw_wb directly and
use them to get the instance index.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 72
There is no need to assign a result to temp varable just to return it
two lines below. Drop the temporary variable.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
There is no need to assign a result to temp varable just to return it
after a goto. Drop the temporary variable and goto and return the result
directly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 10 ++
1 file changed, 2 insertions(+), 8
Hi Krzysztof,
On Thu, May 11, 2023 at 07:54:46PM +0200, Krzysztof Kozlowski wrote:
> Statically allocated array of pointers to hwmon_channel_info can be made
> const for safety.
>
> Acked-by: Jani Nikula
> Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Andi Shyti
Andi
gt;ctx_mgr);
| ^
Caused by commit
2458393a4e98 ("drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure")
I have used the amdgpu tree from next-20230518 for today.
The Starry-himax83102-j02 panel is a TDDI IC. From the datasheet[1],
it seems that the touch can communicate successfully only when the RST
signal is high. Since i2c_hid_core_probe comes after boe_panel_prepare
let's set the default high for RST at boe_panel_add.
[1]:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
downstream for quite sometime. So most of the
Hi,
> -Original Message-
> From: dri-devel On Behalf Of Uwe
> Kleine-Konig
> Sent: Monday, May 15, 2023 6:16 PM
> To: Inki Dae
> Cc: linux-samsung-...@vger.kernel.org; Jingoo Han ;
> Seung-Woo Kim ; Kyungmin Park
> ; dri-devel@lists.freedesktop.org; Krzysztof
> Kozlowski ;
In order to support variable DPHY timings, it's necessary
to enable GENERIC_PHY_MIPI_DPHY so phy_mipi_dphy_get_default_config
can be used to determine the nominal values for a given resolution
and refresh rate.
Signed-off-by: Adam Ford
Tested-by: Frieder Schrempf
Reviewed-by: Frieder Schrempf
The DPHY timings are currently hard coded. Since the input
clock can be variable, the phy timings need to be variable
too. To facilitate this, we need to cache the hs_clock
based on what is generated from the PLL.
The phy_mipi_dphy_get_default_config_for_hsclk function
configures the DPHY
On 19/05/2023 02:33, Kuogee Hsieh wrote:
Currently DSC flushing happens during interface configuration at
dpu_hw_ctl_intf_cfg_v1(). Separate DSC flush away from
dpu_hw_ctl_intf_cfg_v1() by adding dpu_hw_ctl_update_pending_flush_dsc_v1()
to handle both per-DSC engine and DSC flush bits at same
This series fixes the blanking pack size and the PMS calculation. It then
adds support to allows the DSIM to dynamically DPHY clocks, and support
non-burst mode while allowing the removal of the hard-coded clock values
for the PLL for imx8m mini/nano/plus, and it allows the removal of the
According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
and max values for M and the frequency range for the VCO_out
calculator were incorrect. This information was contradicted in other
parts of the mini, nano and plus manuals. After reaching out to my
NXP Rep, when confronting
Make the pll-clock-frequency optional. If it's present, use it
to maintain backwards compatibility with existing hardware. If it
is absent, read clock rate of "sclk_mipi" to determine the rate.
Since it can be optional, change the message from an error to
dev_info.
Signed-off-by: Adam Ford
From: Lucas Stach
Scale the blanking packet sizes to match the ratio between HS clock
and DPI interface clock. The controller seems to do internal scaling
to the number of active lanes, so we don't take those into account.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
Tested-by: Chen-Yu
The high-speed clock is hard-coded to the burst-clock
frequency specified in the device tree. However, when
using devices like certain bridge chips without burst mode
and varying resolutions and refresh rates, it may be
necessary to set the high-speed clock dynamically based
on the desired pixel
This series adds the DPU side changes to support DSC 1.2 encoder. This
was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor.
The DSI and DP parts will be pushed later on top of this change.
This seriel is rebase on [1], [2] and catalog fixes from rev-4 of [3].
[1]:
From: Abhinav Kumar
Some platforms have DSC blocks which have not been declared in the catalog.
Complete DSC 1.1 support for all platforms by adding the missing blocks to
MSM8998 and SC8180X.
Changes in v9:
-- add MSM8998 and SC8180x to commit titil
Changes in v10:
-- fix grammar at commit
| ctx->ctx_mgr = &(fpriv->ctx_mgr);
| ^
Caused by commit
2458393a4e98 ("drm/amdgpu: keep amdgpu_ctx_mgr in ctx structure")
I have used the amdgpu tree from next-20230518 for today.
--
Cheers,
Stephen Rothwell
pgp8QV8SOcZyQ.pgp
Descript
Hi Inki,
On Fri, May 19, 2023 at 09:04:07AM +0900, Inki Dae wrote:
> Fix a wrong error return by dropping an error return.
>
> When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
> then only what we have to is to free ctx->raw_edid so that driver removing
> can work
Hi Andi, :)
> -Original Message-
> From: Andi Shyti
> Sent: Friday, May 19, 2023 9:27 AM
> To: Inki Dae
> Cc: dri-devel@lists.freedesktop.org; linux-samsung-...@vger.kernel.org; Andi
> Shyti
> Subject: Re: [PATCH] drm/exynos: vidi: fix a wrong error return
>
> Hi Inki,
>
> On Fri,
On 19/05/2023 02:46, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Up to now the driver has been using encoder to allocate hardware
resources. Switch it to use CRTC id in preparation for the next step.
This decision to use encoder id instead of CRTC has been there
Rework dpu_encoder initialization code, simplifying calling sequences
and separating common init parts.
Changes since v1:
- Withdrawn two pathes for a later consideration
- Changed dpu_encoder_phys_init() to return void (Abhinav)
- Added small simplifications of dpu_encoder_phys_cmd_init() and
The function dpu_encoder_get_wb() returns controller_id if the
corresponding WB is present in the catalog. We can inline this function
and rely on dpu_rm_get_wb() returning NULL for indices for which the
WB is not present on the device.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
There is little sense to get intf index just to call dpu_rm_get_intf()
on it. Move dpu_rm_get_intf() call to dpu_encoder_get_intf() function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 20
1 file changed, 8
There is no reason to split the dpu_encoder interface into separate
_init() and _setup() phases. Merge them into a single function.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 55 +
Move common DPU physical encoder initialization code to the new function
dpu_encoder_phys_init().
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 29 +--
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 3 ++
Hi Inki,
On Fri, May 19, 2023 at 02:26:40AM +0200, Andi Shyti wrote:
> Hi Inki,
>
> On Fri, May 19, 2023 at 09:04:07AM +0900, Inki Dae wrote:
> > Fix a wrong error return by dropping an error return.
> >
> > When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info
> > then
From: Fei Yang
To comply with the design that buffer objects shall have immutable
cache setting through out their life cycle, {set, get}_caching ioctl's
are no longer supported from MTL onward. With that change caching
policy can only be set at object creation time. The current code
applies a
From: Fei Yang
The design is to keep Buffer Object's caching policy immutable through
out its life cycle. This patch ends the support for set caching ioctl
from MTL onward. While doing that we also set BO's to be 1-way coherent
at creation time because GPU is no longer automatically snooping CPU
From: Fei Yang
This series introduce a new extension for GEM_CREATE,
1. end support for set caching ioctl [PATCH 1/2]
2. add set_pat extension for gem_create [PATCH 2/2]
v2: drop one patch that was merged separately
commit 341ad0e8e254 ("drm/i915/mtl: Add PTE encode function")
v3: rebased
Il 09/05/23 17:07, Jason-JH.Lin ha scritto:
1. Move output drm connector from each ddp_path array to connector array.
2. Add dynamic select available connector flow in crtc create and enable.
Signed-off-by: Nancy Lin
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
---
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after
programming the actual table to avoid potential visual glitches during
table modification.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 -
1
Add support for 12-bit gamma lookup tables and introduce the first
user for it: MT8195.
While at it, also reorder the variables in mtk_gamma_set_common()
and rename `lut_base` to `lut0_base` to improve readability.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
Use drm_color_lut_extract() to avoid open-coding the bits reduction
calculations for each color channel and use a struct drm_color_lut
to temporarily store the information instead of an array of u32.
Also, slightly improve the precision of the HW LUT calculation in the
LUT DIFF case by performing
All of the SoCs that don't have dithering control in the gamma IP
have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is
"descending" (bit set) or "rising" (bit cleared): make sure to set
it correctly after programming the LUT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by:
Newer Gamma IP have got multiple LUT banks: support specifying the
size of the LUT banks and handle bank-switching before programming
the LUT in mtk_gamma_set_common() in preparation for adding support
for MT8195 and newer SoCs.
Suggested-by: Jason-JH.Lin
[Angelo: Refactored original commit]
Newer SoCs support a bigger Gamma LUT table: wire up a callback
to retrieve the correct LUT size for each different Gamma IP.
Co-developed-by: Jason-JH.Lin
Signed-off-by: Jason-JH.Lin
[Angelo: Rewritten commit message/description + porting]
Signed-off-by: AngeloGioacchino Del Regno
Renesas PMIC RAA215300 exposes two separate i2c devices, one for the main
device and another for rtc device.
Enhance i2c_new_ancillary_device() to instantiate a real device.
(eg: Instantiate rtc device from PMIC driver)
Added helper function __i2c_new_dummy_device to share the code
between
On Tue, May 16, 2023 at 5:27 AM Adam Ford wrote:
>
> According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
> and max values for M and the frequency range for the VCO_out
> calculator were incorrect. This information was contradicted in other
> parts of the mini, nano and plus
On Tue, May 16, 2023 at 5:27 AM Adam Ford wrote:
>
> Make the pll-clock-frequency optional. If it's present, use it
> to maintain backwards compatibility with existing hardware. If it
> is absent, read clock rate of "sclk_mipi" to determine the rate.
> Since it can be optional, change the
In case you were waiting for me looking at the rest of the series, there
was this reply from the previous round I can expand on.
On 02/05/2023 08:50, Tvrtko Ursulin wrote:
On 01/05/2023 17:58, Rob Clark wrote:
On Fri, Apr 28, 2023 at 4:05 AM Tvrtko Ursulin
wrote:
On 27/04/2023 18:53,
On Wed, 10 May 2023, Maximilian Weigand wrote:
> From: Maximilian Weigand
>
> Use backlight_is_blank() to determine if the led strings should be turned
> off in the update_status() functions of both strings.
>
> Reviewed-by: Daniel Thompson
I moved this tag to the correct place and ...
>
On 2023-05-17 18:14:31, Jessica Zhang wrote:
> Introduce MSM-specific DSC helper methods, as some calculations are
> common between DP and DSC.
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Marijn Suijten
Thanks!
> ---
> drivers/gpu/drm/msm/msm_dsc_helper.h | 38
>
Il 09/05/23 17:07, Jason-JH.Lin ha scritto:
Add DSI as main display output for mt8188 vdosys0.
Signed-off-by: Nathan Lu
Signed-off-by: Jason-JH.Lin
Reviewed-by: Matthias Brugger
---
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
Changes in v4:
- Fixed assignment typo appeared in v3
Changes in v3:
- Fixed issues due to variables renaming during cleanup (oops)
- This is actually the right series, since v2 was taken from the
wrong kernel tree :-)
Changes in v2:
- Added explicit inclusion of linux/bitfield.h in
Invert the check for state->gamma_lut and move it at the beginning
of the function to reduce indentation: this prepares the code for
keeping readability on later additions.
This commit brings no functional changes.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
From: "Jason-JH.Lin"
Adjust the parameters in mtk_drm_gamma_set_common()
- add (struct device *dev) to get lut_diff from gamma's driver data
- remove (bool lut_diff) and use false as default value in the function
Signed-off-by: Jason-JH.Lin
Signed-off-by: AngeloGioacchino Del Regno
---
Make the code more robust and improve readability by using bitfield
macros instead of open coding bit operations.
While at it, also add a definition for LUT_BITS_DEFAULT.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41
New SoCs, like MT8195, not only may support bigger lookup tables, but
have got a different register layout to support bigger precision:
support specifying the number of `lut_bits` for each SoC and use it
in mtk_gamma_set_common() to perform the right calculation.
Signed-off-by: AngeloGioacchino
Disable relay mode at the end of LUT programming to make sure that the
processed image goes through.
Signed-off-by: AngeloGioacchino Del Regno
Reviewed-by: Jason-JH.Lin
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4
1 file changed, 4 insertions(+)
diff --git
On Tue, May 16, 2023 at 5:27 AM Adam Ford wrote:
>
> From: Lucas Stach
>
> Scale the blanking packet sizes to match the ratio between HS clock
> and DPI interface clock. The controller seems to do internal scaling
> to the number of active lanes, so we don't take those into account.
>
>
Le 17/05/2023 à 20:33, Hamza Mahfooz a écrit :
get_available_dsc_slices() returns the number of indices set, and all of
the users of get_available_dsc_slices() don't cross the returned bound
when iterating over available_slices[]. So, the memset() in
get_available_dsc_slices() is redundant and
On 2023-05-17 16:22:37, Abhinav Kumar wrote:
> >> @@ -529,6 +539,19 @@ static const struct dpu_pingpong_sub_blks
> >> sc7280_pp_sblk = {
> >>.features = _features, \
> >>}
> >>
> >> +/*
> >> + * NOTE: Each display compression engine (DCE) contains dual hard
> >> + * slice DSC encoders
Hello,
syzbot tried to test the proposed patch but the build/boot failed:
failed to apply patch:
checking file drivers/usb/core/urb.c
patch: unexpected end of file in patch
Tested on:
commit: a4422ff2 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
git tree:
* syzbot :
> syzbot found the following issue on:
>
> HEAD commit:a4422ff22142 usb: typec: qcom: Add Qualcomm PMIC Type-C dr..
> git tree:
> https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
> console output:
On 5/17/2023 10:26 PM, Jeffrey Hugo wrote:
From: Tom Rix
clang static analysis reports
drivers/accel/qaic/qaic_data.c:610:2: warning: Undefined or garbage
value returned to caller [core.uninitialized.UndefReturn]
return ret;
^~
From a code analysis of the
On 2023-05-18 03:35:31, Dmitry Baryshkov wrote:
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > index 6292002..d5f3ef8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
On 04.04.2023 13:10, Maxime Ripard wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The SAM9x5 main clock implements a mux with a set_parent hook, but
> doesn't provide a determine_rate implementation.
>
> This is a bit odd, since
On Wed, May 17 2023 at 05:50:22 PM +0530, Jagan Teki
wrote:
> Just to add a few pieces of information for you to understand better
> on the context of dsi panels. DSI panels can be part of
panel-simple.c
> or panel-.c DSI panels whose init and exit sequence is
> generic are suitable to add it
On Wed, May 17, 2023 at 08:56:53AM +0200, Christoph Hellwig wrote:
> Just thinking out loud:
>
> - what if we always way overallocate the swiotlb buffer
> - and then mark the second half / two thirds / of the thin air> slots as used, and make that region available
>through a special CMA
On 5/17/2023 9:56 AM, Jeffrey Hugo wrote:
From: Tom Rix
clang static analysis reports
drivers/accel/qaic/qaic_data.c:610:2: warning: Undefined or garbage
value returned to caller [core.uninitialized.UndefReturn]
return ret;
^~
From a code analysis of the
No invocation of get_user_pages() use the vmas parameter, so remove it.
The GUP API is confusing and caveated. Recent changes have done much to
improve that, however there is more we can do. Exporting vmas is a prime
target as the caller has to be extremely careful to preclude their use
after the
On 04.04.2023 13:11, Maxime Ripard wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The Atmel SAM9x5 SMD clocks implements a mux with a set_parent
> hook, but doesn't provide a determine_rate implementation.
>
> This is a bit odd, since
On 04.04.2023 13:10, Maxime Ripard wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The SAM9x5 slow clock implements a mux with a set_parent hook, but
> doesn't provide a determine_rate implementation.
>
> This is a bit odd, since
On Wed, May 17, 2023 at 11:58:21AM +0200, Petr Tesařík wrote:
> On Wed, 17 May 2023 10:41:19 +0100
> Catalin Marinas wrote:
> > On Wed, May 17, 2023 at 08:56:53AM +0200, Christoph Hellwig wrote:
> > > Just thinking out loud:
> > >
> > > - what if we always way overallocate the swiotlb buffer
>
The rq pointer points inside the drm_gpu_scheduler structure. Thus
it can't be NULL.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: c61cdbdbffc1 ("drm/scheduler: Fix hang when sched_entity released")
Signed-off-by: Vladislav Efanov
---
Hi Bagas,
On Fri, Feb 03, 2023 at 05:02:15PM +0700, Bagas Sanjaya wrote:
> Stephen Rothwell reported htmldocs warning:
>
> include/media/v4l2-subdev.h:1088: warning: Function parameter or member
> 'privacy_led' not described in 'v4l2_subdev'
>
> Describe privacy_led field to fix the warning.
>
Don't assume that only the driver would be accessing LNKCTL. ASPM
policy changes can trigger write to LNKCTL outside of driver's control.
And in the case of upstream bridge, the driver does not even own the
device it's changing the registers for.
Use RMW capability accessors which do proper
Hello,
If I understood you correctly you'd prefer it to be named
fannal,c3004.yaml? My logic is that if more panels were to be added that
means that each one would have yaml files that would look exactly the
same with the same user.
Best regards,
Paulo
On 5/17/23 09:03, Krzysztof
Don't assume that only the driver would be accessing LNKCTL. ASPM
policy changes can trigger write to LNKCTL outside of driver's control.
And in the case of upstream bridge, the driver does not even own the
device it's changing the registers for.
Use RMW capability accessors which do proper
On 5/15/2023 7:21 PM, Ville Syrjälä wrote:
On Fri, May 12, 2023 at 11:54:08AM +0530, Ankit Nautiyal wrote:
In Bigjoiner check for DSC, bigjoiner interface bits for DP for
DISPLAY > 13 is 36 (Bspec: 49259).
v2: Corrected Display ver to 13.
v3: Follow convention for conditional statement.
Hi,
I don't know the status here, but if it works, you should probably merge
it. I think you first need to get commit access to drm-misc. That will
also allow you to merge the other fixes you sent recently.
See
https://drm.pages.freedesktop.org/maintainer-tools/commit-access.html#drm-misc
On Tue, May 16, 2023 at 5:27 AM Adam Ford wrote:
>
> The high-speed clock is hard-coded to the burst-clock
> frequency specified in the device tree. However, when
> using devices like certain bridge chips without burst mode
> and varying resolutions and refresh rates, it may be
> necessary to
On Tue, May 16, 2023 at 5:27 AM Adam Ford wrote:
>
> The DPHY timings are currently hard coded. Since the input
> clock can be variable, the phy timings need to be variable
> too. To facilitate this, we need to cache the hs_clock
> based on what is generated from the PLL.
>
> The
Thanks Stan and Ville for the review comments.
I agree can have some documentation about the values used, instead of
magic numbers.
Also, Ville's approach for dsc_{sink,source}_{min,max}_bpp() seems good,
and that can be used as helpers in MST case too.
Will add the changes in the next
On 2023-05-17 15:52, Alexandre Bailon wrote:
Some APU devices are behind an IOMMU.
For some of these devices, we can't use DMA API because
they use static addresses so we have to manually use
IOMMU API to correctly map the buffers.
Except you still need to use the DMA for the sake of cache
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
MTL HW only uses StreamId0 and StreamId3 that map to TBU0 and TBU2.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 2023-05-17 19:35, Luben Tuikov wrote:
> Rename drm_sched_wakeup() to drm_sched_wakeup_if_canqueue() since the former
> is misleading, as it wakes up the GPU scheduler _only if_ more jobs can be
> queued to the underlying hardware.
>
> This distinction is important to make, since the wake
From: Karol Wachowski
Program additional fourth level required for mappings with VA above 38bits.
Co-developed-by: Raymond Tan
Signed-off-by: Raymond Tan
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
---
drivers/accel/ivpu/ivpu_mmu.c
From: Karol Wachowski
Future devices will have different dma bit mask, make it hw specific.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
---
drivers/accel/ivpu/ivpu_drv.c | 4 +++-
drivers/accel/ivpu/ivpu_hw.h | 1 +
2 files changed, 4
From: Karol Wachowski
MTL HW only uses StreamId0 and StreamId3 that map to TBU0 and TBU2.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
---
drivers/accel/ivpu/ivpu_hw_mtl.c | 19 ---
1 file changed, 4 insertions(+), 15
Update MMU code in order to support future generations of hardware.
Karol Wachowski (5):
accel/ivpu: Remove configuration of MMU TBU1 and TBU3
accel/ivpu: Add MMU support for 4 level page mappings
accel/ivpu: Make DMA bit mask HW specific
accel/ivpu: Rename and cleanup MMU600 page tables
On 5/18/2023 7:16 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Program additional fourth level required for mappings with VA above 38bits.
Co-developed-by: Raymond Tan
Signed-off-by: Raymond Tan
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw
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