current we use 'r+b' to open the RAW file, it report failure for the
read-only files. so this patch change it to use 'rb' to open the file
since we only read it and no need to write.
Cc: Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by:
Vladimir:
You add one library INF into FDF file, then cause this issue?
Thanks
Liming
From: Vladimir Olovyannikov [mailto:vladimir.olovyanni...@broadcom.com]
Sent: Wednesday, September 14, 2016 11:20 AM
To: Gao, Liming
Cc: edk2-devel@lists.01.org
Hi,
Thanks for reply. I found the reason: I should have add the Shell
application (which is actually a library) to the ShellPkg instead of trying
to add it in the .fdf.
Thank you,
Vladimir
On Sep 13, 2016 8:17 PM, "Gao, Liming" wrote:
> Hi,
> The below message is caused
Hi,
The below message is caused by the missing map file of the driver. In build
output directory /uefi/Build/NS2Pkg/DEBUG_GCC5, please check whether the map
file is generated for each driver.
Thanks
Liming
> -Original Message-
> From: edk2-devel
Ok, I will update the commit title to highlight it's a change in XhciDxe.
Thanks
Feng
-Original Message-
From: Zeng, Star
Sent: Wednesday, September 14, 2016 10:58 AM
To: Tian, Feng
Cc: edk2-devel@lists.01.org
Subject: RE: [patch] MdeModulePkg/Xhci: add 1ms delay
How about to use XhciDxe instead of Xhci in the title to be more differentiated
with another change in XhciPei?
Reviewed-by: Star Zeng
Thanks,
Star
-Original Message-
From: Tian, Feng
Sent: Wednesday, September 14, 2016 9:37 AM
To: Zeng, Star
Reviewed-by: Star Zeng
-Original Message-
From: Tian, Feng
Sent: Wednesday, September 14, 2016 9:49 AM
To: Zeng, Star
Cc: edk2-devel@lists.01.org
Subject: [patch] MdeModulePkg/XhciPei: 1ms delay before accessing MMIO reg in
reset
Some XHCI
Some XHCI HCs require to have 1ms delay before accessing any MMIO
register in reset.
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian
---
MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 1 +
1 file changed, 1
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian
---
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 6
Thanks Laurie. A summary of proposed changes in this version is as follows
(green = added text; red = removed text). Please reply to this email with any
feedback.- Kevin
* Revision History:
[cid:image002.png@01D20851.7AE7A3E0]
* 2.0, FDF Design Discussion:
Announcing FDF 1.27 Review Draft for review.
Goto the EDK II Specifications
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Specifications
page to download the latest FDF 1.27 Review Draft documentation.
Please Review By EOW
thanks,
Laurie
laurie.jarlst...@intel.com
Intel
Hello,
I have just got this error building UEFI for AARCH64.
Here is an excerpt from the output:
Fd File Name:BL33_AP_UEFI
Generate Region at Offset 0x0
Region Size = 0xF
Region Name = FV
Generating FVMAIN_COMPACT FV
Generating FVMAIN FV
On 09/13/16 19:28, Ard Biesheuvel wrote:
> The BaseMemoryLibStm implementation under ArmPkg/ is being deprecated,
> in favor of the generic versions under MdePkg, now that ARM and AARCH64
> support has been added to both the generic C version (BaseMemoryLib) and
> the accelerated version
> On Sep 13, 2016, at 10:49 AM, Ard Biesheuvel
> wrote:
>
> On 13 September 2016 at 18:45, Andrew Fish wrote:
>>
>>> On Sep 13, 2016, at 10:27 AM, Ard Biesheuvel
>>> wrote:
>>>
>>> Without an explicit .align directive,
On 13 September 2016 at 18:45, Andrew Fish wrote:
>
>> On Sep 13, 2016, at 10:27 AM, Ard Biesheuvel
>> wrote:
>>
>> Without an explicit .align directive, the Clang assembler defaults to
>> no alignment, which may result in instructions appearing
The BaseMemoryLibStm implementation under ArmPkg/ is being deprecated,
in favor of the generic versions under MdePkg, now that ARM and AARCH64
support has been added to both the generic C version (BaseMemoryLib) and
the accelerated version (BaseMemoryLibOptDxe). The latter uses unaligned
accesses
Fix two bugs:
- Erroneous shift of 2 in a bytes to bits conversion.
- Use reverse subtract rather than negate for value that is subsequently
used as operand #2 in a shift operation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
Without an explicit .align directive, the Clang assembler defaults to
no alignment, which may result in instructions appearing misaligned in
the final executable. So use word alignment in all cases.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
On 13 September 2016 at 16:55, Achin Gupta wrote:
> On Tue, Sep 13, 2016 at 04:25:32PM +0100, Ard Biesheuvel wrote:
>> On 13 September 2016 at 16:16, Achin Gupta wrote:
>> > On Tue, Sep 13, 2016 at 03:43:41PM +0100, Ard Biesheuvel wrote:
>> >> On 13
On Tue, Sep 13, 2016 at 04:25:32PM +0100, Ard Biesheuvel wrote:
> On 13 September 2016 at 16:16, Achin Gupta wrote:
> > On Tue, Sep 13, 2016 at 03:43:41PM +0100, Ard Biesheuvel wrote:
> >> On 13 September 2016 at 15:12, Ard Biesheuvel
> >> wrote:
On 13 September 2016 at 16:16, Achin Gupta wrote:
> On Tue, Sep 13, 2016 at 03:43:41PM +0100, Ard Biesheuvel wrote:
>> On 13 September 2016 at 15:12, Ard Biesheuvel
>> wrote:
>> > On 13 September 2016 at 15:03, Achin Gupta
On Tue, Sep 13, 2016 at 03:43:41PM +0100, Ard Biesheuvel wrote:
> On 13 September 2016 at 15:12, Ard Biesheuvel
> wrote:
> > On 13 September 2016 at 15:03, Achin Gupta wrote:
> >> Hi All,
> >>
> >> Upon entry into UEFI, the
I have no comment.
Reviewed-by: Liming Gao
From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
Sent: Tuesday, September 13, 2016 10:50 PM
To: edk2-devel-01 ; Gao, Liming
; Leif Lindholm ; Kinney,
Adding Andrew, Mike,
On Tue, Sep 13, 2016 at 08:43:39AM +0100, Ard Biesheuvel wrote:
> On 13 September 2016 at 06:46, Ni, Ruiyu wrote:
> >>* Another idea is to check a dynamic PCD that the platform can set. New
> >>PCDs are frowned upon in MdeModulePkg however, so I don't
Liming: do you have any comments on this patch?
On 9 September 2016 at 15:00, Ard Biesheuvel wrote:
> The new accelerated ARM and AARCH64 implementations take advantage of
> features that are only available when the MMU and Dcache are on. So
> restrict the use of this
On 13 September 2016 at 15:12, Ard Biesheuvel wrote:
> On 13 September 2016 at 15:03, Achin Gupta wrote:
>> Hi All,
>>
>> Upon entry into UEFI, the ArmPlatformPkg/PrePi/PeiUniCore.inf SEC module
>> executes directly from within the firmware volume.
When parsing the device tree to find the memory node, we are still running
with the MMU off, which means unaligned memory accesses are not allowed.
Since the FDT only mandates 32-bit alignment, 64-bit quantities are not
guaranteed to appear naturally aligned, and so should be accessed using
32-bit
On 13 September 2016 at 15:03, Achin Gupta wrote:
> Hi All,
>
> Upon entry into UEFI, the ArmPlatformPkg/PrePi/PeiUniCore.inf SEC module
> executes directly from within the firmware volume. The FV would typically be
> loaded in DRAM by ARM Trusted Firmware. The rule in
Reviewed-by: Sriram Subramanian
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fu Siyuan
Sent: Tuesday, September 13, 2016 7:56 AM
To: edk2-devel@lists.01.org
Cc: Zhang Lubo ; Wu Jiaxin
Hi All,
Upon entry into UEFI, the ArmPlatformPkg/PrePi/PeiUniCore.inf SEC module
executes directly from within the firmware volume. The FV would typically be
loaded in DRAM by ARM Trusted Firmware. The rule in ArmJuno.fdf for SEC file
types converts a PE-COFF module into a stripped Terse
On Thu, Sep 08, 2016 at 12:24:46PM +0200, Laszlo Ersek wrote:
> On 09/08/16 11:38, Anthony PERARD wrote:
> > Hello,
> >
> > We are introducing a new virtualisation mode in Xen called PVHv2 (also
> > called hvmlite in the past). We would like to have a UEFI firmware
> > running on it to make it
On 09/13/16 10:33, Thomas Huth wrote:
> Correct some typos in the header files of the OvmfPkg
> (which have been discovered with the codespell utility).
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Thomas Huth
> ---
> Sorry, in my previous
On Fri, Sep 09, 2016 at 09:15:39AM +0100, Ard Biesheuvel wrote:
> The FVP model has up to 8 GB of memory (on the Base model), where the
> top 6GB starts at 0x8_8000_, and all other memory regions of interest
> live below that. This means we can cover the whole VA space with 36-bits
> worth of
On Fri, Sep 09, 2016 at 09:15:38AM +0100, Ard Biesheuvel wrote:
> We can cover the entire MMIO range and 512 GB of memory starting at
> 0x80__ using 40 bits of VA space, both in the page tables and
> in the GCD memory map.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
>
On Fri, Sep 09, 2016 at 11:48:36AM +0100, Ard Biesheuvel wrote:
> Patch #1 replaces the needlessly complex routine to determine the number of
> translation levels and the size and alignment of the root table based on the
> T0SZ setting.
>
> Patch #2 fixes the fix for allocating page aligned
Reviewed-by: Ye Ting
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Fu Siyuan
Sent: Tuesday, September 13, 2016 10:26 AM
To: edk2-devel@lists.01.org
Cc: Zhang, Lubo ; Wu, Jiaxin
Reviewed-By: Wu Jiaxin
Best Regards!
Jiaxin
> -Original Message-
> From: Fu, Siyuan
> Sent: Tuesday, September 13, 2016 10:26 AM
> To: edk2-devel@lists.01.org
> Cc: Wu, Jiaxin ; Zhang, Lubo
> Subject: [Patch] NetworkPkg:
On 13 September 2016 at 06:46, Ni, Ruiyu wrote:
>
>
> Regards,
> Ray
>
>>-Original Message-
>>From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Laszlo
>>Ersek
>>Sent: Monday, September 12, 2016 9:49 PM
>>To: Ard Biesheuvel
Looks good to me
Reviewed-by: Feng Tian
Thanks
Feng
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Jeff Fan
Sent: Friday, September 9, 2016 3:59 PM
To: edk2-devel@lists.01.org
Subject: [edk2] [Patch 0/7] Re-install SEC
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