The major features of this patchset:
1 Upgrade trusted firmware to 1.4
2 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214
3 Delete some binary for open-source version
4 Update binary follow changing DmaLib to CoherentDmaLib
Code can also be found in github:
1. Rebuild SnpPV600Dxe binary for switching DmaLib to CoherentDmaLib.
2. Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front of the
chassis) to the first one in BootManage for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657
Note:
This
From: Jason Zhang
An open-source version coming to edk2-platfroms replaces this version.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang
Signed-off-by: Ming Huang
Signed-off-by: Heyi
An open-source version coming to edk2-platforms replaces this version.
This patch is related to "Open SnpPlatform source code" and
"Change DmaLib to CoherentDmaLib".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Update SasDriverDxe binary for changing DmaLib to CoherentDmaLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
---
Yes, you are right.
L"String" and "String" still support, and we add L'String' and 'String'
L"ab" ==> {0x61, 0x00, 0x62, 0x00, 0x00, 0x00}
L'ab' ==> {0x61, 0x00, 0x62, 0x00}
Any question, please let me know. Thanks.
Best Regards
Feng, Yunhua
-Original Message-
From: Yao, Jiewen
On 02/02/18 11:06, Ard Biesheuvel wrote:
> On 31 January 2018 at 10:40, Laszlo Ersek wrote:
>> On 01/30/18 23:25, Kinney, Michael D wrote:
>>> Laszlo,
>>>
>>> I agree that the function is better than a macro.
>>>
>>> I thought of the alignment issues as well. CopyMem()
>>> is
On 02/02/18 14:28, Leif Lindholm wrote:
> On Fri, Feb 02, 2018 at 10:06:07AM +, Ard Biesheuvel wrote:
>> On 31 January 2018 at 10:40, Laszlo Ersek wrote:
>>> On 01/30/18 23:25, Kinney, Michael D wrote:
Laszlo,
I agree that the function is better than a macro.
Good.
I am just confused on the commit message --- when the value is L'' or '', will
report error.
Would you please clarify what does that mean?
Thank you
Yao Jiewen
> -Original Message-
> From: Feng, YunhuaX
> Sent: Friday, February 2, 2018 9:42 PM
> To: Yao, Jiewen
All edk2 toolchains use NASM for compiling X86 assembly source code. We
plan to remove X86 *.S and *.asm files globally, in order to reduce
maintenance and confusion:
Rename the variable to "gPatchSmmCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmmInit.nasm".
Cc: Eric Dong
(This patch is the 64-bit variant of commit e75ee97224e5,
"UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup()",
2018-01-31.)
The SmmStartup() function executes in SMM, which is very similar to real
mode. Add "BITS 16" before it and "BITS 64" after it (just before the
@LongMode
Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmiEntry.nasm".
Cc: Eric Dong
"mXdSupported" is a global BOOLEAN variable, initialized to TRUE. The
CheckFeatureSupported() function is executed on all processors (not
concurrently though), called from SmmInitHandler(). If XD support is found
to be missing on any CPU, then "mXdSupported" is set to FALSE, and further
processors
Like "gSmmCr4" in the previous patch, "gSmmCr0" is not only used for
machine code patching, but also as a means to communicate the initial CR0
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr0Value" instruction's binary
representation
"#endif" preprocessing directives near the top of "BaseLib.h" helpfully
repeat the preprocessing conditions from their matching "#if", "#ifdef",
and "#ifndef" directives. This practice has been less followed recently;
supplement the missing comments.
Cc: Ard Biesheuvel
Rename the variable to "gPatchSmmInitStack" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmmInit.nasm".
The size of the
Unlike "gSmmCr3" in the previous patch, "gSmmCr4" is not only used for
machine code patching, but also as a means to communicate the initial CR4
value from SmmRelocateBases() to InitSmmS3ResumeState(). In other words,
the last four bytes of the "mov eax, Cr4Value" instruction's binary
(1) SmmRelocationSemaphoreComplete32() runs in 32-bit mode, so wrap it in
a (BITS 32 ... BITS 64) bracket.
(2) SmmRelocationSemaphoreComplete32() currently compiles to:
> 02AE C60501mov byte [dword 0x0],0x1
> 02B5 FF25 jmp dword [dword 0x0]
where the
The IA32 version of "SmmInit.nasm" does not need "gSmmJmpAddr" at all (its
PiSmmCpuSmmInitFixupAddress() variant doesn't do anything either). We can
simply use the NASM syntax for the following Mixed-Size Jump:
> jmp PROTECT_MODE_CS : dword @32bit
The generated object code for the instruction is
On 02/02/18 07:45, Ruiyu Ni wrote:
> From: Michael D Kinney
>
> Add support for platform specific reset filters and platform
> specific reset handlers to ResetSystem(). A filter may modify
> the reset type and reset data and call ResetSystem() with the
> modified
Excellent question.
Comment inline.
From: Marvin H?user [mailto:marvin.haeu...@outlook.com]
Sent: Wednesday, January 31, 2018 1:54 AM
To: edk2-devel@lists.01.org; Yao, Jiewen
Subject: MinPlatformPkg/PlatformInit: FV code
Dear developers, dear Jiewen,
I have been
On 02/02/18 11:47, Ruiyu Ni wrote:
> Today's implementation of [Ascii]StrnCpyS/[Ascii]StrnCatS doesn't
> directly return the the length of source string is 0.
>
> When length of source string is 0, it means the Source points to
> a memory that shouldn't be deferenced at all.
> So it's not proper
On Fri, Feb 02, 2018 at 10:06:07AM +, Ard Biesheuvel wrote:
> On 31 January 2018 at 10:40, Laszlo Ersek wrote:
> > On 01/30/18 23:25, Kinney, Michael D wrote:
> >> Laszlo,
> >>
> >> I agree that the function is better than a macro.
> >>
> >> I thought of the alignment
Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.
PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206
Contributed-under: TianoCore Contribution Agreement 1.1
Hisilicon-specific PlatformBootManagerLib added. It is convenient
to add specific feature, like BMC control boot option.
Remove Intel BDS from dsc file because it is out of use.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
This module support updating the boot CPU firmware only.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Ard Biesheuvel
Replace the old string with short one. The old one is
too long that can not be show integrallty in Setup nemu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
Add ITS affinity structure in SRAT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Ard Biesheuvel
Reviewed-by: Graeme Gregory
---
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Signed-off-by: GongChengYa
Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif
modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2,
indicator to obtain the processor family from the Processor Family 2 field.
ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing
table.
Contributed-under: TianoCore Contribution Agreement 1.1
In order to replace command line parameter pcie_aspm=off, BIOS needs to
disable Pcie Aspm support during Pcie initilization.
D03 and D05 do not support PCIe ASPM, so we disable it in BIOS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
1. This driver install a protocol for SnpPV600Dxe driver.
The protocol indicate which ethernet port to use and port sequence.
2. Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front
of the chassis) to the first one in BootManage for
This module install a protocol for SasDriverDxe. the protocol
include main information of sas controller, like controller ID,
enable or disable,base address of registers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang
Signed-off-by:
In SCT test,we find SP805 watchdog driver can't reset when timeout
so we use another driver in MdeModulePkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Signed-off-by: GongChengYa
Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
sorry
L'' and '' is single quote and not include any character, so we will report
error message
Any question, please let me know. Thanks.
Best Regards
Feng, Yunhua
-Original Message-
From: Yao, Jiewen
Sent: Friday, February 2, 2018 9:45 PM
To: Feng, YunhuaX ;
Update NativeOhci bianry for changing DmaLib to CoherentDmaLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
---
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
1 Workarounds for CVE-2017-5715 on Cortex A57/A72/A73 and A75 #1214.
2 Upgrade trusted firmware to 1.4
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Leif Lindholm
Repo: https://github.com/lersek/edk2.git
Branch: patch_insn_x86
Patch 01 is a comment cleanup patch for "BaseLib.h".
Patch 02 introduces PatchInstructionX86() to BaseLib, based on the
recent discussion.
Patch 03 removes *.S and *.asm files from PiSmmCpuDxeSmm, so that the
rest of the series
Rename the variable to "gPatchSmbase" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
UINT8, and patch it with PatchInstructionX86(). This lets us remove the
binary (DB) encoding of some instructions in "SmiEntry.nasm".
Cc: Eric Dong
The major features of this patchset include
adding PPTT support,
switching to Generic BDS driver,
adding capsule upgrade support,
open-source version for SnpPlatform and SasPlatform
changing DmaLib to CoherentDmaLib.
Note: The patch PPTT is related to the edk2 patch "MdePkg ACPI: Add some macros
Move definition of Madt struct to head file, so PPTT driver
can include it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
Reviewed-by: Ard Biesheuvel
Reviewed-by:
Hello
May I know why we do not support L"String" ?
My understanding is that L'String' is a string without NULL terminator,
L"String" is a string with NULL terminator, right?
Thank you
Yao Jiewen
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf
Hi,
On 02/01/2018 09:42 PM, Huangming (Mark) wrote:
On 2018/2/1 9:11, Jeremy Linton wrote:
Hi,
On 01/26/2018 02:00 AM, Ming Huang wrote:
Add Processor Properties Topology Table, PPTT include
(trimming)
+STATIC
+VOID
+InitCacheInfo (
+ VOID
+ )
+{
+ UINT8
Good point with the DxeCore, I didn't consider that. Though OsBoot would be
irrelevant to the PEI phase, wouldn't it be?
Thanks,
Marvin
From: Yao, Jiewen [mailto:jiewen@intel.com]
Sent: Friday, February 2, 2018 1:40 PM
To: Marvin H?user ; edk2-devel@lists.01.org
> -Original Message-
> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> Sent: Friday, February 2, 2018 4:22 PM
> To: Ni, Ruiyu
> Cc: Guo Heyi ,Dong Wei ; Dong,
> Eric ; edk2-devel@lists.01.org;
On 2018/1/30 1:33, Leif Lindholm wrote:
> So, I'm mostly happy with this set, but:
>
> Sender (and hence Author for all patches that do not have a second
> From: statement after Subject: ) for all patches here is
> Ming Huang
>
> Can you please address this, either by
Add prompt & help string for PcdTpm2CurrentIrqNum, PcdTpm2PossibleIrqNumBuf
Cc: Dandan Bi
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chao Zhang
---
SecurityPkg/SecurityPkg.uni | 11 ++-
1 file changed, 10
Marvin
I have filed 2 bugzilla to record this.
https://bugzilla.tianocore.org/show_bug.cgi?id=872
https://bugzilla.tianocore.org/show_bug.cgi?id=871
Thank you
Yao Jiewen
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Yao,
> Jiewen
> Sent:
Add UefiLib unit tests for the new API
EfiLocateProtocolBuffer().
Cc: Sean Brogan
Cc: Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D Kinney
---
Laszlo,
Thanks for all the work on this series and the very
detailed commit messages.
Liming's email on removing the .S and .asm files is an
RFC. We need to see this RFC approved before we can
commit changes to remove .S and .asm files. This should
be a separate activity.
One odd thing I see
https://bugzilla.tianocore.org/show_bug.cgi?id=838
Add new API to the UefiLib that locates and returns
an array of protocols instances that match a given
protocol.
Cc: Sean Brogan
Cc: Jiewen Yao
Cc: Liming Gao
From: Michael D Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=838
Add new API to the UefiLib that locates and returns
an array of protocols instances that match a given
protocol.
Cc: Sean Brogan
Cc: Jiewen Yao
Add functions that have been added to MdePkg/UefiLib.
* GetVariable2()
* GetEfiGlobalVariable2
Cc: Sean Brogan
Cc: Jiewen Yao
Cc: Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Michael D
V2:
* Use gBS->AllocatePool() instead of AllocatePool()
* Use gBS->FreePool() instead of FreePool()
* Add EfiLocateProtocolBuffer() to IntelFrameworkPkg/FrameworkUefiLib
* Add GetVariable2() to IntelFrameworkPkg/FrameworkUefiLib
* Add GetEfiGlobalVariable2 to IntelFrameworkPkg/FrameworkUefiLib
Ah, good catch.
That is correct - it is irrelevant to PEI. To put to FV Hob is enough, I
believe.
Appreciate your careful review, which helps us clean up the code. :-)
Thank you
Yao Jiewen
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>
Hi, experts:
I have a question about using compiler's intrinsic function.
It seems EDKII's compiler option doesn't support using intrinsic function.
Such as:
mmintrin.h MMX
xmmintrin.hSSE
emmintrin.h SSE2
pmmintrin.h SSE3
tmmintrin.hSSSE3
intrin.h SSE4A
smmintrin.h
Add a check for DatumType format, eg: VOID *, original Tool will crash
but no detail error message which cause confusion to user.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yonghong Zhu
---
BaseTools/Source/Python/Workspace/DecBuildData.py | 7
From: "Gao, Liming"
V3:
Add "FPDT_" prefix for related definitions.
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao
Signed-off-by: Dandan Bi
V3:
a. Add "FPDT_" prefix for related definitions in ExtendedFirmwarePerformance.h.
b. Refine the code logic.
V2:
a. Update DxecorePerformanceLib/SmmCorePerformanceLib to report the
boot performance table address instead of records contents.
b. Update FirmwarePerformanceDxe/FirmwarePerformanceSmm
Type VOID* support L'a' and 'a', the value transfer to c style value.
L'a' --> {0x61, 0x00}
L'ab' --> {0x61, 0x00, 0x62, 0x00}
'a' --> {0x61}
'ab' --> {0x61, 0x62}
when the value is L'' or '', will report error
Cc: Liming Gao
Cc: Yonghong Zhu
On 2 February 2018 at 00:34, Ni, Ruiyu wrote:
>
>
>> -Original Message-
>> From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
>> Sent: Friday, February 2, 2018 1:23 AM
>> To: Ni, Ruiyu
>> Cc: Guo Heyi ,Dong Wei
V3:
a. Handle the case when string is empty in String Record.
b. refine the code logic.
V2:
Update DxecorePerformanceLib to report the boot performance table
address instead of records contents.
Updated to convert Pref entry to FPDT record in DXE phase and then
allocate boot performance table to
Cc: Liming Gao
Cc: Star Zeng
Cc: Ruiyu Ni
Cc: Jaben Carsey
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi
---
Add FPDT records into boot performance table for S3 phase
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi
---
.../FirmwarePerformancePei.c | 59
V3:
a. Handle the case when string is empty in String Record.
b. Use gEdkiiFpdtExtendedFirmwarePerformanceGuid to report status
code to distinguish with the one in DxeCorePerformanceLib.
c. Refine the code logic.
V2:
Update SmmCorePerformanceLib to report the buffer address of
boot performance
V3:Add handling for the case when performance feature is not enabled.
V2:
Update FirmwarePerformanceDxe to receive the address
of performance records instead of records content.
1. Remove the macro EXTENSION_RECORD_SIZE, since the extension
size can be got through PcdExtFpdtBootRecordPadSize.
V3:Handle the case when string is empty in String Record.
Updated to convert Pref entry to FPDT record in PEI phase and then
report the records to DxeCorePerfLib through GUID hob.
Cc: Liming Gao
Cc: Star Zeng
Contributed-under: TianoCore Contribution
V3:
a. Remove unused definitions
b. Get records size form the records buffer when getting size action
is triggered.
V2:
Update FirmwarePerformanceSmm to receive the address
of performance records instead of records content.
Receive buffer address of Boot performance records
which are reported by
Reviewed-by: Star Zeng
BTW, do you want to say " the second call may hang " instead of " the second
hang may hang " in the commit log?
Thanks,
Star
-Original Message-
From: Ni, Ruiyu
Sent: Thursday, February 1, 2018 6:16 PM
To: edk2-devel@lists.01.org
Cc: Yao,
Today's implementation of [Ascii]StrnCpyS/[Ascii]StrnCatS doesn't
directly return the the length of source string is 0.
When length of source string is 0, it means the Source points to
a memory that shouldn't be deferenced at all.
So it's not proper to call StrnLenS() in such situation.
In a pool
Hi, Liming:
Got it!
Thanks
Best wishes,
-邮件原件-
发件人: Gao, Liming [mailto:liming@intel.com]
发送时间: 2018年1月31日 17:44
收件人: Tiger Liu(BJ-RD) ; edk2-devel@lists.01.org
主题: RE: [edk2] difference between asm16 and asm files
Tiger:
Nasm compiler supports to generate
On 31 January 2018 at 10:40, Laszlo Ersek wrote:
> On 01/30/18 23:25, Kinney, Michael D wrote:
>> Laszlo,
>>
>> I agree that the function is better than a macro.
>>
>> I thought of the alignment issues as well. CopyMem()
>> is a good solution. We could also consider
>>
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