If anyone is familiar with gEDA, the schematic to netlist tool is written in
scheme and can target multiple formats. Perhaps it could be of use?
-Travis Ayres
On Jul 12, 2010 2:11 PM, "Devil Dragon" wrote:
You need to specify the full file directly path to the executable as seen on
th
Did you properly define your subcircuit for LTSpice? Can you post your
ltspice netlist?
On Aug 19, 2013 6:31 AM, "Joaquin Cury" wrote:
> Hello, I made the schematic and the layout of an oscillator but when I am
> trying to simulate the layout, the Electric tells me:
>
> Unkown subcircuit call in:
If I remember correctly, effective channel width is the channel width after
diffusion (it is not the same as the drawn channel width because diffusion
'blurs' the edges). It looks like you have a variable that is saying take
your drawn channel width, add some amount for diffusion, that is your
eff
The "r" is missing in capacitor on the netlist line for xcapacitor. If that
doesn't fix it, let me know, Ill break out the help file and we will get it
running!
On Aug 19, 2013 7:29 AM, "Joaquin Cury" wrote:
>
>
> El lunes, 19 de agosto de 2013 10:31:15 UTC-3, Joaquin Cury escribió:
>>
>> Hello,
What work have you done so far? Do you have a schematic? Have you done any
calculations?
On Oct 28, 2013 6:33 AM, "OFIR DELLY" wrote:
>
> --
> You received this message because you are subscribed to the Google Groups
> "Electric VLSI Editor" group.
> To unsubscribe from this group and stop recei
Can you attach your files?
On Nov 10, 2013 3:13 PM, wrote:
> The error, Parts (hash code), can be seen in the attached image.
>
> The circuit is quite simple and I hope my mistake is simple as well.
>
> The error occurs when I LVS. It does *not* occur everytime I LVS,
> however.
>
> Any solutio
Did you check your SPICE netlist?
Remember that in SPICE you have to write 1MEG, as 1M becomes 1*10^-3. 1Mhz
matches against 1M and not 1MEG.
Hope this helps,
-Travis
On Mon, Mar 31, 2014 at 7:30 AM, Joaquin Cury wrote:
> Hi,
>
> I am using in Electric an AC voltage source. I choose differents
What is the W/L you are using for both your nmos and pmos?
On Wed, May 7, 2014 at 7:24 AM, Puneeth R wrote:
>
> I am developing a standard cell library using electric. The image here
> shows the 1x inverter i have designed.Please help me how to
>
I'd say if speed was your bottleneck, minimize capacitance
On Wed, May 7, 2014 at 1:56 PM, sudheer k Muhammed <
sudheerkmuham...@gmail.com> wrote:
> If speed is ur bottleneck;
>
> use a chain of inverters having 1x,2x,4x,...
>
>
> On 7 May 2014 22:33, S Narasimha Kamath wrote:
>
>> Hi Puneeth,
You are plotting the wrong voltage? Send your spice netlists and we'll take
a look.
On May 23, 2014 4:20 PM, "Emrah login" wrote:
> I disconnected a inverter from vdd and i still got an output 2.5 V even my
> input is zero or 5 V. Any explanations?
>
> --
> You received this message because you a
Show your work - where are you stuck?
On Wed, Aug 13, 2014 at 9:39 AM, Komal Bhadoriya
wrote:
> HII EVERYONE
> i want to work on lt spice please help me out with the procedures, please
> tell me how to implement 6t sram using lt spice
>
> --
> You received this message because you are subscrib
The spice deck you are running mentions UC Spice - check the .options
syntax for LTSpice, find the corresponding options (if they are nevessary)
and replace them. I can give you a more detailed answer in a few hours.
On Oct 10, 2014 6:17 AM, "Andrew Laksh" wrote:
>
> Dear Group members
>
> Please
Have you seen professor Baker's videos @ cmosedu?
On Dec 4, 2014 7:40 AM, "harsha parime" wrote:
> HI, i recently started using electric. i had drawn a schematic for a nand
> gate i want to convert it to layout what is the procedure for it. i was
> struggling for it please help me . thanks in adv
...Is this your homework?
What do you have so far?
On Mon, Apr 27, 2015 at 6:12 PM, Shobit Agarwal
wrote:
> CAn Anyone do this for me???
>
> *Design and simulate a Diff. amplifier with following specifications:*
>
> CMOS technology node: 180nm
>
> Supply rails: 1.8V, gnd
>
> Max Power dissipati
>
> On Tuesday, April 28, 2015 at 9:33:41 AM UTC+5:30, Travis Ayres wrote:
>>
>> ...Is this your homework?
>> What do you have so far?
>>
>> On Mon, Apr 27, 2015 at 6:12 PM, Shobit Agarwal
>> wrote:
>>
>>> CAn Anyone do this for m
Dr. Baker's website, CMOSEDU, has a set of tutorials both written and video
on the subject:
http://cmosedu.com/videos/electric/electric_videos.htm
On Thu, Oct 8, 2015 at 7:37 AM, Neha Parker wrote:
> I'm implementing a schematic circuit of current conveyor.I have technology
> file in text form
Did we ever get XML for the 45nm PDK?
Having an open PDK would really be useful for Electric.
-Travis
On Tuesday, April 5, 2016 at 11:25:22 AM UTC-7, Steven Rubin wrote:
>
> This looks good. Apache 2.0 is compatible with the Electric license (GPL
> 3) so I believe the two can be combined.
>
> D
LTSpice has no limit on the number of nodes; it is freeware, and available
for Windows (it runs fine under Wine on Linux).
Dr. Robert Baker at cmosedu.com has instructions for setting up Electric
VLSI with LTSpice, including videos.
On Wed, Jun 22, 2016 at 2:18 AM, Yogita Gajare wrote:
> which
Hi Yogita,
I used the setup @ CMOSEDU:
http://cmosedu.com/cmos1/ltspice/ltspice_electric.htm
To setup Electric with LTSpice. Please give it a try and let me know how it
works for you.
On Sun, Feb 19, 2017 at 8:38 PM, Yogita Gajare wrote:
> hello all,
>
> let me know please which option we shou
For fabrication, electric can output GDSII files which can be used to
generate masks.
http://www.staticfreesoft.com/jmanual/mchap07-03-03.html
On Feb 22, 2017 7:35 AM, "Yogita Gajare" wrote:
> hello all,
>
> let me know plz, i design circuit in electric so will u plz tell me that
> same circuit
It's a good start; I'd like to see more information on taking a design all
the way through MOSIS to get some working chips.
On Wed, Mar 8, 2017 at 11:51 AM, Diego Deotti wrote:
> Very good!
>
> Thank you!
>
>
>
>
>
> *AMS DesignerMaster candidate
> at
FreePDK15 has extra licensing restrictions that preclude it's use and
inclusion, iirc.
FreePDK45 was recently made fully available under an Apache license,
however, and I think it could be used and included in Electric without
issue (I am not a lawyer, however).
On Mar 11, 2017 8:50 AM, "izmirli
The NDAs for the foundaries will stop you cold as soon as you go below
about 180nm.
An option would be to use laser direct writing and expose and dope the
wafers yourself. You could theoretically do this in a clean room you setup
in a garage, but you'd still probably need 40k of equipment and mate
n
> possible).
>
>
> Please feel free to add as many problems I may find and probable solutions!
>
> Kind regards,
> Mauricio De Carvalho
>
>
> On Mon, May 15, 2017 at 10:39 PM, Patryk S wrote:
>
>> https://opencores.org
>> https://en.wikipedia.org/wiki
t;> <http://groups.google.com/group/electricvlsi/t/56b11324395373c4?utm_source=digest&utm_medium=email>
>> Justin Spencer : May 15 06:31AM -0700
>>
>> Dear Mr. Carvalho,
>>
>> Good day. I would also like to help with this endeavor in any way
>> possible.
&g
Looks like a totally non-functional clone of efabless, with marketing
materials stolen from Aldec thrown in!
On Sun, Jan 7, 2018 at 6:46 PM, Maxim Cournoyer
wrote:
> Sanjeev Gupta writes:
>
> > One can also refer to www.webchip.in for open source based chip design
> > flow. Flow has been create
Is there a donate button? Could we fund a developer or two?
On Thu, Sep 13, 2018, 10:47 AM Steven Rubin
wrote:
> For anyone who has ever wanted to enhance Electric, but was daunted by
> the bulk of the code, this is your opportunity. I am looking for new
> developers who want to continue to push
Nice idea. Never going to happen, but nice idea.
On Tue, Feb 19, 2019, 8:40 AM Alexandre Rusev http://www.futureware.at/CrowdFunding/OpenPDK/
>
> https://www.vlsisystemdesign.com/paper-1-padframe-generator-for-qflow/
>
> --
> You received this message because you are subscribed to the Google Grou
Francesc Serra-Graells has also produced the "Academic PDK" which is
sufficient for some very good exploration:
http://www.cnm.es/~pserra/apdk/
On Wed, May 8, 2019 at 8:57 AM Alexandre Rusev wrote:
> Glade is free but not opensource
>
> Not sure that analog workflow is developed to the same ex
r.
>
> john
>
> On May 8, 2019, at 11:31 AM, Travis Ayres wrote:
>
> Francesc Serra-Graells has also produced the "Academic PDK" which is
> sufficient for some very good exploration:
> http://www.cnm.es/~pserra/apdk/
>
>
>
> On Wed, May 8, 2019 at 8:57 A
Oklahoma State also had a FreePDK45 release, iirc:
https://vlsiarch.ecen.okstate.edu/flows/
What needs to be done?
On Mon, Sep 2, 2019, 7:08 PM lingraj hiremath
wrote:
> Hi Joselito,
>
> I tried to download 45nm PDK free PDK from the following website.
>
> https://www.eda.ncsu.edu/wiki/FreePDK
I'll bet anything that all Cadence files specify in their license that you
are not to use them with other tools, not to use them for the purpose of
implementing them in other tools, and probably required by license not to
think of other tools while you're using them.
I'm not a lawyer, but I sincer
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