Good points, all – thanks.
Ken Javor
Phone: (256) 650-5261
From: Joe Randolph
Reply-To: Joe Randolph
Date: Fri, 29 Jan 2021 13:58:32 -0500
To:
Subject: Re: [PSES] Digital logic question
I am not an expert in EMC, but I have a pretty good understanding of the
basics. I’ve been watching
t: Re: [PSES] Digital logic question
Agree with Ken (both of them!)
Chas
_
From: Ken Javor mailto:ken.ja...@emccompliance.com> >
Sent: Tuesday, January 26, 2021 2:16 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG <mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
Subject: Re: [PSES
Agree with Ken (both of them!)
Chas
From: Ken Javor
Sent: Tuesday, January 26, 2021 2:16 PM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: Re: [PSES] Digital logic question
This message originated outside of DISH and was sent by:
owner-emc-p...@listserv.ieee.org
Makes sense. Awaiting test results...
Ken Javor
Phone: (256) 650-5261
From: Ken Wyatt
Reply-To: Ken Wyatt
Date: Tue, 26 Jan 2021 11:56:58 -0700
To:
Subject: Re: [PSES] Digital logic question
I agree. In the early days at HP, we would commonly place a simple low-pass
R-C filter after
, to simply slow it down with an RC
> filter, as opposed to redesigning the board stack-up to provide glitch-free
> operation.
>
> Agree/disagree?
>
> Ken Javor
> Phone: (256) 650-5261
>
>
> From: Ken Wyatt >
> Reply-To: Ken Wyatt >
> Date: Tue, 26 J
-free
operation.
Agree/disagree?
Ken Javor
Phone: (256) 650-5261
From: Ken Wyatt
Reply-To: Ken Wyatt
Date: Tue, 26 Jan 2021 11:34:04 -0700
To:
Subject: Re: [PSES] Digital logic question
Hi Ken,
The biggest problem I see when faced with RE issues is that clocks,
data/address buses
specs on the
> processor which is very slow, customer is going to measure clock waveform.
>
> Ken Javor
> Phone: (256) 650-5261
>
>
> From: "Grasso, Charles" >
> Date: Tue, 26 Jan 2021 16:19:30 +0000
> To: "EMC-PSTC@LISTSERV.IEEE.ORG "
> &
-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] Digital logic question
This message originated outside of DISH and was sent by:
owner-emc-p...@listserv.ieee.org
Have a customer who I suspect has way too fast a risetime for his application.
Clock runs at 4 MHz. I'm seeing an ugly damped sine occurring
Have a customer who I suspect has way too fast a risetime for his
application. Clock runs at 4 MHz. I¹m seeing an ugly damped sine occurring
at 2 MHz rate, leading to broadband outages around 200 MHz. Suspect that a
risetime somewhere is being corrupted.
Is it enough to slow down the clock¹s
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