?When you say damped sine - does the amplitude decrease with time? (I presume 
that the measurement is at the destination).  Typically there is too much 
series impedance (filtering?) on the signal.?

________________________________
From: Ken Javor <ken.ja...@emccompliance.com>
Sent: Monday, January 25, 2021 9:28 AM
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] Digital logic question


 This message originated outside of DISH and was sent by: 
owner-emc-p...@listserv.ieee.org

Have a customer who I suspect has way too fast a risetime for his application.  
Clock runs at 4 MHz. I'm seeing an ugly damped sine occurring at 2 MHz rate, 
leading to broadband outages around 200 MHz. Suspect that a risetime somewhere 
is being corrupted.

Is it enough to slow down the clock's rise and fall times, or do the logic 
chips fed by the clock act as Schmitt triggers and square things up again if 
they operate off a fast logic family?

Thank you,

Ken Javor
Phone: (256) 650-5261
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