Have a customer who I suspect has way too fast a risetime for his application. Clock runs at 4 MHz. I¹m seeing an ugly damped sine occurring at 2 MHz rate, leading to broadband outages around 200 MHz. Suspect that a risetime somewhere is being corrupted.
Is it enough to slow down the clock¹s rise and fall times, or do the logic chips fed by the clock act as Schmitt triggers and square things up again if they operate off a fast logic family? Thank you, Ken Javor Phone: (256) 650-5261 - ---------------------------------------------------------------- This message is from the IEEE Product Safety Engineering Society emc-pstc discussion list. To post a message to the list, send your e-mail to <emc-p...@ieee.org> All emc-pstc postings are archived and searchable on the web at: http://www.ieee-pses.org/emc-pstc.html Attachments are not permitted but the IEEE PSES Online Communities site at http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used formats), large files, etc. Website: http://www.ieee-pses.org/ Instructions: http://www.ieee-pses.org/list.html (including how to unsubscribe) List rules: http://www.ieee-pses.org/listrules.html For help, send mail to the list administrators: Scott Douglas <sdoug...@ieee.org> Mike Cantwell <mcantw...@ieee.org> For policy questions, send mail to: Jim Bacher: <j.bac...@ieee.org> David Heald: <dhe...@gmail.com>
