On 21.08.2014, at 22:40, Kieran Kunhya wrote:
>> It does that, but on older SSE2 cpus with not-so-good OOO execution grouping
>> instructions like this might help reduce dependencies a bit.
>
> Are any older SSE2 CPUs actually capable of decoding reasonable HEVC?
Of course they are. Not in real
On 21/08/14 5:40 PM, Kieran Kunhya wrote:
>> It does that, but on older SSE2 cpus with not-so-good OOO execution grouping
>> instructions like this might help reduce dependencies a bit.
>
> Are any older SSE2 CPUs actually capable of decoding reasonable HEVC?
Probably not (at least nothing above
> It does that, but on older SSE2 cpus with not-so-good OOO execution grouping
> instructions like this might help reduce dependencies a bit.
Are any older SSE2 CPUs actually capable of decoding reasonable HEVC?
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On 21/08/14 2:15 PM, Christophe Gisquet wrote:
> Hi,
>
> 2014-08-21 0:42 GMT+02:00 James Almer :
>> * Reduced xmm register count to 7 (As such they are now enabled for x86_32).
>> * Removed four movdqa (affects the sse2 version only).
>> * pxor is now used to clear m0 only once.
>
> OK.
Pushed.
Hi,
2014-08-21 0:42 GMT+02:00 James Almer :
> * Reduced xmm register count to 7 (As such they are now enabled for x86_32).
> * Removed four movdqa (affects the sse2 version only).
> * pxor is now used to clear m0 only once.
OK.
--
Christophe
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On 21/08/14 10:03 AM, Hendrik Leppkes wrote:
> On Thu, Aug 21, 2014 at 12:42 AM, James Almer wrote:
>> * Reduced xmm register count to 7 (As such they are now enabled for x86_32).
>> * Removed four movdqa (affects the sse2 version only).
>> * pxor is now used to clear m0 only once.
>>
>> ~5% faste
On Thu, Aug 21, 2014 at 12:42 AM, James Almer wrote:
> * Reduced xmm register count to 7 (As such they are now enabled for x86_32).
> * Removed four movdqa (affects the sse2 version only).
> * pxor is now used to clear m0 only once.
>
> ~5% faster.
>
> Signed-off-by: James Almer
> ---
Good job,
