On Fri, Apr 05, 2024 at 10:41:28AM +0200, Konrad Dybcio wrote:
> Newer (SM8550+) SoCs don't seem to have a nice speedbin fuse anymore,
> but instead rely on a set of combinations of "feature code" (FC) and
> "product code" (PC) identifiers to match the bins. This series adds
> support for that.
>
On Fri, Apr 05, 2024 at 10:41:33AM +0200, Konrad Dybcio wrote:
> Add speebin data for A740, as found on SM8550 and derivative SoCs.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git
On Fri, Apr 05, 2024 at 10:41:32AM +0200, Konrad Dybcio wrote:
> On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is
> abstracted through SMEM, instead of being directly available in a fuse.
>
> Add support for SMEM-based speed binning, which includes getting
> "feature code" and
On Fri, Apr 05, 2024 at 10:41:31AM +0200, Konrad Dybcio wrote:
> From: Neil Armstrong
>
> Usually, speedbin 0 is the "super SKU", a.k.a the one which can clock
> the highest. Falling back to it when things go wrong is largely
> suboptimal, as more often than not, the top frequencies are not
>
On Fri, Apr 05, 2024 at 10:41:29AM +0200, Konrad Dybcio wrote:
> In preparation for parsing the chip "feature code" (FC) and "product
> code" (PC) (essentially the parameters that let us conclusively
> characterize the sillicon we're running on, including various speed
> bins), move the socinfo
On Fri, Apr 05, 2024 at 10:41:30AM +0200, Konrad Dybcio wrote:
> Introduce getters for SoC product and feature codes and export them.
>
> Signed-off-by: Konrad Dybcio
> ---
> drivers/soc/qcom/smem.c | 66
> +++
> include/linux/soc/qcom/smem.h | 2
On Fri, Apr 05, 2024 at 05:17:14PM -0700, Abhinav Kumar wrote:
> From: Kuogee Hsieh
>
> In the external HPD case, hotplug event is delivered by pmic glink to DP
> driver
> using drm_aux_hpd_bridge_notify().
There can be other drivers in front of the DP chain. For example,
altmode driver uses
On Fri, 5 Apr 2024 at 18:59, Arnd Bergmann wrote:
>
> From: Arnd Bergmann
>
> The modification to a6xx_get_shader_block() had no effect other
> than causing a warning:
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:843:6: error: variable 'out' set
> but not used
On Fri, 5 Apr 2024 at 21:17, Abhinav Kumar wrote:
>
>
>
> On 4/5/2024 11:16 AM, Dmitry Baryshkov wrote:
> > On Fri, 5 Apr 2024 at 20:20, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/9/2024 7:09 AM, Dmitry Baryshkov wrote:
>
On Fri, 5 Apr 2024 at 20:20, Abhinav Kumar wrote:
>
>
>
> On 3/9/2024 7:09 AM, Dmitry Baryshkov wrote:
> > All the bridges that are being used with the MSM DSI hosts have been
> > converted to support DRM_BRIDGE_ATTACH_NO_CONNECTOR. Drop the fallb
On Fri, 5 Apr 2024 at 20:35, Abhinav Kumar wrote:
>
>
>
> On 3/9/2024 7:09 AM, Dmitry Baryshkov wrote:
> > Currently the MSM DSI driver looks for the next bridge during
> > msm_dsi_modeset_init(). If the bridge is not registered at that point,
> > this might resu
the passing pipeline for apq8016 with this change:
>
> https://gitlab.freedesktop.org/drm/msm/-/jobs/57050562
>
> Signed-off-by: Abhinav Kumar
> ---
> drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt | 13 +
> 1 file changed, 1 insertion(+), 12 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
b.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 4 ++--
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 24 +--
> drivers/gpu/drm/msm/msm_fb.c | 10
> 5 files changed, 24 insertions(+), 24 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
o the wrong register space, and maybe some other
> version of this phy relies on this.
>
> Cc: Douglas Anderson
> Cc: Abhinav Kumar
> Cc: Dmitry Baryshkov
> Cc: Neil Armstrong
> Cc: Abel Vesa
> Cc: Steev Klimaszewski
> Cc: Johan Hovold
> Cc: Bjorn Andersson
e
> monitors are very specific about their link clk frequency and if the
> default power on reset value is still there the monitor will show a
> blank screen or a garbled display. Other monitors are perfectly happy to
> get a bad clock signal.
>
> Cc: Douglas Anderson
> Cc: Abhinav Ku
On Wed, Apr 03, 2024 at 10:22:37AM -0700, Kuogee Hsieh wrote:
> Dmitry,
>
> Any more comments?
>
> On 3/29/2024 12:50 PM, Kuogee Hsieh wrote:
> > Currently qmp_combo_dp_power_on() always return 0 in regardless of
> > return value of cfg->configure_dp_phy(). This patch propagate
> > return value
On Wed, 3 Apr 2024 at 20:24, Kuogee Hsieh wrote:
>
> Dmitry,
>
> any more comments?
>
No, it was picked by Abhinav for msm-fixes.
--
With best wishes
Dmitry
On Wed, 3 Apr 2024 at 17:44, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年4月3日周三 17:57写道：
> >
> > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> > >
> > > From: Jonathan Marek
> > >
> > > Add necessary DPU timing and control changes for DSC to
On Wed, 3 Apr 2024 at 17:27, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年4月3日周三 17:49写道：
> >
> > On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
> > >
> > > This is follow up update to Jonathan's patch set.
> > >
> > > Changes
On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
>
> From: Jonathan Marek
>
> Support slice_per_pkt in msm driver.
>
> Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt"
> comment is incorrect.
>
> Also trim the code to simplify the dsc reference.
>
> Signed-off-by: Jonathan Marek
nfiguration")
> Signed-off-by: Jonathan Marek
> Reviewed-by: Dmitry Baryshkov
You S-o-b is missing
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
> b/drivers/gpu/drm/msm/d
On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
>
> From: Jonathan Marek
>
> The value returned by msm_dsi_wide_bus_enabled() doesn't match what the
> driver is doing in video mode. Fix that by actually enabling widebus for
> video mode.
>
> Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for
On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
>
> From: Jonathan Marek
>
> Add necessary DPU timing and control changes for DSC to work with DSI
> video mode.
>
> Signed-off-by: Jonathan Marek
> Signed-off-by: Jun Nie
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 9 +
>
On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
>
> This is follow up update to Jonathan's patch set.
>
> Changes vs V2:
> - Rebase to latest mainline.
> - Drop the INTF_CFG2_DATA_HCTL_EN change as it is handled in
> latest mainline code.
> - Drop the bonded DSI patch as I do not have device to
On Wed, 3 Apr 2024 at 12:11, Jun Nie wrote:
>
> Add variable for slice number of a DSC compression bit stream packet.
> Its value shall be specified in panel driver, or default value can be set
> in display controller driver if panel driver does not set it.
This is not a part of the standard.
As Qualcomm SM8150 got support for the DisplayPort, add displayport@
node as a valid child to the MDSS node.
Fixes: 88806318e2c2 ("dt-bindings: display: msm: dp: declare compatible string
for sm8150")
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Dmitry Baryshkov
---
.../devicetre
DisplayPort nodes must declare the dp_p1 register space in addition to
dp_p0. Add corresponding resource to DisplayPort DT nodes.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6
The property #stream-id-cells is legacy, it is not documented as valid
for the GPU. Drop it now.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Reviewed-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1
by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 99462b42cfc5..6d74867d3b61 100644
--- a/arch/arm6
Fix several warnings produced by the display nodes.
Please excuse me for the spam for sending v3 soon after v2.
Signed-off-by: Dmitry Baryshkov
---
Changes in v3:
- Added tags which I forgot in v2
- Added the Fixes tag to the dp_p1 fix
- Link to v2:
https://lore.kernel.org/r/20240402-fd-fix
DisplayPort nodes must declare the dp_p1 register space in addition to
dp_p0. Add corresponding resource to DisplayPort DT nodes.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot
Fix several warnings produced by the display nodes.
Signed-off-by: Dmitry Baryshkov
---
Changes in v2:
- Added Fixes tag to the DP change (Abhinav)
- Switched the schema patch to use contains (Krzysztof)
- Link to v1:
https://lore.kernel.org/r/20240326-fd-fix-schema-v1-0-4475d6d6d...@linaro.org
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-
As Qualcomm SM8150 got support for the DisplayPort, add displayport@
node as a valid child to the MDSS node.
Fixes: 88806318e2c2 ("dt-bindings: display: msm: dp: declare compatible string
for sm8150")
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/qcom,sm8150
The property #stream-id-cells is legacy, it is not documented as valid
for the GPU. Drop it now.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 -
1 file changed, 1 deletio
On Mon, 1 Apr 2024 at 23:15, Kuogee Hsieh wrote:
>
>
> On 4/1/2024 9:25 AM, Kuogee Hsieh wrote:
> >
> > On 2/3/2024 5:47 AM, Dmitry Baryshkov wrote:
> >> Both dp_link_adjust_levels() and dp_ctrl_update_vx_px() limit swing and
> >> pre-emphasis to 2, w
Now as the headers are generated during the build step, drop
pre-generated copies of the Adreno A6xx GMU header.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 422 --
1 file changed, 422 deletions(-)
diff --git a/drivers/gpu/drm/msm
As a preparation to removal of a6xx.xml.h, drop the C++ part of the
heder, it is not used by the kernel anyway.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 2478 -
1 file changed, 2478 deletions(-)
diff --git a/drivers/gpu/drm/msm
Import the gen_headers.py script from Mesa, commit b5414e716684
("freedreno/registers: Add license header"). This script will be used to
generate MSM register files on the fly during compilation.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/registers/gen_heade
Generate DRM/MSM headers on the fly during kernel build. This removes a
need to push register changes to Mesa with the following manual
synchronization step. Existing headers will be removed in the following
commits (split away to ease reviews).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
Two core driver files include headers from Adreno subdir, which also
brings dependency on the Adreno register headers. Rework those includes
to remove unnecessary dependency.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
drivers/gpu/drm/msm/msm_gpu.c | 2 +-
2 files
The qfprom.xml.h contains definitions for the nvmem code. They are not
used in the existing code. Also if we were to use them later, we should
have used nvmem cell API instead of using these defs. Drop the file.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm
The msm_gpummu.c implementation is used only on A2xx and it is tied to
the A2xx registers. Rename the source file accordingly.
Reviewed-by: Akhil P Oommen
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
The mmss_cc.xml.h file describes bits of the MMSS clock controller on
APQ8064 / MSM8960 platforms. They are not used by the driver and do not
belong to the DRM MSM driver. Drop the file.
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 131
In order to stop patching the mdp5 headers, import definitions for the
writeback blocks. This part is extracted from the old Rob's patch.
Co-developed-by: Rob Clark
Signed-off-by: Rob Clark
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5
be synced
between Mesa and the kernel tree.
Unless there are any objections, I'd like to consider this a final
revision with the target of it being merged for 6.10. Please review.
Signed-off-by: Dmitry Baryshkov
---
Changes in v5:
- Updated gen_header.py to include licence header (Abhinav, Akhil)
- Split
ernel
output")
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 94
]
[drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0
ret:-22, enable true/0
[drm:dpu_encoder_phys_cmd_control_vblank_irq] *ERROR* vblank irq err id:31 pp:0
ret:-22, enable false/0
Fixes: d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
Signed-off-by: Dmitry Baryshkov
---
.
On Fri, 29 Mar 2024 at 18:48, Kuogee Hsieh wrote:
>
> At current x1e80100 interface table, interface #3 is wrongly
> connected to DP controller #0 and interface #4 wrongly connected
> to DP controller #2. Fix this problem by connect Interface #3 to
> DP controller #0 and interface #4 connect to
On Fri, 29 Mar 2024 at 06:02, Bjorn Andersson wrote:
>
> Now that the connector_type is dynamically determined, the
> connector_type of the struct msm_dp_desc is unused. Clean it up.
>
> Signed-off-by: Bjorn Andersson
> ---
> This cleans up after, and hence depends on,
>
On Fri, 29 Mar 2024 at 04:47, Jun Nie wrote:
>
> Dmitry Baryshkov 于2024年3月28日周四 23:05写道：
> >
> > On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote:
> > >
> > > Fix DSC timing and control configurations in DPU for DSI video mode.
> > > Onl
On Fri, 29 Mar 2024 at 04:16, Abhinav Kumar wrote:
>
>
>
> On 3/28/2024 5:10 PM, Dmitry Baryshkov wrote:
> > On Fri, 29 Mar 2024 at 01:42, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/28/2024 3:50 PM, Dmitry Baryshkov wrote:
>
On Fri, 29 Mar 2024 at 01:42, Abhinav Kumar wrote:
>
>
>
> On 3/28/2024 3:50 PM, Dmitry Baryshkov wrote:
> > On Thu, 28 Mar 2024 at 23:21, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/28/2024 1:58 PM, Stephen Boyd wrote:
>
On Thu, 28 Mar 2024 at 23:21, Abhinav Kumar wrote:
>
>
>
> On 3/28/2024 1:58 PM, Stephen Boyd wrote:
> > Quoting Abhinav Kumar (2024-03-28 13:24:34)
> >> + Johan and Bjorn for FYI
> >>
> >> On 3/28/2024 1:04 PM, Kuogee Hsieh wrote:
> >>> For internal HPD case, hpd_event_thread is created to
On Thu, 28 Mar 2024 at 23:36, Abhinav Kumar wrote:
>
>
>
> On 3/28/2024 2:07 PM, Kuogee Hsieh wrote:
> > Currently qmp_combo_dp_power_on() always return 0 in regardless of
> > return value of cfg->configure_dp_phy(). This patch propagate
> > return value of cfg->configure_dp_phy() all the way
nsertions(+)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote:
>
> Enable display compression (DSC v1.2) for 1080x2400 Visionox
> VTDR6130 AMOLED DSI panel. DTS property is needed to enable DSC.
> Default configuration is video mode + non-DSC for any back
> compatibility.
The changelog talks about the DSC only,
On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote:
>
> Add DSI mode property and compression mode property
>
> Signed-off-by: Jun Nie
> ---
> .../bindings/display/panel/visionox,vtdr6130.yaml | 8
> 1 file changed, 8 insertions(+)
>
> diff --git
>
On Thu, 28 Mar 2024 at 13:12, Jun Nie wrote:
>
> Fix DSC timing and control configurations in DPU for DSI video mode.
> Only compression ratio 3:1 is handled and tested.
>
> This patch is modified from patchs of Jonathan Marek.
>
> Signed-off-by: Jun Nie
This almost looks like a joke, except it
> drivers/gpu/drm/msm/dp/dp_debug.h | 38 +++-
> drivers/gpu/drm/msm/dp/dp_display.c | 10 ++-
> 3 files changed, 31 insertions(+), 76 deletions(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Wed, 27 Mar 2024 at 10:45, Krzysztof Kozlowski
wrote:
>
> On 26/03/2024 21:02, Dmitry Baryshkov wrote:
> > diff --git
> > a/Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml
> > b/Documentation/devicetree/bindings/display/msm/qcom,sm8150-mdss.yam
On Wed, 27 Mar 2024 at 01:49, Abhinav Kumar wrote:
>
>
>
> On 3/22/2024 3:57 PM, Dmitry Baryshkov wrote:
> > Generate DRM/MSM headers on the fly during kernel build. This removes a
> > need to push register changes to Mesa with the following manual
> > synchron
On Wed, 27 Mar 2024 at 00:34, Abhinav Kumar wrote:
>
>
>
> On 3/26/2024 3:25 PM, Dmitry Baryshkov wrote:
> > On Wed, 27 Mar 2024 at 00:19, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/22/2024 3:57 PM, Dmitry Baryshkov wrote:
&g
On Wed, 27 Mar 2024 at 00:19, Abhinav Kumar wrote:
>
>
>
> On 3/22/2024 3:57 PM, Dmitry Baryshkov wrote:
> > Import the gen_headers.py script from Mesa, commit FIXME. This script
> > will be used to generate MSM register files on the fly during
> > compilation.
On Tue, 26 Mar 2024 at 23:39, Abhinav Kumar wrote:
>
>
>
> On 3/22/2024 3:56 PM, Dmitry Baryshkov wrote:
> > In order to stop patching the mdp5 headers, import definitions for the
> > writeback blocks. This part is extracted from the old Rob's patch.
> >
> > Co
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-
DisplayPort nodes must declare the dp_p1 register space in addition to
dp_p0. Add corresponding resource to DisplayPort DT nodes.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot
As Qualcomm SM8150 got support for the DisplayPort, add displayport@
node as a valid child to the MDSS node.
Signed-off-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/qcom,sm8150-mdss.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git
a/Documentation
The property #stream-id-cells is legacy, it is not documented as valid
for the GPU. Drop it now.
Fixes: 494dec9b6f54 ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 -
1 file changed, 1 deletio
Fix several warnings produced by the display nodes.
Signed-off-by: Dmitry Baryshkov
---
Dmitry Baryshkov (4):
dt-bindings: display/msm: sm8150-mdss: add DP node
arm64: dts: qcom: sc8180x: drop legacy property #stream-id-cells
arm64: dts: qcom: sc8180x: Drop flags for mdss irqs
On Tue, 26 Mar 2024 at 21:32, Abhinav Kumar wrote:
>
>
>
> On 3/26/2024 12:10 PM, Dmitry Baryshkov wrote:
> > On Tue, 26 Mar 2024 at 20:31, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/26/2024 11:19 AM, Dmitry Baryshkov wrote:
&
On Tue, 26 Mar 2024 at 20:31, Abhinav Kumar wrote:
>
>
>
> On 3/26/2024 11:19 AM, Dmitry Baryshkov wrote:
> > On Tue, 26 Mar 2024 at 20:05, Miguel Ojeda
> > wrote:
> >>
> >> Hi,
> >>
> >> In today's next, I got:
> >>
> &g
On Tue, 26 Mar 2024 at 20:05, Miguel Ojeda
wrote:
>
> Hi,
>
> In today's next, I got:
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:843:6: error: variable
> 'out' set but not used [-Werror,-Wunused-but-set-variable]
>
> `out` seems to be there since commit 64d6255650d4 ("drm/msm: More
>
gt; drivers/gpu/drm/msm/dp/dp_catalog.c | 39
> +
> drivers/gpu/drm/msm/dp/dp_catalog.h | 18 +
> 3 files changed, 28 insertions(+), 49 deletions(-)
Reviewed-by: Dmitry Baryshkov
Thanks a lot for the cleanup!
--
With best wishes
Dmitry
files changed, 17 insertions(+), 18 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
an across the calling of the functions,
> so replace this member with a function argument.
Definitely yes, thank you!
Reviewed-by: Dmitry Baryshkov
>
> Signed-off-by: Bjorn Andersson
> ---
> drivers/gpu/drm/msm/dp/dp_aux.c | 9 +++--
> drivers/gpu/drm/msm/dp/dp_catalog.c
gpu/drm/msm/dp/dp_ctrl.c| 17 +
> drivers/gpu/drm/msm/dp/dp_panel.h | 1 -
> 4 files changed, 3 insertions(+), 19 deletions(-)
Reviewed-by: Dmitry Baryshkov
Kuogee could you possibly comment, why was this necessary at all?
--
With best wishes
Dmitry
On Tue, 26 Mar 2024 at 17:06, Bjorn Andersson wrote:
>
> From: Bjorn Andersson
>
> The members of struct dp_debug are no longer used, so the only purpose
> of this struct is as a type of the return value of dp_debug_get(), to
> signal success/error.
>
> Drop the struct in favor of signalling the
it into somewhat logical chunks,
but I think it doesn't make sense for such cleanup.
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
ssed that while migrating to drm_dbg wrappers.
>
> Fixes: 7cb017db1896 ("drm/msm: Move FB debug prints to drm_dbg_state()")
> Fixes: 721c6e0c6aed ("drm/msm: Move vblank debug prints to drm_dbg_vbl()")
> Signed-off-by: Stephen Boyd
Reviewed-by: Dmitry Baryshk
On Mon, 25 Mar 2024 at 15:33, Akhil P Oommen wrote:
>
> On Sun, Mar 24, 2024 at 12:57:43PM +0200, Dmitry Baryshkov wrote:
> > On Sun, 24 Mar 2024 at 12:30, Akhil P Oommen
> > wrote:
> > >
> > > On Sat, Mar 23, 2024 at 12:57:02AM +0200, Dmitry Baryshkov wro
n DT, therefore, assume it's eDP if panel node
> is present.
>
> Signed-off-by: Abel Vesa
> ---
> drivers/gpu/drm/msm/dp/dp_display.c | 29 -
> 1 file changed, 28 insertions(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Sun, 24 Mar 2024 at 11:55, Akhil P Oommen wrote:
>
> On Sat, Mar 23, 2024 at 12:56:56AM +0200, Dmitry Baryshkov wrote:
> > The msm_gpummu.c implementation is used only on A2xx and it is tied to
> > the A2xx registers. Rename the source file accordingly.
> >
>
>
On Sun, 24 Mar 2024 at 12:30, Akhil P Oommen wrote:
>
> On Sat, Mar 23, 2024 at 12:57:02AM +0200, Dmitry Baryshkov wrote:
> > Generate DRM/MSM headers on the fly during kernel build. This removes a
> > need to push register changes to Mesa with the following manual
> &
Now as the headers are generated during the build step, drop
pre-generated copies of the Adreno A6xx GMU header.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 422 --
1 file changed, 422 deletions(-)
diff --git a/drivers/gpu/drm/msm
Generate DRM/MSM headers on the fly during kernel build. This removes a
need to push register changes to Mesa with the following manual
synchronization step. Existing headers will be removed in the following
commits (split away to ease reviews).
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu
Import the gen_headers.py script from Mesa, commit FIXME. This script
will be used to generate MSM register files on the fly during
compilation.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/registers/gen_header.py | 957
1 file changed, 957 insertions
The msm_gpummu.c implementation is used only on A2xx and it is tied to
the A2xx registers. Rename the source file accordingly.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/Makefile | 2 +-
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 4 +-
drivers/gpu
The qfprom.xml.h contains definitions for the nvmem code. They are not
used in the existing code. Also if we were to use them later, we should
have used nvmem cell API instead of using these defs. Drop the file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/hdmi/qfprom.xml.h | 61
The mmss_cc.xml.h file describes bits of the MMSS clock controller on
APQ8064 / MSM8960 platforms. They are not used by the driver and do not
belong to the DRM MSM driver. Drop the file.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 131
to consider this a final
revision with the target of it being merged for 6.10. Please review.
Signed-off-by: Dmitry Baryshkov
---
Changes in v4:
- Updated headers, schema and script to the latest version merged to
Mesa
- Further split of Adreno XML / Adreno headers patches in order to pass
In order to stop patching the mdp5 headers, import definitions for the
writeback blocks. This part is extracted from the old Rob's patch.
Co-developed-by: Rob Clark
Signed-off-by: Rob Clark
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h | 11 +++
1 file
On Fri, 22 Mar 2024 at 15:36, Abel Vesa wrote:
>
> On 24-03-22 15:30:54, Dmitry Baryshkov wrote:
> > On Fri, 22 Mar 2024 at 15:22, Abel Vesa wrote:
> > >
> > > Instead of relying on different compatibles for eDP and DP, lookup
> > > the panel node in devi
On Fri, 22 Mar 2024 at 15:22, Abel Vesa wrote:
>
> Add the X1E80100 DP descs and compatible. This platform will be using
> a single compatible for both eDP and DP mode. The actual mode will
> be set based on the presence of the panel node in DT.
>
> Signed-off-by: Abel Vesa
R
On Fri, 22 Mar 2024 at 15:22, Abel Vesa wrote:
>
> Instead of relying on different compatibles for eDP and DP, lookup
> the panel node in devicetree to figure out the connector type and
> then pass on that information to the PHY. External DP is not described
Nit: External DP doesn't have a panel
On Thu, 21 Mar 2024 at 20:28, Abhinav Kumar wrote:
>
>
>
> On 3/21/2024 11:09 AM, Dmitry Baryshkov wrote:
> > On Thu, 21 Mar 2024 at 19:36, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/21/2024 8:43 AM, Dmitry Baryshkov wrote:
>
On Thu, 21 Mar 2024 at 19:36, Abhinav Kumar wrote:
>
>
>
> On 3/21/2024 8:43 AM, Dmitry Baryshkov wrote:
> > On Fri, 23 Feb 2024 at 22:48, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 2/22/2024 3:43 AM, Dmitry Baryshkov wrote:
On Fri, 23 Feb 2024 at 22:48, Abhinav Kumar wrote:
>
>
>
> On 2/22/2024 3:43 AM, Dmitry Baryshkov wrote:
> > The DPU driver provides support for 4:2:0 planar YCbCr plane formats.
> > Extend it to also support 4:2:2 and 4:4:4 plat formats.
> >
>
>
On Tue, 19 Mar 2024 at 23:35, Abhinav Kumar wrote:
>
>
>
> On 3/19/2024 1:43 PM, Dmitry Baryshkov wrote:
> > On Tue, 19 Mar 2024 at 22:34, Abhinav Kumar
> > wrote:
> >>
> >>
> >>
> >> On 3/13/2024 6:10 PM, Dmitry Bary
On Tue, 19 Mar 2024 at 22:34, Abhinav Kumar wrote:
>
>
>
> On 3/13/2024 6:10 PM, Dmitry Baryshkov wrote:
> > Move perf mode handling for the bandwidth to
> > _dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
> > and then aggregating known valu
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