On Wed, Apr 22, 2015 at 5:34 PM, H.J. Lu hongjiu...@intel.com wrote:
Normally, with PIE, GCC accesses globals that are extern to the module
using GOT. This is two instructions, one to get the address of the global
from GOT and the other to get the value. Examples:
---
extern int a_glob;
On Mon, Apr 13, 2015 at 12:25 PM, Joseph Myers jos...@codesourcery.com wrote:
On Mon, 13 Apr 2015, Hale Wang wrote:
Yes, you are right. It's my fault to add the only here. Thank you to point
out this.
Beside this, is this patch OK for you?
I don't think it's a good idea for libgcc to
On Wed, Apr 22, 2015 at 9:32 AM, Hale Wang hale.w...@arm.com wrote:
-Original Message-
From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
Sent: Wednesday, April 22, 2015 3:50 PM
To: Joseph Myers
Cc: Hale Wang; GCC Patches
Subject: Re: [PATCH] [1/2] [ARM] [libgcc] Support
On Mon, Apr 20, 2015 at 7:50 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
As comments at PR65767 and PR65718, we should use namespace other than std
to avoid duplicated definition problem on arm-none-eabi. This patch fixes
the issue. It is an obvious change, but I will wait for approval
On Thu, Apr 9, 2015 at 12:10 PM, Yvan Roux yvan.r...@linaro.org wrote:
Hi
On 7 April 2015 at 22:02, Yvan Roux yvan.r...@linaro.org wrote:
On 7 April 2015 at 21:33, Jakub Jelinek ja...@redhat.com wrote:
On Tue, Apr 07, 2015 at 09:28:51PM +0200, Yvan Roux wrote:
validation is ongoing, but here
On Tue, Apr 14, 2015 at 9:33 AM, Jakub Jelinek ja...@redhat.com wrote:
On Tue, Apr 14, 2015 at 10:32:16AM +0200, Yvan Roux wrote:
The issue is more related to armv6 than M profile, but if it is widely
tested as well I can just commit the torture test if it's ok for
Jakub.
If it is tested by
On Mon, Feb 9, 2015 at 12:34 PM, Christian Bruel christian.br...@st.com wrote:
Hello,
I'd like to ping with a respin of the 7 patches for
the attribute target (thumb,arm) [0-6] :
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02455.html
On Thu, Mar 5, 2015 at 1:34 PM, Xingxing Pan xxing...@marvell.com wrote:
Hi,
The expanding of widen-sum pattern always fails. The vectorizer expects the
operands to have the same size, while the current implementation of
widen-sum pattern dose not conform to this.
This patch implements the
On Mon, Apr 13, 2015 at 2:49 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is an update to
https://gcc.gnu.org/ml/gcc-patches/2014-11/msg02706.html,
rebased on top of the new cores that went in since that time.
It's just a refactoring.
Bootstrapped and tested on arm-linux.
On Tue, Apr 14, 2015 at 1:37 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The load/store-multiple expanders reject a number of registers outside of
[2-14]
but the arm_gen_{load,store}_multiple functions that they called down to
have an even
stricter restriction of =
On Mon, Mar 23, 2015 at 4:15 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The ICE in the PR happens on arm during the hoist pass when the code
generates a SET rtx of the form:
(set (reg:OI) (const_int 0)). It checks whether const_int 0 is a
general_operand for OImode which
On Fri, Apr 3, 2015 at 5:17 PM, Sebastian Pop seb...@gmail.com wrote:
Hi,
On Thu, Apr 2, 2015 at 5:51 PM, James Greenhalgh
james.greenha...@arm.com wrote:
Trunk is currently in Stage 4 development, these patches are fairly
low-risk, but they are certainly not regression fixes. I'll defer
to
On Wed, Mar 18, 2015 at 10:19 AM, Yvan Roux yvan.r...@linaro.org wrote:
Hi,
This is a fix for PR64208 where LRA loops when dealing with
iwmmxt_arm_movdi insn. As explain in the PR, the issue was introduced
on trunk and 4.9 branch by fix of PR rtl-optimization/60969 and then
workaround by
On Tue, Mar 17, 2015 at 3:34 AM, Bin.Cheng amker.ch...@gmail.com wrote:
On Fri, Mar 13, 2015 at 7:56 PM, Ramana Radhakrishnan
ramana@googlemail.com wrote:
On Fri, Mar 6, 2015 at 7:46 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
This patch is the second part fixing memset-inline-{4,5,6,8,9
On 03/03/15 17:59, Kyrylo Tkachov wrote:
-Original Message-
From: Kyrylo Tkachov
Sent: 27 February 2015 14:30
To: Kyrylo Tkachov; GCC Patches
Cc: Ramana Radhakrishnan; Richard Earnshaw
Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with -
mtune=xscale: properly sign
On Fri, Mar 6, 2015 at 7:42 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
This patch is the first part fixing memset-inline-{4,5,6,8,9}.c failures on
cortex-a9. GCC/arm doesn't generate any tuning information in assembly, it
can't tell whether we are compiling for cortex-a9 tune if the compiler
On Fri, Mar 6, 2015 at 7:46 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
This patch is the second part fixing memset-inline-{4,5,6,8,9}.c failures on
cortex-a9. It adds a function checking CPU tuning information in dejagnu,
it also uses that function to skip related testcase when we are
On 11/03/2015 02:11, 박준모 wrote:
Hi all,
This patch only affect sha2 crypto instruction's order when gcc
performs instruction scheduling(rtl-sched1,2).
There are no definition for crypto_sha256_fast, crypto_sha256_slow on
cortex-a57.md.
This makes poor result of instruction
Attached patch as text.
2015-03-11 Junmo Park junmoz.p...@samsung.com
* config/arm/cortex-a57.md (cortex_a57_crypto_simple): Add
crypto_sha256_fast.
(cortex_a57_crypto_complex): Add crypto_sha256_slow.
Ok to commit to trunk?
OK, Thanks Sebastian.
regards
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7bf5b4d..777230e 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -6392,14 +6392,8 @@ arm_set_default_type_attributes (tree type)
static bool
arm_function_in_section_p (tree decl, section *section)
{
- /* We
On Thu, Dec 18, 2014 at 10:13 AM, Xingxing Pan xxing...@marvell.com wrote:
Hi,
This patch contains Marvell Whitney core's pipeline description.
Test on arm-linux-gnueabi and no new regression are found.
Is it OK for trunk?
I haven't had a chance to review this in detail but I think it's too
;; Crude Advanced SIMD approximation.
(define_insn_reservation cortex_53_advsimd 4
(and (eq_attr tune cortexa53)
(eq_attr:q is_neon_type yes))
cortex_a53_simd0)
Does it mean that all AdvSIMD instructions
On Thu, Feb 19, 2015 at 9:17 AM, Marat Zakirov m.zaki...@samsung.com wrote:
Hi all!
During my investigation I found that GCC does not performs load/store
widening (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65088). Could you
please answer is it so? And is there any plans to make it? I also
On Fri, Jan 23, 2015 at 8:23 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
Hi Ramana,
From: Ramana Radhakrishnan [mailto:ramana@googlemail.com]
Sent: Wednesday, January 14, 2015 7:21 PM
On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
When
On Tue, Jan 20, 2015 at 5:06 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
Currently on GCC 4.8 and 4.9, constant pool entries for QImode, HImode and
SImode values are filled as 32-bit quantities. This works fine for little
endian system but gives some incorrect results for big
On Fri, Jan 23, 2015 at 2:07 AM, Sandra Loosemore
san...@codesourcery.com wrote:
The ARM run-time ABI says that long long division by zero should return the
result of calling __aeabi_ldiv0 with an argument that is either zero if the
numerator is zero, the largest value of the type if the
On Thu, Feb 12, 2015 at 3:18 PM, Ulrich Weigand uweig...@de.ibm.com wrote:
Hello,
we're running into a problem related to use of initial-exec access to
TLS variables in dynamically-loaded libraries. Now, in general, this
is actually not supported. However, there seems to an inofficial
Changelog:
* gcc.dg/guality/pr36728-1.c: Skip some tests for arm.
Segher and I discussed an alternative approach - marking these as m
(arg1) , m (arg2) etc in the asm blocks also gives us the same
effect and then probably removes the need to rely on such target
markers. I've just
On 04/02/2015 11:10, Jakub Jelinek wrote:
On Wed, Feb 04, 2015 at 11:03:29AM +, Ramana Radhakrishnan wrote:
Changelog:
* gcc.dg/guality/pr36728-1.c: Skip some tests for arm.
Segher and I discussed an alternative approach - marking these as m
(arg1) , m (arg2) etc in the asm
On 04/02/2015 11:40, Jakub Jelinek wrote:
On Wed, Feb 04, 2015 at 11:33:19AM +, Ramana Radhakrishnan wrote:
--- a/gcc/testsuite/gcc.dg/guality/pr36728-1.c
+++ b/gcc/testsuite/gcc.dg/guality/pr36728-1.c
@@ -49,5 +49,6 @@ main ()
int l = 0;
asm ( : =r (l) : 0 (l));
a = foo (l
On Wed, Feb 4, 2015 at 10:36 AM, Matthew Wahab matthew.wa...@arm.com wrote:
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as the
Cortex-A57. This patch adds support for the command line option
-mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option,
On Wed, Feb 4, 2015 at 12:57 PM, Marcus Shawcroft
marcus.shawcr...@gmail.com wrote:
On 4 February 2015 at 10:35, Matthew Wahab matthew.wa...@arm.com wrote:
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as the
Cortex-A57. This patch adds support for the command
Hi,
I decided to spend some time looking at the large number of guality
test failures on arm. I see a number of fails with
gcc.dg/guality/pr36728-1.c as below. pr36728-2.c also fails in similar
sort of ways. Before I go adjusting too many other tests I'd like to get
some feedback regarding
On 29/01/15 11:40, Kyrill Tkachov wrote:
Hi all,
This is another cleanup patch that simplifies some expressions of the
form (expr ? true : false) or if (boolean == true) and other minor
cleanups.
Tested arm-none-eabi.
Ok for trunk? Or should this wait for the next stage?
Thanks,
Kyrill
On Fri, Jan 9, 2015 at 7:43 AM, Terry Guo terry@arm.com wrote:
-Original Message-
From: Richard Earnshaw
Sent: Monday, December 08, 2014 7:31 PM
To: Terry Guo; gcc-patches@gcc.gnu.org
Cc: Ramana Radhakrishnan
Subject: Re: [Patch, ARM/Thumb1]Add a Thumb1 insn pattern to legalize
On Tue, Jan 27, 2015 at 4:06 PM, Alex Velenko alex.vele...@arm.com wrote:
Hi,
This patch fixes arm/atomic-op-consume.c test to expect safe LDAEX
instruction to be generated when __ATOMIC_CONSUME semantics is requested.
This patch was tested by running the modified test on arm-none-eabi and
On Mon, Jan 19, 2015 at 5:44 PM, James Greenhalgh
james.greenha...@arm.com wrote:
On Fri, Jan 16, 2015 at 11:14:42AM +, Ramana Radhakrishnan wrote:
On 16/01/15 10:20, Marcus Shawcroft wrote:
On 15 January 2015 at 09:50, James Greenhalgh james.greenha...@arm.com
wrote:
2015-01-15
On Thu, Jan 15, 2015 at 12:10 PM, Tony Liu tony@arm.com wrote:
Hi,
This is the patch to improve the test case gcc.target/arm/scd42-1.c for both
UAL and non-UAL. It now checks UAL format assembly code for Thumb1 and
Thumb2 while non-UAL format assembly code for ARM mode.
OK.
Ramana
On 19/01/15 18:14, Maxim Kuvyrkov wrote:
On Jan 19, 2015, at 6:05 PM, Richard Earnshaw rearn...@arm.com wrote:
On 16/01/15 15:06, Maxim Kuvyrkov wrote:
@@ -1874,7 +1889,8 @@ const struct tune_params arm_cortex_a15_tune =
true, true, /* Prefer 32-bit
On 19/01/15 21:05, James Greenhalgh wrote:
On Mon, Jan 19, 2015 at 08:57:31PM +, Gerald Pfeifer wrote:
On Monday 2015-01-19 17:52, James Greenhalgh wrote:
OK after the Cortex-A57 scheduling description goes in to the ARM port?
Yes, thanks, except that once will be sufficient. ;-) (The
On Tue, Jan 13, 2015 at 1:32 PM, Matthew Wahab matthew.wa...@arm.com wrote:
Hello,
The LRA register alloator is enabled by default for the ARM backend and
-mno-lra should no longer be used. This patch removes the -mlra/-mno-lra
option from the ARM backend.
arm-none-linux-gnueabihf passes
and looked at it.
Applied.
Ramana
DATE Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/64532
* doc/md.texi (ARM Constraints): Document register constraints.
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 7bc7842..0050ba7 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc
What is aarch64 specific on the testcase?
The number of if-then-else's required to get the compiler to generate
cmp branch sequences rather than the tbnz instruction.
Ramana
On Thu, Jan 15, 2015 at 4:11 AM, Andrew Pinski pins...@gmail.com wrote:
Hi,
I have some code where we generate some weird code that has stores
followed by a load from the same location.
For an example we get:
add x14, sp, 240
add x15, sp, 232
str x14, [sp, 136]
mov w2, w27
ldr w1, [sp,
On 16/01/15 10:20, Marcus Shawcroft wrote:
On 15 January 2015 at 09:50, James Greenhalgh james.greenha...@arm.com wrote:
2015-01-15 James Greenhalgh james.greenha...@arm.com
* config/arm/cortex-a57.md: New.
* config/aarch64/aarch64.md: Include it.
*
On Thu, Nov 13, 2014 at 5:54 AM, Bin Cheng bin.ch...@arm.com wrote:
Hi,
As commented at https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00684.html,
this is a simple patch enabling neon memset inlining on
cortex-a53/cortex-a57 in AArch32 mode.
Test on
On Fri, Jan 16, 2015 at 3:06 PM, Maxim Kuvyrkov
maxim.kuvyr...@linaro.org wrote:
On Nov 19, 2014, at 12:27 PM, Ramana Radhakrishnan
ramana.radhakrish...@arm.com wrote:
Hi Ramana,
Hi Vladimir,
I still don't have SPEC2000/SPEC2006 benchmark numbers for this patch. Since
stage3 is about
On Fri, Jan 16, 2015 at 3:06 PM, James Greenhalgh
james.greenha...@arm.com wrote:
On Fri, Jan 16, 2015 at 10:20:40AM +, Marcus Shawcroft wrote:
On 15 January 2015 at 09:50, James Greenhalgh james.greenha...@arm.com
wrote:
2015-01-15 James Greenhalgh james.greenha...@arm.com
On 16/01/15 16:56, Kyrill Tkachov wrote:
Hi all,
As the simple PR says we should call va_end before returning early from
a function that started processing the va_list with va_start.
The C spec agrees:
Each invocation of the va_start and va_copy macros
shall be matched by a corresponding
would fail without Patch 2/3 please don't add them.
Ramana
Best regards,
Thomas
-Original Message-
From: Richard Earnshaw
Sent: Wednesday, January 14, 2015 2:53 PM
To: Thomas Preud'homme; Tony Wang; gcc-patches@gcc.gnu.org
Cc: Ramana Radhakrishnan
Subject: Re: [PATCH 3/3, ARM, libgcc
On 13/01/15 21:01, Andrew Stubbs wrote:
On 12/01/15 13:50, Ramana Radhakrishnan wrote:
In principle ok, but I'd like a comment in there explaining why we've
done this. Can you also post under what configurations these have been
tested ?
Is this better?
I tested it by running the vect.exp
On Mon, Jan 12, 2015 at 2:29 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Now with patch attached
Kyrill
On 12/01/15 14:27, Kyrill Tkachov wrote:
Hi all,
In this PR we ICE when compiling with -mtune=xscale. The ICE is a
segfault in xscale_sched_adjust_cost.
The root cause is that
On Wed, Jan 14, 2015 at 10:20 AM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
When compiling for size, live high registers are not saved in function prolog
in ARM backend in Thumb mode. The problem comes from
arm_conditional_register_usage setting call_used_regs for all high register
On 14/01/15 10:14, Hale Wang wrote:
Hi,
This patch is tuned particularly for benchmark performance on cortex-m7.
Tested with GCC regression test, no regressions. Is it ok for trunk?
BR,
Hale Wang
gcc/ChangeLog
2014-12-24 Hale Wang hale.w...@arm.com
* config/arm/arm.c: Tune the
On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/ChangeLog-2014| 10 ++
gcc/config/arm/arm-cores.def | 1 +
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md| 3 ++-
gcc/config/arm/arm.c | 22 ++
On Sun, Jan 11, 2015 at 9:55 PM, Andreas Tobler andreast-l...@fgznet.ch wrote:
Hi,
I have here a possible way to make the enum_9.f90 and the enum_10.f90 work
under arm*-*-freebsd*. The solution for enum_9.f90 is straight forward. But
the one for enum_10.f90 requires a reordering of the
On 12/01/15 20:15, Philipp Tomsich wrote:
---
gcc/config/aarch64/aarch64.md | 2 +-
gcc/config/arm/types.md | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1f6b1b6..98f4f30 100644
---
On Thu, Jan 8, 2015 at 8:51 PM, Andreas Tobler andreast-l...@fgznet.ch wrote:
On 08.01.15 17:27, Richard Earnshaw wrote:
On 29/12/14 18:44, Andreas Tobler wrote:
All,
here is the third attempt to support ARM with FreeBSD.
In the meantime we found another issue in the unwinder where I had
On 19/11/14 02:43, Joey Ye wrote:
Current thumb2 -Os generates suboptimal code for following tail call case:
int f4(int b, int a, int c, int d);
int g(int a, int b, int c, int d)
{ return f4(b, a, c, d); }
arm-none-eabi-gcc -Os -mthumb -mcpu=cortex-m3 test.c
push
{r4, lr}
mov r4, r1
mov r1,
Sorry about the slow response- have been on holiday and still catching
up on email.
On 12/01/15 13:16, Andrew Stubbs wrote:
Ping.
On 23/12/14 16:46, Andrew Stubbs wrote:
On 03/12/14 15:03, Andrew Stubbs wrote:
The tools have always allowed us to drop down the arch to
march=armv5te along
On Thu, Dec 4, 2014 at 9:19 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 02/12/14 22:58, Ramana Radhakrishnan wrote:
On Tue, Nov 11, 2014 at 11:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com
wrote:
Hi all,
This is the arm implementation of the macro fusion hook.
It tries to fuse
On Thu, Dec 11, 2014 at 9:34 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
While looking in this area on other business I noticed we could be using the
names R0_REGNUM
and R1_REGNUM when creating those REG rtxs since it's a bit more descriptive
that just 0 and 1.
Tested
On Tue, Sep 23, 2014 at 4:07 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Some intrinsics had the wrong name (inconsistent with the NEON intrinsics
spec). This patch fixes that and adds the vrndx_f32 and vrndxq_f32
intrinsics that were missing.
These map down to vrintx.f32 NEON
On Mon, Dec 8, 2014 at 11:24 AM, Bernd Edlinger
bernd.edlin...@hotmail.de wrote:
Hi Kyrill,
Hi all,
As the subject says, this just fixes a typo in the fprofile-generate
option name and rewords the text in the next sentence a bit.
Ok to commit?
Thanks,
Kyrill
I think this kind of
On 20/11/14 11:54, Tom de Vries wrote:
Richard,
This patch fixes PR63718, which currently breaks Thumb1 bootstrap.
The problem is that in Thumb1 mode, we emit the epilogue in RTL, but the last
insn - epilogue_insns - does not accurately model the corresponding insns
emitted in the asm file.
On 29/11/14 06:50, Chen Shanyao wrote:
I've backported this fix to 4.8 4.9 branch.
These patches have been tested for armeb-none-eabi-gcc/g++ with qemu,
and both the test results were ok.
The Changelog should mention all authors of the original patches i.e.
include my name.
Otherwise
On Tue, Dec 2, 2014 at 2:01 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
On 23/09/14 09:27, James Greenhalgh wrote:
On Mon, Sep 15, 2014 at 11:56:03AM +0100, Andrew Stubbs wrote:
On 15/09/14 10:46, Richard Earnshaw wrote:
Hmm, I wonder if arm_override_options should reject neon + (arch
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
The following patch-series adds optimized support for the APM X-Gene 1
by providing a cost-model and pipeline-model. The pipeline-model has a
few long reservation-chains, but looking at the stats for
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
To keep this change separately buildable from the pipeline model,
this patch directs the APM XGene-1 to use the generic scheduling
model.
---
gcc/ChangeLog| 8 +++
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
---
gcc/ChangeLog | 6 +
gcc/config/aarch64/aarch64.md | 3 +-
gcc/config/arm/xgene1.md | 532
++
3 files changed, 540
CCing release maintainers as well as they need to approve this
backport if Vlad is happy with it.
Vlad - is this ok to go back as it fixes a bug for ARM in the 4.9 tree
that came up in building bits of debian.
Ramana
On Mon, Dec 1, 2014 at 5:24 PM, Renlin Li renlin...@arm.com wrote:
On
On Tue, Nov 11, 2014 at 11:55 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is the arm implementation of the macro fusion hook.
It tries to fuse movw+movt operations together. It also tries to take lo_sum
RTXs into account since those generate movt instructions as well.
intend to backport the same to the 4.9 branch as the issue exists there
too and this is just in the configury and build of the baremetal toolchain.
regards
Ramana
2014-11-28 Ramana Radhakrishnan ramana.radhakrish...@arm.com
* config/arm/t-aprofile (MULTILIB_MATCHES): New entry
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds support for the Cortex-A17 processor to the arm backend.
Cortex-A17 is an ARMv7ve core with the same architectural features as the
Cortex-A7, A12 and A15 cores.
The -m{tune, cpu}=cortex-a17
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
The Cortex-A12 very close to the Cortex-A17 and this patch updates the
tuning struct
parameters to match the Cortex-A17 ones.
This has improved performance in a number of benchmarks that I tried.
The
5:33 PM
To: Thomas Preud'homme
Cc: Tony Wang; gcc-patches@gcc.gnu.org; d...@debian.org; aph-
g...@littlepinkcloud.com; Richard Earnshaw; Ramana Radhakrishnan;
libstd...@gcc.gnu.org
Subject: Re: [Patch, ARM, ping1] Fix PR target/56846
On 26/11/14 17:23 -, Thomas Preud'homme wrote:
Ping?
I'm
On Thu, Nov 13, 2014 at 4:03 PM, Thomas Preud'homme
thomas.preudho...@arm.com wrote:
[Taking over Tony's patch]
Ping?
Best regards,
Thomas
-Original Message-
From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
ow...@gcc.gnu.org] On Behalf Of Tony Wang
Sent: Thursday,
, 2014 3:31 PM
To: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw
Subject: [PATCH][ARM] Fix PR59593/PR63742: arm *movhi_insn_arch4
pattern for big-endian
Currently, constant pool entries for QImode, HImode and SImode values
are filled as 32-bit quantities. This works fine
On Tue, Nov 18, 2014 at 10:40 AM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
Following up from adding Cortex-A17 support this patch adds a big.LITTLE
option cortex-a17.cortex-a7.
Similar to the existing cortex-a15.cortex-a7 support we schedule for
Cortex-A7 and make the other
On Wed, Oct 29, 2014 at 10:20 AM, Jiong Wang jiong.w...@arm.com wrote:
On 26/08/14 13:36, Richard Earnshaw wrote:
On 29/07/14 15:49, Jiong Wang wrote:
test done
===
no regression on the full toolchain test on arm-none-eabi.
ok to install?
Hmm, I think this is wrong for DF mode. The
On Wed, Nov 19, 2014 at 2:54 PM, Christian Bruel christian.br...@st.com wrote:
On 11/19/2014 03:18 PM, Ramana Radhakrishnan wrote:
On Wed, Nov 19, 2014 at 1:24 PM, Christian Bruel christian.br...@st.com
wrote:
I think I missed the stage3, Anyway would it be OK for stage1 when it
reopens
On 27/11/14 11:09, Kyrill Tkachov wrote:
On 27/11/14 08:52, Ramana Radhakrishnan wrote:
On Thu, Nov 13, 2014 at 5:25 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This patch adds support for the Cortex-A17 processor to the arm backend.
Cortex-A17 is an ARMv7ve core with the same
?
regards
Ramana
2014-11-20 Ramana Radhakrishnan ramana.radhakrish...@arm.com
PR target/59593
* config/arm/arm.md (*movhi_insn): Use right formatting
for immediate.
Index: gcc/ChangeLog
===
--- gcc
On Wed, Nov 19, 2014 at 9:42 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
Here's an updated patch with Kyrill's and Andrew's comments integrated.
I left the file in the config/arm-directory, as XGene-family is capable of
executing ARMv7 and we will wire this into the 32bit
On 14/11/14 15:12, Maxim Kuvyrkov wrote:
On Nov 14, 2014, at 8:38 AM, Jeff Law l...@redhat.com wrote:
On 10/20/14 22:06, Maxim Kuvyrkov wrote:
Hi,
Ramana, this change requires benchmarking, which I can't easily do
at
the moment. I would appreciate any benchmarking results that you can
On 19/11/14 09:29, Yangfei (Felix) wrote:
Sorry for missing the point. It seems to me that 't2' here will conflict with
condition of the pattern *movhi_insn_arch4:
TARGET_ARM
arm_arch4
(register_operand (operands[0], HImode)
|| register_operand (operands[1],
On Wed, Nov 19, 2014 at 1:24 PM, Christian Bruel christian.br...@st.com wrote:
I think I missed the stage3, Anyway would it be OK for stage1 when it
reopens ?
Since you submitted this well during stage1 and given that these
patches address comments from earlier in the review process we should
A testcase is added for all targets as I think it's a middle-end
issue. And sorry for not being able to simplify it.
arm-none-eabi has been test on the model, no new issues. bootstrapping
and regression tested on x86, no new issues.
Is it Okay to commit?
Yes. Thanks very much for working on
On 06/11/14 08:35, Yangfei (Felix) wrote:
The idea is simple: Use movw for certain const source operand instead of
ldrh. And exclude the const values which cannot be handled by
mov/mvn/movw.
I am doing regression test for this patch. Assuming no issue pops up,
OK for trunk?
On Wed, Nov 12, 2014 at 4:38 PM, Kyrill Tkachov kyrylo.tkac...@arm.com wrote:
Hi all,
This is a much-delayed respin of the patch in response to Richards feedback
at:
http://gcc.gnu.org/ml/gcc-patches/2014-05/msg00068.html
We now let recursion do its magic and just add the cost of the
On Wed, Nov 12, 2014 at 5:08 PM, James Greenhalgh
james.greenha...@arm.com wrote:
Hi,
I was taking a look at fixing the issues in the ARM back-end exposed
by Marc Glisse's patch in [1], and hoped to fix them by adapting the
patch recently commited by Tejas ([2]).
As I looked, I realised
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
As part of some wider cleanup I'd like to do to ARM's Neon Builtin
infrastructure, my first step will be to remove the Magic Words used
to decide which variant of an instruction should be emitted.
The Magic Words interface allows a single
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
If we want to move all the code relating to builtin initialisation and
expansion to a common file, we must share the processor flags with that
common file.
This patch pulls those definitions out to config/arm/arm-protos.h
Bootstrapped and
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
The config/arm/arm.c file has always seemed a worrying size to me.
This patch pulls out the builtin related code to its own file. I think
this will be a good idea as we move forward. It seems a more sensible
separation of concerns. There are no
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
These macros can always be defined as a base case of VAR1 and a recursive
case of VARn-1. At the moment, the body of VAR1 is duplicated to each
macro.
This patch makes that change.
Regression tested on arm-none-linux-gnueabihf with no issues.
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
Now we have everything we need to start keeping track of the correct
qualifiers for each Neon builtin class in the arm back-end.
Some of the ARM Neon itypes are redundant when mapped to the qualifiers
framework. For now, don't change these, we
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
The poly types end up going through the default mangler, but only
sometimes.
We don't want to change the mangling for poly types with the next patch in
this series, so add a test which should pass before and after.
I've checked that the new
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
This patch wires up builtin initialisation similar to the AArch64 backend,
making use of the qualifiers arrays to decide on types for each builtin
we hope to initialise.
We could take an old snapshot of the qualifiers code from AArch64, but as
On 12/11/14 17:10, James Greenhalgh wrote:
Hi,
This final patch clears up the remaining data structures which we no
longer have any use for...
* _QUALIFIERS macros which do not name a distinct pattern of
arguments/return types.
* The neon_builtin_type_mode enum is not needed, we can
On Mon, Nov 17, 2014 at 5:06 AM, Hale Wang hale.w...@arm.com wrote:
Hi,
Refer to the previous small multiply patch (r217175).
The conditions in the small multiply test cases are not restrictive enough.
If forcing the march=armv4t/armv5t, these cases will fail.
These cases can be used only
601 - 700 of 1493 matches
Mail list logo
