Re: [PATCH] PR82964: Fix 128-bit immediate ICEs

On Mon, Jan 15, 2018 at 11:34:19AM +, Wilco Dijkstra wrote: > This fixes PR82964 which reports ICEs for some CONST_WIDE_INT immediates. > It turns out decimal floating point CONST_DOUBLE get changed into > CONST_WIDE_INT without checking the constraint on the operand, which > results in

Re: [PATCH][WWWDOCS][AArch64][ARM] Update GCC 8 release notes

On Tue, Jan 16, 2018 at 02:21:30PM +, Tamar Christina wrote: > Hi Kyrill, > > > > > xgene1 was added a few releases ago, better to use one of the new additions > > from the above list. > > For example -mtune=cortex-r52. > > Thanks, I have updated the patch. I'll wait for an ok from an

Re: [PATCH 5/5][AArch64] fp16fml support

On Tue, Jan 09, 2018 at 06:28:09PM +, Michael Collison wrote: > Patch updated per Richard's comments. Ok for trunk? This patch adds a lot of code, much of which looks like it ought to be possible to common up using the iterators. I'm going to OK it as is, as I'd like to see this make GCC 8,

Re: [1/4] [AArch64] SVE backend support

On Fri, Jan 05, 2018 at 11:41:25AM +, Richard Sandiford wrote: > Here's the patch updated to apply on top of the v8.4 and > __builtin_load_no_speculate support. It also handles the new > vec_perm_indices and CONST_VECTOR encoding and uses VNx... names > for the SVE modes. > > Richard

Re: [PATCH][GCC][AArch64] Enable dotproduct by default for Armv8.4-a

On Tue, Jan 09, 2018 at 10:36:23AM +, Tamar Christina wrote: > Hi All, > > This patch makes the Dot Product extension mandatory on Armv8.4-A. > > Regtested on aarch64-none-elf and no regressions. OK. Thanks, James > gcc/ > 2018-01-09 Tamar Christina > >

Re: [PATCH 4/5][AArch64] Crypto sha512 and sha3

On Wed, Jan 03, 2018 at 05:30:33PM +, Michael Collison wrote: > Hi All, > > This patch adds support for the SHA-512 and SHA-3 instructions added in > Armv8.4-a. Support for the new instructions is in the form of new ACLE > intrinsics. A new command line feature modifier, +sha3, is added to

Re: [PATCH 3/5][AArch64] Crypto SM4 Support

On Wed, Jan 03, 2018 at 05:25:57PM +, Michael Collison wrote: > Hi All, > > This patch adds support for the SM3/SM4 cryptographic instructions added in > Armv8.4-a. Support for the new instructions is in the form of new ACLE > intrinsics. A new command line feature modifier, +sm4, is added to

Re: [PATCH 2/5][AArch64] Add v8.4 architecture

On Wed, Jan 03, 2018 at 05:25:17PM +, Michael Collison wrote: > Hi all, > > This patch adds support for the Arm architecture v8.4. A new command line > option, -march=armv8.4-a, is added as well as documentation. > > Bootstrapped on aarch64-none-elf. Tested with new binutils and verified all

Re: [PATCH 1/5][AArch64] Crypto command line split

On Wed, Jan 03, 2018 at 05:21:27PM +, Michael Collison wrote: > Hi all, > > This patch adds two new command line options for the legacy cryptographic > extensions AES (+aes) and SHA-1/SHA-2 (+sha2). Backward compatibility is > retained by modifying the +crypto feature modifier to enable +aes

Re: [AArch64] Reject (high (const (plus anchor offset)))

On Thu, Jan 04, 2018 at 06:15:58PM +, Richard Sandiford wrote: > The aarch64_legitimate_constant_p tests for HIGH and CONST seem > to be the wrong way round: (high (const ...)) is valid rtl that > could be passed in, but (const (high ...)) isn't. As it stands, > we disallow anchor+offset but

Re: [13/13] [AArch64] Use vec_perm_indices helper routines

On Thu, Jan 04, 2018 at 11:27:56AM +, Richard Sandiford wrote: > Ping**2 This is OK. It took me a while to get the hang of the interface - a worked example in the comment in vec-perm-indices.c would probably have been helpful. It took until your code for REV for this to really make sense to

Re: [0/4] [AArch64] Add SVE support

(Resending; this bounced) On Sat, Jan 06, 2018 at 07:39:46PM +, Richard Sandiford wrote: > James Greenhalgh <james.greenha...@arm.com> writes: > > On Fri, Nov 24, 2017 at 03:59:58PM +, Richard Sandiford wrote: > >> Richard Sandiford <richard.s

Re: Support for aliasing with variable strides

On Thu, Dec 14, 2017 at 11:00:36AM +, Richard Biener wrote: > On Fri, Nov 17, 2017 at 11:17 PM, Richard Sandiford > wrote: > > This patch adds runtime alias checks for loops with variable strides, > > so that we can vectorise them even without a restrict

Re: Allow gather loads to be used for grouped accesses

On Wed, Dec 13, 2017 at 04:53:27PM +, Jeff Law wrote: > On 11/17/2017 03:04 PM, Richard Sandiford wrote: > > Following on from the previous patch for strided accesses, this patch > > allows gather loads to be used with grouped accesses, if we otherwise > > would need to fall back to

Re: Use gather loads for strided accesses

On Wed, Dec 13, 2017 at 04:47:40PM +, Jeff Law wrote: > On 11/17/2017 03:02 PM, Richard Sandiford wrote: > > This patch tries to use gather loads for strided accesses, > > rather than falling back to VMAT_ELEMENTWISE. > > > > Tested on aarch64-linux-gnu (with and without SVE),

Re: Use single-iteration epilogues when peeling for gaps

On Wed, Dec 13, 2017 at 04:42:02PM +, Jeff Law wrote: > On 11/17/2017 08:38 AM, Richard Sandiford wrote: > > This patch adds support for fully-masking loops that require peeling > > for gaps. It peels exactly one scalar iteration and uses the masked > > loop to handle the rest. Previously we

Re: Allow single-element interleaving for non-power-of-2 strides

On Fri, Nov 17, 2017 at 06:40:13PM +, Jeff Law wrote: > On 11/17/2017 08:33 AM, Richard Sandiford wrote: > > This allows LD3 to be used for isolated a[i * 3] accesses, in a similar > > way to the current a[i * 2] and a[i * 4] for LD2 and LD4 respectively. > > Given the problems with the cost

Re: Handle peeling for alignment with masking

On Thu, Dec 14, 2017 at 12:12:01AM +, Jeff Law wrote: > On 11/17/2017 08:13 AM, Richard Sandiford wrote: > > This patch adds support for aligning vectors by using a partial > > first iteration. E.g. if the start pointer is 3 elements beyond > > an aligned address, the first iteration will

Re: Allow the number of iterations to be smaller than VF

On Mon, Nov 20, 2017 at 12:12:38AM +, Jeff Law wrote: > On 11/17/2017 08:11 AM, Richard Sandiford wrote: > > Fully-masked loops can be profitable even if the iteration > > count is smaller than the vectorisation factor. In this case > > we're effectively doing a complete unroll followed by

Re: Add support for masked load/store_lanes

On Tue, Dec 12, 2017 at 12:59:33AM +, Jeff Law wrote: > On 11/17/2017 02:36 AM, Richard Sandiford wrote: > > Richard Sandiford writes: > >> This patch adds support for vectorising groups of IFN_MASK_LOADs > >> and IFN_MASK_STOREs using conditional

Re: Handle more SLP constant and extern definitions for variable VF

On Mon, Dec 11, 2017 at 11:04:28PM +, Jeff Law wrote: > On 11/09/2017 07:20 AM, Richard Sandiford wrote: > > This patch adds support for vectorising SLP definitions that are > > constant or external (i.e. from outside the loop) when the vectorisation > > factor isn't known at compile time. It

Re: Add support for SVE scatter stores

On Thu, Dec 14, 2017 at 12:34:54AM +, Jeff Law wrote: > On 11/17/2017 03:10 PM, Richard Sandiford wrote: > > This is mostly a mechanical extension of the previous gather load > > support to scatter stores. The internal functions in this case are: > > > > IFN_SCATTER_STORE (base, offsets,

Re: Add support for SVE gather loads

On Thu, Dec 14, 2017 at 01:16:26AM +, Jeff Law wrote: > On 11/17/2017 02:58 PM, Richard Sandiford wrote: > > This patch adds support for SVE gather loads. It uses the basically > > the same analysis code as the AVX gather support, but after that > > there are two major differences: > > > > -

Re: Rework the legitimize_address_displacement hook

On Fri, Nov 17, 2017 at 07:45:28PM +, Jeff Law wrote: > On 11/17/2017 09:03 AM, Richard Sandiford wrote: > > This patch: > > > > - tweaks the handling of legitimize_address_displacement > > so that it gets called before rather than after the address has > > been expanded. This means that

Re: Add support for conditional reductions using SVE CLASTB

On Wed, Dec 13, 2017 at 04:59:00PM +, Jeff Law wrote: > On 11/17/2017 08:29 AM, Richard Sandiford wrote: > > This patch uses SVE CLASTB to optimise conditional reductions. It means > > that we no longer need to maintain a separate index vector to record > > the most recent valid value, and no

Re: Add support for vectorising live-out values using SVE LASTB

On Wed, Dec 13, 2017 at 04:36:47PM +, Jeff Law wrote: > On 11/17/2017 08:24 AM, Richard Sandiford wrote: > > This patch uses the SVE LASTB instruction to optimise cases in which > > a value produced by the final scalar iteration of a vectorised loop is > > live outside the loop. Previously

Re: Add an empty_mask_is_expensive hook

On Fri, Nov 17, 2017 at 06:12:49PM +, Jeff Law wrote: > On 11/17/2017 08:15 AM, Richard Sandiford wrote: > > This patch adds a hook to control whether we avoid executing masked > > (predicated) stores when the mask is all false. We don't want to do > > that by default for SVE. > > > > Tested

Re: Add support for reductions in fully-masked loops

On Wed, Dec 13, 2017 at 04:34:34PM +, Jeff Law wrote: > On 11/17/2017 07:59 AM, Richard Sandiford wrote: > > This patch removes the restriction that fully-masked loops cannot > > have reductions. The key thing here is to make sure that the > > reduction accumulator doesn't include any values

Re: [3/4] [AArch64] SVE tests

On Sat, Jan 06, 2018 at 07:13:22PM +, Richard Sandiford wrote: > James Greenhalgh <james.greenha...@arm.com> writes: > > On Fri, Nov 03, 2017 at 05:50:54PM +, Richard Sandiford wrote: > >> This patch adds gcc.target/aarch64 tests for SVE, and forces some > >

Re: Add support for fully-predicated loops

On Mon, Dec 18, 2017 at 07:40:00PM +, Jeff Law wrote: > On 11/17/2017 07:56 AM, Richard Sandiford wrote: > > This patch adds support for using a single fully-predicated loop instead > > of a vector loop and a scalar tail. An SVE WHILELO instruction generates > > the predicate for each

Re: Add support for bitwise reductions

On Thu, Dec 14, 2017 at 12:36:58AM +, Jeff Law wrote: > On 11/22/2017 11:12 AM, Richard Sandiford wrote: > > Richard Sandiford writes: > >> This patch adds support for the SVE bitwise reduction instructions > >> (ANDV, ORV and EORV). It's a fairly mechanical

Re: SLP reductions with variable-length vectors

On Thu, Dec 14, 2017 at 12:43:11AM +, Jeff Law wrote: > On 11/22/2017 11:10 AM, Richard Sandiford wrote: > > Richard Sandiford writes: > >> Two things stopped us using SLP reductions with variable-length vectors: > >> > >> (1) We didn't have a way of constructing

Re: [0/4] [AArch64] Add SVE support

On Fri, Nov 24, 2017 at 03:59:58PM +, Richard Sandiford wrote: > Richard Sandiford writes: > > This series adds support for ARM's Scalable Vector Extension. > > More details on SVE can be found here: > > > > > >

Re: [3/4] [AArch64] SVE tests

On Fri, Nov 03, 2017 at 05:50:54PM +, Richard Sandiford wrote: > This patch adds gcc.target/aarch64 tests for SVE, and forces some > existing Advanced SIMD tests to use -march=armv8-a. I'm going to assume that these new testcases are broadly sensible, and not spend any significant time

Re: [2/4] [AArch64] Testsuite markup for SVE

On Fri, Nov 03, 2017 at 05:49:56PM +, Richard Sandiford wrote: > This patch adds new target selectors for SVE and updates existing > selectors accordingly. It also XFAILs some tests that don't yet > work for some SVE modes; most of these go away with follow-on > vectorisation enhancements.

Re: PING: [11/nn] [AArch64] Set NUM_POLY_INT_COEFFS to 2

On Fri, Jan 05, 2018 at 11:26:59AM +, Richard Sandiford wrote: > Ping. Here's the patch updated to apply on top of the v8.4 and > __builtin_load_no_speculate support. > > Richard Sandiford writes: > > This patch switches the AArch64 port to use 2 poly_int

Re: [Patch][Aarch64] Fix multi-arch support in ILP32 mode

On Thu, Dec 21, 2017 at 06:56:22PM +, Steve Ellcey wrote: > This one line patch for multi-arch support on Aarch64 and ILP32 was > submitted over a year ago and pinged a number of time since then, > since no one has objected and since it is only one line I am going > to check it in as an

Re: [Patch combine] Don't create vector mode ZERO_EXTEND from subregs

On Sun, Dec 17, 2017 at 03:14:08AM +, Segher Boessenkool wrote: > Hi! > > On Mon, Dec 11, 2017 at 02:18:53PM +0000, James Greenhalgh wrote: > > > > In simplify_set we try transforming the paradoxical subreg expression: > > > > (set FOO (subreg:M (mem:N BAR)

Re: [Patch][Aarch64] Fix aarch64 libatomic build with older binutils

On Thu, Dec 07, 2017 at 11:56:55PM +, Steve Ellcey wrote: > James, > > Here is a patch that will turn off the use of IFUNC and the LSE > instructions in libatomic if the compiler/assembler toolchain do not > understand the '-march=armv8-a+lse' option (changed from > -march=armv8.1-a).  Rather

Re: [PATCH PR81228][AARCH64] Fix ICE by adding LTGT in vec_cmp

On Wed, Dec 13, 2017 at 04:45:33PM +, Sudi Das wrote: > On 13/12/17 16:42, Sudakshina Das wrote: > > Hi > > > > This patch is a follow up to the existing discussions on > > https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01904.html > > Bin had earlier submitted a patch to fix the ICE that

Re: [PATCH][AArch64] Specify fp16 support for Cortex-A55 and Cortex-A75

On Mon, Dec 11, 2017 at 01:44:23PM +, Kyrill Tkachov wrote: > Hi all, > > The Cortex-A55 and Cortex-A75 processors support the fp16 extension. > We already specify them as such in the arm port. > This patch makes aarch64 consistent on this front. > > Bootstrapped and tested on

[patch AArch64] Do not perform a vector splat for vector initialisation if it is not useful

. Are the non-AArch64 parts OK? Thanks, James --- 2017-12-11 James Greenhalgh <james.greenha...@arm.com> * config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify code generation for cases where splatting a value is not useful. * simplify

[Patch combine] Don't create vector mode ZERO_EXTEND from subregs

on a branch in which I'm trying to tackle some performance regressions, so I have no live testcase for this, but it is wrong by observation. Tested on aarch64-none-elf and bootstrapped on aarch64-none-linux-gnu with no issues. OK? Thanks, James --- 2017-12-11 James Greenhalgh <james.gree

Re: [patch, fortran] Implement maxval for characters

On Wed, Dec 06, 2017 at 11:38:21AM +, Christophe Lyon wrote: > Hi, > > > On 28 November 2017 at 19:40, Thomas Koenig wrote: > > Hello world, > > > > the attached patch implements maxval for characters, an F2003 feature > > that we were missing up to now. > > > >

Re: [Patch][aarch64] Use IFUNCs to enable LSE instructions in libatomic on aarch64

On Fri, Sep 29, 2017 at 09:29:37PM +0100, Steve Ellcey wrote: > On Thu, 2017-09-28 at 12:31 +0100, Szabolcs Nagy wrote: > >  > > i think this should be improved, see below. > > diff --git a/libatomic/Makefile.am b/libatomic/Makefile.am > index d731406..92d19c6 100644 > --- a/libatomic/Makefile.am

Re: [AArch64] Fix ICEs in aarch64_print_operand

On Tue, Dec 05, 2017 at 05:57:37PM +, Richard Sandiford wrote: > Three related regression fixes: > > - We can't use asserts like: > > gcc_assert (GET_MODE_SIZE (mode) == 16); > > in aarch64_print_operand because it could trigger for invalid user input. > > - The

Re: [Patch][aarch64] Add missing thunderx2-t99 instruction scheduling pipeline descriptions.

On Mon, Dec 04, 2017 at 05:33:37PM +, Steve Ellcey wrote: > On Mon, 2017-12-04 at 17:18 +, Kyrill Tkachov wrote: > > > > +(define_insn_reservation "thunderx2t99_multiple" 1 > > > +  (and (eq_attr "tune" "thunderx2t99") > > > +   (eq_attr "type" "multiple")) > > > +  

Re: [AArch64] Fix some define_insn_and_split conditions

On Tue, Dec 05, 2017 at 02:28:56PM +, Richard Sandiford wrote: > The split conditions for aarch64_simd_bsldi_internal and > aarch64_simd_bsldi_alt were: > > "&& GP_REGNUM_P (REGNO (operands[0]))" > > But since they (deliberately) can be split before reload, the operand > matched by

Re: [PATCH][AArch64] Fix address printing on ILP32

On Thu, Nov 30, 2017 at 05:27:47PM +, Wilco Dijkstra wrote: > Fix address printing for ILP32. The md file uses 'a' in assembler > templates for symbolic addresses in adrp/add, which end up calling > aarch64_print_operand_address. However in ILP32 these are not valid > memory addresses

Re: [PATCH][AArch64] Fix ICE due to store_pair_lanes

On Mon, Nov 27, 2017 at 03:20:29PM +, Wilco Dijkstra wrote: > The recently added store_pair_lanes causes ICEs in output_operand. > This is due to aarch64_classify_address treating it like a 128-bit STR > rather than a STP. The valid immediate offsets don't fully overlap, > causing it to return

Re: [RFA][PATCH] Stack clash protection 07/08 -- V4 (aarch64 bits)

On Wed, Nov 22, 2017 at 06:28:24PM +, Jeff Law wrote: > On 11/21/2017 04:57 AM, James Greenhalgh wrote: > > I've finally built up enough courage to start getting my head around this... > Can't blame you for avoiding :-) This stuff isn't my idea of fun either. Right, here's

Re: [PATCH][GCC][DOCS][AArch64][ARM] Documentation updates adding -A extensions.

On Wed, Nov 15, 2017 at 11:51:15AM +, Tamar Christina wrote: > Hi All, > > This patch updates the documentation for AArch64 and ARM correcting the use > of the > architecture namings by adding the -A suffix in appropriate places. > > Build done on aarch64-none-elf and arm-none-eabi and no

Re: [Patch][aarch64] Use IFUNCs to enable LSE instructions in libatomic on aarch64

On Mon, Nov 20, 2017 at 07:22:15PM +, Steve Ellcey wrote: > On Mon, 2017-11-20 at 18:27 +0000, James Greenhalgh wrote: > > > > If you have the time, would you mind giving me a quick run-down of what > > design decisions went in to this patch, and why they are the right t

Re: [RFA][PATCH] Stack clash protection 07/08 -- V4 (aarch64 bits)

I've finally built up enough courage to start getting my head around this... I see one outstanding issue sitting on this patch version: On Sat, Oct 28, 2017 at 05:08:54AM +0100, Jeff Law wrote: > On 10/13/2017 02:26 PM, Wilco Dijkstra wrote: > > --param=stack-clash-protection-probe-interval=13 >

Re: [Patch][aarch64] Use IFUNCs to enable LSE instructions in libatomic on aarch64

On Mon, Nov 20, 2017 at 05:39:25PM +, Steve Ellcey wrote: > Re-ping with a CC to the Aarch64 maintainers. If I'm completely honest with myself, I don't know enough about this area to review the patch. Szabolcs' OK holds a lot of weight with me, but I'd like to understand more of the

Re: [PATCH][AArch64] Restrict POST_INC operand in aarch64_simd_mem_operand_p to register

_p doesn’t seem to check > POST_INC’s operand. Here is a patch that fixes this for me, although I am not > sure if this is the right way to address this. GCC bootstraps and it causes > no test regressions. OK! Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James >

Re: [GCC][PATCH][AArch64] Add negative tests for dotprod and set minimum version to v8.2 in the target bit.

On Tue, Nov 14, 2017 at 03:54:56PM +, Tamar Christina wrote: > Hi All, > > Dot Product is intended to only be available for Armv8.2-a and newer. > While this restriction is reflected in the intrinsics, the patterns > themselves were missing the Armv8.2-a bit. > > This means that using

Re: [COMMITTED][AArch64] Fix frame tests

On Thu, Nov 16, 2017 at 11:34:46AM +, Wilco Dijkstra wrote: > Improve the AArch64 frame tests - add -f(no-)omit-frame-pointer, > update checks and add missing tests. As a result all tests now > pass. > > Committed as obvious. Some of these are far from obvious... Even if they were obvious

Re: [PATCH][aarch64] Fix pr81356 - copy empty string with wrz, not a ldrb/strb

e I have on it points at an incorrect PR number. So, I think this is probably a safe and sensible choice. OK. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > Bootstrapped and tested without regressions, OK to checkin? > > Steve Ellcey > sell...@cavium.c

Re: [PATCH][aarch64] Put vector fnma instruction into canonical form for better code generation.

g the neg operator on  > the first operand and instead has it on the second.  This  > results in sub-optimal code generation (an extra dup instruction). > > I have moved the 'neg', rebuilt GCC and retested with this patch > There were no regressions.  OK to checkin? OK. Thanks, Jam

Re: [PATCH][AArch64] Set SLOW_BYTE_ACCESS

On Fri, Nov 17, 2017 at 03:21:31PM +, Wilco Dijkstra wrote: > Contrary to all documentation, SLOW_BYTE_ACCESS simply means accessing > bitfields by their declared type, which results in better codegeneration on > practically > any target. > > I'm thinking we should completely remove all

Re: [PATCH, AArch64] Adjust tuning parameters for Falkor

On Wed, Nov 15, 2017 at 03:00:53AM +, Luis Machado wrote: > > I think the best thing is to leave this tuning structure in place and > > just change default_opt_level to -1 to disable it at -O3. > > > > Thanks, > > Andrew > > > > Indeed that seems to be more appropriate if re-enabling

Re: [AARCH64] implements neon vld1_*_x2 intrinsics

On Wed, Nov 15, 2017 at 09:58:28AM +, Kyrill Tkachov wrote: > Hi Kugan, > > On 07/11/17 04:10, Kugan Vivekanandarajah wrote: > > Hi, > > > > Attached patch implements the vld1_*_x2 intrinsics as defined by the > > neon document. > > > > Bootstrap for the latest patch is ongoing on

Re: [PATCH][GCC][AARCH64]Bad code-gen for structure/block/unaligned memory access

On Tue, Nov 14, 2017 at 04:05:12PM +, Tamar Christina wrote: > Hi James, > > I have split off the aarch64 bit off from the generic parts and processed > your feedback. > > Attached is the reworked patch. > > Ok for Tunk? Thanks for the respin, I'm a bit confused by this comment. > diff

Re: [Patch AArch64] Stop generating BSL for simple integer code

On Wed, Oct 04, 2017 at 05:44:07PM +0100, James Greenhalgh wrote: > > On Thu, Jul 27, 2017 at 06:49:01PM +0100, James Greenhalgh wrote: > > > > On Mon, Jun 12, 2017 at 02:44:40PM +0100, James Greenhalgh wrote: > > > [Sorry for the re-send. I spotted that th

Re: [AArch64] Tweak aarch64_classify_address interface

On Mon, Oct 23, 2017 at 06:58:29PM +0100, Richard Sandiford wrote: > Ping. Makes sense. OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> James > Richard Sandiford <richard.sandif...@linaro.org> writes: > > Richard Sandiford <richard.sandif...@lin

Re: [03/nn] [AArch64] Rework interface to add constant/offset routines

se the same. > */ Some of the restrictions listed in this comment are important to keep here. > - Since this function may be used to adjust the stack pointer, we must > - ensure that it cannot cause transient stack deallocation (for example > - by first incrementing SP and then decrementing when adjusting by a > - large immediate). */ This one in particular seems like we'd want it kept nearby the code. OK with some sort of change to make the restrictions on what this code should do clear on both functions. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James

Re: [05/nn] [AArch64] Rewrite aarch64_simd_valid_immediate

rom the old CHECK macros. Thanks for the patch, this is OK for trunk. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> James > > > 2017-10-26 Richard Sandiford <richard.sandif...@linaro.org> > Alan Hayward <alan.hayw...@arm.com> >

Re: [4/4] SVE unwinding

2.c part. Thanks, James Reviewed-by: James Greenhalgh <james.greenha...@arm.com> > 2017-11-03 Richard Sandiford <richard.sandif...@linaro.org> > > libgcc/ > * config/aarch64/value-unwind.h (aarch64_vg): New function. > (DWARF_LAZY_REGISTER_VALUE):

Re: [PATCH][AArch64] Improve scheduling model for X-Gene

nary and faster build > time. Survives bootstrap. I'm trusting your judgment on whether these numbers make sense, as I have no access to specifications for xgene. OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> > > Best, > Dominik > > gcc/ChangeLog: >

Re: [PATCH][AArch64] Simplify aarch64_can_eliminate

On Tue, Aug 15, 2017 at 05:25:06PM +0100, Wilco Dijkstra wrote: > > ping > > > From: Wilco Dijkstra > Sent: 07 August 2017 15:13 > To: GCC Patches; James Greenhalgh > Cc: nd; Richard Earnshaw > Subject: [PATCH][AArch64] Simplify aarch64_can_eliminate >   &g

Re: [PATCH][AArch64] Remove aarch64_frame_pointer_required

ifferent lie which reduces complexity. It all still seems tenuous, but I think I understand the reasoning, and we've got a solid 6 months to figure out what breaks. OK (assuming this has been tested *recently* against aarch64-none-linux-gnu). Reviewed-By: James Greenhalgh <james.greenha...

Re: Be stricter about CONST_VECTOR operands

On Mon, Nov 06, 2017 at 09:10:23AM +, Richard Sandiford wrote: > The recent gen_vec_duplicate patches used CONST_VECTOR for all > constants, but the documentation says: > > @findex const_vector > @item (const_vector:@var{m} [@var{x0} @var{x1} @dots{}]) > Represents a vector constant.

Re: [PATCH][AArch64] Set default sched pressure algorithm

e mostly due to less spilling, so enable this on AArch64 > by default. > > OK for commit? OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > 2017-11-02 Wilco Dijkstra <wdijk...@arm.com> > > * config/aarch64/aarch64.c (aa

Re: [12/nn] [AArch64] Add const_offset field to aarch64_address_info

t64 routines to manipulate the offset, rather than > just handling CONST_INTs. OK. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > 2017-10-27 Richard Sandiford <richard.sandif...@linaro.org> > Alan Hayward <alan.hayw...@arm.com> &

Re: [09/nn] [AArch64] Pass number of units to aarch64_expand_vec_perm(_const)

On Fri, Oct 27, 2017 at 02:29:30PM +0100, Richard Sandiford wrote: > This patch passes the number of units to aarch64_expand_vec_perm > and aarch64_expand_vec_perm_const, which avoids a to_constant () > once GET_MODE_NUNITS is variable. OK. Reviewed-by: James Greenhalgh <james.greenh

Re: [08/nn] [AArch64] Pass number of units to aarch64_simd_vect_par_cnst_half

On Fri, Oct 27, 2017 at 02:28:57PM +0100, Richard Sandiford wrote: > This patch passes the number of units to aarch64_simd_vect_par_cnst_half, > which avoids a to_constant () once GET_MODE_NUNITS is variable. OK. Reviewed-by: James GReenhalgh <james.greenha...@arm.com> Thanks, Jame

Re: [07/nn] [AArch64] Pass number of units to aarch64_reverse_mask

On Fri, Oct 27, 2017 at 02:28:27PM +0100, Richard Sandiford wrote: > This patch passes the number of units to aarch64_reverse_mask, > which avoids a to_constant () once GET_MODE_NUNITS is variable. OK Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James >

Re: [06/nn] [AArch64] Add an endian_lane_rtx helper routine

t_mode needs to be used instead. > > This patch therefore replaces instances of: > > GEN_INT (ENDIAN_LANE_N (builtin_mode, INTVAL (op[opc]))) > > with uses of a new endian_lane_rtx function. OK. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks

Re: [PATCH][AArch64] Define MALLOC_ABI_ALIGNMENT

of anything greater than 16 bytes would require 16-byte alignment. So, assuming this macro isn't required to desribe possibly unaligned smaller allocations (for example 1 byte allocations), this is OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > 20

Re: [10/nn] [AArch64] Minor rtx costs tweak

Handling SVE modes in aarch64_hard_regno_nregs is then enough to get > the correct SET cost as well. OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > > 2017-10-27 Richard Sandiford <richard.sandif...@linaro.org> >

Re: [04/nn] [AArch64] Rename the internal "Upl" constraint

an internal-only constraint by the > addition patterns, so this patch renames it to "Uaa" ("two adds > needed"). OK. Reviewed-By: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > > 2017-10-27 Richard Sandiford <richard.sandif...@linaro.or

Re: [02/nn] [AArch64] Move code around

later patch. OK. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > > 2017-10-26 Richard Sandiford <richard.sandif...@linaro.org> > Alan Hayward <alan.hayw...@arm.com> > David Sherwood <david.sherw...@arm.c

Re: [01/nn] [AArch64] Generate permute patterns using rtx builders

easily miss an unreconizable insn. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > > 2017-10-27 Richard Sandiford <richard.sandif...@linaro.org> > Alan Hayward <alan.hayw...@arm.com> > David Sherwood <

Re: [PATCH][GCC][testsuite][mid-end][ARM][AARCH64] Fix failing vec align tests.

aks. Reviewed-by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > From: Tamar Christina > Sent: Monday, October 16, 2017 11:17 AM > To: Christophe Lyon > Cc: Rainer Orth; gcc-patches@gcc.gnu.org; nd; James Greenhalgh; Ric

Re: [PATCH][AArch64] Simplify frame layout for stack probing

On Thu, Oct 26, 2017 at 04:19:35PM +0100, James Greenhalgh wrote: > On Tue, Jul 25, 2017 at 02:58:04PM +0100, Wilco Dijkstra wrote: > > This patch makes some changes to the frame layout in order to simplify > > stack probing. We want to use the save of LR as a probe in any non-le

Re: [PATCH][AArch64] Introduce emit_frame_chain

s no alloca, SP must remain valid for the epilog to work correctly. OK. Reviewed by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > ChangeLog: > 2017-08-03 Wilco Dijkstra <wdijk...@arm.com> > > gcc/ > * config/aarch64/aarch64.h (EXIT_IGN

Re: [PATCH][AArch64] Improve aarch64_legitimate_constant_p

dress (the CONST case). OK with that case handled too (assuming that passes a bootstrap and test). Reviewed by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > ChangeLog: > 2017-07-07 Wilco Dijkstra <wdijk...@arm.com> > > * config/aarch64/aarch64.

Re: [PATCH][AArch64] Simplify frame layout for stack probing

to GCC7)? OK. Leave it a week before backporting. Reviewed by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > ChangeLog: > 2017-07-25 Wilco Dijkstra <wdijk...@arm.com> > > * config/aarch64/aarch64.c (aarch64_layout_frame): >

Re: [PATCH][AArch64] Improve addressing of TI/TFmode

> stp xzr, xzr, [x1, 24] > > rather than: > > mov x1, sp > add x1, x1, 28 > stp xzr, xzr, [x1] > > OK for commit? OK. Reviewed by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > ChangeLog: > 2017-06-2

[Patch obvious][arm testsuite] Fixup expected location in require-pic-register-loc.c

-25 James Greenhalgh <james.greenha...@arm.com> * gcc.target/arm/require-pic-register-loc.c: Use wider regex for column information. diff --git a/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c b/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c index b

Re: [PING][PATCH][Aarch64] Improve int<->FP conversions

* { dg-final { scan-assembler "fcvtzu\\t(x|d)\[0-9\]+, d\[0-9\]+" } } */ > /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" } } */ > /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" } } */ > /* { dg-final { scan-assembler "fcvtzu\\tv\[0-9\]+\.2d, v\[0-9\]+\.2d" } } */ Personally I'd have used \[ws\] but this works too. Reviewed by: James Greenhalgh <james.greenha...@arm.com> James

Re: [PATCH][GCC][ARM][AArch64] Testsuite framework changes and execution tests [Patch (8/8)]

On Thu, Oct 26, 2017 at 08:10:28AM +0100, Tamar Christina wrote: > Hi James, > > > > b3e4a2d7f5b0 100644 > > > --- a/gcc/doc/sourcebuild.texi > > > +++ b/gcc/doc/sourcebuild.texi > > > @@ -1684,6 +1684,17 @@ ARM target supports executing instructions from > > > ARMv8.2 with the FP16 extension.

Re: [PATCH][AArch64] PR60580: Fix frame pointer option magic

e backporting. This code is a mess, would macroing your magic number 2 help at all? All the double negatives give me a massive headache! Reviewed by: James Greenhalgh <james.greenha...@arm.com> Thanks, James > > ChangeLog: > 2017-08-04 Wilco Dijkstra <wdijk...@arm.com> >

Re: [PATCH][GCC][AArch64] Restrict lrint inlining on ILP32.

is a bug where > the pattern is always passed DI as the smallest mode, > and later takes a sub-reg of it to SI. This would prevent an overflow > where one was expected. > > This fixed PR/81800. > > Regtested on aarch64-none-linux-gnu and no regressions. > > Ok for tr

Re: [PATCH][GCC][ARM][AArch64] Testsuite framework changes and execution tests [Patch (8/8)]

and aarch64_be-none-elf with no issues found. > > Ok for trunk? OK from my perspective with minor fixups below, but much of this is Arm target specific so will need an Arm maintainer to look at. Any thoughts Kyrill, Ramana, Richard, Nick? Reviewed by: James Greenhalgh <james.greenha...@arm.com>

Re: [PATCH][GCC][Testsuite][ARM][AArch64] Enable Dot Product for generic tests for ARM and AArch64 [Patch (7/8)]

On Fri, Oct 06, 2017 at 01:45:15PM +0100, Tamar Christina wrote: > Hi All, > > this is a respin with the changes suggested. Note that this patch is no 8/8 > in the series. > > Regtested on arm-none-eabi, armeb-none-eabi, > aarch64-none-elf and aarch64_be-none-elf with no issues found. > > Ok

Re: [PING][PATCH][Aarch64] Improve int<->FP conversions

On Tue, Oct 17, 2017 at 01:17:04AM +0100, Michael Collison wrote: > Patch updated with all comments from James. OK with an appropriate ChangeLog and assuming it has been tested as required. Thanks, James Reviewed-by:

Re: [Patch AArch64] Stop generating BSL for simple integer code

On Thu, Jul 27, 2017 at 06:49:01PM +0100, James Greenhalgh wrote: > > On Mon, Jun 12, 2017 at 02:44:40PM +0100, James Greenhalgh wrote: > > [Sorry for the re-send. I spotted that the attributes were not right for the > > new pattern I was adding. The change between this and

Re: [PING][PATCH][Aarch64] Improve int<->FP conversions

On Sun, Oct 01, 2017 at 02:07:57AM +0100, Michael Collison wrote: > Sorry. Here is the patch. I think this needs a small amount fo rework in iterators.md - the names you've used don't follow conventions in that file (e.g. "V" normally has something to do with vectors) so could do with patching

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