[gem5-dev] changeset in gem5: slicc: fix error in conflicing symbol declara...

changeset d87a25259254 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d87a25259254 description: slicc: fix error in conflicing symbol declaration diffstat: src/mem/slicc/symbols/SymbolTable.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12

[gem5-dev] changeset in gem5: ruby: change advance_stage for flit_d

changeset a47c4db94389 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a47c4db94389 description: ruby: change advance_stage for flit_d Sets m_stage.second to the second parameter of the function. Then, for every place where advance_stage is called,

[gem5-dev] changeset in gem5: slicc: improved stalling support in protocols

changeset b300dcda5896 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b300dcda5896 description: slicc: improved stalling support in protocols Adds features to allow protocols to reschedule controllers when conditionally stalling within inport logic

[gem5-dev] changeset in gem5: ruby: change router pipeline stages to 2

changeset 6036e4555eda in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6036e4555eda description: ruby: change router pipeline stages to 2 This patch changes the router pipeline stages from 4 to 2. The canonical 4-stage router is conservative while a

[gem5-dev] changeset in gem5: slicc: enable overloading in functions not in...

changeset a86f453a7caa in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a86f453a7caa description: slicc: enable overloading in functions not in classes For many years the slicc symbol table has supported overloaded functions in external classes. This

[gem5-dev] changeset in gem5: ruby: improved stall and wait debugging

changeset 4fbe4b0adb4d in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4fbe4b0adb4d description: ruby: improved stall and wait debugging Added dprintfs and asserts for identifying stall and wait bugs. diffstat: src/mem/ruby/network/MessageBuffer.cc

Re: [gem5-dev] Review Request 2981: ruby: call setMRU from L1 controllers, not from sequencer

On July 31, 2015, 4:05 p.m., Joel Hestness wrote: I'm still pretty ambivalent about this change. There are now 4 potential ways to update MRU: (1) direct call from an action to a cache's setMRU, (2)/(3) calling an action from a transition that updates a specific cache's MRU, and (4)

[gem5-dev] changeset in gem5: slicc: support for transitions with a wildcar...

changeset 2b4fe083d17b in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=2b4fe083d17b description: slicc: support for transitions with a wildcard next state This patches adds support for transitions of the form: transition(START, EVENTS, *) { ACTIONS }

[gem5-dev] changeset in gem5: slicc: isinstance bugfix

changeset 1b21c87b7c18 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=1b21c87b7c18 description: slicc: isinstance bugfix This fix prevents spurious errors when searching for a symbol that may be located in one of multiple symbol tables. diffstat:

[gem5-dev] changeset in gem5: ruby: add useful dprints to sequencer

changeset 255ebb0b32b4 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=255ebb0b32b4 description: ruby: add useful dprints to sequencer Added two data block dprints that are useful when tracking down data check failures in the ruby random tester.

[gem5-dev] changeset in gem5: util: added .mk makefile extension to file_ty...

changeset c6c28616a57c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c6c28616a57c description: util: added .mk makefile extension to file_types.py diffstat: util/file_types.py | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diffs (11 lines): diff -r

[gem5-dev] changeset in gem5: ruby: re-added the addressToInt slicc interfa...

changeset 19515f842044 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=19515f842044 description: ruby: re-added the addressToInt slicc interface function This helper function is very useful converting address offsets to integers that can be used for

[gem5-dev] changeset in gem5: slicc: fix missing inline function in LocalVa...

changeset 198726a3c723 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=198726a3c723 description: slicc: fix missing inline function in LocalVariableAST diffstat: src/mem/slicc/ast/LocalVariableAST.py | 9 + 1 files changed, 9 insertions(+), 0 deletions(-)

[gem5-dev] changeset in gem5: ruby: give access to cache tag/data latencies...

changeset a588fceeb834 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a588fceeb834 description: ruby: give access to cache tag/data latencies from SLICC This patch exposes the tag and data array latencies to the SLICC state machines so that it can

[gem5-dev] changeset in gem5: slicc: support for multiple cache entry types...

changeset bde347fc89ae in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bde347fc89ae description: slicc: support for multiple cache entry types in the same state machine To have multiple Entry types (e.g., a cache Entry type and a directory Entry

[gem5-dev] changeset in gem5: ruby: initialize replacement policies with th...

changeset ea8bdb1d9f1e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=ea8bdb1d9f1e description: ruby: initialize replacement policies with their own simobjs this is in preparation for other replacement policies that take additional parameters.

[gem5-dev] changeset in gem5: slicc: Fix bug in enqueue and peek statements.

changeset b36204de88c0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=b36204de88c0 description: slicc: Fix bug in enqueue and peek statements. These were not generating the correct c names for types declared within a machine scope. diffstat:

Re: [gem5-dev] changeset in gem5: mem: add request types for acquire and release

Besides performance issues and unnecessary complexity, one key issue with the flags/commands are modified is that it breaks backwards compatibility with any existing packet trace. Andreas On 01/08/2015 19:17, gem5-dev on behalf of Andreas Hansson gem5-dev-boun...@gem5.org on behalf of

Re: [gem5-dev] Review Request 2981: ruby: call setMRU from L1 controllers, not from sequencer

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2981/ --- (Updated Aug. 1, 2015, 6:37 p.m.) Review request for Default. Repository: gem5

[gem5-dev] changeset in gem5: util: added .cl OpenCL extension to file_type.py

changeset 30c2e8004c0a in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=30c2e8004c0a description: util: added .cl OpenCL extension to file_type.py diffstat: util/file_types.py | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diffs (11 lines): diff -r

[gem5-dev] changeset in gem5: slicc: fatal-panic on invalid transitions

changeset 7233a5f7ac8f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7233a5f7ac8f description: slicc: fatal-panic on invalid transitions diffstat: src/mem/slicc/symbols/StateMachine.py | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines):

Re: [gem5-dev] Review Request 2787: ruby: Fixed pipeline squashes caused by aliased requests

On July 31, 2015, 11:13 p.m., Joel Hestness wrote: src/mem/ruby/system/Sequencer.cc, line 553 http://reviews.gem5.org/r/2787/diff/3/?file=48362#file48362line553 I'm still not convinced that this should be allowed, since this assumes the L1 cache is RFO. My preference is that the

[gem5-dev] changeset in gem5: syscall: Add readlink to x86 with special cas...

changeset 9abf6a7c14ab in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9abf6a7c14ab description: syscall: Add readlink to x86 with special case /proc/self/exe This patch implements the correct behavior. diffstat: src/arch/x86/linux/process.cc | 6 +++---

[gem5-dev] changeset in gem5: x86: x86 instruction-implementation bug fixes

changeset 30c700ee0d47 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=30c700ee0d47 description: x86: x86 instruction-implementation bug fixes Added explicit data sizes and an opcode type for correct execution. diffstat:

[gem5-dev] changeset in gem5: ruby: Fix for stallAndWait bug

changeset 9b3b9be42dd9 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=9b3b9be42dd9 description: ruby: Fix for stallAndWait bug It was previously possible for a stalled message to be reordered after an incomming message. This patch ensures that any

[gem5-dev] changeset in gem5: ruby: adds size and empty apis to the msg buf...

changeset 3c11859e4a81 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3c11859e4a81 description: ruby: adds size and empty apis to the msg buffer stallmap diffstat: src/mem/protocol/RubySlicc_Types.sm | 2 ++ src/mem/ruby/network/MessageBuffer.hh | 2 ++ 2

[gem5-dev] changeset in gem5: ruby: fix deadlock bug in banked array resour...

changeset 436d5dde4bb7 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=436d5dde4bb7 description: ruby: fix deadlock bug in banked array resource checks The Ruby banked array resource checks (initiated from SLICC) did a check and allocate at the same

[gem5-dev] changeset in gem5: ruby: expose access permission to replacement...

changeset 7de6f95a0817 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=7de6f95a0817 description: ruby: expose access permission to replacement policies This patch adds support that allows the replacement policy to identify each cache block's access

[gem5-dev] changeset in gem5: config: add base class for ruby controllers

changeset c0a9bdc36e52 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c0a9bdc36e52 description: config: add base class for ruby controllers The CntrlBase python class handles configuration parameters such as running counts of controllers and

[gem5-dev] changeset in gem5: slicc: support for multiple message types on ...

changeset 51f40b101a56 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=51f40b101a56 description: slicc: support for multiple message types on the same buffer This patch allows SLICC protocols to use more than one message type with a message buffer.

[gem5-dev] changeset in gem5: slicc: improve support for prefix operations

changeset 6f433e7f9767 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=6f433e7f9767 description: slicc: improve support for prefix operations This patch fixes the type handling when prefix operations are used. Previously prefix operators would

[gem5-dev] changeset in gem5: slicc: support for arbitrary DPRINTF flags (n...

changeset 53d6346f in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=53d6346f description: slicc: support for arbitrary DPRINTF flags (not just RubySlicc) This patch allows DPRINTFs to be used in SLICC state machines similar to how they are

[gem5-dev] changeset in gem5: mem: add request types for acquire and release

changeset eba4e93665fc in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=eba4e93665fc description: mem: add request types for acquire and release Add support for acquire and release requests. These synchronization operations are commonly supported by

[gem5-dev] changeset in gem5: slicc: support for local variable declaration...

changeset 3ed88c8334f1 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=3ed88c8334f1 description: slicc: support for local variable declarations in action blocks diffstat: src/mem/slicc/ast/ExprStatementAST.py | 7 +-- 1 files changed, 5 insertions(+), 2

[gem5-dev] changeset in gem5: ruby: allocate a block in CacheMemory without...

changeset bbdf1177f250 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=bbdf1177f250 description: ruby: allocate a block in CacheMemory without updating LRU state diffstat: src/mem/protocol/RubySlicc_Types.sm| 1 + src/mem/ruby/structures/CacheMemory.cc | 6

[gem5-dev] changeset in gem5: ruby: speed up function used for cache walks

changeset 4820cc8408b0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=4820cc8408b0 description: ruby: speed up function used for cache walks This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a

Re: [gem5-dev] Review Request 2984: sim: clocked object: function for converting cycles to ticks.

On July 31, 2015, 11:24 p.m., Joel Hestness wrote: src/sim/clocked_object.hh, line 222 http://reviews.gem5.org/r/2984/diff/1/?file=48302#file48302line222 Minor: Can you please add a comment on this function and ticksToCycles that these should only be used to convert ticks-cycles

Re: [gem5-dev] changeset in gem5: mem: add request types for acquire and release

Hi all, This patch has outstanding issues that were _not_ addressed. In particular, it unnecessarily increases the flag size, and adds both flags and request types when only one is needed. I suggest we either revert it or fix the outstanding issues. Thanks, Andreas On 01/08/2015 17:51,

Re: [gem5-dev] Review Request 2981: ruby: call setMRU from L1 controllers, not from sequencer

On July 31, 2015, 4:05 p.m., Joel Hestness wrote: I'm still pretty ambivalent about this change. There are now 4 potential ways to update MRU: (1) direct call from an action to a cache's setMRU, (2)/(3) calling an action from a transition that updates a specific cache's MRU, and (4)

[gem5-dev] changeset in gem5: mem: Hit callback delay fix

changeset cf35e8b92a5c in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cf35e8b92a5c description: mem: Hit callback delay fix This patch was created by Bihn Pham during his internship at AMD. There is no need to delay hit callback response messages by

[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic passed. * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing passed. *