Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-06-02 Thread Andreas Hansson via gem5-dev
On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-05-30 Thread Andreas Hansson via gem5-dev
On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-05-30 Thread Andreas Hansson via gem5-dev
On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-05-30 Thread Andreas Hansson via gem5-dev
On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: Hi Andreas, According to the literature, both tCL and tWR should be independent of the memory technology because they are buffer constraint timings and they reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758).

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-05-20 Thread Andreas Hansson via gem5-dev
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2109/#review5106 --- With the last patches that went in, the DRAM controller now has e.g. tWR

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-05-20 Thread Sophiane SENNI via gem5-dev
On May 20, 2014, 8:21 a.m., Andreas Hansson wrote: With the last patches that went in, the DRAM controller now has e.g. tWR added to the constraints. Does that provide enough detail, or is there still a need for turning tCL into tWL and tRL? If so, it would be good to see an updated

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2014-04-09 Thread Andreas Hansson
On Dec. 6, 2013, 3:54 p.m., Amin Farmahini wrote: I don't think having two different tCL values is a good idea. I would instead suggest adding tCWD and tWR. Andreas Hansson wrote: Great idea Sophiane. I'll put another vote down for Amin's suggestion though. I should be able to

[gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2013-12-06 Thread Sophiane SENNI
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2109/ --- Review request for Default. Summary (updated) - Different

Re: [gem5-dev] Review Request 2109: Different SimpleDRAM latency for read and write access

2013-12-06 Thread Andreas Hansson
On Dec. 6, 2013, 3:54 p.m., Amin Farmahini wrote: I don't think having two different tCL values is a good idea. I would instead suggest adding tCWD and tWR. Great idea Sophiane. I'll put another vote down for Amin's suggestion though. - Andreas