[gem5-dev] Change in gem5/gem5[develop]: python: Add simulator instantiation checks
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53923 )
Change subject: python: Add simulator instantiation checks
..
python: Add simulator instantiation checks
Check that m5.instantiate() has been called before m5.simulate() and
that m5.instantiate() is only called once.
Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Signed-off-by: Andreas Sandberg
---
M src/python/m5/simulate.py
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index b5b8c78..0e222cf 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -62,11 +62,19 @@
_drain_manager = _m5.drain.DrainManager.instance()
-# The final hook to generate .ini files. Called from the user script
-# once the config is built.
+_instantiated = False # Has m5.instantiate() been called?
+
+# The final call to instantiate the SimObject graph and initialize the
+# system.
def instantiate(ckpt_dir=None):
+global _instantiated
from m5 import options
+if _instantiated:
+fatal("m5.instantiate() called twice.")
+
+_instantiated = True
+
root = objects.Root.getInstance()
if not root:
@@ -148,6 +156,10 @@
need_startup = True
def simulate(*args, **kwargs):
global need_startup
+global _instantiated
+
+if not _instantiated:
+fatal("m5.instantiate() must be called before m5.simulate().")
if need_startup:
root = objects.Root.getInstance()
--
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Gerrit-Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Gerrit-Change-Number: 53923
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary Python 2.x workaround
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50407 )
Change subject: python: Remove unnecessary Python 2.x workaround
..
python: Remove unnecessary Python 2.x workaround
We needed to explicitly cast the return value from getCode() to int to
avoid a Python 2.x issue where sys.exit() got confused by an
unexpected long argument. This isn't an issue in Python 3 since long
has been removed as a separate type.
Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50407
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/pybind11/event.cc
1 file changed, 0 insertions(+), 11 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index 794b6e3..aefe50a 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -134,18 +134,7 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
.def("getCause", ::getCause)
-#if PY_MAJOR_VERSION >= 3
.def("getCode", ::getCode)
-#else
-// Workaround for an issue where PyBind11 converts the exit
-// code to a long. This is normally fine, but sys.exit treats
-// any non-int type as an error and exits with status 1 if it
-// is passed a long.
-.def("getCode", [](GlobalSimLoopExitEvent *e) {
-return py::reinterpret_steal(
-PyInt_FromLong(e->getCode()));
-})
-#endif
;
// Event base class. These should never be returned directly to
--
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Gerrit-Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Gerrit-Change-Number: 50407
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu-kvm: Reinitialize threads on drainResume
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50409 )
Change subject: cpu-kvm: Reinitialize threads on drainResume
..
cpu-kvm: Reinitialize threads on drainResume
Event queue service threads may have been re-created while the
simulator was drained. We therefore need to initialize the new thread
by setting correct signal masks and re-attaching performance counters.
Change-Id: Ic0dab80543928327021cade037770c917e73a47f
Signed-off-by: Andreas Sandberg
---
M src/cpu/kvm/base.cc
M src/cpu/kvm/base.hh
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index c7c72a8..ea43595 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2015, 2017 ARM Limited
+ * Copyright (c) 2012, 2015, 2017, 2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -154,9 +154,9 @@
inform("KVM: Coalesced not supported by host OS\n");
}
-Event *startupEvent(
-new EventFunctionWrapper([this]{ startupThread(); }, name(),
true));
-schedule(startupEvent, curTick());
+schedule(new EventFunctionWrapper([this]{
+restartEqThread();
+}, name(), true), curTick());
}
BaseKvmCPU::Status
@@ -228,7 +228,7 @@
}
void
-BaseKvmCPU::startupThread()
+BaseKvmCPU::restartEqThread()
{
// Do thread-specific initialization. We need to setup signal
// delivery for counters and timers from within the thread that
@@ -381,6 +381,13 @@
{
assert(!tickEvent.scheduled());
+/* The simulator may have terminated the threads servicing event
+ * queues. In that case, we need to re-initialize the new
+ * threads. */
+schedule(new EventFunctionWrapper([this]{
+restartEqThread();
+}, name(), true), curTick());
+
// We might have been switched out. In that case, we don't need to
// do anything.
if (switchedOut())
@@ -1275,6 +1282,11 @@
.samplePeriod(42);
}
+// We might be re-attaching counters due threads being
+// re-initialised after fork.
+if (hwCycles.attached())
+hwCycles.detach();
+
hwCycles.attach(cfgCycles,
0); // TID (0 => currentThread)
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index e5b047e..4f40064 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -682,11 +682,12 @@
* example, when setting up timers, we need to know the TID of the
* thread executing in KVM in order to deliver the timer signal to
* that thread. This method is called as the first event in this
- * SimObject's event queue.
+ * SimObject's event queue and after drainResume to handle changes
+ * to event queue service threads.
*
* @see startup
*/
-void startupThread();
+void restartEqThread();
/** Try to drain the CPU if a drain is pending */
bool tryDrain();
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unnecessary Python 2.x workaround
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50407 )
Change subject: python: Remove unnecessary Python 2.x workaround
..
python: Remove unnecessary Python 2.x workaround
We needed to explicitly cast the return value from getCode() to int to
avoid a Python 2.x issue where sys.exit() got confused by an
unexpected long argument. This isn't an issue in Python 3 since long
has been removed as a separate type.
Change-Id: I7770d0f180e826ac7e6c92c13bc6a61447e3f851
Signed-off-by: Andreas Sandberg
---
M src/python/pybind11/event.cc
1 file changed, 0 insertions(+), 11 deletions(-)
diff --git a/src/python/pybind11/event.cc b/src/python/pybind11/event.cc
index 794b6e3..aefe50a 100644
--- a/src/python/pybind11/event.cc
+++ b/src/python/pybind11/event.cc
@@ -134,18 +134,7 @@
std::unique_ptr>(
m, "GlobalSimLoopExitEvent")
.def("getCause", ::getCause)
-#if PY_MAJOR_VERSION >= 3
.def("getCode", ::getCode)
-#else
-// Workaround for an issue where PyBind11 converts the exit
-// code to a long. This is normally fine, but sys.exit treats
-// any non-int type as an error and exits with status 1 if it
-// is passed a long.
-.def("getCode", [](GlobalSimLoopExitEvent *e) {
-return py::reinterpret_steal(
-PyInt_FromLong(e->getCode()));
-})
-#endif
;
// Event base class. These should never be returned directly to
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix fork for multithreaded simulations
_t i = 1; i < numMainEventQueues; i++) {
-threads.push_back(new std::thread(thread_loop,
mainEventQueue[i]));
-}
-
threads_initialized = true;
simulate_limit_event =
new GlobalSimLoopExitEvent(mainEventQueue[0]->getCurTick(),
@@ -125,6 +141,16 @@
inParallelMode = true;
}
+if (eventThreads.empty()) {
+// the main thread (the one we're currently running on)
+// handles queue 0, so we only need to allocate new threads
+// for queues 1..N-1. We'll call these the "subordinate" threads.
+for (uint32_t i = 1; i < numMainEventQueues; i++) {
+eventThreads.push_back(
+new std::thread(thread_loop, mainEventQueue[i]));
+}
+}
+
// all subordinate (created) threads should be waiting on the
// barrier; the arrival of the main thread here will satisfy the
// barrier, and all threads will enter doSimLoop in parallel
@@ -151,6 +177,31 @@
return global_exit_event;
}
+void
+terminateEventQueueThreads()
+{
+assert(!terminateEqThreads);
+
+/* This function should only be called when the simulator is
+ * handling a global exit event (typically from Python). This
+ * means that the helper threads will be waiting on the
+ * barrier. Tell the helper threads to exit and release them from
+ * their barrier. */
+terminateEqThreads = true;
+threadBarrier->wait();
+
+/* Wait for all of the threads to terminate */
+for (auto : eventThreads) {
+thread->join();
+delete thread;
+thread = nullptr;
+}
+
+terminateEqThreads = false;
+eventThreads.clear();
+}
+
+
/**
* Test and clear the global async_event flag, such that each time the
* flag is cleared, only one thread returns true (and thus is assigned
diff --git a/src/sim/simulate.hh b/src/sim/simulate.hh
index 0817bbd..5ef4995 100644
--- a/src/sim/simulate.hh
+++ b/src/sim/simulate.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 Arm Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -34,6 +46,15 @@
class GlobalSimLoopExitEvent;
GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
+
+/**
+ * Terminate helper threads when running in parallel mode.
+ *
+ * @pre Simulator must have returned from simulate() to service a
+ * GlobalExitEvent prior to calling this function.
+ */
+void terminateEventQueueThreads();
+
extern GlobalSimLoopExitEvent *simulate_limit_event;
} // namespace gem5
--
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[gem5-dev] Change in gem5/gem5[stable]: python: Fix incorrect prefixes is m5.utils.convert
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42783 ) Change subject: python: Fix incorrect prefixes is m5.utils.convert .. python: Fix incorrect prefixes is m5.utils.convert The conversion functions incorrectly assumed that kibibytes are 'kiB' rather than 'KiB' (correct). Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39375 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro (cherry picked from commit b67b917345e85d6c02aa8c37dc40524eac5622c6) --- M src/python/m5/util/convert.py 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py index 077b6b4..ae667b3 100644 --- a/src/python/m5/util/convert.py +++ b/src/python/m5/util/convert.py @@ -62,7 +62,7 @@ 'Gi': gibi, 'G': giga, 'M': mega, -'ki': kibi, +'Ki': kibi, 'k': kilo, 'Mi': mebi, 'm': milli, @@ -84,7 +84,7 @@ 'G' : gibi, 'Mi': mebi, 'M' : mebi, -'ki': kibi, +'Ki': kibi, 'k' : kibi, } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42783 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: stable Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Gerrit-Change-Number: 42783 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code
BILITY OF SUCH DAMAGE. -from __future__ import print_function - import argparse import m5 import os diff --git a/src/systemc/tests/verify.py b/src/systemc/tests/verify.py index 2c0ebc9..6b4cf5c 100755 --- a/src/systemc/tests/verify.py +++ b/src/systemc/tests/verify.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import argparse import collections import difflib @@ -38,7 +36,6 @@ import os import re import subprocess -import six import sys script_path = os.path.abspath(inspect.getfile(inspect.currentframe())) @@ -110,8 +107,7 @@ super(TestPhaseMeta, cls).__init__(name, bases, d) -@six.add_metaclass(TestPhaseMeta) -class TestPhaseBase(object): +class TestPhaseBase(object, metaclass=TestPhaseMeta): abstract = True def __init__(self, main_args, *args): diff --git a/src/unittest/genini.py b/src/unittest/genini.py index 2575fc0..854ce02 100755 --- a/src/unittest/genini.py +++ b/src/unittest/genini.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import getopt, os, os.path, sys from os.path import join as joinpath, realpath -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39758 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a Gerrit-Change-Number: 39758 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code
develop Gerrit-Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168 Gerrit-Change-Number: 39757 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )
Change subject: tests: Remove Python 2.7 glue code from testlib
..
tests: Remove Python 2.7 glue code from testlib
Remove the dependency on six in testlib.
Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39759
Reviewed-by: Bobby R. Bruce
Tested-by: kokoro
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
import os
import re
-from six import add_metaclass
from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol
from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
# one in the list will be saved.
common_args = AttrDict({arg.name:arg for arg in common_args})
-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
class ExtendAction(argparse.Action):
def __call__(self, parser, namespace, values, option_string=None):
items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@
'''
-from __future__ import print_function
-
import multiprocessing
import os
import sys
@@ -46,7 +44,7 @@
import testlib.state as state
import testlib.terminal as terminal
-from six.moves import queue as Queue
+from queue import Queue
from testlib.configuration import constants
diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@
import os
import re
-import six
import sys
import traceback
diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
'''
import testlib.wrappers as wrappers
-from six import add_metaclass
-
class LogLevel():
Fatal = 0
Error = 1
@@ -56,8 +54,7 @@
RecordTypeCounterMetaclass.counter += 1
-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
'''
A generic object that is passed to the :class:`Log` and its handlers.
diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
import fcntl
import termios
import struct
-import six
# Intended usage example:
#
@@ -85,7 +84,7 @@
def __init__(self, cap_string):
for i, c in enumerate(color_names):
setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
setattr(self, name, cap_string(cap))
termcap = ColorStrings(cap_string)
--
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Gerrit-Change-Number: 39759
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code from testlib
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39759 )
Change subject: tests: Remove Python 2.7 glue code from testlib
..
tests: Remove Python 2.7 glue code from testlib
Remove the dependency on six in testlib.
Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Signed-off-by: Andreas Sandberg
---
M ext/testlib/configuration.py
M ext/testlib/handlers.py
M ext/testlib/loader.py
M ext/testlib/log.py
M ext/testlib/terminal.py
5 files changed, 4 insertions(+), 13 deletions(-)
diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index e5b7598..f2d93d6 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -83,7 +83,6 @@
import os
import re
-from six import add_metaclass
from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol
from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -602,8 +601,7 @@
# one in the list will be saved.
common_args = AttrDict({arg.name:arg for arg in common_args})
-@add_metaclass(abc.ABCMeta)
-class ArgParser(object):
+class ArgParser(object, metaclass=abc.ABCMeta):
class ExtendAction(argparse.Action):
def __call__(self, parser, namespace, values, option_string=None):
items = getattr(namespace, self.dest, [])
diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index 723a855..b62322f 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -31,8 +31,6 @@
'''
-from __future__ import print_function
-
import multiprocessing
import os
import sys
@@ -46,7 +44,7 @@
import testlib.state as state
import testlib.terminal as terminal
-from six.moves import queue as Queue
+from queue import Queue
from testlib.configuration import constants
diff --git a/ext/testlib/loader.py b/ext/testlib/loader.py
index 2d76996..58b1b2e 100644
--- a/ext/testlib/loader.py
+++ b/ext/testlib/loader.py
@@ -67,7 +67,6 @@
import os
import re
-import six
import sys
import traceback
diff --git a/ext/testlib/log.py b/ext/testlib/log.py
index 1bdb373..fb5907c 100644
--- a/ext/testlib/log.py
+++ b/ext/testlib/log.py
@@ -32,8 +32,6 @@
'''
import testlib.wrappers as wrappers
-from six import add_metaclass
-
class LogLevel():
Fatal = 0
Error = 1
@@ -56,8 +54,7 @@
RecordTypeCounterMetaclass.counter += 1
-@add_metaclass(RecordTypeCounterMetaclass)
-class Record(object):
+class Record(object, metaclass=RecordTypeCounterMetaclass):
'''
A generic object that is passed to the :class:`Log` and its handlers.
diff --git a/ext/testlib/terminal.py b/ext/testlib/terminal.py
index bc4c855..be489f5 100644
--- a/ext/testlib/terminal.py
+++ b/ext/testlib/terminal.py
@@ -28,7 +28,6 @@
import fcntl
import termios
import struct
-import six
# Intended usage example:
#
@@ -85,7 +84,7 @@
def __init__(self, cap_string):
for i, c in enumerate(color_names):
setattr(self, c, cap_string('setaf', i))
-for name, cap in six.iteritems(capability_map):
+for name, cap in capability_map.items():
setattr(self, name, cap_string(cap))
termcap = ColorStrings(cap_string)
--
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Gerrit-Change-Id: I247088d119cf8f9d815632eae16a1cbf87930516
Gerrit-Change-Number: 39759
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code
73d5..38fdbc8 100644 --- a/configs/splash2/run.py +++ b/configs/splash2/run.py @@ -27,9 +27,6 @@ # Splash2 Run Script # -from __future__ import print_function -from __future__ import absolute_import - import os import optparse import sys diff --git a/configs/topologies/BaseTopology.py b/configs/topologies/BaseTopology.py index 74e197f..848f230 100644 --- a/configs/topologies/BaseTopology.py +++ b/configs/topologies/BaseTopology.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - import m5 class BaseTopology(object): diff --git a/configs/topologies/Cluster.py b/configs/topologies/Cluster.py index 76ee50c..5d292c9 100644 --- a/configs/topologies/Cluster.py +++ b/configs/topologies/Cluster.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from topologies.BaseTopology import BaseTopology class Cluster(BaseTopology): diff --git a/configs/topologies/Crossbar.py b/configs/topologies/Crossbar.py index 8248fdf..63e90bd 100644 --- a/configs/topologies/Crossbar.py +++ b/configs/topologies/Crossbar.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/CrossbarGarnet.py b/configs/topologies/CrossbarGarnet.py index ef58f71..db7dc27 100644 --- a/configs/topologies/CrossbarGarnet.py +++ b/configs/topologies/CrossbarGarnet.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/MeshDirCorners_XY.py b/configs/topologies/MeshDirCorners_XY.py index e0aea52..b4100ff 100644 --- a/configs/topologies/MeshDirCorners_XY.py +++ b/configs/topologies/MeshDirCorners_XY.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Mesh_XY.py b/configs/topologies/Mesh_XY.py index faec1e3..8926bcd 100644 --- a/configs/topologies/Mesh_XY.py +++ b/configs/topologies/Mesh_XY.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Mesh_westfirst.py b/configs/topologies/Mesh_westfirst.py index 057fe12..9b73c05 100644 --- a/configs/topologies/Mesh_westfirst.py +++ b/configs/topologies/Mesh_westfirst.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Pt2Pt.py b/configs/topologies/Pt2Pt.py index 335ff15..fb75549 100644 --- a/configs/topologies/Pt2Pt.py +++ b/configs/topologies/Pt2Pt.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/__init__.py b/configs/topologies/__init__.py index 98ab3ae..4fe0002 100644 --- a/configs/topologies/__init__.py +++ b/configs/topologies/__init__.py @@ -32,6 +32,3 @@ # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from __future__ import print_function -from __future__ import absolute_import -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39755 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a Gerrit-Change-Number: 39
[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )
Change subject: util: Remove Python 2.7 glue code
..
util: Remove Python 2.7 glue code
Remove uses of six and from __future__ imports as they are no longer
needed.
Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39756
Reviewed-by: Gabe Black
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/build_cross_gcc/build_cross_gcc.py
b/util/build_cross_gcc/build_cross_gcc.py
index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
import os.path
import pickle
import shutil
-import six
import subprocess
import textwrap
@@ -145,9 +144,9 @@
# Settings.
#
-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
key = d.get('key', None)
if key is not None:
assert('default' in d)
@@ -157,9 +156,7 @@
all_settings[key] = instance
return cls
-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
key = None
@abc.abstractmethod
@@ -420,17 +417,15 @@
# Steps of the build process.
#
-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
number = d.get('number', None)
if number is not None:
all_steps[number] = cls()
return cls
-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
'Steps to set up a cross compiling gcc.'
number = None
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
# upgraders in private branches.
-
-from six.moves import configparser
+import configparser
import glob, types, sys, os
import os.path as osp
diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
import re
import sys
-from six import add_metaclass
-
from . import style
from . import sort_includes
from .region import *
@@ -102,8 +100,7 @@
return regions
-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
"""Base class for style verifiers
Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
"""
pass
-@add_metaclass(ABCMeta)
class LineVerifier(Verifier):
def check(self, filename, regions=all_regions, fobj=None,
silent=False):
close = False
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models
std::vector temps = ls.solve();
for (unsigned i = 0; i < eq_nodes.size(); i++)
-eq_nodes[i]->temp = temps[i];
+eq_nodes[i]->temp = Temperature::fromKelvin(temps[i]);
// Schedule next computation
schedule(stepEvent, curTick() + SimClock::Int::s * _step);
@@ -233,11 +234,11 @@
entities.push_back(r);
}
-double
-ThermalModel::getTemp() const
+Temperature
+ThermalModel::getTemperature() const
{
// Just pick the highest temperature
-double temp = 0;
+Temperature temp = Temperature::fromKelvin(0.0);
for (auto & n : eq_nodes)
temp = std::max(temp, n->temp);
return temp;
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 95d0c7a..d3717df 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -40,6 +40,7 @@
#include
+#include "base/temperature.hh"
#include "sim/clocked_object.hh"
#include "sim/power/thermal_domain.hh"
#include "sim/power/thermal_entity.hh"
@@ -122,8 +123,8 @@
LinearEquation getEquation(ThermalNode * tn, unsigned n,
double step) const override;
-/* Fixed temperature value in centigrate degrees */
-const double _temperature;
+/* Fixed temperature value */
+const Temperature _temperature;
/* Nodes connected to the resistor */
ThermalNode * node;
};
@@ -150,7 +151,7 @@
void addNode(ThermalNode * n) { nodes.push_back(n); }
-double getTemp() const;
+Temperature getTemperature() const;
void startup() override;
void doStep();
diff --git a/src/sim/power/thermal_node.hh b/src/sim/power/thermal_node.hh
index 68867b3..e9d4096 100644
--- a/src/sim/power/thermal_node.hh
+++ b/src/sim/power/thermal_node.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
#ifndef __SIM_THERMAL_NODE_HH__
#define __SIM_THERMAL_NODE_HH__
+#include "base/temperature.hh"
#include "sim/sim_object.hh"
struct ThermalNodeParams;
@@ -54,7 +55,7 @@
int id;
bool isref;
-double temp;
+Temperature temp;
};
#endif
--
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Gerrit-Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Gerrit-Change-Number: 39455
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2.7 glue code
git a/configs/topologies/BaseTopology.py b/configs/topologies/BaseTopology.py index 74e197f..848f230 100644 --- a/configs/topologies/BaseTopology.py +++ b/configs/topologies/BaseTopology.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - import m5 class BaseTopology(object): diff --git a/configs/topologies/Cluster.py b/configs/topologies/Cluster.py index 76ee50c..5d292c9 100644 --- a/configs/topologies/Cluster.py +++ b/configs/topologies/Cluster.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from topologies.BaseTopology import BaseTopology class Cluster(BaseTopology): diff --git a/configs/topologies/Crossbar.py b/configs/topologies/Crossbar.py index 8248fdf..63e90bd 100644 --- a/configs/topologies/Crossbar.py +++ b/configs/topologies/Crossbar.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/CrossbarGarnet.py b/configs/topologies/CrossbarGarnet.py index ef58f71..db7dc27 100644 --- a/configs/topologies/CrossbarGarnet.py +++ b/configs/topologies/CrossbarGarnet.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/MeshDirCorners_XY.py b/configs/topologies/MeshDirCorners_XY.py index e0aea52..b4100ff 100644 --- a/configs/topologies/MeshDirCorners_XY.py +++ b/configs/topologies/MeshDirCorners_XY.py @@ -24,9 +24,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Mesh_XY.py b/configs/topologies/Mesh_XY.py index faec1e3..8926bcd 100644 --- a/configs/topologies/Mesh_XY.py +++ b/configs/topologies/Mesh_XY.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Mesh_westfirst.py b/configs/topologies/Mesh_westfirst.py index 057fe12..9b73c05 100644 --- a/configs/topologies/Mesh_westfirst.py +++ b/configs/topologies/Mesh_westfirst.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/Pt2Pt.py b/configs/topologies/Pt2Pt.py index 335ff15..fb75549 100644 --- a/configs/topologies/Pt2Pt.py +++ b/configs/topologies/Pt2Pt.py @@ -25,9 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function -from __future__ import absolute_import - from m5.params import * from m5.objects import * diff --git a/configs/topologies/__init__.py b/configs/topologies/__init__.py index 98ab3ae..4fe0002 100644 --- a/configs/topologies/__init__.py +++ b/configs/topologies/__init__.py @@ -32,6 +32,3 @@ # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -from __future__ import print_function -from __future__ import absolute_import -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39755 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I6e2f270557d7343bbad30c8e6d743e363c43715a Gerrit-Change-Number: 39755 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Remove Python 2.7 glue code
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39757 ) Change subject: tests: Remove Python 2.7 glue code .. tests: Remove Python 2.7 glue code Remove uses of six and from __future__ imports as they are no longer needed. Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168 Signed-off-by: Andreas Sandberg --- M tests/configs/gpu-ruby.py M tests/gem5/configs/base_config.py M tests/gem5/configs/checkpoint.py M tests/gem5/configs/switcheroo.py M tests/gem5/fixture.py M tests/gem5/fs/linux/arm/run.py M tests/gem5/memory/test.py M tests/main.py M tests/run.py 9 files changed, 4 insertions(+), 17 deletions(-) diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py index a463fe3..b561d02 100644 --- a/tests/configs/gpu-ruby.py +++ b/tests/configs/gpu-ruby.py @@ -33,8 +33,6 @@ # Author: Brad Beckmann # -from __future__ import print_function - import m5 from m5.objects import * from m5.defines import buildEnv diff --git a/tests/gem5/configs/base_config.py b/tests/gem5/configs/base_config.py index 5623db8..b18cecf 100644 --- a/tests/gem5/configs/base_config.py +++ b/tests/gem5/configs/base_config.py @@ -42,12 +42,10 @@ from common import Options from common.Caches import * from ruby import Ruby -from six import add_metaclass _have_kvm_support = 'BaseKvmCPU' in globals() -@add_metaclass(ABCMeta) -class BaseSystem(object): +class BaseSystem(object, metaclass=ABCMeta): """Base system builder. This class provides some basic functionality for creating an ARM diff --git a/tests/gem5/configs/checkpoint.py b/tests/gem5/configs/checkpoint.py index a652094..3545095 100644 --- a/tests/gem5/configs/checkpoint.py +++ b/tests/gem5/configs/checkpoint.py @@ -33,8 +33,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - from multiprocessing import Process import sys import os diff --git a/tests/gem5/configs/switcheroo.py b/tests/gem5/configs/switcheroo.py index cb47f90..fb1db81 100644 --- a/tests/gem5/configs/switcheroo.py +++ b/tests/gem5/configs/switcheroo.py @@ -33,8 +33,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import m5 import _m5 from m5.objects import * diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py index 467eb43..5ffb248 100644 --- a/tests/gem5/fixture.py +++ b/tests/gem5/fixture.py @@ -44,7 +44,8 @@ import threading import gzip -from six.moves import urllib +import urllib.error +import urllib.request from testlib.fixture import Fixture from testlib.configuration import config, constants diff --git a/tests/gem5/fs/linux/arm/run.py b/tests/gem5/fs/linux/arm/run.py index a0d782b..3dccebb 100644 --- a/tests/gem5/fs/linux/arm/run.py +++ b/tests/gem5/fs/linux/arm/run.py @@ -36,8 +36,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import sys import os import os.path diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py index 7b839f2..db20ab5 100644 --- a/tests/gem5/memory/test.py +++ b/tests/gem5/memory/test.py @@ -28,7 +28,6 @@ Test file for simple memory test TODO: Add stats checking ''' -import six from testlib import * @@ -50,7 +49,7 @@ for name, params in simple_mem_params: -args = ['--' + key + '=' + val for key,val in six.iteritems(params)] +args = ['--' + key + '=' + val for key,val in params.items()] gem5_verify_config( name='simple_mem_' + name, diff --git a/tests/main.py b/tests/main.py index 3287ef1..39717f6 100755 --- a/tests/main.py +++ b/tests/main.py @@ -5,7 +5,6 @@ Discovers and runs all tests from a given root directory. ''' -from __future__ import print_function import sys import os diff --git a/tests/run.py b/tests/run.py index a8b612b..c3360ac 100644 --- a/tests/run.py +++ b/tests/run.py @@ -36,8 +36,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import os import sys import re -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39757 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I74b5250722abe1e202f31a9ec1d4cc04039df168 Gerrit-Change-Number: 39757 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To u
[gem5-dev] Change in gem5/gem5[develop]: arch, mem, cpu, systemc: Remove Python 2.7 glue code
ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import argparse import collections import difflib @@ -38,7 +36,6 @@ import os import re import subprocess -import six import sys script_path = os.path.abspath(inspect.getfile(inspect.currentframe())) @@ -110,8 +107,7 @@ super(TestPhaseMeta, cls).__init__(name, bases, d) -@six.add_metaclass(TestPhaseMeta) -class TestPhaseBase(object): +class TestPhaseBase(object, metaclass=TestPhaseMeta): abstract = True def __init__(self, main_args, *args): diff --git a/src/unittest/genini.py b/src/unittest/genini.py index 2575fc0..854ce02 100755 --- a/src/unittest/genini.py +++ b/src/unittest/genini.py @@ -25,8 +25,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from __future__ import print_function - import getopt, os, os.path, sys from os.path import join as joinpath, realpath -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39758 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib10d01d9398795f46eedeb91a02736f248917b6a Gerrit-Change-Number: 39758 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util: Remove Python 2.7 glue code
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39756 )
Change subject: util: Remove Python 2.7 glue code
..
util: Remove Python 2.7 glue code
Remove uses of six and from __future__ imports as they are no longer
needed.
Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Signed-off-by: Andreas Sandberg
---
M util/build_cross_gcc/build_cross_gcc.py
M util/cpt_upgrader.py
M util/style/verifiers.py
3 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/util/build_cross_gcc/build_cross_gcc.py
b/util/build_cross_gcc/build_cross_gcc.py
index 51f7fcc..3afd4bf 100755
--- a/util/build_cross_gcc/build_cross_gcc.py
+++ b/util/build_cross_gcc/build_cross_gcc.py
@@ -32,7 +32,6 @@
import os.path
import pickle
import shutil
-import six
import subprocess
import textwrap
@@ -145,9 +144,9 @@
# Settings.
#
-class MetaSetting(type):
+class MetaSetting(abc.ABCMeta):
def __new__(mcls, name, bases, d):
-cls = super(MetaSetting, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
key = d.get('key', None)
if key is not None:
assert('default' in d)
@@ -157,9 +156,7 @@
all_settings[key] = instance
return cls
-@six.add_metaclass(MetaSetting)
-@six.add_metaclass(abc.ABCMeta)
-class Setting(object):
+class Setting(object, metaclass=MetaSetting):
key = None
@abc.abstractmethod
@@ -420,17 +417,15 @@
# Steps of the build process.
#
-class MetaStep(type):
+class MetaStep(abc.ABCMeta):
def __new__(mcls, name, bases, d):
-cls = super(MetaStep, mcls).__new__(mcls, name, bases, d)
+cls = super().__new__(mcls, name, bases, d)
number = d.get('number', None)
if number is not None:
all_steps[number] = cls()
return cls
-@six.add_metaclass(MetaStep)
-@six.add_metaclass(abc.ABCMeta)
-class Step(object):
+class Step(object, metaclass=MetaStep):
'Steps to set up a cross compiling gcc.'
number = None
diff --git a/util/cpt_upgrader.py b/util/cpt_upgrader.py
index 9964aac..15dc2ab 100755
--- a/util/cpt_upgrader.py
+++ b/util/cpt_upgrader.py
@@ -69,8 +69,7 @@
# upgraders in private branches.
-
-from six.moves import configparser
+import configparser
import glob, types, sys, os
import os.path as osp
diff --git a/util/style/verifiers.py b/util/style/verifiers.py
index 7d27fda..798ddfc 100644
--- a/util/style/verifiers.py
+++ b/util/style/verifiers.py
@@ -47,8 +47,6 @@
import re
import sys
-from six import add_metaclass
-
from . import style
from . import sort_includes
from .region import *
@@ -102,8 +100,7 @@
return regions
-@add_metaclass(ABCMeta)
-class Verifier(object):
+class Verifier(object, metaclass=ABCMeta):
"""Base class for style verifiers
Verifiers check for style violations and optionally fix such
@@ -224,7 +221,6 @@
"""
pass
-@add_metaclass(ABCMeta)
class LineVerifier(Verifier):
def check(self, filename, regions=all_regions, fobj=None,
silent=False):
close = False
--
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Gerrit-Change-Id: I8d6aae84d8192b301d541b8dc81275f4932f9f2f
Gerrit-Change-Number: 39756
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFrequency and anyToLatency
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )
Change subject: python: Require a unit in anyToFrequency and anyToLatency
..
python: Require a unit in anyToFrequency and anyToLatency
The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.
Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39435
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 1d78f82..e66eb5c 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -199,32 +199,40 @@
return toMetricFloat(value, 'latency', 's')
def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""
-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be
unambiguous.")
def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""
-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be
unambiguous.")
def toNetworkBandwidth(value):
return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py
b/tests/pyunit/util/test_convert.py
index a9c9d46..da61843 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
self.assertEqual(conv('1kHz'), 1e-3)
self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')
def test_anyToFrequency(self):
conv = convert.anyToFrequency
-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
self.assertEqual(conv('42kHz'), 42e3)
self.assertEqual(conv('0.1s'), 10.0)
self.assertEqual(conv('1ms'), 1000.0)
self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')
def test_toNetworkBandwidth(self):
conv = convert.toNetworkBandwidth
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Gerrit-Change-Number: 39435
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sa
[gem5-dev] Change in gem5/gem5[develop]: base, python: Add a Temperature type and associated param
.def_readwrite("tm_sec", ::tm_sec)
diff --git a/tests/pyunit/util/test_convert.py
b/tests/pyunit/util/test_convert.py
index 6d02b51..a9c9d46 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -275,3 +275,16 @@
self.assertEqual(conv('42'), 42)
self.assertEqual(conv('42J'), 42)
self.assertEqual(conv('42kJ'), 42e3)
+
+def test_temperature(self):
+conv = convert.toTemperature
+
+self.assertEqual(conv("1.0K"), 1.0)
+self.assertEqual(conv("1.0mK"), 1.0e-3)
+
+self.assertEqual(conv("0C"), 273.15)
+self.assertEqual(conv("-1C"), 272.15)
+self.assertRaises(ValueError, conv, "1.0")
+self.assertRaises(ValueError, conv, "-1K")
+
+self.assertEqual(conv("32F"), 273.15)
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I5783cc4f4fecbea5aba9821dfc71bfa77c3f75a9
Gerrit-Change-Number: 39218
Gerrit-PatchSet: 10
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature param type
or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db Gerrit-Change-Number: 39219 Gerrit-PatchSet: 10 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: Add Python unit tests for m5.util.convert
nit") + +runner = unittest.runner.TextTestRunner(verbosity=2) +runner.run(tests) + -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39377 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I80d1aabbe1d87b01b48280972f9418317e648779 Gerrit-Change-Number: 39377 Gerrit-PatchSet: 5 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Consistently use ISO prefixes
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39579 )
Change subject: sim: Consistently use ISO prefixes
..
sim: Consistently use ISO prefixes
We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.
Here are some examples of commonly used in the industry:
* Storage vendors define 1 MB as 10**6 bytes
* Memory vendors define 1 MB as 2**20 bytes
* Network equipment treats 1Mbit/s as 10**6 bits/s
* Memory vendors define 1Mbit as 2**20 bits
In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.
The quantity 2MX is treated differently by gem5 depending on the unit
X:
* Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
* Interconnect and NoC bandwidths (B/s) use binary prefixes.
* Network bandwidths (bps) use decimal prefixes.
* Memory sizes and storage sizes (B) use binary prefixes.
Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.
Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39579
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/Process.py
M src/sim/syscall_emul.hh
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
useArchPT = Param.Bool('false', 'maintain an in-memory version of the
page\
table in an architecture-specific format')
kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in
SE')
-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')
uid = Param.Int(100, 'user id')
euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 581e8db..d6afec8 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1822,7 +1822,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1865,7 +1865,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
--
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Gerrit-Change-Number: 39579
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in gem5/gem5[develop]: python: Consistently use ISO prefixes
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39577 ) Change subject: python: Consistently use ISO prefixes .. python: Consistently use ISO prefixes We currently use the traditional SI-like prefixes to represent binary multipliers in some contexts. This is ambiguous in many cases since they overload the meaning of the SI prefix. Here are some examples of commonly used in the industry: * Storage vendors define 1 MB as 10**6 bytes * Memory vendors define 1 MB as 2**20 bytes * Network equipment treats 1Mbit/s as 10**6 bits/s * Memory vendors define 1Mbit as 2**20 bits In practice, this means that a FLASH chip on a storage bus uses decimal prefixes, but that same flash chip on a memory bus uses binary prefixes. It would also be reasonable to assume that the contents of a 1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet link. That's however not the case due to different meanings of the prefix. The quantity 2MX is treated differently by gem5 depending on the unit X: * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes. * Interconnect and NoC bandwidths (B/s) use binary prefixes. * Network bandwidths (bps) use decimal prefixes. * Memory sizes and storage sizes (B) use binary prefixes. Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes for binary multipliers for parameters and comments where appropriate. Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39577 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/params.py 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Daniel Carvalho: Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 5ff5071..6227fad 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -678,7 +678,7 @@ class MemorySize(CheckedInt): cxx_type = 'uint64_t' -ex_str = '512MB' +ex_str = '512MiB' size = 64 unsigned = True def __init__(self, value): @@ -690,7 +690,7 @@ class MemorySize32(CheckedInt): cxx_type = 'uint32_t' -ex_str = '512MB' +ex_str = '512MiB' size = 32 unsigned = True def __init__(self, value): @@ -710,7 +710,7 @@ else: try: # Often addresses are referred to with sizes. Ex: A device -# base address is at "512MB". Use toMemorySize() to convert +# base address is at "512MiB". Use toMemorySize() to convert # these into addresses. If the address is not specified with a # "size", an exception will occur and numeric translation will # proceed below. @@ -1734,7 +1734,7 @@ class MemoryBandwidth(float,ParamValue): cxx_type = 'float' -ex_str = "1GB/s" +ex_str = "1GiB/s" cmd_line_settable = True def __new__(cls, value): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39577 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93 Gerrit-Change-Number: 39577 Gerrit-PatchSet: 4 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes
-_mem_regions = [ AddrRange('2GB', size='2GB') ]
+_mem_regions = [ AddrRange('2GiB', size='2GiB') ]
# Ranges based on excluding what is part of on-chip I/O (gic,
# a9scu)
-_off_chip_ranges = [AddrRange(0x2F00, size='16MB'),
-AddrRange(0x3000, size='256MB'),
-AddrRange(0x4000, size='512MB'),
-AddrRange(0x1800, size='64MB'),
-AddrRange(0x1C00, size='64MB')]
+_off_chip_ranges = [AddrRange(0x2F00, size='16MiB'),
+AddrRange(0x3000, size='256MiB'),
+AddrRange(0x4000, size='512MiB'),
+AddrRange(0x1800, size='64MiB'),
+AddrRange(0x1C00, size='64MiB')]
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x1400, proc_id1=0x1400,
@@ -790,7 +790,7 @@
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c09, interrupt=ArmSPI(num=37))
pci_host = GenericPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=16,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=16,
pci_pio_base=0)
sys_counter = SystemCounter()
@@ -814,9 +814,9 @@
cf_ctrl.BAR0 = PciLegacyIoBar(addr='0x1C1A', size='256B')
cf_ctrl.BAR1 = PciLegacyIoBar(addr='0x1C1A0100', size='4096B')
-bootmem= SimpleMemory(range = AddrRange('64MB'),
+bootmem= SimpleMemory(range = AddrRange('64MiB'),
conf_table_reported = False)
-vram = SimpleMemory(range = AddrRange(0x1800,
size='32MB'),
+vram = SimpleMemory(range = AddrRange(0x1800,
size='32MiB'),
conf_table_reported = False)
rtc= PL031(pio_addr=0x1C17, interrupt=ArmSPI(num=36))
@@ -884,12 +884,12 @@
cur_sys, boot_loader, 0x800, 0x8000)
class VExpress_EMM64(VExpress_EMM):
-# Three memory regions are specified totalling 512GB
-_mem_regions = [ AddrRange('2GB', size='2GB'),
- AddrRange('34GB', size='30GB'),
- AddrRange('512GB', size='480GB') ]
+# Three memory regions are specified totalling 512GiB
+_mem_regions = [ AddrRange('2GiB', size='2GiB'),
+ AddrRange('34GiB', size='30GiB'),
+ AddrRange('512GiB', size='480GiB') ]
pci_host = GenericPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f00)
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
@@ -1038,7 +1038,7 @@
"""
# Everything above 2GiB is memory
-_mem_regions = [ AddrRange('2GB', size='510GB') ]
+_mem_regions = [ AddrRange('2GiB', size='510GiB') ]
_off_chip_ranges = [
# CS1-CS5
@@ -1047,15 +1047,15 @@
AddrRange(0x2f00, 0x8000),
]
-bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
+bootmem = SimpleMemory(range=AddrRange(0, size='64MiB'),
conf_table_reported=False)
# NOR flash, flash0
-flash0 = SimpleMemory(range=AddrRange(0x0800, size='64MB'),
+flash0 = SimpleMemory(range=AddrRange(0x0800, size='64MiB'),
conf_table_reported=False)
# Trusted SRAM
-trusted_sram = SimpleMemory(range=AddrRange(0x0400, size='256kB'),
+trusted_sram = SimpleMemory(range=AddrRange(0x0400, size='256KiB'),
conf_table_reported=False)
# Non-Trusted SRAM
@@ -1134,7 +1134,7 @@
### gem5-specific off-chip devices ###
pci_host = GenericArmPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f00,
pci_mem_base=0x4000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
@@ -1354,7 +1354,7 @@
its=NULL)
pci_host = GenericArmPciHost(
- conf_base=0x4000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x4000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x5000,
pci_mem_base=0x4,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
--
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Gerrit-Change-Number: 39575
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
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Gerrit-Reviewer: kokoro
Gerrit-CC: Gabe Black
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[gem5-dev] Change in gem5/gem5[develop]: mem: Consistently use ISO prefixes
" which we track statistics")
+min_tracked_cache_size = Param.MemorySize("128KiB", "Minimum cache
size"
+ " for which we track
statistics")
# This tag uses its own embedded indexing
indexing_policy = NULL
--
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Gerrit-Change-Id: I2d24682d207830f3b7b0ad2ff82b55e082cccb32
Gerrit-Change-Number: 39576
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code
_writer.py
index 8b757e8..7b10fdc 100644
--- a/src/python/m5/util/dot_writer.py
+++ b/src/python/m5/util/dot_writer.py
@@ -53,9 +53,6 @@
#
#
-from __future__ import print_function
-from __future__ import absolute_import
-
import m5, os, re
from m5.SimObject import isRoot, isSimObjectVector
from m5.params import PortRef, isNullPointer
diff --git a/src/python/m5/util/fdthelper.py
b/src/python/m5/util/fdthelper.py
index 7ad3aba..d9dec11 100644
--- a/src/python/m5/util/fdthelper.py
+++ b/src/python/m5/util/fdthelper.py
@@ -35,10 +35,6 @@
#
# Author: Glenn Bergmans
-import six
-if six.PY3:
-long = int
-
from m5.ext.pyfdt import pyfdt
import re
import os
@@ -56,7 +52,7 @@
words = [words]
# Make sure all values are ints (use automatic base detection if
the
# type is str)
-words = [long(w, base=0) if type(w) == str else long(w) for w in
words]
+words = [int(w, base=0) if type(w) == str else int(w) for w in
words]
super(FdtPropertyWords, self).__init__(name, words)
class FdtPropertyStrings(pyfdt.FdtPropertyStrings):
@@ -122,7 +118,7 @@
def int_to_cells(self, value, cells):
"""Helper function for: generates a list of 32 bit cells from an
int,
used to split up addresses in appropriate 32 bit chunks."""
-value = long(value)
+value = int(value)
if (value >> (32 * cells)) != 0:
fatal("Value %d doesn't fit in %d cells" % (value, cells))
diff --git a/src/python/m5/util/grammar.py b/src/python/m5/util/grammar.py
index e09c989..9aba746 100644
--- a/src/python/m5/util/grammar.py
+++ b/src/python/m5/util/grammar.py
@@ -25,7 +25,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-from six import string_types
import ply.lex
import ply.yacc
@@ -94,7 +93,7 @@
"'%s' object has no attribute '%s'" % (type(self), attr))
def parse_string(self, data, source='', debug=None,
tracking=0):
-if not isinstance(data, string_types):
+if not isinstance(data, str):
raise AttributeError(
"argument must be a string, was '%s'" % type(f))
@@ -113,7 +112,7 @@
return result
def parse_file(self, f, **kwargs):
-if isinstance(f, string_types):
+if isinstance(f, str):
source = f
f = open(f, 'r')
elif isinstance(f, file):
diff --git a/src/python/m5/util/jobfile.py b/src/python/m5/util/jobfile.py
index e1bd5b2..e262cf1 100644
--- a/src/python/m5/util/jobfile.py
+++ b/src/python/m5/util/jobfile.py
@@ -24,9 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-from __future__ import absolute_import
-
import sys
class Data(object):
diff --git a/src/python/m5/util/multidict.py
b/src/python/m5/util/multidict.py
index 1558907..78b2c8b 100644
--- a/src/python/m5/util/multidict.py
+++ b/src/python/m5/util/multidict.py
@@ -24,8 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
__all__ = [ 'multidict' ]
class multidict(object):
diff --git a/src/python/m5/util/pybind.py b/src/python/m5/util/pybind.py
index 18df3bb..bb73be9 100644
--- a/src/python/m5/util/pybind.py
+++ b/src/python/m5/util/pybind.py
@@ -33,14 +33,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-from __future__ import absolute_import
-from six import add_metaclass
-
from abc import *
-@add_metaclass(ABCMeta)
-class PyBindExport(object):
+class PyBindExport(object, metaclass=ABCMeta):
@abstractmethod
def export(self, code, cname):
pass
diff --git a/src/python/m5/util/terminal.py b/src/python/m5/util/terminal.py
index bb4ac80..f50e92db 100644
--- a/src/python/m5/util/terminal.py
+++ b/src/python/m5/util/terminal.py
@@ -26,9 +26,6 @@
#
# Author: Steve Reinhardt
-from __future__ import print_function
-from __future__ import absolute_import
-
import sys
# Intended usage example:
--
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Gerrit-Change-Number: 39584
Gerrit-PatchSet: 3
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[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code
bol_declaration + ' = {')
cpp_code.indent()
step = 16
-for i in six.moves.range(0, len(data), step):
+for i in range(0, len(data), step):
x = array.array('B', data[i:i+step])
cpp_code(''.join('%d,' % d for d in x))
cpp_code.dedent()
@@ -487,8 +483,7 @@
cls.all = []
-@six.add_metaclass(ExecutableMeta)
-class Executable(object):
+class Executable(object, metaclass=ExecutableMeta):
'''Base class for creating an executable from sources.'''
abstract = True
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index b31416d..aab0355 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -26,8 +26,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import os
import sys
diff --git a/src/systemc/tests/SConscript b/src/systemc/tests/SConscript
index cf50514..de330cb 100644
--- a/src/systemc/tests/SConscript
+++ b/src/systemc/tests/SConscript
@@ -23,8 +23,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
Import('*')
if env['USE_SYSTEMC'] and GetOption('with_systemc_tests'):
--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes
r(size='4kB'))
+BARs = (PciIoBar(size='256B'), PciMemBar(size='4KiB'))
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
@@ -232,12 +233,12 @@
cxx_header = "dev/net/sinic.hh"
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
-tx_max_copy = Param.MemorySize('16kB', "tx max copy")
+tx_max_copy = Param.MemorySize('16KiB', "tx max copy")
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
-rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
-rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
-tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
-tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
+rx_fifo_threshold = Param.MemorySize('384KiB', "rx fifo high
threshold")
+rx_fifo_low_mark = Param.MemorySize('128KiB', "rx fifo low threshold")
+tx_fifo_high_mark = Param.MemorySize('384KiB', "tx fifo high
threshold")
+tx_fifo_threshold = Param.MemorySize('128KiB', "tx fifo low threshold")
virtual_count = Param.UInt32(1, "Virtualized SINIC")
zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
zero_copy_threshold = Param.UInt32(256,
@@ -252,7 +253,7 @@
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
-BARs = PciMemBar(size='64kB')
+BARs = PciMemBar(size='64KiB')
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py
index f5a0f9e..62d9bd7 100644
--- a/src/dev/pci/CopyEngine.py
+++ b/src/dev/pci/CopyEngine.py
@@ -48,10 +48,10 @@
InterruptLine = 0x20
InterruptPin = 0x01
-BAR0 = PciMemBar(size='1kB')
+BAR0 = PciMemBar(size='1KiB')
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
-XferCap = Param.MemorySize('4kB',
+XferCap = Param.MemorySize('4KiB',
"Number of bits of transfer size that are supported")
latBeforeBegin = Param.Latency('20ns',
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 0ed2648..736f068 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -41,7 +41,7 @@
class PcPciHost(GenericPciHost):
conf_base = 0xC000
-conf_size = "16MB"
+conf_size = "16MiB"
pci_pio_base = 0x8000
@@ -70,7 +70,7 @@
default_bus = IOXBar()
# A device to handle accesses to unclaimed IO ports.
-empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64kB',
+empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64KiB',
ret_data8=0, ret_data16=0, ret_data32=0,
ret_data64=0,
pio=default_bus.mem_side_ports)
--
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Gerrit-Change-Id: I6ab03934af850494d95a37dcda5c2000794b4d3a
Gerrit-Change-Number: 39578
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Richard Cooper
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs
00 100644 --- a/configs/example/arm/workloads.py +++ b/configs/example/arm/workloads.py @@ -34,9 +34,6 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -from __future__ import print_function -from __future__ import absolute_import - import inspect import m5 from m5.objects import * -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39581 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad Gerrit-Change-Number: 39581 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Richard Cooper Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )
Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..
arch-arm, dev-arm: Remove Python 2 compatibility code
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.
Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39580
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
# root instead of appended.
def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(FdtPropertyWords("reg",
state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@
def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
node.append(FdtPropertyWords("reg",
state.addrCells(pio_addr) +
state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
idreg = Param.UInt32(0x, "ID Register, SYS_ID")
def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
node.appendCompatible("arm,vexpress-sysreg")
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@
def generateDeviceTree(self, state):
phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
node.appendCompatible("arm,vexpress-osc")
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
@@ -595,7 +595,7 @@
super(MmioSRAM, self).__init__(**kwargs)
def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
node.appendCompatible(["mmio-sram"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
def generateDeviceTree(self, state):
reg_addr = self.reg_map.start
reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
node.appendCompatible("arm,smmu-v3")
node.append(FdtPropertyWords("reg",
state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
scp = Param.Scp(Parent.any, "System Control Processor")
def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
node.appendCompatible(["arm,mhu", "arm,primecell"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples
self.realview.attachIO(self.iobus) -self.system_port = self.membus.slave +self.system_port = self.membus.cpu_side_ports def numCpuClusters(self): return len(self._clusters) @@ -377,8 +378,8 @@ key=lambda c: c.clk_domain.clock[0]) self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) self.toL3Bus = L2XBar(width=64) -self.toL3Bus.master = self.l3.cpu_side -self.l3.mem_side = self.membus.slave +self.toL3Bus.mem_side_ports = self.l3.cpu_side +self.l3.mem_side = self.membus.cpu_side_ports cluster_mem_bus = self.toL3Bus # connect each cluster to the memory hierarchy diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 85213ee..1df548d 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -119,7 +119,7 @@ object_file=SysPaths.binary(kernel)), readfile=bootscript) -sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master) +sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.mem_side_ports) for r in sys.mem_ranges ] sys.connect() diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 23da8e7..15fcad7 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -97,7 +97,7 @@ # Wire up the system port that gem5 uses to load the kernel # and to perform debug accesses. -self.system_port = self.membus.slave +self.system_port = self.membus.cpu_side_ports # Add CPUs to the system. A cluster of CPUs typically have -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39582 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I11fea3e0df945ac64075b647766570604b70cad8 Gerrit-Change-Number: 39582 Gerrit-PatchSet: 2 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Remove Python 2.7 compatibility code
_future__ import absolute_import
-
import m5, os, re
from m5.SimObject import isRoot, isSimObjectVector
from m5.params import PortRef, isNullPointer
diff --git a/src/python/m5/util/fdthelper.py
b/src/python/m5/util/fdthelper.py
index 7ad3aba..d9dec11 100644
--- a/src/python/m5/util/fdthelper.py
+++ b/src/python/m5/util/fdthelper.py
@@ -35,10 +35,6 @@
#
# Author: Glenn Bergmans
-import six
-if six.PY3:
-long = int
-
from m5.ext.pyfdt import pyfdt
import re
import os
@@ -56,7 +52,7 @@
words = [words]
# Make sure all values are ints (use automatic base detection if
the
# type is str)
-words = [long(w, base=0) if type(w) == str else long(w) for w in
words]
+words = [int(w, base=0) if type(w) == str else int(w) for w in
words]
super(FdtPropertyWords, self).__init__(name, words)
class FdtPropertyStrings(pyfdt.FdtPropertyStrings):
@@ -122,7 +118,7 @@
def int_to_cells(self, value, cells):
"""Helper function for: generates a list of 32 bit cells from an
int,
used to split up addresses in appropriate 32 bit chunks."""
-value = long(value)
+value = int(value)
if (value >> (32 * cells)) != 0:
fatal("Value %d doesn't fit in %d cells" % (value, cells))
diff --git a/src/python/m5/util/grammar.py b/src/python/m5/util/grammar.py
index e09c989..9aba746 100644
--- a/src/python/m5/util/grammar.py
+++ b/src/python/m5/util/grammar.py
@@ -25,7 +25,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
-from six import string_types
import ply.lex
import ply.yacc
@@ -94,7 +93,7 @@
"'%s' object has no attribute '%s'" % (type(self), attr))
def parse_string(self, data, source='', debug=None,
tracking=0):
-if not isinstance(data, string_types):
+if not isinstance(data, str):
raise AttributeError(
"argument must be a string, was '%s'" % type(f))
@@ -113,7 +112,7 @@
return result
def parse_file(self, f, **kwargs):
-if isinstance(f, string_types):
+if isinstance(f, str):
source = f
f = open(f, 'r')
elif isinstance(f, file):
diff --git a/src/python/m5/util/jobfile.py b/src/python/m5/util/jobfile.py
index e1bd5b2..e262cf1 100644
--- a/src/python/m5/util/jobfile.py
+++ b/src/python/m5/util/jobfile.py
@@ -24,9 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-from __future__ import absolute_import
-
import sys
class Data(object):
diff --git a/src/python/m5/util/multidict.py
b/src/python/m5/util/multidict.py
index 1558907..78b2c8b 100644
--- a/src/python/m5/util/multidict.py
+++ b/src/python/m5/util/multidict.py
@@ -24,8 +24,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
__all__ = [ 'multidict' ]
class multidict(object):
diff --git a/src/python/m5/util/pybind.py b/src/python/m5/util/pybind.py
index 18df3bb..bb73be9 100644
--- a/src/python/m5/util/pybind.py
+++ b/src/python/m5/util/pybind.py
@@ -33,14 +33,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-from __future__ import absolute_import
-from six import add_metaclass
-
from abc import *
-@add_metaclass(ABCMeta)
-class PyBindExport(object):
+class PyBindExport(object, metaclass=ABCMeta):
@abstractmethod
def export(self, code, cname):
pass
diff --git a/src/python/m5/util/terminal.py b/src/python/m5/util/terminal.py
index bb4ac80..f50e92db 100644
--- a/src/python/m5/util/terminal.py
+++ b/src/python/m5/util/terminal.py
@@ -26,9 +26,6 @@
#
# Author: Steve Reinhardt
-from __future__ import print_function
-from __future__ import absolute_import
-
import sys
# Intended usage example:
--
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Gerrit-Owner: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove Python 2 compatibility code in Arm configs
https://gem5-review.googlesource.com/c/public/gem5/+/39581 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad Gerrit-Change-Number: 39581 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs: Weed out old port terminology in Arm examples
self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) self.toL3Bus = L2XBar(width=64) -self.toL3Bus.master = self.l3.cpu_side -self.l3.mem_side = self.membus.slave +self.toL3Bus.mem_side_ports = self.l3.cpu_side +self.l3.mem_side = self.membus.cpu_side_ports cluster_mem_bus = self.toL3Bus # connect each cluster to the memory hierarchy diff --git a/configs/example/arm/fs_bigLITTLE.py b/configs/example/arm/fs_bigLITTLE.py index 85213ee..1df548d 100644 --- a/configs/example/arm/fs_bigLITTLE.py +++ b/configs/example/arm/fs_bigLITTLE.py @@ -119,7 +119,7 @@ object_file=SysPaths.binary(kernel)), readfile=bootscript) -sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.master) +sys.mem_ctrls = [ SimpleMemory(range=r, port=sys.membus.mem_side_ports) for r in sys.mem_ranges ] sys.connect() diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py index 23da8e7..15fcad7 100644 --- a/configs/example/arm/starter_se.py +++ b/configs/example/arm/starter_se.py @@ -97,7 +97,7 @@ # Wire up the system port that gem5 uses to load the kernel # and to perform debug accesses. -self.system_port = self.membus.slave +self.system_port = self.membus.cpu_side_ports # Add CPUs to the system. A cluster of CPUs typically have -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39582 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I11fea3e0df945ac64075b647766570604b70cad8 Gerrit-Change-Number: 39582 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Remove Python 2.7 compatibility code
% d for d in x))
cpp_code.dedent()
@@ -487,8 +483,7 @@
cls.all = []
-@six.add_metaclass(ExecutableMeta)
-class Executable(object):
+class Executable(object, metaclass=ExecutableMeta):
'''Base class for creating an executable from sources.'''
abstract = True
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index b31416d..aab0355 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -26,8 +26,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
import os
import sys
diff --git a/src/systemc/tests/SConscript b/src/systemc/tests/SConscript
index cf50514..de330cb 100644
--- a/src/systemc/tests/SConscript
+++ b/src/systemc/tests/SConscript
@@ -23,8 +23,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from __future__ import print_function
-
Import('*')
if env['USE_SYSTEMC'] and GetOption('with_systemc_tests'):
--
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[gem5-dev] Change in gem5/gem5[develop]: cpu: Don't use deprecated port names
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39583 )
Change subject: cpu: Don't use deprecated port names
..
cpu: Don't use deprecated port names
The BaseCPU has a couple of helper methods that wire up ports using
the deprecated port names. Fix that.
Change-Id: I68452eeef921347e8773d50efd210d2c6844fd90
Signed-off-by: Andreas Sandberg
---
M src/cpu/BaseCPU.py
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 025e985..d981570 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -192,13 +192,13 @@
def connectCachedPorts(self, bus):
for p in self._cached_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)
def connectUncachedPorts(self, bus):
for p in self._uncached_interrupt_response_ports:
-exec('self.%s = bus.master' % p)
+exec('self.%s = bus.mem_side_ports' % p)
for p in self._uncached_interrupt_request_ports:
-exec('self.%s = bus.slave' % p)
+exec('self.%s = bus.cpu_side_ports' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
--
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Gerrit-Change-Number: 39583
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Remove Python 2 compatibility code
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39580 )
Change subject: arch-arm, dev-arm: Remove Python 2 compatibility code
..
arch-arm, dev-arm: Remove Python 2 compatibility code
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.
Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg
---
M src/arch/arm/ArmSystem.py
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/SMMUv3.py
M src/dev/arm/css/MHU.py
5 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 7ab4b6e..f7d9cd5 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -108,7 +108,7 @@
# root instead of appended.
def generateMemNode(mem_range):
-node = FdtNode("memory@%x" % long(mem_range.start))
+node = FdtNode("memory@%x" % int(mem_range.start))
node.append(FdtPropertyStrings("device_type", ["memory"]))
node.append(FdtPropertyWords("reg",
state.addrCells(mem_range.start) +
diff --git a/src/dev/Device.py b/src/dev/Device.py
index af49504..46e992c 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -51,7 +51,7 @@
def generateBasicPioDeviceNode(self, state, name, pio_addr,
size, interrupts = None):
-node = FdtNode("%s@%x" % (name, long(pio_addr)))
+node = FdtNode("%s@%x" % (name, int(pio_addr)))
node.append(FdtPropertyWords("reg",
state.addrCells(pio_addr) +
state.sizeCells(size) ))
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8fa0edd..81d1f07 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -211,7 +211,7 @@
idreg = Param.UInt32(0x, "ID Register, SYS_ID")
def generateDeviceTree(self, state):
-node = FdtNode("sysreg@%x" % long(self.pio_addr))
+node = FdtNode("sysreg@%x" % int(self.pio_addr))
node.appendCompatible("arm,vexpress-sysreg")
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@
def generateDeviceTree(self, state):
phandle = state.phandle(self)
-node = FdtNode("osc@" + format(long(phandle), 'x'))
+node = FdtNode("osc@" + format(int(phandle), 'x'))
node.appendCompatible("arm,vexpress-osc")
node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
[0x1, int(self.device)]))
@@ -595,7 +595,7 @@
super(MmioSRAM, self).__init__(**kwargs)
def generateDeviceTree(self, state):
-node = FdtNode("sram@%x" % long(self.range.start))
+node = FdtNode("sram@%x" % int(self.range.start))
node.appendCompatible(["mmio-sram"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.range.start) +
diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index f444d64..85c10ad 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -187,7 +187,7 @@
def generateDeviceTree(self, state):
reg_addr = self.reg_map.start
reg_size = self.reg_map.size()
-node = FdtNode("smmuv3@%x" % long(reg_addr))
+node = FdtNode("smmuv3@%x" % int(reg_addr))
node.appendCompatible("arm,smmu-v3")
node.append(FdtPropertyWords("reg",
state.addrCells(reg_addr) +
diff --git a/src/dev/arm/css/MHU.py b/src/dev/arm/css/MHU.py
index 878ca22..f5bb7e5 100644
--- a/src/dev/arm/css/MHU.py
+++ b/src/dev/arm/css/MHU.py
@@ -89,7 +89,7 @@
scp = Param.Scp(Parent.any, "System Control Processor")
def generateDeviceTree(self, state):
-node = FdtNode("mailbox@%x" % long(self.pio_addr))
+node = FdtNode("mailbox@%x" % int(self.pio_addr))
node.appendCompatible(["arm,mhu", "arm,primecell"])
node.append(FdtPropertyWords("reg",
state.addrCells(self.pio_addr) +
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Consistently use ISO prefixes
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39579 )
Change subject: sim: Consistently use ISO prefixes
..
sim: Consistently use ISO prefixes
We currently use the traditional SI-like prefixes for to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.
Here are some examples of commonly used in the industry:
* Storage vendors define 1 MB as 10**6 bytes
* Memory vendors define 1 MB as 2**20 bytes
* Network equipment treats 1Mbit/s as 10**6 bits/s
* Memory vendors define 1Mbit as 2**20 bits
In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.
The quantity 2MX is treated differently by gem5 depending on the unit
X:
* Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
* Interconnect and NoC bandwidths (B/s) use binary prefixes.
* Network bandwidths (bps) use decimal prefixes.
* Memory sizes and storage sizes (B) use binary prefixes.
Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.
Change-Id: I797163c8690ae0092e00e371d75f5e7cebbcd1f5
Signed-off-by: Andreas Sandberg
---
M src/sim/Process.py
M src/sim/syscall_emul.hh
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
useArchPT = Param.Bool('false', 'maintain an in-memory version of the
page\
table in an architecture-specific format')
kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in
SE')
-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')
uid = Param.Int(100, 'user id')
euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 79cd35a..16fd175 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1824,7 +1824,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1867,7 +1867,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Consistently use ISO prefixes
max copy")
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
-rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
-rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
-tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
-tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
+rx_fifo_threshold = Param.MemorySize('384KiB', "rx fifo high
threshold")
+rx_fifo_low_mark = Param.MemorySize('128KiB', "rx fifo low threshold")
+tx_fifo_high_mark = Param.MemorySize('384KiB', "tx fifo high
threshold")
+tx_fifo_threshold = Param.MemorySize('128KiB', "tx fifo low threshold")
virtual_count = Param.UInt32(1, "Virtualized SINIC")
zero_copy_size = Param.UInt32(64, "Bytes to copy if below threshold")
zero_copy_threshold = Param.UInt32(256,
@@ -252,7 +253,7 @@
SubClassCode = 0x00
ClassCode = 0x02
ProgIF = 0x00
-BARs = PciMemBar(size='64kB')
+BARs = PciMemBar(size='64KiB')
MaximumLatency = 0x34
MinimumGrant = 0xb0
InterruptLine = 0x1e
diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py
index f5a0f9e..62d9bd7 100644
--- a/src/dev/pci/CopyEngine.py
+++ b/src/dev/pci/CopyEngine.py
@@ -48,10 +48,10 @@
InterruptLine = 0x20
InterruptPin = 0x01
-BAR0 = PciMemBar(size='1kB')
+BAR0 = PciMemBar(size='1KiB')
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
-XferCap = Param.MemorySize('4kB',
+XferCap = Param.MemorySize('4KiB',
"Number of bits of transfer size that are supported")
latBeforeBegin = Param.Latency('20ns',
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 0ed2648..736f068 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -41,7 +41,7 @@
class PcPciHost(GenericPciHost):
conf_base = 0xC000
-conf_size = "16MB"
+conf_size = "16MiB"
pci_pio_base = 0x8000
@@ -70,7 +70,7 @@
default_bus = IOXBar()
# A device to handle accesses to unclaimed IO ports.
-empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64kB',
+empty_isa = IsaFake(pio_addr=x86IOAddress(0), pio_size='64KiB',
ret_data8=0, ret_data16=0, ret_data32=0,
ret_data64=0,
pio=default_bus.mem_side_ports)
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Consistently use ISO prefixes
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39577 ) Change subject: python: Consistently use ISO prefixes .. python: Consistently use ISO prefixes We currently use the traditional SI-like prefixes for to represent binary multipliers in some contexts. This is ambiguous in many cases since they overload the meaning of the SI prefix. Here are some examples of commonly used in the industry: * Storage vendors define 1 MB as 10**6 bytes * Memory vendors define 1 MB as 2**20 bytes * Network equipment treats 1Mbit/s as 10**6 bits/s * Memory vendors define 1Mbit as 2**20 bits In practice, this means that a FLASH chip on a storage bus uses decimal prefixes, but that same flash chip on a memory bus uses binary prefixes. It would also be reasonable to assume that the contents of a 1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet link. That's however not the case due to different meanings of the prefix. The quantity 2MX is treated differently by gem5 depending on the unit X: * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes. * Interconnect and NoC bandwidths (B/s) use binary prefixes. * Network bandwidths (bps) use decimal prefixes. * Memory sizes and storage sizes (B) use binary prefixes. Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes for binary multipliers for parameters and comments where appropriate. Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93 Signed-off-by: Andreas Sandberg --- M src/python/m5/params.py 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 45082d7..2b52b93 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -692,7 +692,7 @@ class MemorySize(CheckedInt): cxx_type = 'uint64_t' -ex_str = '512MB' +ex_str = '512MiB' size = 64 unsigned = True def __init__(self, value): @@ -704,7 +704,7 @@ class MemorySize32(CheckedInt): cxx_type = 'uint32_t' -ex_str = '512MB' +ex_str = '512MiB' size = 32 unsigned = True def __init__(self, value): @@ -724,7 +724,7 @@ else: try: # Often addresses are referred to with sizes. Ex: A device -# base address is at "512MB". Use toMemorySize() to convert +# base address is at "512MiB". Use toMemorySize() to convert # these into addresses. If the address is not specified with a # "size", an exception will occur and numeric translation will # proceed below. @@ -1748,7 +1748,7 @@ class MemoryBandwidth(float,ParamValue): cxx_type = 'float' -ex_str = "1GB/s" +ex_str = "1GiB/s" cmd_line_settable = True def __new__(cls, value): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39577 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3d0bbfa00968486af8d57c36be2c8bee034bae93 Gerrit-Change-Number: 39577 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes
or 16 banks depending on capacity
# Starting with 4Gb dies, 16 banks are defined
@@ -1146,10 +1146,10 @@
burst_length = 32
# size of device in bytes
-device_size = '1GB'
+device_size = '1GiB'
-# 2kB page with BG mode
-device_rowbuffer_size = '2kB'
+# 2KiB page with BG mode
+device_rowbuffer_size = '2KiB'
# Use a 1x16 configuration
devices_per_rank = 1
@@ -1279,8 +1279,8 @@
# Configuring for 8-bank mode, burst of 32
class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32):
-# 4kB page with 8B mode
-device_rowbuffer_size = '4kB'
+# 4KiB page with 8B mode
+device_rowbuffer_size = '4KiB'
# LPDDR5 supports configurable bank options
# 8B : BL32, all frequencies
@@ -1384,8 +1384,8 @@
# Configuring for 8-bank mode, burst of 32
class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32):
-# 4kB page with 8B mode
-device_rowbuffer_size = '4kB'
+# 4KiB page with 8B mode
+device_rowbuffer_size = '4KiB'
# LPDDR5 supports configurable bank options
# 8B : BL32, all frequencies
diff --git a/src/mem/NVMInterface.py b/src/mem/NVMInterface.py
index 3f6fbc4..20f51fc 100644
--- a/src/mem/NVMInterface.py
+++ b/src/mem/NVMInterface.py
@@ -76,7 +76,7 @@
device_rowbuffer_size = '256B'
# 8X capacity compared to DDR4 x4 DIMM with 8Gb devices
-device_size = '512GB'
+device_size = '512GiB'
# Mimic 64-bit media agnostic DIMM interface
device_bus_width = 64
devices_per_rank = 1
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 6e4b915..e8eac69 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -45,7 +45,7 @@
port = ResponsePort("This port sends responses and receives requests")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency
variance")
-# The memory bandwidth limit default is set to 12.8GB/s which is
+# The memory bandwidth limit default is set to 12.8GiB/s which is
# representative of a x64 DDR3-1600 channel.
-bandwidth = Param.MemoryBandwidth('12.8GB/s',
+bandwidth = Param.MemoryBandwidth('12.8GiB/s',
"Combined read and write bandwidth")
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index c162584..2dfe7c1 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -138,7 +138,7 @@
system = Param.System(Parent.any, "System that the crossbar belongs
to.")
# Sanity check on max capacity to track, adjust if needed.
-max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop
filter")
+max_capacity = Param.MemorySize('8MiB', "Maximum capacity of snoop
filter")
# We use a coherent crossbar to connect multiple requestors to the L2
# caches. Normally this crossbar would be part of the cache itself.
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 758803f..0840c60 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -293,7 +293,7 @@
"Limit the strides checked up to -X/X, if 0, disable the limit")
start_degree = Param.Unsigned(4,
"Initial degree (Maximum number of prefetches generated")
-hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
+hot_zone_size = Param.MemorySize("2KiB", "Memory covered by a hot
zone")
access_map_table_entries = Param.MemorySize("256",
"Number of entries in the access map table")
access_map_table_assoc = Param.Unsigned(8,
@@ -456,7 +456,7 @@
cxx_class = "Prefetcher::STeMS"
cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh"
-spatial_region_size = Param.MemorySize("2kB",
+spatial_region_size = Param.MemorySize("2KiB",
"Memory covered by a hot zone")
active_generation_table_entries = Param.MemorySize("64",
"Number of entries in the active generation table")
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index ce086fa..1e5b355 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -119,8 +119,8 @@
cxx_class = 'FALRU'
cxx_header = "mem/cache/tags/fa_lru.hh"
-min_tracked_cache_size = Param.MemorySize("128kB", "Minimum cache size
for"
- " which we track statistics")
+min_tracked_cache_size = Param.MemorySize("128KiB", "Minimum cache
size"
+ " for which we track
statistics")
# This tag uses its own embedded indexing
indexing_policy = NULL
--
To view, visit https://gem5-review.g
[gem5-dev] Change in gem5/gem5[develop]: arch-arm, dev-arm: Consistently use ISO prefixes
AddrRange(0x3000, size='256MB'),
-AddrRange(0x4000, size='512MB'),
-AddrRange(0x1800, size='64MB'),
-AddrRange(0x1C00, size='64MB')]
+_off_chip_ranges = [AddrRange(0x2F00, size='16MiB'),
+AddrRange(0x3000, size='256MiB'),
+AddrRange(0x4000, size='512MiB'),
+AddrRange(0x1800, size='64MiB'),
+AddrRange(0x1C00, size='64MiB')]
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x1400, proc_id1=0x1400,
@@ -790,7 +790,7 @@
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c09, interrupt=ArmSPI(num=37))
pci_host = GenericPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=16,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=16,
pci_pio_base=0)
sys_counter = SystemCounter()
@@ -814,9 +814,9 @@
cf_ctrl.BAR0 = PciLegacyIoBar(addr='0x1C1A', size='256B')
cf_ctrl.BAR1 = PciLegacyIoBar(addr='0x1C1A0100', size='4096B')
-bootmem= SimpleMemory(range = AddrRange('64MB'),
+bootmem= SimpleMemory(range = AddrRange('64MiB'),
conf_table_reported = False)
-vram = SimpleMemory(range = AddrRange(0x1800,
size='32MB'),
+vram = SimpleMemory(range = AddrRange(0x1800,
size='32MiB'),
conf_table_reported = False)
rtc= PL031(pio_addr=0x1C17, interrupt=ArmSPI(num=36))
@@ -884,12 +884,12 @@
cur_sys, boot_loader, 0x800, 0x8000)
class VExpress_EMM64(VExpress_EMM):
-# Three memory regions are specified totalling 512GB
-_mem_regions = [ AddrRange('2GB', size='2GB'),
- AddrRange('34GB', size='30GB'),
- AddrRange('512GB', size='480GB') ]
+# Three memory regions are specified totalling 512GiB
+_mem_regions = [ AddrRange('2GiB', size='2GiB'),
+ AddrRange('34GiB', size='30GiB'),
+ AddrRange('512GiB', size='480GiB') ]
pci_host = GenericPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f00)
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
@@ -1038,7 +1038,7 @@
"""
# Everything above 2GiB is memory
-_mem_regions = [ AddrRange('2GB', size='510GB') ]
+_mem_regions = [ AddrRange('2GiB', size='510GiB') ]
_off_chip_ranges = [
# CS1-CS5
@@ -1047,15 +1047,15 @@
AddrRange(0x2f00, 0x8000),
]
-bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
+bootmem = SimpleMemory(range=AddrRange(0, size='64MiB'),
conf_table_reported=False)
# NOR flash, flash0
-flash0 = SimpleMemory(range=AddrRange(0x0800, size='64MB'),
+flash0 = SimpleMemory(range=AddrRange(0x0800, size='64MiB'),
conf_table_reported=False)
# Trusted SRAM
-trusted_sram = SimpleMemory(range=AddrRange(0x0400, size='256kB'),
+trusted_sram = SimpleMemory(range=AddrRange(0x0400, size='256KiB'),
conf_table_reported=False)
# Non-Trusted SRAM
@@ -1134,7 +1134,7 @@
### gem5-specific off-chip devices ###
pci_host = GenericArmPciHost(
-conf_base=0x3000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x3000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f00,
pci_mem_base=0x4000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
@@ -1354,7 +1354,7 @@
its=NULL)
pci_host = GenericArmPciHost(
- conf_base=0x4000, conf_size='256MB', conf_device_bits=12,
+conf_base=0x4000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x5000,
pci_mem_base=0x4,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect prefixes is m5.utils.convert
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/39375 ) Change subject: python: Fix incorrect prefixes is m5.utils.convert .. python: Fix incorrect prefixes is m5.utils.convert The conversion functions incorrectly assumed that kibibytes are 'kiB' rather than 'KiB' (correct). Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39375 Reviewed-by: Daniel Carvalho Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/util/convert.py 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Daniel Carvalho: Looks good to me, approved kokoro: Regressions pass Objections: Gabe Black: I would prefer this is not merged as is diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py index d3088f6..73335e6 100644 --- a/src/python/m5/util/convert.py +++ b/src/python/m5/util/convert.py @@ -62,7 +62,7 @@ 'Gi': gibi, 'G': giga, 'M': mega, -'ki': kibi, +'Ki': kibi, 'k': kilo, 'Mi': mebi, 'm': milli, @@ -84,7 +84,7 @@ 'G' : gibi, 'Mi': mebi, 'M' : mebi, -'ki': kibi, +'Ki': kibi, 'k' : kibi, } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39375 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Gerrit-Change-Number: 39375 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim, mem, dev, arch: Consistently use ISO prefixes
sentative of a x64 DDR3-1600 channel.
-bandwidth = Param.MemoryBandwidth('12.8GB/s',
+bandwidth = Param.MemoryBandwidth('12.8GiB/s',
"Combined read and write bandwidth")
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index c162584..2dfe7c1 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -138,7 +138,7 @@
system = Param.System(Parent.any, "System that the crossbar belongs
to.")
# Sanity check on max capacity to track, adjust if needed.
-max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop
filter")
+max_capacity = Param.MemorySize('8MiB', "Maximum capacity of snoop
filter")
# We use a coherent crossbar to connect multiple requestors to the L2
# caches. Normally this crossbar would be part of the cache itself.
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index 758803f..0840c60 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -293,7 +293,7 @@
"Limit the strides checked up to -X/X, if 0, disable the limit")
start_degree = Param.Unsigned(4,
"Initial degree (Maximum number of prefetches generated")
-hot_zone_size = Param.MemorySize("2kB", "Memory covered by a hot zone")
+hot_zone_size = Param.MemorySize("2KiB", "Memory covered by a hot
zone")
access_map_table_entries = Param.MemorySize("256",
"Number of entries in the access map table")
access_map_table_assoc = Param.Unsigned(8,
@@ -456,7 +456,7 @@
cxx_class = "Prefetcher::STeMS"
cxx_header = "mem/cache/prefetch/spatio_temporal_memory_streaming.hh"
-spatial_region_size = Param.MemorySize("2kB",
+spatial_region_size = Param.MemorySize("2KiB",
"Memory covered by a hot zone")
active_generation_table_entries = Param.MemorySize("64",
"Number of entries in the active generation table")
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index ce086fa..1e5b355 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -119,8 +119,8 @@
cxx_class = 'FALRU'
cxx_header = "mem/cache/tags/fa_lru.hh"
-min_tracked_cache_size = Param.MemorySize("128kB", "Minimum cache size
for"
- " which we track statistics")
+min_tracked_cache_size = Param.MemorySize("128KiB", "Minimum cache
size"
+ " for which we track
statistics")
# This tag uses its own embedded indexing
indexing_policy = NULL
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 45082d7..2b52b93 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -692,7 +692,7 @@
class MemorySize(CheckedInt):
cxx_type = 'uint64_t'
-ex_str = '512MB'
+ex_str = '512MiB'
size = 64
unsigned = True
def __init__(self, value):
@@ -704,7 +704,7 @@
class MemorySize32(CheckedInt):
cxx_type = 'uint32_t'
-ex_str = '512MB'
+ex_str = '512MiB'
size = 32
unsigned = True
def __init__(self, value):
@@ -724,7 +724,7 @@
else:
try:
# Often addresses are referred to with sizes. Ex: A device
-# base address is at "512MB". Use toMemorySize() to
convert
+# base address is at "512MiB". Use toMemorySize() to
convert
# these into addresses. If the address is not specified
with a
# "size", an exception will occur and numeric translation
will
# proceed below.
@@ -1748,7 +1748,7 @@
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
-ex_str = "1GB/s"
+ex_str = "1GiB/s"
cmd_line_settable = True
def __new__(cls, value):
diff --git a/src/sim/Process.py b/src/sim/Process.py
index bdcb826..767dbfa 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -44,7 +44,7 @@
useArchPT = Param.Bool('false', 'maintain an in-memory version of the
page\
table in an architecture-specific format')
kvmInSE = Param.Bool('false', 'initialize the process for KvmCPU in
SE')
-maxStackSize = Param.MemorySize('64MB', 'maximum size of the stack')
+maxStackSize = Param.MemorySize('64MiB', 'maximum size of the stack')
uid = Param.Int(100, 'user id')
euid = Param.Int(100, 'effective user id')
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 79cd35a..16fd175 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1824,7 +1824,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
@@ -1867,7 +1867,7 @@
const ByteOrder bo = OS::byteOrder;
switch (resource) {
case OS::TGT_RLIMIT_STACK:
-// max stack size in bytes: make up a number (8MB for now)
+// max stack size in bytes: make up a number (8MiB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
rlp->rlim_cur = htog(rlp->rlim_cur, bo);
rlp->rlim_max = htog(rlp->rlim_max, bo);
--
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Gerrit-Change-Id: I0849b97d75e17fca2c782166185f41dd2cf6b0a5
Gerrit-Change-Number: 39475
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature type in power/thermal models
h"
@@ -123,7 +124,7 @@
double step) const override;
/* Fixed temperature value in centigrate degrees */
-const double _temperature;
+const Temperature _temperature;
/* Nodes connected to the resistor */
ThermalNode * node;
};
@@ -150,7 +151,7 @@
void addNode(ThermalNode * n) { nodes.push_back(n); }
-double getTemp() const;
+Temperature getTemperature() const;
void startup() override;
void doStep();
diff --git a/src/sim/power/thermal_node.hh b/src/sim/power/thermal_node.hh
index 68867b3..e9d4096 100644
--- a/src/sim/power/thermal_node.hh
+++ b/src/sim/power/thermal_node.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -38,6 +38,7 @@
#ifndef __SIM_THERMAL_NODE_HH__
#define __SIM_THERMAL_NODE_HH__
+#include "base/temperature.hh"
#include "sim/sim_object.hh"
struct ThermalNodeParams;
@@ -54,7 +55,7 @@
int id;
bool isref;
-double temp;
+Temperature temp;
};
#endif
--
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Gerrit-Change-Id: I22d0261ae102f30d86051f24a2d88b067b321c91
Gerrit-Change-Number: 39455
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[gem5-dev] Change in gem5/gem5[develop]: python: Require a unit in anyToFreuency and anyToLatency
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39435 )
Change subject: python: Require a unit in anyToFreuency and anyToLatency
..
python: Require a unit in anyToFreuency and anyToLatency
The anytToFrequency and anyToLatency conversion functions are
currently ambiguous when called without a unit. Fix this by always
requiring a unit.
Change-Id: I5ea94e655f7ca82c0efe70b9f9f7f734fbf711c1
Signed-off-by: Andreas Sandberg
---
M src/python/m5/util/convert.py
M tests/pyunit/util/test_convert.py
2 files changed, 32 insertions(+), 34 deletions(-)
diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index ce06ea4..12d3aa1 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -203,32 +203,40 @@
return toMetricFloat(value, 'latency', 's')
def anyToLatency(value):
-"""result is a clock period"""
-try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
-pass
+"""Convert a magnitude and unit to a clock period."""
-try:
-return toLatency(value)
-except ValueError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='latency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 's':
+return magnitude
+elif unit == 'Hz':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to clock period")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be
unambiguous.")
def anyToFrequency(value):
-"""result is a clock period"""
-try:
-return toFrequency(value)
-except ValueError:
-pass
+"""Convert a magnitude and unit to a clock frequency."""
-try:
-return 1 / toLatency(value)
-except ValueError as ZeroDivisionError:
-pass
-
-raise ValueError("cannot convert '%s' to clock period" % value)
+magnitude, unit = toNum(value,
+target_type='frequency',
+units=('Hz', 's'),
+prefixes=metric_prefixes,
+converter=float)
+if unit == 'Hz':
+return magnitude
+elif unit == 's':
+try:
+return 1.0 / magnitude
+except ZeroDivisionError:
+raise ValueError(f"cannot convert '{value}' to frequency")
+else:
+raise ValueError(f"'{value}' needs a valid unit to be
unambiguous.")
def toNetworkBandwidth(value):
return toMetricFloat(value, 'network bandwidth', 'bps')
diff --git a/tests/pyunit/util/test_convert.py
b/tests/pyunit/util/test_convert.py
index 6d02b51..fcfedc4 100644
--- a/tests/pyunit/util/test_convert.py
+++ b/tests/pyunit/util/test_convert.py
@@ -163,28 +163,18 @@
self.assertEqual(conv('1kHz'), 1e-3)
self.assertRaises(ValueError, conv, '42k')
-
-@unittest.expectedFailure
-def test_anyToLatency_ambiguous(self):
-# This the behavior of anyToFrequency is currently ambiguous
-# (and surprising) for unitless quantities. The following
-# should be true to be consistent with the other conversion
-# functions, but that isn't currently the case.
-self.assertEqual(convert.anyToLatency('42'), 42.0)
-
+self.assertRaises(ValueError, conv, '42')
def test_anyToFrequency(self):
conv = convert.anyToFrequency
-# This is ambiguous and should probably not be allowed.
-self.assertEqual(conv('42'), 42.0)
-
self.assertEqual(conv('42kHz'), 42e3)
self.assertEqual(conv('0.1s'), 10.0)
self.assertEqual(conv('1ms'), 1000.0)
self.assertRaises(ValueError, conv, '42k')
+self.assertRaises(ValueError, conv, '42')
def test_toNetworkBandwidth(self):
conv = convert.toNetworkBandwidth
--
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Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialise params in thermal models
st override; @@ -104,7 +98,7 @@ private: /* Capacitance value in J/K */ -double _capacitance; +const double _capacitance; /* Nodes connected to the resistor */ ThermalNode * node1, * node2; }; @@ -128,11 +122,8 @@ LinearEquation getEquation(ThermalNode * tn, unsigned n, double step) const override; -void serialize(CheckpointOut ) const override; -void unserialize(CheckpointIn ) override; - /* Fixed temperature value in centigrate degrees */ -double _temperature; +const double _temperature; /* Nodes connected to the resistor */ ThermalNode * node; }; @@ -164,8 +155,6 @@ void startup() override; void doStep(); -void serialize(CheckpointOut ) const override; -void unserialize(CheckpointIn ) override; private: /* Keep track of all components used for the thermal model */ @@ -184,8 +173,7 @@ EventFunctionWrapper stepEvent; /** Step in seconds for thermal updates */ -double _step; - +const double _step; }; #endif -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39221 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idc4438b68c0db1fe312d37888c901f2ea87b1d60 Gerrit-Change-Number: 39221 Gerrit-PatchSet: 4 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Thermal model style fixes
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/39220 )
Change subject: sim: Thermal model style fixes
..
sim: Thermal model style fixes
Fix various style issues in the thermal model implementation.
Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39220
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
2 files changed, 23 insertions(+), 9 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 408642c..9f970de 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -39,6 +39,7 @@
#include "base/statistics.hh"
#include "params/ThermalCapacitor.hh"
+#include "params/ThermalModel.hh"
#include "params/ThermalReference.hh"
#include "params/ThermalResistor.hh"
#include "sim/clocked_object.hh"
@@ -253,24 +254,37 @@
schedule(stepEvent, curTick() + SimClock::Int::s * _step);
}
-void ThermalModel::addDomain(ThermalDomain * d) {
+void
+ThermalModel::addDomain(ThermalDomain * d)
+{
domains.push_back(d);
entities.push_back(d);
}
-void ThermalModel::addReference(ThermalReference * r) {
+
+void
+ThermalModel::addReference(ThermalReference * r)
+{
references.push_back(r);
entities.push_back(r);
}
-void ThermalModel::addCapacitor(ThermalCapacitor * c) {
+
+void
+ThermalModel::addCapacitor(ThermalCapacitor * c)
+{
capacitors.push_back(c);
entities.push_back(c);
}
-void ThermalModel::addResistor(ThermalResistor * r) {
+
+void
+ThermalModel::addResistor(ThermalResistor * r)
+{
resistors.push_back(r);
entities.push_back(r);
}
-double ThermalModel::getTemp() const {
+double
+ThermalModel::getTemp() const
+{
// Just pick the highest temperature
double temp = 0;
for (auto & n : eq_nodes)
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 81c1de8..295e508 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -40,16 +40,16 @@
#include
-#include "params/ThermalCapacitor.hh"
-#include "params/ThermalModel.hh"
-#include "params/ThermalReference.hh"
-#include "params/ThermalResistor.hh"
#include "sim/clocked_object.hh"
#include "sim/power/thermal_domain.hh"
#include "sim/power/thermal_entity.hh"
#include "sim/power/thermal_node.hh"
#include "sim/sim_object.hh"
+struct ThermalCapacitorParams;
+struct ThermalModelParams;
+struct ThermalReferenceParams;
+struct ThermalResistorParams;
/**
* A ThermalResistor is used to model a thermal resistance between two
--
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Gerrit-Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Gerrit-Change-Number: 39220
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add Python unit tests for m5.util.convert
v("1.2.3.4/255.255.255.0"),
+ (_ip(1, 2, 3, 4), 24))
+
+self.assertEqual(conv("1.2.3.4/0"), (_ip(1, 2, 3, 4), 0))
+self.assertEqual(conv("1.2.3.4/0.0.0.0"),
+ (_ip(1, 2, 3, 4), 0))
+
+self.assertRaises(ValueError, conv, "0.0.0.0")
+self.assertRaises(ValueError, conv, "0.0.0.0/")
+self.assertRaises(ValueError, conv, "0.0.0.0/64")
+
+def test_toIpWithPort(self):
+conv = convert.toIpWithPort
+
+self.assertEqual(conv("1.2.3.4:42"), (_ip(1, 2, 3, 4), 42))
+
+self.assertRaises(ValueError, conv, "0.0.0.0")
+self.assertRaises(ValueError, conv, "0.0.0.0:")
+self.assertRaises(ValueError, conv, "0.0.0.0:65536")
+
+def test_toVoltage(self):
+conv = convert.toVoltage
+
+self.assertEqual(conv('42'), 42)
+self.assertEqual(conv('42V'), 42)
+self.assertEqual(conv('42kV'), 42e3)
+
+def test_toCurrent(self):
+conv = convert.toCurrent
+
+self.assertEqual(conv('42'), 42)
+self.assertEqual(conv('42A'), 42)
+self.assertEqual(conv('42kA'), 42e3)
+
+def test_toEnergy(self):
+conv = convert.toEnergy
+
+self.assertEqual(conv('42'), 42)
+self.assertEqual(conv('42J'), 42)
+self.assertEqual(conv('42kJ'), 42e3)
diff --git a/tests/run_pyunit.py b/tests/run_pyunit.py
new file mode 100644
index 000..dcd8984
--- /dev/null
+++ b/tests/run_pyunit.py
@@ -0,0 +1,51 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2021 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+if __name__ == "__main__":
+import sys
+print("ERROR: This file must be run from gem5.", file=sys.stderr)
+sys.exit(1)
+
+if __name__ == "__m5_main__":
+import unittest
+
+loader = unittest.TestLoader()
+tests = loader.discover("pyunit")
+
+runner = unittest.runner.TextTestRunner(verbosity=2)
+runner.run(tests)
+
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect anyToLatency conversion
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39376 )
Change subject: python: Fix incorrect anyToLatency conversion
..
python: Fix incorrect anyToLatency conversion
The anyToLatency conversion function incorrectly inverted values
without units.
Change-Id: Ife0aa6837bf7d830b9a3f2611c77f6501cfe19ab
Signed-off-by: Andreas Sandberg
---
M src/python/m5/util/convert.py
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 73335e6..4dab2e6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -156,13 +156,13 @@
def anyToLatency(value):
"""result is a clock period"""
try:
-return 1 / toFrequency(value)
-except (ValueError, ZeroDivisionError):
+return toLatency(value)
+except ValueError:
pass
try:
-return toLatency(value)
-except ValueError:
+return 1 / toFrequency(value)
+except (ValueError, ZeroDivisionError):
pass
raise ValueError("cannot convert '%s' to clock period" % value)
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix incorrect prefixes is m5.utils.convert
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/39375 ) Change subject: python: Fix incorrect prefixes is m5.utils.convert .. python: Fix incorrect prefixes is m5.utils.convert The conversion functions incorrectly assumed that kibibytes are 'kiB' rather than 'KiB' (correct). Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Signed-off-by: Andreas Sandberg --- M src/python/m5/util/convert.py 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py index d3088f6..73335e6 100644 --- a/src/python/m5/util/convert.py +++ b/src/python/m5/util/convert.py @@ -62,7 +62,7 @@ 'Gi': gibi, 'G': giga, 'M': mega, -'ki': kibi, +'Ki': kibi, 'k': kilo, 'Mi': mebi, 'm': milli, @@ -84,7 +84,7 @@ 'G' : gibi, 'Mi': mebi, 'M' : mebi, -'ki': kibi, +'Ki': kibi, 'k' : kibi, } -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39375 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7ef9e54546fdb3379435b40af6d9f619ad9b37a5 Gerrit-Change-Number: 39375 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: python: Refactor toNum to support a selection of units
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39217 )
Change subject: python: Refactor toNum to support a selection of units
..
python: Refactor toNum to support a selection of units
Add support for matching one of several different units in toNum. The
units parameter can now either be a tuple or a string describing the
supported unit(s). The function now returns a (magnitude, unit) tuple.
Change-Id: I683819722a93ade91a6def2bfa77209c29b4b39e
Signed-off-by: Andreas Sandberg
---
M src/python/m5/util/convert.py
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index d3088f6..772fba2 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2005 The Regents of The University of Michigan
# Copyright (c) 2010 Advanced Micro Devices, Inc.
# All rights reserved.
@@ -92,34 +104,46 @@
if not isinstance(value, str):
raise TypeError("wrong type '%s' should be str" % type(value))
+def _find_suffix(value, suffixes, default=''):
+matches = [ sfx for sfx in suffixes if value.endswith(sfx) ]
+assert len(matches) <= 1
+
+return matches[0] if matches else default
# memory size configuration stuff
def toNum(value, target_type, units, prefixes, converter):
assertStr(value)
def convert(val):
+return converter(val)
try:
return converter(val)
except ValueError:
raise ValueError(
"cannot convert '%s' to %s" % (value, target_type))
-if units and not value.endswith(units):
-units = None
+# Units can be None, the empty string, or an a list/tuple. Convert
+# to a tuple for consistent handling.
if not units:
-return convert(value)
+units = tuple()
+elif isinstance(units, str):
+units = (units,)
+else:
+units = tuple(units)
-value = value[:-len(units)]
+unit = _find_suffix(value, units)
-prefix = next((p for p in prefixes.keys() if value.endswith(p)), None)
-if not prefix:
-return convert(value)
-value = value[:-len(prefix)]
+# We only allow a prefix if there is a unit
+if unit:
+prefix = _find_suffix(value[:-len(unit)], prefixes)
+scale = prefixes[prefix] if prefix else 1
+else:
+prefix, scale = '', 1
-return convert(value) * prefixes[prefix]
+return convert(value[:len(value) - len(unit) - len(prefix)]) * scale,
unit
def toFloat(value, target_type='float', units=None, prefixes=[]):
-return toNum(value, target_type, units, prefixes, float)
+return toNum(value, target_type, units, prefixes, float)[0]
def toMetricFloat(value, target_type='float', units=None):
return toFloat(value, target_type, units, metric_prefixes)
@@ -128,8 +152,8 @@
return toFloat(value, target_type, units, binary_prefixes)
def toInteger(value, target_type='integer', units=None, prefixes=[]):
-intifier = lambda x: int(x, 0)
-return toNum(value, target_type, units, prefixes, intifier)
+return toNum(value, target_type, units, prefixes,
+ lambda x: int(x, 0))[0]
def toMetricInteger(value, target_type='integer', units=None):
return toInteger(value, target_type, units, metric_prefixes)
--
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[gem5-dev] Change in gem5/gem5[develop]: base, python: Add a Temperature type and associated param
'NetworkBandwidth', 'MemoryBandwidth',
'AddrRange',
'MaxAddr', 'MaxTick', 'AllMemory',
diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 772fba2..2b75591 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -271,3 +271,26 @@
def toEnergy(value):
return toMetricFloat(value, 'energy', 'J')
+
+def toTemperature(value):
+"""Convert a string value specified to a temperature in Kelvin"""
+
+def convert(magnitude, unit):
+if unit == 'K':
+return magnitude
+elif unit == 'C':
+return magnitude + 273.15
+elif unit == 'F':
+return (magnitude + 459.67) / 1.8
+else:
+raise ValueError(f"'{value}' needs a valid temperature unit.")
+
+kelvin = convert(*toNum(value,
+target_type='temperature',
+units=('K', 'C', 'F'),
+prefixes=metric_prefixes,
+converter=float))
+if kelvin < 0:
+raise ValueError(f"{value} is an invalid temperature")
+
+return kelvin
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index 8655d73..a372d47 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, 2019 ARM Limited
+ * Copyright (c) 2017, 2019, 2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -52,6 +52,7 @@
#include "base/logging.hh"
#include "base/random.hh"
#include "base/socket.hh"
+#include "base/temperature.hh"
#include "base/types.hh"
#include "sim/core.hh"
#include "sim/drain.hh"
@@ -220,6 +221,19 @@
.def("__sub__", ::operator-)
;
+py::class_(m_core, "Temperature")
+.def(py::init<>())
+.def(py::init())
+.def_static("from_celsius", ::fromCelsius)
+.def_static("from_kelvin", ::fromKelvin)
+.def("__add__", ::operator+)
+.def("__sub__", ::operator-)
+.def("__truediv__", ::operator/)
+.def("__mul__", ::operator*)
+.def("celsius", ::toCelsius)
+.def("kelvin", ::toKelvin)
+;
+
py::class_(m_core, "tm")
.def_static("gmtime", [](std::time_t t) { return *std::gmtime();
})
.def_readwrite("tm_sec", ::tm_sec)
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Don't serialise params in thermal models
grees */ -double _temperature; +const double _temperature; /* Nodes connected to the resistor */ ThermalNode * node; }; @@ -164,8 +155,6 @@ void startup() override; void doStep(); -void serialize(CheckpointOut ) const override; -void unserialize(CheckpointIn ) override; private: /* Keep track of all components used for the thermal model */ @@ -184,8 +173,7 @@ EventFunctionWrapper stepEvent; /** Step in seconds for thermal updates */ -double _step; - +const double _step; }; #endif -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/39221 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idc4438b68c0db1fe312d37888c901f2ea87b1d60 Gerrit-Change-Number: 39221 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Use the Temperature param type
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39219 )
Change subject: sim: Use the Temperature param type
..
sim: Use the Temperature param type
Add support for passing typed temperatures using the new Temperature
param type.
Change-Id: If68d619fd824e171d895a5cbbe4d0325d4c4f4db
Signed-off-by: Andreas Sandberg
---
M src/sim/power/PowerModel.py
M src/sim/power/ThermalDomain.py
M src/sim/power/ThermalModel.py
M src/sim/power/power_model.cc
M src/sim/power/thermal_domain.cc
M src/sim/power/thermal_model.cc
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/sim/power/PowerModel.py b/src/sim/power/PowerModel.py
index 2047c64..cfbd8cb 100644
--- a/src/sim/power/PowerModel.py
+++ b/src/sim/power/PowerModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2018 ARM Limited
+# Copyright (c) 2016-2018, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -63,4 +63,4 @@
pm_type = Param.PMType("All", "Type of power model")
# Ambient temperature to be used when no thermal model is present
-ambient_temp = Param.Float(25.0, "Ambient temperature")
+ambient_temp = Param.Temperature("25.0C", "Ambient temperature")
diff --git a/src/sim/power/ThermalDomain.py b/src/sim/power/ThermalDomain.py
index 3fd5cad..57c53b2 100644
--- a/src/sim/power/ThermalDomain.py
+++ b/src/sim/power/ThermalDomain.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -46,4 +46,4 @@
]
# Static temperature which may change over time
-initial_temperature = Param.Float(25.0, "Initial temperature")
+initial_temperature = Param.Temperature("25.0C", "Initial temperature")
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index 2894dd8..90710e1 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2015 ARM Limited
+# Copyright (c) 2015, 2021 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@
]
# Static temperature which may change over time
-temperature = Param.Float(25.0, "Operational temperature in Celsius")
+temperature = Param.Temperature("25.0C", "Operational temperature")
# Represents a thermal capacitor
diff --git a/src/sim/power/power_model.cc b/src/sim/power/power_model.cc
index fbc67d3..42515ac 100644
--- a/src/sim/power/power_model.cc
+++ b/src/sim/power/power_model.cc
@@ -66,7 +66,7 @@
// The temperature passed here will be overwritten, if there is
// a thermal model present
for (auto & pms: states_pm){
-pms->setTemperature(p.ambient_temp);
+pms->setTemperature(p.ambient_temp.toCelsius());
}
dynamicPower
diff --git a/src/sim/power/thermal_domain.cc
b/src/sim/power/thermal_domain.cc
index e9f4d3c..a2276c5 100644
--- a/src/sim/power/thermal_domain.cc
+++ b/src/sim/power/thermal_domain.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,7 +50,7 @@
#include "sim/sub_system.hh"
ThermalDomain::ThermalDomain(const Params )
-: SimObject(p), _initTemperature(p.initial_temperature),
+: SimObject(p), _initTemperature(p.initial_temperature.toCelsius()),
node(NULL), subsystem(NULL),
ADD_STAT(currentTemp, "Temperature in centigrade degrees")
{
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index 408642c..ce2abe3 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -51,7 +51,7 @@
* ThermalReference
*/
ThermalReference::ThermalReference(const Params )
-: SimObject(p), _temperature(p.temperature), node(NULL)
+: SimObject(p), _temperature(p.temperature.toCelsius()), node(NULL)
{
}
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Thermal model style fixes
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39220 )
Change subject: sim: Thermal model style fixes
..
sim: Thermal model style fixes
Fix various style issues in the thermal model implementation.
Change-Id: Ie31c862a23885f32f2931e927d7f87b7992bd099
Signed-off-by: Andreas Sandberg
---
M src/sim/power/thermal_model.cc
M src/sim/power/thermal_model.hh
2 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/src/sim/power/thermal_model.cc b/src/sim/power/thermal_model.cc
index ce2abe3..306a4fa 100644
--- a/src/sim/power/thermal_model.cc
+++ b/src/sim/power/thermal_model.cc
@@ -39,6 +39,7 @@
#include "base/statistics.hh"
#include "params/ThermalCapacitor.hh"
+#include "params/ThermalModel.hh"
#include "params/ThermalReference.hh"
#include "params/ThermalResistor.hh"
#include "sim/clocked_object.hh"
@@ -253,24 +254,37 @@
schedule(stepEvent, curTick() + SimClock::Int::s * _step);
}
-void ThermalModel::addDomain(ThermalDomain * d) {
+void
+ThermalModel::addDomain(ThermalDomain * d)
+{
domains.push_back(d);
entities.push_back(d);
}
-void ThermalModel::addReference(ThermalReference * r) {
+
+void
+ThermalModel::addReference(ThermalReference * r)
+{
references.push_back(r);
entities.push_back(r);
}
-void ThermalModel::addCapacitor(ThermalCapacitor * c) {
+
+void
+ThermalModel::addCapacitor(ThermalCapacitor * c)
+{
capacitors.push_back(c);
entities.push_back(c);
}
-void ThermalModel::addResistor(ThermalResistor * r) {
+
+void
+ThermalModel::addResistor(ThermalResistor * r)
+{
resistors.push_back(r);
entities.push_back(r);
}
-double ThermalModel::getTemp() const {
+double
+ThermalModel::getTemp() const
+{
// Just pick the highest temperature
double temp = 0;
for (auto & n : eq_nodes)
diff --git a/src/sim/power/thermal_model.hh b/src/sim/power/thermal_model.hh
index 81c1de8..295e508 100644
--- a/src/sim/power/thermal_model.hh
+++ b/src/sim/power/thermal_model.hh
@@ -40,16 +40,16 @@
#include
-#include "params/ThermalCapacitor.hh"
-#include "params/ThermalModel.hh"
-#include "params/ThermalReference.hh"
-#include "params/ThermalResistor.hh"
#include "sim/clocked_object.hh"
#include "sim/power/thermal_domain.hh"
#include "sim/power/thermal_entity.hh"
#include "sim/power/thermal_node.hh"
#include "sim/sim_object.hh"
+struct ThermalCapacitorParams;
+struct ThermalModelParams;
+struct ThermalReferenceParams;
+struct ThermalResistorParams;
/**
* A ThermalResistor is used to model a thermal resistance between two
--
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[gem5-dev] Change in gem5/gem5[develop]: misc: Convert MAINTAINERS to YAML
ack + +util-docker: + status: maintained + maintainers: +- Bobby Bruce + +util-m5: + status: maintained + maintainers: +- Gabe Black + +website: + desc: >- +The gem5-website repo which contains the gem5.org site + status: maintained + maintainers: +- Bobby Bruce +- Hoa Nguyen -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37035 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0 Gerrit-Change-Number: 37035 Gerrit-PatchSet: 5 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-CC: Gabe Black Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util: Add a library to parser MAINTAINERS.yaml
ef _load_maintainers_file(cls,
+ path_or_file: Optional[Union[TextIO, str]])
\
+ -> Mapping[str, Any]:
+if path_or_file is None:
+path_or_file = cls.DEFAULT_MAINTAINERS
+
+if isinstance(path_or_file, str):
+with open(path_or_file, 'r') as fin:
+return yaml.load(fin)
+else:
+return yaml.load(path_or_file)
+
+@classmethod
+def _parse_subsystem(cls, tag: str, ydict: Mapping[str, Any]) ->
Subsystem:
+raw_maintainers = ydict.get('maintainers', None)
+maintainers = map(email.utils.parseaddr, raw_maintainers) \
+ if raw_maintainers is not None else []
+status = Status.from_str(ydict.get('status', 'orphaned'))
+return Subsystem(tag, maintainers=maintainers, status=status,
+ description=ydict.get('desc', ''))
+
+def __iter__(self) -> Iterator[Tuple[str, Subsystem]]:
+return iter(self._subsystems.items())
+
+def _main():
+maintainers = Maintainers()
+for tag, subsys in maintainers:
+print(f'{tag}: {subsys.description}')
+print(f' Status: {subsys.status}')
+print(f' Maintainers:')
+for maint in subsys.maintainers:
+print(f'- {maint[0]} <{maint[1]}>')
+print()
+
+if __name__ == '__main__':
+_main()
--
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Gerrit-Owner: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[develop]: misc: Convert MAINTAINERS to YAML
nclair +- Tony Gutierrez +- Steve Reinhardt + +arch: + desc: >- +General architecture-specific components + status: maintained + maintainers: +- Gabe Black + +arch-arm: + status: maintained + maintainers: +- Andreas Sandberg +- Giacomo Travaglini + +arch-gcn3: + status: maintained + maintainers: +- Tony Gutierrez + +arch-mips: + status: orphaned + +arch-power: + status: orphaned + +arch-riscv: + status: maintained + maintainers: +- Alec Roelke + +arch-sparc: + status: maintained + maintainers: +- Gabe Black + +arch-x86: + status: maintained + maintainers: +- Gabe Black + +base: + status: maintained + maintainers: + +configs: + status: maintained + maintainers: +- Jason Lowe-Power + +cpu: + desc: >- +General changes to all CPU models (e.g., BaseCPU) + +cpu-kvm: + status: maintained + maintainers: +- Andreas Sandberg + +cpu-minor: + status: maintained + +cpu-o3: + status: maintained + +cpu-simple: + status: maintained + +dev: + status: maintained + +dev-hsa: + status: maintained + maintainers: +- Tony Gutierrez + +dev-virtio: + status: maintained + maintainers: +- Andreas Sandberg + +dev-arm: + status: maintained + maintainers: +- Andreas Sandberg +- Giacomo Travaglini + +ext: + desc: Components external to gem5 + +fastmodel: + desc: Changes relating to ARM Fast Models + maintainers: +- Gabe Black + +gpu-compute: + maintainers: +- Tony Gutierrez +- Matt Poremba + +learning-gem5: + desc: >- +The code and configs for the Learning gem5 book (see +learning.gem5.com) + maintainers: +- Jason Lowe-Power + +mem: + desc: General memory system (e.g., XBar, Packet) + maintainers: +- Nikos Nikoleris + +mem-cache: + desc: Classic caches and coherence + maintainers: +- Nikos Nikoleris + +mem-garnet: + desc: Garnet subcomponent of Ruby + maintainers: +- Tushar Krishna + +mem-ruby: + desc: Ruby structures and protocols + maintainers: +- Brad Beckmann +- Jason Lowe-Power + +misc: + desc: Anything outside of the other categories + +python: + desc: Python SimObject wrapping and infrastructure + maintainers: +- Andreas Sandberg + +scons: + desc: Build system + maintainers: +- Gabe Black + +sim: + desc: General simulation components + maintainers: +- Jason Lowe-Power + +sim-se: + desc: Syscall emulation + maintainers: +- Brandon Potter + +sim-power: + desc: Power modeling + maintainers: +- Andreas Sandberg + +stats: + desc: Updates to statistics for regressions + +system: + desc: System boot code and related components + +system-arm: + maintainers: +- Andreas Sandberg +- Giacomo Travaglini + +systemc: + desc: Code for the gem5 SystemC implementation and interface + maintainers: +- Gabe Black + +tests: + desc: testing changes (not stats updates for tests. See stats:) + maintainers: +- Bobby Bruce + +util: + maintainers: +- Gabe Black -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/37035 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0 Gerrit-Change-Number: 37035 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Test if binaries can embed the Python interpreter
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36383 )
Change subject: scons: Test if binaries can embed the Python interpreter
..
scons: Test if binaries can embed the Python interpreter
Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.
Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36383
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 33 insertions(+), 3 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 8e7ec34..a057da3 100755
--- a/SConstruct
+++ b/SConstruct
@@ -575,6 +575,27 @@
context.Result(ret)
return ret
+def CheckPythonLib(context):
+context.Message('Checking Python version... ')
+ret = context.TryRun(r"""
+#include
+
+int
+main(int argc, char **argv) {
+pybind11::scoped_interpreter guard{};
+pybind11::exec(
+"import sys\n"
+"vi = sys.version_info\n"
+"sys.stdout.write('%i.%i.%i' % (vi.major, vi.minor,
vi.micro));\n");
+return 0;
+}
+""", extension=".cc")
+context.Result(ret[1] if ret[0] == 1 else 0)
+if ret[0] == 0:
+return None
+else:
+return tuple(map(int, ret[1].split(".")))
+
# Platform-specific configuration. Note again that we assume that all
# builds under a given build root run on the same host platform.
conf = Configure(main,
@@ -582,6 +603,7 @@
log_file = joinpath(build_root, 'scons_config.log'),
custom_tests = {
'CheckMember' : CheckMember,
+'CheckPythonLib' : CheckPythonLib,
})
# Check if we should compile a 64 bit binary on Mac OS X/Darwin
@@ -637,9 +659,6 @@
main['PYTHON_CONFIG'])
print("Info: Using Python config: %s" % (python_config, ))
-if python_config != 'python3-config':
-warning('python3-config could not be found.\n'
-'Future releases of gem5 will drop support for python2.')
py_includes = readCommand([python_config, '--includes'],
exception='').split()
@@ -697,6 +716,17 @@
marshal_env = main.Clone()
marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+py_version = conf.CheckPythonLib()
+if not py_version:
+error("Can't find a working Python installation")
+
+# Found a working Python installation. Check if it meets minimum
+# requirements.
+if py_version[0] < 3 or \
+ (py_version[0] == 3 and py_version[1] < 6):
+error('Python version too old. Version 3.6 or newer is required.')
+elif py_version[0] > 3:
+warning('Python version too new. Python 3 expected.')
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Gerrit-Change-Number: 36383
Gerrit-PatchSet: 4
Gerrit-Owner: Andreas Sandberg
Gerrit-Assignee: Bobby R. Bruce
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Bobby R. Bruce
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Don't check for Python 2
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36535 )
Change subject: scons: Don't check for Python 2
..
scons: Don't check for Python 2
The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.
Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36535
Reviewed-by: Gabe Black
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Daniel Carvalho: Looks good to me, but someone else must approve
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index a057da3..5033344 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,7 @@
('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler
flags', ''),
('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
('PYTHON_CONFIG', 'Python config binary to use',
-
[ 'python3-config', 'python-config', 'python2.7-config', 'python2-config']
+ [ 'python3-config', 'python-config']
),
('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
('BATCH', 'Use batch pool for build and tests', False),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Gerrit-Change-Number: 36535
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg
Gerrit-Assignee: Jason Lowe-Power
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Don't check for Python 2
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36535 )
Change subject: scons: Don't check for Python 2
..
scons: Don't check for Python 2
The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.
Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/SConstruct b/SConstruct
index 3b157f0..8005a98 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,7 @@
('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler
flags', ''),
('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
('PYTHON_CONFIG', 'Python config binary to use',
-
[ 'python3-config', 'python-config', 'python2.7-config', 'python2-config']
+ [ 'python3-config', 'python-config']
),
('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
('BATCH', 'Use batch pool for build and tests', False),
--
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Gerrit-Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Gerrit-Change-Number: 36535
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Test if binaries can embed the Python interpreter
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36383 )
Change subject: scons: Test if binaries can embed the Python interpreter
..
scons: Test if binaries can embed the Python interpreter
Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.
Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg
---
M SConstruct
1 file changed, 37 insertions(+), 3 deletions(-)
diff --git a/SConstruct b/SConstruct
index 8e7ec34..16558d2 100755
--- a/SConstruct
+++ b/SConstruct
@@ -575,6 +575,27 @@
context.Result(ret)
return ret
+def CheckPythonLib(context):
+context.Message('Checking for Python...')
+ret = context.TryRun(r"""
+#include
+
+int
+main(int argc, char **argv) {
+pybind11::scoped_interpreter guard{};
+pybind11::exec(
+"import sys\n"
+"vi = sys.version_info\n"
+"sys.stdout.write('%i.%i.%i' % (vi.major, vi.minor,
vi.micro));\n");
+return 0;
+}
+""", extension=".cc")
+context.Result(ret[1] if ret[0] == 1 else 0)
+if ret[0] == 0:
+return None
+else:
+return tuple((int(x) for x in ret[1].split(".")))
+
# Platform-specific configuration. Note again that we assume that all
# builds under a given build root run on the same host platform.
conf = Configure(main,
@@ -582,6 +603,7 @@
log_file = joinpath(build_root, 'scons_config.log'),
custom_tests = {
'CheckMember' : CheckMember,
+'CheckPythonLib' : CheckPythonLib,
})
# Check if we should compile a 64 bit binary on Mac OS X/Darwin
@@ -637,9 +659,6 @@
main['PYTHON_CONFIG'])
print("Info: Using Python config: %s" % (python_config, ))
-if python_config != 'python3-config':
-warning('python3-config could not be found.\n'
-'Future releases of gem5 will drop support for python2.')
py_includes = readCommand([python_config, '--includes'],
exception='').split()
@@ -697,6 +716,21 @@
marshal_env = main.Clone()
marshal_env.Append(CCFLAGS='$MARSHAL_CCFLAGS_EXTRA')
marshal_env.Append(LINKFLAGS='$MARSHAL_LDFLAGS_EXTRA')
+py_version = conf.CheckPythonLib()
+if not py_version:
+error("Can't find a working Python installation")
+else:
+# Found a working Python installation. Check if it meets minimum
+# requirements.
+if py_version[0] < 2 or \
+ (py_version[0] == 2 and py_version[1] < 7) or \
+ (py_version[0] == 3 and py_version[1] < 6):
+error('Python version too old. '
+ 'At least version Python 2.7 or 3.6 is required.')
+elif py_version[0] == 2:
+warning('Future releases of gem5 will drop support for Python 2.7')
+elif py_version[0] > 3:
+warning('Python version too new. Python 3.x expected.')
# On Solaris you need to use libsocket for socket ops
if not
conf.CheckLibWithHeader(None, 'sys/socket.h', 'C++', 'accept(0,0,0);'):
--
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[gem5-dev] Change in gem5/gem5[develop]: stats: Output new-world stats before legacy stats
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35617 ) Change subject: stats: Output new-world stats before legacy stats .. stats: Output new-world stats before legacy stats Now that global stats have been converted to new-style stats, it's desirable to output them before legacy stats. This ensures that global statistics (e.g., host_seconds) show up first in the stat file. Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260 Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35617 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/m5/stats/__init__.py 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/m5/stats/__init__.py b/src/python/m5/stats/__init__.py index 6c4a42c..1fc6c9c 100644 --- a/src/python/m5/stats/__init__.py +++ b/src/python/m5/stats/__init__.py @@ -345,13 +345,13 @@ for p in reversed(root.path_list()): visitor.endGroup() else: +# New stats starting from root. +dump_group(Root.getInstance()) + # Legacy stats for stat in stats_list: stat.visit(visitor) -# New stats starting from root. -dump_group(Root.getInstance()) - lastDump = 0 # List[SimObject]. global_dump_roots = [] -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35617 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260 Gerrit-Change-Number: 35617 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim, stats: Move global stats to Root
b5a3ca1 --- /dev/null +++ b/src/sim/stats.cc @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2020 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sim/stats.hh" + +#include "sim/root.hh" + +Stats::Formula = rootStats.simSeconds; +Stats::Value = rootStats.simTicks; +Stats::Value = rootStats.simFreq; +Stats::Value = rootStats.hostSeconds; diff --git a/src/sim/stats.hh b/src/sim/stats.hh index 4e17f64..a46539e 100644 --- a/src/sim/stats.hh +++ b/src/sim/stats.hh @@ -31,9 +31,9 @@ #include "base/statistics.hh" -extern Stats::Formula simSeconds; -extern Stats::Value simTicks; -extern Stats::Value simFreq; -extern Stats::Value hostSeconds; +extern Stats::Formula +extern Stats::Value +extern Stats::Value +extern Stats::Value #endif // __SIM_SIM_STATS_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35616 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e Gerrit-Change-Number: 35616 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: stats: Make Stats::Group::mergeStatGroup public
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35615 )
Change subject: stats: Make Stats::Group::mergeStatGroup public
..
stats: Make Stats::Group::mergeStatGroup public
The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.
This change adds some error checking to mergeStatGroup and marks it as
a public method.
Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35615
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/stats/group.cc
M src/base/stats/group.hh
2 files changed, 17 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a76ad4f..f1eda1d 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -47,7 +47,7 @@
namespace Stats {
Group::Group(Group *parent, const char *name)
-: mergedParent(name ? nullptr : parent)
+: mergedParent(nullptr)
{
if (parent && name) {
parent->addStatGroup(name, this);
@@ -152,7 +152,22 @@
void
Group::mergeStatGroup(Group *block)
{
+panic_if(!block, "No stat block provided");
+panic_if(block->mergedParent,
+ "Stat group already merged into another group");
+panic_if(block == this, "Stat group can't merge with itself");
+
+// Track the new stat group
mergedStatGroups.push_back(block);
+
+// We might not have seen stats that were associated with the
+// child group before it was merged, so add them here.
+for (auto : block->stats)
+addStat(s);
+
+// Setup the parent pointer so the child know that it needs to
+// register new stats with the parent.
+block->mergedParent = this;
}
const std::map &
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 985bf61..ef223bc 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -194,7 +194,6 @@
*/
const Info * resolveStat(std::string name) const;
- private:
/**
* Merge the contents (stats & children) of a block to this block.
*
@@ -205,7 +204,7 @@
private:
/** Parent pointer if merged into parent */
-Group *const mergedParent;
+Group *mergedParent;
std::map statGroups;
std::vector mergedStatGroups;
--
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Gerrit-Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Gerrit-Change-Number: 35615
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
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[gem5-dev] Change in gem5/gem5[develop]: stats: Output new-world stats before legacy stats
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/35617 ) Change subject: stats: Output new-world stats before legacy stats .. stats: Output new-world stats before legacy stats Now that global stats have been converted to new-style stats, it's desirable to output them before legacy stats. This ensures that global statistics (e.g., host_seconds) show up first in the stat file. Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260 Signed-off-by: Andreas Sandberg --- M src/python/m5/stats/__init__.py 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/python/m5/stats/__init__.py b/src/python/m5/stats/__init__.py index 6c4a42c..1fc6c9c 100644 --- a/src/python/m5/stats/__init__.py +++ b/src/python/m5/stats/__init__.py @@ -345,13 +345,13 @@ for p in reversed(root.path_list()): visitor.endGroup() else: +# New stats starting from root. +dump_group(Root.getInstance()) + # Legacy stats for stat in stats_list: stat.visit(visitor) -# New stats starting from root. -dump_group(Root.getInstance()) - lastDump = 0 # List[SimObject]. global_dump_roots = [] -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35617 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260 Gerrit-Change-Number: 35617 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim, stats: Move global stats to Root
but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "sim/stats.hh" + +#include "sim/root.hh" + +Stats::Formula = rootStats.simSeconds; +Stats::Value = rootStats.simTicks; +Stats::Value = rootStats.simFreq; +Stats::Value = rootStats.hostSeconds; diff --git a/src/sim/stats.hh b/src/sim/stats.hh index 4e17f64..a46539e 100644 --- a/src/sim/stats.hh +++ b/src/sim/stats.hh @@ -31,9 +31,9 @@ #include "base/statistics.hh" -extern Stats::Formula simSeconds; -extern Stats::Value simTicks; -extern Stats::Value simFreq; -extern Stats::Value hostSeconds; +extern Stats::Formula +extern Stats::Value +extern Stats::Value +extern Stats::Value #endif // __SIM_SIM_STATS_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35616 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e Gerrit-Change-Number: 35616 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: stats: Make Stats::Group::mergeStatGroup public
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35615 )
Change subject: stats: Make Stats::Group::mergeStatGroup public
..
stats: Make Stats::Group::mergeStatGroup public
The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.
This change adds some error checking to mergeStatGroup and marks it as
a public method.
Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg
---
M src/base/stats/group.cc
M src/base/stats/group.hh
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/src/base/stats/group.cc b/src/base/stats/group.cc
index a76ad4f..f1eda1d 100644
--- a/src/base/stats/group.cc
+++ b/src/base/stats/group.cc
@@ -47,7 +47,7 @@
namespace Stats {
Group::Group(Group *parent, const char *name)
-: mergedParent(name ? nullptr : parent)
+: mergedParent(nullptr)
{
if (parent && name) {
parent->addStatGroup(name, this);
@@ -152,7 +152,22 @@
void
Group::mergeStatGroup(Group *block)
{
+panic_if(!block, "No stat block provided");
+panic_if(block->mergedParent,
+ "Stat group already merged into another group");
+panic_if(block == this, "Stat group can't merge with itself");
+
+// Track the new stat group
mergedStatGroups.push_back(block);
+
+// We might not have seen stats that were associated with the
+// child group before it was merged, so add them here.
+for (auto : block->stats)
+addStat(s);
+
+// Setup the parent pointer so the child know that it needs to
+// register new stats with the parent.
+block->mergedParent = this;
}
const std::map &
diff --git a/src/base/stats/group.hh b/src/base/stats/group.hh
index 985bf61..ef223bc 100644
--- a/src/base/stats/group.hh
+++ b/src/base/stats/group.hh
@@ -194,7 +194,6 @@
*/
const Info * resolveStat(std::string name) const;
- private:
/**
* Merge the contents (stats & children) of a block to this block.
*
@@ -205,7 +204,7 @@
private:
/** Parent pointer if merged into parent */
-Group *const mergedParent;
+Group *mergedParent;
std::map statGroups;
std::vector mergedStatGroups;
--
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Gerrit-Change-Number: 35615
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Gerrit-Owner: Andreas Sandberg
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[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL
seCPU::numSimulatedOps);
+#else
+simInsts.functor([] { return 0; });
+simOps.functor([] { return 0; });
+#endif
+
simSeconds
.name("sim_seconds")
.desc("Number of seconds simulated")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index cb412a8..cbc30a9 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -50,12 +50,15 @@
#include "base/loader/symtab.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "config/use_kvm.hh"
#if USE_KVM
#include "cpu/kvm/base.hh"
#include "cpu/kvm/vm.hh"
#endif
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/Quiesce.hh"
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 7d77c48..fc93b85 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -52,7 +52,6 @@
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_requestor.hh"
--
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Gerrit-Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Gerrit-Change-Number: 34236
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stats: Move global CPU stats to BaseCPU
space Stats {
@@ -97,42 +94,14 @@
struct Global
{
-Stats::Formula hostInstRate;
-Stats::Formula hostOpRate;
Stats::Formula hostTickRate;
Stats::Value hostMemory;
-Stats::Value hostSeconds;
-
-Stats::Value simInsts;
-Stats::Value simOps;
Global();
};
Global::Global()
{
-simInsts
-.name("sim_insts")
-.desc("Number of instructions simulated")
-.precision(0)
-.prereq(simInsts)
-;
-
-simOps
-.name("sim_ops")
-.desc("Number of ops (including micro ops) simulated")
-.precision(0)
-.prereq(simOps)
-;
-
-#if THE_ISA != NULL_ISA
-simInsts.functor(BaseCPU::numSimulatedInsts);
-simOps.functor(BaseCPU::numSimulatedOps);
-#else
-simInsts.functor([] { return 0; });
-simOps.functor([] { return 0; });
-#endif
-
simSeconds
.name("sim_seconds")
.desc("Number of seconds simulated")
@@ -157,20 +126,6 @@
"(restored from checkpoints and never reset)")
;
-hostInstRate
-.name("host_inst_rate")
-.desc("Simulator instruction rate (inst/s)")
-.precision(0)
-.prereq(simInsts)
-;
-
-hostOpRate
-.name("host_op_rate")
-.desc("Simulator op (including micro ops) rate (op/s)")
-.precision(0)
-.prereq(simOps)
-;
-
hostMemory
.functor(memUsage)
.name("host_mem_usage")
@@ -192,8 +147,6 @@
;
simSeconds = simTicks / simFreq;
-hostInstRate = simInsts / hostSeconds;
-hostOpRate = simOps / hostSeconds;
hostTickRate = simTicks / hostSeconds;
registerResetCallback([]() {
diff --git a/src/sim/stats.hh b/src/sim/stats.hh
index ed68af6..4e17f64 100644
--- a/src/sim/stats.hh
+++ b/src/sim/stats.hh
@@ -34,5 +34,6 @@
extern Stats::Formula simSeconds;
extern Stats::Value simTicks;
extern Stats::Value simFreq;
+extern Stats::Value hostSeconds;
#endif // __SIM_SIM_STATS_HH__
--
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Gerrit-Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76
Gerrit-Change-Number: 34395
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: stats: Move global CPU stats to BaseCPU
prereq(simOps)
-;
-
-#if THE_ISA != NULL_ISA
-simInsts.functor(BaseCPU::numSimulatedInsts);
-simOps.functor(BaseCPU::numSimulatedOps);
-#else
-simInsts.functor([] { return 0; });
-simOps.functor([] { return 0; });
-#endif
-
simSeconds
.name("sim_seconds")
.desc("Number of seconds simulated")
@@ -157,20 +130,6 @@
"(restored from checkpoints and never reset)")
;
-hostInstRate
-.name("host_inst_rate")
-.desc("Simulator instruction rate (inst/s)")
-.precision(0)
-.prereq(simInsts)
-;
-
-hostOpRate
-.name("host_op_rate")
-.desc("Simulator op (including micro ops) rate (op/s)")
-.precision(0)
-.prereq(simOps)
-;
-
hostMemory
.functor(memUsage)
.name("host_mem_usage")
@@ -192,8 +151,6 @@
;
simSeconds = simTicks / simFreq;
-hostInstRate = simInsts / hostSeconds;
-hostOpRate = simOps / hostSeconds;
hostTickRate = simTicks / hostSeconds;
registerResetCallback([]() {
diff --git a/src/sim/stats.hh b/src/sim/stats.hh
index ed68af6..4e17f64 100644
--- a/src/sim/stats.hh
+++ b/src/sim/stats.hh
@@ -34,5 +34,6 @@
extern Stats::Formula simSeconds;
extern Stats::Value simTicks;
extern Stats::Value simFreq;
+extern Stats::Value hostSeconds;
#endif // __SIM_SIM_STATS_HH__
--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in VirtIO devices
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33296 )
Change subject: dev: Use the new ByteOrder param type in VirtIO devices
..
dev: Use the new ByteOrder param type in VirtIO devices
VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).
Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33296
Tested-by: kokoro
Reviewed-by: Gabe Black
---
M src/dev/virtio/VirtIO.py
M src/dev/virtio/base.cc
2 files changed, 3 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index bebacad..ed8cffa 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -50,6 +50,7 @@
subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")
system = Param.System(Parent.any, "system object")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")
class VirtIODummyDevice(VirtIODeviceBase):
type = 'VirtIODummyDevice'
diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 6b4fe0a..84841af 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -37,10 +37,10 @@
#include "dev/virtio/base.hh"
+#include "base/trace.hh"
#include "debug/VIO.hh"
#include "params/VirtIODeviceBase.hh"
#include "params/VirtIODummyDevice.hh"
-#include "sim/system.hh"
VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
@@ -326,7 +326,7 @@
size_t config_size, FeatureBits
features)
: SimObject(params),
guestFeatures(0),
- byteOrder(params->system->getGuestByteOrder()),
+ byteOrder(params->byte_order),
deviceId(id), configSize(config_size), deviceFeatures(features),
_deviceStatus(0), _queueSelect(0)
{
--
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Gerrit-Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Gerrit-Change-Number: 33296
Gerrit-PatchSet: 7
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in SimpleUart
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33295 )
Change subject: dev: Use the new ByteOrder param type in SimpleUart
..
dev: Use the new ByteOrder param type in SimpleUart
Use the new ByteOrder param type in SimpleUart. The default value is
currently little endian. However, it is expected that most users of
this device will use single-byte accesses which aren't affected by
endianness.
Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33295
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/dev/serial/Uart.py
M src/dev/serial/simple.cc
2 files changed, 2 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 97efcdd..7955d69 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -52,7 +52,7 @@
class SimpleUart(Uart):
type = 'SimpleUart'
cxx_header = "dev/serial/simple.hh"
-big_endian = Param.Bool(False, "Is the device Big Endian?")
+byte_order = Param.ByteOrder("little", "Device byte order")
pio_size = Param.Addr(0x4, "Size of address range")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
"received on the UART")
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
index 97018ab..339d6b9 100644
--- a/src/dev/serial/simple.cc
+++ b/src/dev/serial/simple.cc
@@ -43,9 +43,7 @@
#include "sim/sim_exit.hh"
SimpleUart::SimpleUart(const SimpleUartParams *p)
-: Uart(p, p->pio_size),
- byteOrder(p->big_endian ? ByteOrder::big : ByteOrder::little),
- endOnEOT(p->end_on_eot)
+: Uart(p, p->pio_size), byteOrder(p->byte_order),
endOnEOT(p->end_on_eot)
{
}
--
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Gerrit-Change-Number: 33295
Gerrit-PatchSet: 6
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base, sim, mem, arch: Remove the dummy CPU in NULL
ht holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_NULL_CPU_DUMMY_HH__
-#define __ARCH_NULL_CPU_DUMMY_HH__
-
-#include "sim/core.hh"
-
-class BaseCPU
-{
- public:
-static int numSimulatedInsts() { return 0; }
-static int numSimulatedOps() { return 0; }
-static void wakeup(ThreadID tid) { ; }
-};
-
-#endif // __ARCH_NULL_CPU_DUMMY_HH__
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 3ef5519..82bec20 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -48,7 +48,7 @@
// and if so stop here
#include "config/the_isa.hh"
#if THE_ISA == NULL_ISA
-#include "arch/null/cpu_dummy.hh"
+#error Including BaseCPU in a system without CPU support
#else
#include "arch/generic/interrupts.hh"
#include "base/statistics.hh"
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index f1e9dba..b53e231 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -45,7 +45,6 @@
#include "arch/locked_mem.hh"
#include "base/loader/memory_image.hh"
#include "base/loader/object_file.hh"
-#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 4e484e5..68cc1ed 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -48,7 +48,6 @@
#include
#include "base/intmath.hh"
-#include "cpu/base.hh"
#include "mem/cache/base.hh"
#include "params/BasePrefetcher.hh"
#include "sim/system.hh"
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 9464c0d..0f5ae7e 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -53,7 +53,10 @@
#include "base/hostinfo.hh"
#include "base/statistics.hh"
#include "base/time.hh"
+#include "config/the_isa.hh"
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "sim/global_event.hh"
using namespace std;
@@ -108,6 +111,7 @@
Global::Global()
{
+#if THE_ISA != NULL_ISA
simInsts
.functor(BaseCPU::numSimulatedInsts)
.name("sim_insts")
@@ -123,6 +127,7 @@
.precision(0)
.prereq(simOps)
;
+#endif
simSeconds
.name("sim_seconds")
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 8185f13..da454b0 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -50,12 +50,15 @@
#include "base/loader/symtab.hh"
#include "base/str.hh"
#include "base/trace.hh"
+#include "config/the_isa.hh"
#include "config/use_kvm.hh"
#if USE_KVM
#include "cpu/kvm/base.hh"
#include "cpu/kvm/vm.hh"
#endif
+#if THE_ISA != NULL_ISA
#include "cpu/base.hh"
+#endif
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "debug/Quiesce.hh"
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8b31b2f..5e7e688 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -52,7 +52,6 @@
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "cpu/base.hh"
#include "cpu/pc_event.hh"
#include "enums/MemoryMode.hh"
#include "mem/mem_master.hh"
--
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Gerrit-Change-Number: 34236
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )
Change subject: sim: Expose the system's byte order as a param
..
sim: Expose the system's byte order as a param
There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.
Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro
Reviewed-by: Gabe Black
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/System.py b/src/sim/System.py
index dcef74b..caf32fb 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -48,6 +48,11 @@
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
'atomic_noncaching']
+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+default_byte_order = 'big'
+else:
+default_byte_order = 'little'
+
class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
@@ -84,6 +89,9 @@
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
+byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
exit_on_work_items = Param.Bool(False, "Exit from the simulation loop
when "
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 8e2c472..8b31b2f 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
ByteOrder
getGuestByteOrder() const
{
-#if THE_ISA != NULL_ISA
-return TheISA::GuestByteOrder;
-#else
-panic("The NULL ISA has no endianness.");
-#endif
+return _params->byte_order;
}
/**
--
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Gerrit-Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Gerrit-Change-Number: 33175
Gerrit-PatchSet: 5
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup debug flags API
-bool status() const { return _tracing; }
-operator bool() const { return _tracing; }
-bool operator!() const { return !_tracing; }
+bool status() const override { return _tracing; }
-void enable() { _status = true; sync(); }
-void disable() { _status = false; sync(); }
-
-void sync() { _tracing = _active && _status; }
-
-static void enableAll();
-static void disableAll();
+void enable() override { _status = true; sync(); }
+void disable() override { _status = false; sync(); }
};
class CompoundFlag : public Flag
@@ -97,10 +112,11 @@
{
}
-std::vector kids() { return _kids; }
+const std::vector () const { return _kids; }
-void enable();
-void disable();
+void enable() override;
+void disable() override;
+bool status() const override;
};
typedef std::map FlagsMap;
diff --git a/src/base/trace.cc b/src/base/trace.cc
index 8f97a94..ed6fbd2 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -91,13 +91,13 @@
void
enable()
{
-Debug::SimpleFlag::enableAll();
+Debug::Flag::globalEnable();
}
void
disable()
{
-Debug::SimpleFlag::disableAll();
+Debug::Flag::globalDisable();
}
ObjectMatch ignore;
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index a3d5e35..6b45b16 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -34,24 +34,18 @@
from m5.util import printList
def help():
+sorted_flags = sorted(flags.items(), key=lambda kv: kv[0])
+
print("Base Flags:")
-for name in sorted(flags):
-if name == 'All':
-continue
-flag = flags[name]
-children = [c for c in flag.kids() ]
-if not children:
-print("%s: %s" % (name, flag.desc()))
+for name, flag in filter(lambda kv: not isinstance(kv[1],
CompoundFlag),
+ sorted_flags):
+print("%s: %s" % (name, flag.desc))
print()
print("Compound Flags:")
-for name in sorted(flags):
-if name == 'All':
-continue
-flag = flags[name]
-children = [c for c in flag.kids() ]
-if children:
-print("%s: %s" % (name, flag.desc()))
-printList([ c.name() for c in children ], indent=8)
+for name, flag in filter(lambda kv: isinstance(kv[1], CompoundFlag),
+ sorted_flags):
+print("%s: %s" % (name, flag.desc))
+printList([ c.name for c in flag.kids() ], indent=8)
print()
class AllFlags(Mapping):
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 766ccea..ed2942b 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -94,16 +94,16 @@
py::class_ c_flag(m_debug, "Flag");
c_flag
-.def("name", ::Flag::name)
-.def("desc", ::Flag::desc)
-.def("kids", ::Flag::kids)
+.def_property_readonly("name", ::Flag::name)
+.def_property_readonly("desc", ::Flag::desc)
.def("enable", ::Flag::enable)
.def("disable", ::Flag::disable)
-.def("sync", ::Flag::sync)
;
py::class_(m_debug, "SimpleFlag", c_flag);
-py::class_(m_debug, "CompoundFlag", c_flag);
+py::class_(m_debug, "CompoundFlag", c_flag)
+.def("kids", ::CompoundFlag::kids)
+;
py::module m_trace = m_native.def_submodule("trace");
--
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Gerrit-Change-Number: 34118
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify arch enum generation
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )
Change subject: scons: Simplify arch enum generation
..
scons: Simplify arch enum generation
C++ allows a trailing comma after the last item in an enum, so there
is no need for a special case.
Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34116
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/SConscript
1 file changed, 4 insertions(+), 10 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index 4b6db44..9f82bdc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,11 +645,8 @@
# create an enum for any run-time determination of the ISA, we
# reuse the same name as the namespaces
code('enum class Arch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code(' $0 = $1', namespace(isa), define(isa))
-else:
-code(' $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code(' $0 = $1,', namespace(isa), define(isa))
code('};')
code('''
@@ -690,11 +687,8 @@
# create an enum for any run-time determination of the ISA, we
# reuse the same name as the namespaces
code('enum class GPUArch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code(' $0 = $1', namespace(isa), define(isa))
-else:
-code(' $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code(' $0 = $1,', namespace(isa), define(isa))
code('};')
code('''
--
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Gerrit-Change-Number: 34116
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove unused Debug::All flag
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )
Change subject: base: Remove unused Debug::All flag
..
base: Remove unused Debug::All flag
The Debug::All flag doesn't seem to be used. Remove it.
Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34117
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 0 insertions(+), 31 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/debug.cc b/src/base/debug.cc
index b165f64..47febd0 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -125,35 +125,6 @@
k->disable();
}
-struct AllFlags : public Flag
-{
-AllFlags()
-: Flag("All", "All Flags")
-{}
-
-void
-enable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->enable();
-}
-
-void
-disable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->disable();
-}
-};
-
-AllFlags theAllFlags;
-Flag *const All =
bool
changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 479a830..1d35be0 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -108,8 +108,6 @@
Flag *findFlag(const std::string );
-extern Flag *const All;
-
bool changeFlag(const char *s, bool value);
} // namespace Debug
--
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Gerrit-Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Gerrit-Change-Number: 34117
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Daniel Carvalho
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unused debug APIs
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )
Change subject: python: Remove unused debug APIs
..
python: Remove unused debug APIs
The following APIs are not exported from the _m5 namespace and not
used by any of the debug glue code:
* m5.debug.findFlag
* m5.debug.setDebugFlag
* m5.debug.clearDebugFlag
* m5.debug.dumpDebugFlags
All of them have a clean Python interface where flags are exported
using the m5.debug.flags dictionary. There is also an m5.debug.help
function that lists the available debug flags.
Remove the unused APIs to avoid confusion.
Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34120
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/pybind11/debug.cc
1 file changed, 0 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 69c497c..84673f1 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -83,10 +83,6 @@
m_debug
.def("getAllFlagsVersion", []() { return Debug::allFlagsVersion; })
.def("allFlags", ::allFlags,
py::return_value_policy::reference)
-.def("findFlag", ::findFlag)
-.def("setDebugFlag", )
-.def("clearDebugFlag", )
-.def("dumpDebugFlags", )
.def("schedBreak", )
.def("setRemoteGDBPort", )
--
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Gerrit-Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Gerrit-Change-Number: 34120
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup Debug::CompoundFlag
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )
Change subject: base: Cleanup Debug::CompoundFlag
..
base: Cleanup Debug::CompoundFlag
Compound flags are currently constructed using a constructor with a
finite set of arguments that default to nullptr that refer to child
flags. C++11 introduces two cleaner ways to achieve the same thing,
variadic templates and initializer_list. Use an initializer list to
pass dependent flags.
Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34115
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/SConscript
M src/base/debug.hh
2 files changed, 9 insertions(+), 29 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/SConscript b/src/SConscript
index d9cde28..4b6db44 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1071,15 +1071,12 @@
if not compound:
code('SimpleFlag $name("$name", "$desc");')
else:
-comp_code('CompoundFlag $name("$name", "$desc",')
+comp_code('CompoundFlag $name("$name", "$desc", {')
comp_code.indent()
-last = len(compound) - 1
-for i,flag in enumerate(compound):
-if i != last:
-comp_code('&$flag,')
-else:
-comp_code('&$flag);')
+for flag in compound:
+comp_code('&$flag,')
comp_code.dedent()
+comp_code('});')
code.append(comp_code)
code()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7c9834c..479a830 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -30,6 +30,7 @@
#ifndef __BASE_DEBUG_HH__
#define __BASE_DEBUG_HH__
+#include
#include
#include
#include
@@ -87,31 +88,13 @@
protected:
std::vector _kids;
-void
-addFlag(Flag *f)
-{
-if (f != nullptr)
-_kids.push_back(f);
-}
-
public:
+template
CompoundFlag(const char *name, const char *desc,
-Flag *f00 = nullptr, Flag *f01 = nullptr,
-Flag *f02 = nullptr, Flag *f03 = nullptr,
-Flag *f04 = nullptr, Flag *f05 = nullptr,
-Flag *f06 = nullptr, Flag *f07 = nullptr,
-Flag *f08 = nullptr, Flag *f09 = nullptr,
-Flag *f10 = nullptr, Flag *f11 = nullptr,
-Flag *f12 = nullptr, Flag *f13 = nullptr,
-Flag *f14 = nullptr, Flag *f15 = nullptr,
-Flag *f16 = nullptr, Flag *f17 = nullptr,
-Flag *f18 = nullptr, Flag *f19 = nullptr)
-: Flag(name, desc)
+ std::initializer_list flags)
+: Flag(name, desc),
+ _kids(flags)
{
-addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03);
addFlag(f04);
-addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08);
addFlag(f09);
-addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13);
addFlag(f14);
-addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);
addFlag(f19);
}
std::vector kids() { return _kids; }
--
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Gerrit-Change-Number: 34115
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Assignee: Bobby R. Bruce
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
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Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Add the ability to check if a debug flag has been enabled
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )
Change subject: python: Add the ability to check if a debug flag has been
enabled
..
python: Add the ability to check if a debug flag has been enabled
There is currently no Python API to check if a debug flag is
enabled. Add a new status property that can be read or set to control
the status of a flag. The stat of a flag can also be queried by
converting it to a bool.
For example:
m5.debug.flags["XBar"].status = True
if m5.debug.flags["XBar"]:
print("XBar debugging is on")
Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34119
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/pybind11/debug.cc
1 file changed, 14 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index ed2942b..69c497c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -98,6 +98,20 @@
.def_property_readonly("desc", ::Flag::desc)
.def("enable", ::Flag::enable)
.def("disable", ::Flag::disable)
+.def_property("status",
+ [](const Debug::Flag *flag) {
+ return flag->status();
+ },
+ [](Debug::Flag *flag, bool state) {
+ if (state) {
+ flag->enable();
+ } else {
+ flag->disable();
+ }
+ })
+.def("__bool__", [](const Debug::Flag *flag) {
+return flag->status();
+})
;
py::class_(m_debug, "SimpleFlag", c_flag);
--
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Gerrit-Change-Number: 34119
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unused debug APIs
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34120 )
Change subject: python: Remove unused debug APIs
..
python: Remove unused debug APIs
The following APIs are not exported from the _m5 namespace and not
used by any of the debug glue code:
* m5.debug.findFlag
* m5.debug.setDebugFlag
* m5.debug.clearDebugFlag
* m5.debug.dumpDebugFlags
All of them have a clean Python interface where flags are exported
using the m5.debug.flags dictionary. There is also an m5.debug.help
function that lists the available debug flags.
Remove the unused APIs to avoid confusion.
Change-Id: I74738451eb5874f83b135adaccd30a0c6b478996
Signed-off-by: Andreas Sandberg
---
M src/python/pybind11/debug.cc
1 file changed, 0 insertions(+), 4 deletions(-)
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 69c497c..84673f1 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -83,10 +83,6 @@
m_debug
.def("getAllFlagsVersion", []() { return Debug::allFlagsVersion; })
.def("allFlags", ::allFlags,
py::return_value_policy::reference)
-.def("findFlag", ::findFlag)
-.def("setDebugFlag", )
-.def("clearDebugFlag", )
-.def("dumpDebugFlags", )
.def("schedBreak", )
.def("setRemoteGDBPort", )
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Add the ability to check if a debug flag has been enabled
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34119 )
Change subject: python: Add the ability to check if a debug flag has been
enabled
..
python: Add the ability to check if a debug flag has been enabled
There is currently no Python API to check if a debug flag is
enabled. Add a new status property that can be read or set to control
the status of a flag. The stat of a flag can also be queried by
converting it to a bool.
For example:
m5.debug.flags["XBar"].status = True
if m5.debug.flags["XBar"]:
print("XBar debugging is on")
Change-Id: I5a50c39ced182ab44e18c061c463d7d9c41ef186
Signed-off-by: Andreas Sandberg
---
M src/python/pybind11/debug.cc
1 file changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index ed2942b..69c497c 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -98,6 +98,20 @@
.def_property_readonly("desc", ::Flag::desc)
.def("enable", ::Flag::enable)
.def("disable", ::Flag::disable)
+.def_property("status",
+ [](const Debug::Flag *flag) {
+ return flag->status();
+ },
+ [](Debug::Flag *flag, bool state) {
+ if (state) {
+ flag->enable();
+ } else {
+ flag->disable();
+ }
+ })
+.def("__bool__", [](const Debug::Flag *flag) {
+return flag->status();
+})
;
py::class_(m_debug, "SimpleFlag", c_flag);
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup debug flags API
void disable() { _status = false; sync(); }
-
-void sync() { _tracing = _active && _status; }
-
-static void enableAll();
-static void disableAll();
+void enable() override { _status = true; sync(); }
+void disable() override { _status = false; sync(); }
};
class CompoundFlag : public Flag
@@ -97,10 +112,11 @@
{
}
-std::vector kids() { return _kids; }
+const std::vector () const { return _kids; }
-void enable();
-void disable();
+void enable() override;
+void disable() override;
+bool status() const override;
};
typedef std::map FlagsMap;
diff --git a/src/base/trace.cc b/src/base/trace.cc
index 8f97a94..ed6fbd2 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -91,13 +91,13 @@
void
enable()
{
-Debug::SimpleFlag::enableAll();
+Debug::Flag::globalEnable();
}
void
disable()
{
-Debug::SimpleFlag::disableAll();
+Debug::Flag::globalDisable();
}
ObjectMatch ignore;
diff --git a/src/python/m5/debug.py b/src/python/m5/debug.py
index a3d5e35..6b45b16 100644
--- a/src/python/m5/debug.py
+++ b/src/python/m5/debug.py
@@ -34,24 +34,18 @@
from m5.util import printList
def help():
+sorted_flags = sorted(flags.items(), key=lambda kv: kv[0])
+
print("Base Flags:")
-for name in sorted(flags):
-if name == 'All':
-continue
-flag = flags[name]
-children = [c for c in flag.kids() ]
-if not children:
-print("%s: %s" % (name, flag.desc()))
+for name, flag in filter(lambda kv: not isinstance(kv[1],
CompoundFlag),
+ sorted_flags):
+print("%s: %s" % (name, flag.desc))
print()
print("Compound Flags:")
-for name in sorted(flags):
-if name == 'All':
-continue
-flag = flags[name]
-children = [c for c in flag.kids() ]
-if children:
-print("%s: %s" % (name, flag.desc()))
-printList([ c.name() for c in children ], indent=8)
+for name, flag in filter(lambda kv: isinstance(kv[1], CompoundFlag),
+ sorted_flags):
+print("%s: %s" % (name, flag.desc))
+printList([ c.name for c in flag.kids() ], indent=8)
print()
class AllFlags(Mapping):
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 766ccea..ed2942b 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -94,16 +94,16 @@
py::class_ c_flag(m_debug, "Flag");
c_flag
-.def("name", ::Flag::name)
-.def("desc", ::Flag::desc)
-.def("kids", ::Flag::kids)
+.def_property_readonly("name", ::Flag::name)
+.def_property_readonly("desc", ::Flag::desc)
.def("enable", ::Flag::enable)
.def("disable", ::Flag::disable)
-.def("sync", ::Flag::sync)
;
py::class_(m_debug, "SimpleFlag", c_flag);
-py::class_(m_debug, "CompoundFlag", c_flag);
+py::class_(m_debug, "CompoundFlag", c_flag)
+.def("kids", ::CompoundFlag::kids)
+;
py::module m_trace = m_native.def_submodule("trace");
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove unused Debug::All flag
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34117 )
Change subject: base: Remove unused Debug::All flag
..
base: Remove unused Debug::All flag
The Debug::All flag doesn't seem to be used. Remove it.
Change-Id: I3d6ad1b2f61a2a0a5c52cbc6d520112855946007
Signed-off-by: Andreas Sandberg
---
M src/base/debug.cc
M src/base/debug.hh
2 files changed, 0 insertions(+), 31 deletions(-)
diff --git a/src/base/debug.cc b/src/base/debug.cc
index b165f64..47febd0 100644
--- a/src/base/debug.cc
+++ b/src/base/debug.cc
@@ -125,35 +125,6 @@
k->disable();
}
-struct AllFlags : public Flag
-{
-AllFlags()
-: Flag("All", "All Flags")
-{}
-
-void
-enable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->enable();
-}
-
-void
-disable()
-{
-FlagsMap::iterator i = allFlags().begin();
-FlagsMap::iterator end = allFlags().end();
-for (; i != end; ++i)
-if (i->second != this)
-i->second->disable();
-}
-};
-
-AllFlags theAllFlags;
-Flag *const All =
bool
changeFlag(const char *s, bool value)
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 479a830..1d35be0 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -108,8 +108,6 @@
Flag *findFlag(const std::string );
-extern Flag *const All;
-
bool changeFlag(const char *s, bool value);
} // namespace Debug
--
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[gem5-dev] Change in gem5/gem5[develop]: scons: Simplify arch enum generation
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34116 )
Change subject: scons: Simplify arch enum generation
..
scons: Simplify arch enum generation
C++ allows a trailing comma after the last item in an enum, so there
is no need for a special case.
Change-Id: I6ead36b4a8562b4a7a5aec88e4f6390182eedf56
Signed-off-by: Andreas Sandberg
---
M src/SConscript
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index 4b6db44..9f82bdc 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -645,11 +645,8 @@
# create an enum for any run-time determination of the ISA, we
# reuse the same name as the namespaces
code('enum class Arch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code(' $0 = $1', namespace(isa), define(isa))
-else:
-code(' $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code(' $0 = $1,', namespace(isa), define(isa))
code('};')
code('''
@@ -690,11 +687,8 @@
# create an enum for any run-time determination of the ISA, we
# reuse the same name as the namespaces
code('enum class GPUArch {')
-for i,isa in enumerate(isas):
-if i + 1 == len(isas):
-code(' $0 = $1', namespace(isa), define(isa))
-else:
-code(' $0 = $1,', namespace(isa), define(isa))
+for isa in isas:
+code(' $0 = $1,', namespace(isa), define(isa))
code('};')
code('''
--
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[gem5-dev] Change in gem5/gem5[develop]: base: Cleanup Debug::CompoundFlag
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34115 )
Change subject: base: Cleanup Debug::CompoundFlag
..
base: Cleanup Debug::CompoundFlag
Compound flags are currently constructed using a constructor with a
finite set of arguments that default to nullptr that refer to child
flags. C++11 introduces two cleaner ways to achieve the same thing,
variadic templates and initializer_list. Use an initializer list to
pass dependent flags.
Change-Id: Iadcd04986ab20efccfae9b92b26c079b9612262e
Signed-off-by: Andreas Sandberg
---
M src/SConscript
M src/base/debug.hh
2 files changed, 9 insertions(+), 29 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index d9cde28..4b6db44 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -1071,15 +1071,12 @@
if not compound:
code('SimpleFlag $name("$name", "$desc");')
else:
-comp_code('CompoundFlag $name("$name", "$desc",')
+comp_code('CompoundFlag $name("$name", "$desc", {')
comp_code.indent()
-last = len(compound) - 1
-for i,flag in enumerate(compound):
-if i != last:
-comp_code('&$flag,')
-else:
-comp_code('&$flag);')
+for flag in compound:
+comp_code('&$flag,')
comp_code.dedent()
+comp_code('});')
code.append(comp_code)
code()
diff --git a/src/base/debug.hh b/src/base/debug.hh
index 7c9834c..479a830 100644
--- a/src/base/debug.hh
+++ b/src/base/debug.hh
@@ -30,6 +30,7 @@
#ifndef __BASE_DEBUG_HH__
#define __BASE_DEBUG_HH__
+#include
#include
#include
#include
@@ -87,31 +88,13 @@
protected:
std::vector _kids;
-void
-addFlag(Flag *f)
-{
-if (f != nullptr)
-_kids.push_back(f);
-}
-
public:
+template
CompoundFlag(const char *name, const char *desc,
-Flag *f00 = nullptr, Flag *f01 = nullptr,
-Flag *f02 = nullptr, Flag *f03 = nullptr,
-Flag *f04 = nullptr, Flag *f05 = nullptr,
-Flag *f06 = nullptr, Flag *f07 = nullptr,
-Flag *f08 = nullptr, Flag *f09 = nullptr,
-Flag *f10 = nullptr, Flag *f11 = nullptr,
-Flag *f12 = nullptr, Flag *f13 = nullptr,
-Flag *f14 = nullptr, Flag *f15 = nullptr,
-Flag *f16 = nullptr, Flag *f17 = nullptr,
-Flag *f18 = nullptr, Flag *f19 = nullptr)
-: Flag(name, desc)
+ std::initializer_list flags)
+: Flag(name, desc),
+ _kids(flags)
{
-addFlag(f00); addFlag(f01); addFlag(f02); addFlag(f03);
addFlag(f04);
-addFlag(f05); addFlag(f06); addFlag(f07); addFlag(f08);
addFlag(f09);
-addFlag(f10); addFlag(f11); addFlag(f12); addFlag(f13);
addFlag(f14);
-addFlag(f15); addFlag(f16); addFlag(f17); addFlag(f18);
addFlag(f19);
}
std::vector kids() { return _kids; }
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Add support for introspecting scalar stats
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/33176 )
Change subject: python: Add support for introspecting scalar stats
..
python: Add support for introspecting scalar stats
This change adds a wrapper for the ScalarInfo stat type to enable
introspection of scalar stats from Python. Due to the slightly
confusing use of proxy objects in the stat system, PyBind11 fails to
automatically cast to the right wrapper type. This is worked around in
the by explicitly casting to the relevant type's Python wrapper.
To make the interface more Python-friendly, this change also changes
the semantics of resolveStat to raise an exception if the stat can't
be found.
Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33176
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/pybind11/stats.cc
1 file changed, 46 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1149eba..b146aa3 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -54,6 +54,25 @@
namespace py = pybind11;
+static const py::object
+cast_stat_info(const Stats::Info *info)
+{
+/* PyBind11 gets confused by the InfoProxy magic, so we need to
+ * explicitly cast to the right wrapper type. */
+
+#define TRY_CAST(T) do {\
+auto _stat = dynamic_cast(info); \
+if (_stat) \
+return py::cast(_stat); \
+} while (0)
+
+TRY_CAST(Stats::ScalarInfo);
+
+return py::cast(info);
+
+#undef TRY_CAST
+}
+
namespace Stats {
void
@@ -120,14 +139,39 @@
.def("visit", ::Info::visit)
;
+py::class_>(
+ m, "ScalarInfo")
+.def("value", ::ScalarInfo::value)
+.def("result", ::ScalarInfo::result)
+.def("total", ::ScalarInfo::total)
+;
+
py::class_>(
m, "Group")
.def("regStats", ::Group::regStats)
.def("resetStats", ::Group::resetStats)
.def("preDumpStats", ::Group::preDumpStats)
-.def("getStats", ::Group::getStats)
+.def("getStats", [](const Stats::Group )
+ -> std::vector {
+
+ auto stats = self.getStats();
+std::vector py_stats;
+py_stats.reserve(stats.size());
+std::transform(stats.begin(), stats.end(),
+ std::back_inserter(py_stats),
+ cast_stat_info);
+return py_stats;
+})
.def("getStatGroups", ::Group::getStatGroups)
.def("addStatGroup", ::Group::addStatGroup)
-.def("resolveStat", ::Group::resolveStat)
+.def("resolveStat", [](const Stats::Group ,
+ const std::string ) -> py::object {
+ const Stats::Info *stat = self.resolveStat(name);
+ if (!stat)
+ throw pybind11::key_error("Unknown stat name");
+
+ return cast_stat_info(stat);
+ })
;
}
--
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Gerrit-Change-Number: 33176
Gerrit-PatchSet: 3
Gerrit-Owner: Andreas Sandberg
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in VirtIO devices
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33296 )
Change subject: dev: Use the new ByteOrder param type in VirtIO devices
..
dev: Use the new ByteOrder param type in VirtIO devices
VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).
Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg
---
M src/dev/virtio/VirtIO.py
M src/dev/virtio/base.cc
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index bebacad..ed8cffa 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -50,6 +50,7 @@
subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")
system = Param.System(Parent.any, "system object")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")
class VirtIODummyDevice(VirtIODeviceBase):
type = 'VirtIODummyDevice'
diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 6b4fe0a..f991625 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -40,7 +40,6 @@
#include "debug/VIO.hh"
#include "params/VirtIODeviceBase.hh"
#include "params/VirtIODummyDevice.hh"
-#include "sim/system.hh"
VirtDescriptor::VirtDescriptor(PortProxy &_memProxy, ByteOrder bo,
VirtQueue &_queue, Index descIndex)
@@ -326,7 +325,7 @@
size_t config_size, FeatureBits
features)
: SimObject(params),
guestFeatures(0),
- byteOrder(params->system->getGuestByteOrder()),
+ byteOrder(params->byte_order),
deviceId(id), configSize(config_size), deviceFeatures(features),
_deviceStatus(0), _queueSelect(0)
{
--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Use the new ByteOrder param type in SimpleUart
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33295 )
Change subject: dev: Use the new ByteOrder param type in SimpleUart
..
dev: Use the new ByteOrder param type in SimpleUart
Use the new ByteOrder param type in SimpleUart. The default value is
inherited from a parent object (likely the system) with a byte_order
param.
Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg
---
M src/dev/serial/Uart.py
M src/dev/serial/simple.cc
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 97efcdd..5e64481 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -52,7 +52,7 @@
class SimpleUart(Uart):
type = 'SimpleUart'
cxx_header = "dev/serial/simple.hh"
-big_endian = Param.Bool(False, "Is the device Big Endian?")
+byte_order = Param.ByteOrder(Parent.byte_order, "Device byte order")
pio_size = Param.Addr(0x4, "Size of address range")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is "\
"received on the UART")
diff --git a/src/dev/serial/simple.cc b/src/dev/serial/simple.cc
index 97018ab..339d6b9 100644
--- a/src/dev/serial/simple.cc
+++ b/src/dev/serial/simple.cc
@@ -43,9 +43,7 @@
#include "sim/sim_exit.hh"
SimpleUart::SimpleUart(const SimpleUartParams *p)
-: Uart(p, p->pio_size),
- byteOrder(p->big_endian ? ByteOrder::big : ByteOrder::little),
- endOnEOT(p->end_on_eot)
+: Uart(p, p->pio_size), byteOrder(p->byte_order),
endOnEOT(p->end_on_eot)
{
}
--
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[gem5-dev] Change in gem5/gem5[develop]: python: Add support for introspecting scalar stats
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33176 )
Change subject: python: Add support for introspecting scalar stats
..
python: Add support for introspecting scalar stats
This change adds a wrapper for the ScalarInfo stat type to enable
introspection of scalar stats from Python. Due to the slightly
confusing use of proxy objects in the stat system, PyBind11 fails to
automatically cast to the right wrapper type. This is worked around in
the by explicitly casting to the relevant type's Python wrapper.
To make the interface more Python-friendly, this change also changes
the semantics of resolveStat to raise an exception if the stat can't
be found.
Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Signed-off-by: Andreas Sandberg
---
M src/python/pybind11/stats.cc
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1149eba..f69aa70 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -54,6 +54,25 @@
namespace py = pybind11;
+static const py::object
+cast_stat_info(const Stats::Info *info)
+{
+/* PyBind11 gets confused by the InfoProxy magic, so we need to
+ * explicitly cast to the right wrapper type. */
+
+#define TRY_CAST(T) do {\
+auto _stat = dynamic_cast(info); \
+if (_stat) \
+return py::cast(_stat); \
+} while (0)
+
+TRY_CAST(Stats::ScalarInfo);
+
+return py::cast(info);
+
+#undef TRY_CAST
+}
+
namespace Stats {
void
@@ -120,14 +139,39 @@
.def("visit", ::Info::visit)
;
+py::class_>(
+ m, "ScalarInfo")
+.def("value", ::ScalarInfo::value)
+.def("result", ::ScalarInfo::result)
+.def("total", ::ScalarInfo::result)
+;
+
py::class_>(
m, "Group")
.def("regStats", ::Group::regStats)
.def("resetStats", ::Group::resetStats)
.def("preDumpStats", ::Group::preDumpStats)
-.def("getStats", ::Group::getStats)
+.def("getStats", [](const Stats::Group )
+ -> std::vector {
+
+ auto stats = self.getStats();
+std::vector py_stats;
+py_stats.reserve(stats.size());
+std::transform(stats.begin(), stats.end(),
+ std::back_inserter(py_stats),
+ cast_stat_info);
+return py_stats;
+})
.def("getStatGroups", ::Group::getStatGroups)
.def("addStatGroup", ::Group::addStatGroup)
-.def("resolveStat", ::Group::resolveStat)
+.def("resolveStat", [](const Stats::Group ,
+ const std::string ) -> py::object {
+ const Stats::Info *stat = self.resolveStat(name);
+ if (!stat)
+ throw pybind11::key_error("Unknown stat name");
+
+ return cast_stat_info(stat);
+ })
;
}
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Expose the system's byte order as a param
Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33175 )
Change subject: sim: Expose the system's byte order as a param
..
sim: Expose the system's byte order as a param
There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.
Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg
---
M src/sim/System.py
M src/sim/system.hh
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/sim/System.py b/src/sim/System.py
index f4a9f82..773bb32 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -54,6 +54,11 @@
'little',
]
+if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
+defult_byte_order = 'big'
+else:
+default_byte_order = 'little'
+
class System(SimObject):
type = 'System'
cxx_header = "sim/system.hh"
@@ -90,6 +95,9 @@
cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
+byte_order = Param.ByteOrder(default_byte_order,
+ "Default byte order of system components")
+
redirect_paths = VectorParam.RedirectPath([], "Path redirections")
exit_on_work_items = Param.Bool(False, "Exit from the simulation loop
when "
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 9480821..b7fb789 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -386,11 +386,7 @@
ByteOrder
getGuestByteOrder() const
{
-#if THE_ISA != NULL_ISA
-return TheISA::GuestByteOrder;
-#else
-panic("The NULL ISA has no endianness.");
-#endif
+return _params->byte_order;
}
/**
--
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[gem5-dev] Change in gem5/gem5[master]: ext: Update fputils to rev 0721843
ions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - *notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above - *copyright notice, this list of conditions and the following - *disclaimer in the documentation and/or other materials provided - *with the distribution. + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg */ #ifndef _TEST_HELPER -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22125 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I46d8a5dfac2f4a95e66ee82a15288ac424d7df90 Gerrit-Change-Number: 22125 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: ext: Update fputils to rev 0721843
ed that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGE. + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg */ #ifndef _TEST_HELPER -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22125 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I46d8a5dfac2f4a95e66ee82a15288ac424d7df90 Gerrit-Change-Number: 22125 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: misc: Add Giacomo Travaglini as an Arm maintainer
Andreas Sandberg has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/21899 ) Change subject: misc: Add Giacomo Travaglini as an Arm maintainer .. misc: Add Giacomo Travaglini as an Arm maintainer I have been delegating a lot of changes to Giacomo T for a long time, making him a de facto Arm co-maintainer. Make this official by adding him to the list of maintainers. Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Signed-off-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21899 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/MAINTAINERS b/MAINTAINERS index a99a49b..4461f61 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,7 @@ arch-alpha: arch-arm: Andreas Sandberg + Giacomo Travaglini arch-hsail: Tony Gutierrez arch-mips: @@ -54,6 +55,10 @@ dev-virtio: Andreas Sandberg +dev-arm: + Andreas Sandberg + Giacomo Travaglini + ext: Components external to gem5 gpu-compute: @@ -93,6 +98,7 @@ system-alpha: system-arm: Andreas Sandberg + Giacomo Travaglini tests: testing changes (not stats updates for tests. See stats:) Andreas Sandberg -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21899 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Gerrit-Change-Number: 21899 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: misc: Add Giacomo Travaglini as an Arm maintainer
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/21899 ) Change subject: misc: Add Giacomo Travaglini as an Arm maintainer .. misc: Add Giacomo Travaglini as an Arm maintainer I have been delegating a lot of changes to Giacomo T for a long time, making him a de facto Arm co-maintainer. Make this official by adding him to the list of maintainers. Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Signed-off-by: Andreas Sandberg --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index a99a49b..4461f61 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,7 @@ arch-alpha: arch-arm: Andreas Sandberg + Giacomo Travaglini arch-hsail: Tony Gutierrez arch-mips: @@ -54,6 +55,10 @@ dev-virtio: Andreas Sandberg +dev-arm: + Andreas Sandberg + Giacomo Travaglini + ext: Components external to gem5 gpu-compute: @@ -93,6 +98,7 @@ system-alpha: system-arm: Andreas Sandberg + Giacomo Travaglini tests: testing changes (not stats updates for tests. See stats:) Andreas Sandberg -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/21899 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee Gerrit-Change-Number: 21899 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: base: Add classes that encapsulate a channel address
are inclusive */
+TEST(ChannelAddrRange, Range)
+{
+ChannelAddrRange range(ChannelAddr(1), ChannelAddr(3));
+
+EXPECT_FALSE(range.contains(ChannelAddr(0)));
+EXPECT_TRUE(range.contains(ChannelAddr(1)));
+EXPECT_TRUE(range.contains(ChannelAddr(2)));
+EXPECT_TRUE(range.contains(ChannelAddr(3)));
+EXPECT_FALSE(range.contains(ChannelAddr(4)));
+
+EXPECT_EQ(range.start(), ChannelAddr(1));
+EXPECT_EQ(range.end(), ChannelAddr(3));
+EXPECT_EQ(range.size(), ChannelAddr(3));
+}
--
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[gem5-dev] Change in gem5/gem5[master]: base: Add addIntlvBits to AddrRange
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/21599 )
Change subject: base: Add addIntlvBits to AddrRange
..
base: Add addIntlvBits to AddrRange
This method performs the opposite operation of removeIntlvBits and can
be used to transform a channel-local address to a global PA.
Change-Id: I2fab587d7c094597e52422305775ac7f31efba34
Signed-off-by: Andreas Sandberg
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21599
Reviewed-by: Nikos Nikoleris
Reviewed-by: Daniel Carvalho
Tested-by: kokoro
---
M src/base/addr_range.hh
M src/base/addr_range.test.cc
2 files changed, 62 insertions(+), 0 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Andreas Sandberg: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/base/addr_range.hh b/src/base/addr_range.hh
index cda6ccf..84a3d4d 100644
--- a/src/base/addr_range.hh
+++ b/src/base/addr_range.hh
@@ -471,6 +471,44 @@
}
/**
+ * This method adds the interleaving bits removed by
+ * removeIntlvBits.
+ */
+inline Addr addIntlvBits(Addr a) const
+{
+// Get the LSB set from each mask
+int masks_lsb[masks.size()];
+for (int i = 0; i < masks.size(); i++) {
+masks_lsb[i] = ctz64(masks[i]);
+}
+
+// Add bits one-by-one from the LSB side.
+std::sort(masks_lsb, masks_lsb + masks.size());
+for (int i = 0; i < masks.size(); i++) {
+const int intlv_bit = masks_lsb[i];
+if (intlv_bit > 0) {
+// on every iteration we add one bit from the input
+// address, and therefore the lowest invtl_bit has
+// also shifted to the left by i positions.
+a = insertBits(a << 1, intlv_bit + i - 1, 0, a);
+} else {
+a <<= 1;
+}
+}
+
+for (int i = 0; i < masks.size(); i++) {
+const int lsb = ctz64(masks[i]);
+const Addr intlv_bit = bits(intlvMatch, i);
+// Calculate the mask ignoring the LSB
+const Addr masked = a & masks[i] & ~(1 << lsb);
+// Set the LSB of the mask to whatever satisfies the selector
bit
+a = insertBits(a, lsb, intlv_bit ^ popCount(masked));
+}
+
+return a;
+}
+
+/**
* Determine the offset of an address within the range.
*
* This function returns the offset of the given address from the
diff --git a/src/base/addr_range.test.cc b/src/base/addr_range.test.cc
index 54eb198..93afbb0 100644
--- a/src/base/addr_range.test.cc
+++ b/src/base/addr_range.test.cc
@@ -121,6 +121,16 @@
}
}
+void testAddRemoveIntlvBits()
+{
+for (Addr addr = start; addr <= end; addr++) {
+AddrRange = range[getIndex(addr)];
+Addr ch_addr = r.removeIntlvBits(addr);
+Addr pa = r.addIntlvBits(ch_addr);
+ASSERT_EQ(addr, pa);
+}
+}
+
static const Addr end = 0x1;
static const Addr start = 0x0;
static const int intlvSize = 4;
@@ -162,6 +172,11 @@
testGetOffset();
}
+TEST_F(AddrRangeCont, AddrRangeAddRemoveIntlvBits)
+{
+testAddRemoveIntlvBits();
+}
+
class AddrRangeContLegacy : public AddrRangeCont {
protected:
@@ -185,6 +200,10 @@
testGetOffset();
}
+TEST_F(AddrRangeContLegacy, AddrRangeAddRemoveIntlvBits)
+{
+testAddRemoveIntlvBits();
+}
class AddrRangeArb : public AddrRangeBase {
protected:
@@ -218,3 +237,8 @@
{
testGetOffset();
}
+
+TEST_F(AddrRangeArb, AddrRangeAddRemoveIntlvBits)
+{
+testAddRemoveIntlvBits();
+}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I2fab587d7c094597e52422305775ac7f31efba34
Gerrit-Change-Number: 21599
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg
Gerrit-Assignee: Nikos Nikoleris
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: base: Add classes that encapsulate a channel address
isit https://gem5-review.googlesource.com/c/public/gem5/+/21600 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I45d4061ebc8507a10d0a4577b28796dc5ec7a469 Gerrit-Change-Number: 21600 Gerrit-PatchSet: 1 Gerrit-Owner: Andreas Sandberg Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
