[gem5-dev] Change in gem5/gem5[develop]: python: more readable Ruby dot topology
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41093 )
Change subject: python: more readable Ruby dot topology
..
python: more readable Ruby dot topology
Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.
Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
---
M src/python/m5/util/dot_writer_ruby.py
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/python/m5/util/dot_writer_ruby.py
b/src/python/m5/util/dot_writer_ruby.py
index 9356a94..4123cac 100644
--- a/src/python/m5/util/dot_writer_ruby.py
+++ b/src/python/m5/util/dot_writer_ruby.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2019 ARM Limited
+# Copyright (c) 2019,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -90,9 +90,24 @@
)
connected[link.dst_node.path()] = link.src_node.path()
+# Find common prefixes and sufixes to generate names
+paths = [link.ext_node.path() for link in network.ext_links]
+rpaths = [link.ext_node.path()[::-1] for link in network.ext_links]
+preffix = os.path.commonprefix(paths)
+suffix = os.path.commonprefix(rpaths)[::-1]
+def strip_right(text, suffix):
+if not text.endswith(suffix):
+return text
+return text[:len(text)-len(suffix)]
+def strip_left(text, prefix):
+if not text.startswith(prefix):
+return text
+return text[len(prefix):]
+
+
for link in network.ext_links:
ctrl = link.ext_node
-label = ctrl._name
+label = strip_right(strip_left(ctrl.path(), preffix), suffix)
if hasattr(ctrl, '_node_type'):
label += ' (' + ctrl._node_type + ')'
callgraph.add_node(
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removes data ptr from RubyRequest
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41113 ) Change subject: mem-ruby: removes data ptr from RubyRequest .. mem-ruby: removes data ptr from RubyRequest It's redundant since we keep the PacketPtr. Change-Id: I421ffe8a25ad6a96454d84c0726715fd87a451e6 --- M src/mem/ruby/slicc_interface/RubyRequest.cc M src/mem/ruby/slicc_interface/RubyRequest.hh M src/mem/ruby/system/Sequencer.cc 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc index f2099db..d45f3d2 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.cc +++ b/src/mem/ruby/slicc_interface/RubyRequest.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 ARM Limited + * Copyright (c) 2019,2021 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -79,8 +79,10 @@ // has to overwrite the data for the timing request, even if the // timing request has still not been ordered globally. -if (!data) - return false; +if (!pkt->hasData() || !m_pkt->hasData()) +return false; + +uint8_t *data = m_pkt->getPtr(); Addr wBase = pkt->getAddr(); Addr wTail = wBase + pkt->getSize(); diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh index ed8dbbb..d27a589 100644 --- a/src/mem/ruby/slicc_interface/RubyRequest.hh +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 ARM Limited + * Copyright (c) 2020,2021 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -62,7 +62,6 @@ RubyAccessMode m_AccessMode; int m_Size; PrefetchBit m_Prefetch; -uint8_t* data; PacketPtr m_pkt; ContextID m_contextId; WriteMask m_writeMask; @@ -72,7 +71,7 @@ bool m_htmFromTransaction; uint64_t m_htmTransactionUid; -RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, +RubyRequest(Tick curTime, uint64_t _paddr, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, ContextID _proc_id = 100, ContextID _core_id = 99) @@ -83,7 +82,6 @@ m_AccessMode(_access_mode), m_Size(_len), m_Prefetch(_pb), - data(_data), m_pkt(_pkt), m_contextId(_core_id), m_htmFromTransaction(false), @@ -92,7 +90,7 @@ m_LineAddress = makeLineAddress(m_PhysicalAddress); } -RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, +RubyRequest(Tick curTime, uint64_t _paddr, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, @@ -106,7 +104,6 @@ m_AccessMode(_access_mode), m_Size(_len), m_Prefetch(_pb), - data(_data), m_pkt(_pkt), m_contextId(_core_id), m_writeMask(_wm_size,_wm_mask), @@ -119,7 +116,7 @@ m_LineAddress = makeLineAddress(m_PhysicalAddress); } -RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, +RubyRequest(Tick curTime, uint64_t _paddr, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, @@ -134,7 +131,6 @@ m_AccessMode(_access_mode), m_Size(_len), m_Prefetch(_pb), - data(_data), m_pkt(_pkt), m_contextId(_core_id), m_writeMask(_wm_size,_wm_mask,_atomicOps), diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 2d51f84..40e0cf4 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -770,8 +770,6 @@ // requests do not std::shared_ptr msg = std::make_shared(clockEdge(), pkt->getAddr(), - pkt->isFlush() ? - nullptr : pkt->getPtr(), pkt->getSize(), pc, secondary_type, RubyAccessMode_Supervisor, pkt, PrefetchBit_No, proc_id, core_id); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41113 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I421ffe8a25ad6a96454d84c0726715fd87a451e6 Gerrit-Change-Number: 41113 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Müc
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix Sequencer latency reporting
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41114 )
Change subject: mem-ruby: fix Sequencer latency reporting
..
mem-ruby: fix Sequencer latency reporting
Most protocols won't set initialRequestTime, forwardRequestTime, and
firstResponseTime, thus leading to calculated latency being always 0.
Change-Id: Id2c73314a964bf6efb262d40b3df515373023b84
Signed-off-by: Tiago Mück
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 2d51f84..b45f34c 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -334,7 +334,7 @@
assert(curCycle() >= issued_time);
Cycles total_lat = completion_time - issued_time;
-if (initialRequestTime < issued_time) {
+if ((initialRequestTime != 0) && (initialRequestTime < issued_time)) {
// if the request was combined in the protocol with an earlier
request
// for the same address, it is possible that it will return an
// initialRequestTime corresponding the earlier request. Since
Cycles
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: warns on masked functional writes
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41133 )
Change subject: mem-ruby: warns on masked functional writes
..
mem-ruby: warns on masked functional writes
It's not expected to issue masked functional writes or to receive
functional writes to an address with a pending masked write.
Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/RubyRequest.cc
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc
b/src/mem/ruby/slicc_interface/RubyRequest.cc
index f2099db..3cafabe 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019,2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -82,6 +82,13 @@
if (!data)
return false;
+if (pkt->isMaskedWrite() || m_pkt->isMaskedWrite()) {
+warn("Skiping functional write to/from a masked write packet"
+" (addr: %#x, other addr: %#x).\n", m_PhysicalAddress,
+ pkt->getAddr());
+return false;
+}
+
Addr wBase = pkt->getAddr();
Addr wTail = wBase + pkt->getSize();
Addr mBase = m_PhysicalAddress;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fixes for masked writes
t (c) 2019-2020 ARM Limited
+ * Copyright (c) 2019-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -575,8 +575,7 @@
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
-data.setData(pkt->getConstPtr(),
- getOffset(request_address), pkt->getSize());
+data.setData(pkt);
} else if (!pkt->isFlush()) {
if ((type == RubyRequestType_LD) ||
(type == RubyRequestType_IFETCH) ||
@@ -587,6 +586,7 @@
data.getData(getOffset(request_address), pkt->getSize()));
DPRINTF(RubySequencer, "read data %s\n", data);
} else if (pkt->req->isSwap()) {
+assert(!pkt->isMaskedWrite());
std::vector overwrite_val(pkt->getSize());
pkt->writeData(&overwrite_val[0]);
pkt->setData(
@@ -597,8 +597,7 @@
} else if (type != RubyRequestType_Store_Conditional ||
llscSuccess) {
// Types of stores set the actual data here, apart from
// failed Store Conditional requests
-data.setData(pkt->getConstPtr(),
- getOffset(request_address), pkt->getSize());
+data.setData(pkt);
DPRINTF(RubySequencer, "set data %s\n", data);
}
}
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix functional reads in abstract ctrl
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41153 )
Change subject: mem-ruby: fix functional reads in abstract ctrl
..
mem-ruby: fix functional reads in abstract ctrl
When calling functionalMemoryRead we need to check the mem req. queue
first as it may have write data not yet forwarded to the memory port.
Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/AbstractController.cc
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1222631..b7da81e 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -317,7 +317,10 @@
void
AbstractController::functionalMemoryRead(PacketPtr pkt)
{
-memoryPort.sendFunctional(pkt);
+// read from mem. req. queue if write data is pending there
+MessageBuffer *req_queue = getMemReqQueue();
+if (!req_queue || !req_queue->functionalRead(pkt))
+memoryPort.sendFunctional(pkt);
}
int
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add wakeup_port statement
SED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeupPortStatementAST(StatementAST):
+def __init__(self, slicc, in_port, address):
+super(StatementAST, self).__init__(slicc)
+self.in_port = in_port
+self.address = address
+
+def __repr__(self):
+return "[WakeupPortStatementAst: %r]" % self.in_port
+
+def generate(self, code, return_type):
+self.in_port.assertType("InPort")
+self.address.assertType("Addr")
+
+in_port_code = self.in_port.var.code
+address_code = self.address.var.code
+code('''
+wakeUpBuffer(&($in_port_code), $address_code);
+''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index c410104..247546f 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
#
@@ -60,6 +72,7 @@
from slicc.ast.PeekStatementAST import *
from slicc.ast.ReturnStatementAST import *
from slicc.ast.StallAndWaitStatementAST import *
+from slicc.ast.WakeupPortStatementAST import *
from slicc.ast.StateDeclAST import *
from slicc.ast.StatementAST import *
from slicc.ast.StatementListAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 51a68d0..73ca835 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -118,6 +118,7 @@
'state_declaration' : 'STATE_DECL',
'peek' : 'PEEK',
'stall_and_wait' : 'STALL_AND_WAIT',
+'wakeup_port' : 'WAKEUP_PORT',
'enqueue' : 'ENQUEUE',
'check_allocate' : 'CHECK_ALLOCATE',
'check_next_cycle' : 'CHECK_NEXT_CYCLE',
@@ -616,6 +617,10 @@
"statement : STALL_AND_WAIT '(' var ',' var ')' SEMI"
p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5])
+def p_statement__wakeup_port(self, p):
+"statement : WAKEUP_PORT '(' var ',' var ')' SEMI"
+p[0] = ast.WakeupPortStatementAST(self, p[3], p[5])
+
def p_statement__peek(self, p):
"statement : PEEK '(' var ',' type pairs ')' statements"
p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: extended transaction profiling
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41158 )
Change subject: mem-ruby: extended transaction profiling
..
mem-ruby: extended transaction profiling
Adds additional stats to accounts for incoming and outgoing retries.
Calling incomingTransactionStart with retried==true indicates the
received request initiating the transaction is a retried request.
Calling outgoingTransactionEnd with retried==true indicates the request
was retried by the requester.
Change-Id: I22fd971d4997fce0c114b5ec030cbbf9b463d0c6
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/slicc/symbols/StateMachine.py
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 4cd6c76..95be144 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019,2020 ARM Limited
+ * Copyright (c) 2017,2019-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -216,10 +216,12 @@
*/
template
void incomingTransactionStart(Addr addr,
-EventType type, StateType initialState)
+EventType type, StateType initialState, bool retried)
{
assert(m_inTrans.find(addr) == m_inTrans.end());
m_inTrans[addr] = {type, initialState, curTick()};
+if (retried)
+ ++(*stats.inTransLatRetries[type]);
}
/**
@@ -237,6 +239,7 @@
[iter->second.state]
[(unsigned)finalState]->sample(
ticksToCycles(curTick() -
iter->second.time));
+++(*stats.inTransLatTotal[iter->second.transaction]);
m_inTrans.erase(iter);
}
@@ -260,12 +263,14 @@
*
* @param addr address of the line with an outstanding transaction
*/
-void outgoingTransactionEnd(Addr addr)
+void outgoingTransactionEnd(Addr addr, bool retried)
{
auto iter = m_outTrans.find(addr);
assert(iter != m_outTrans.end());
stats.outTransLatHist[iter->second.transaction]->sample(
ticksToCycles(curTick() - iter->second.time));
+if (retried)
+ ++(*stats.outTransLatHistRetries[iter->second.transaction]);
m_outTrans.erase(iter);
}
@@ -356,10 +361,13 @@
// states. Only histograms with samples will appear in the stats
std::vector>>
inTransLatHist;
+std::vector inTransLatRetries;
+std::vector inTransLatTotal;
// Initialized by the SLICC compiler for all events.
// Only histograms with samples will appear in the stats.
std::vector outTransLatHist;
+std::vector outTransLatHistRetries;
//! Counter for the number of cycles when the transitions carried
out
//! were equal to the maximum allowed
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 2990612..9c33289 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -856,6 +856,7 @@
}
}
}
+
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
std::string stat_name =
@@ -865,9 +866,28 @@
t->init(5);
t->flags(Stats::pdf | Stats::total |
Stats::oneline | Stats::nozero);
+
+Stats::Scalar* r = new Stats::Scalar;
+stats.outTransLatHistRetries.push_back(r);
+r->name(name() + ".outTransLatHist." +
+${ident}_Event_to_string(event)+ ".retries");
+r->flags(Stats::nozero);
}
+
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
+Stats::Scalar* r = new Stats::Scalar;
+stats.inTransLatTotal.push_back(r);
+r->name(name() + ".inTransLatHist." +
+${ident}_Event_to_string(event)+ ".total");
+r->flags(Stats::nozero);
+
+r = new Stats::Scalar;
+stats.inTransLatRetries.push_back(r);
+r->name(name() + ".inTransLatHist." +
+${ident}_Event_to_string(event)+ ".retries");
+r->flags(Stats::nozero);
+
stats.inTransLatHist.emplace_back();
for (${ident}_State initial_state = ${ident}_State_FIRST;
initial_state < ${ident}_State_NUM; ++initial_state) {
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add andMask to WriteMask
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41154 )
Change subject: mem-ruby: add andMask to WriteMask
..
mem-ruby: add andMask to WriteMask
Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index f1e5f37..895584a 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020,2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -160,6 +160,20 @@
}
void
+andMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = (mMask.at(i)) & (writeMask.mMask.at(i));
+}
+
+if (writeMask.mAtomic) {
+mAtomic = true;
+mAtomicOp = writeMask.mAtomicOp;
+}
+}
+
+void
orMask(const WriteMask & writeMask)
{
assert(mSize == writeMask.mSize);
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 1b67dc6..e48cca5 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -57,6 +57,7 @@
bool isEmpty();
bool isFull();
bool isOverlap(WriteMask);
+ void andMask(WriteMask);
void orMask(WriteMask);
void setInvertedMask(WriteMask);
void fillMask();
--
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Gerrit-Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Gerrit-Change-Number: 41154
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add TBEStorage structure
ge::removeEntryFromSlot(int slot)
+{
+auto iter = m_slots_used.find(slot);
+assert(iter != m_slots_used.end());
+assert(iter->second > 0);
+iter->second -= 1;
+if (iter->second == 0) {
+m_slots_used.erase(iter);
+m_slots_avail.push(slot);
+}
+m_avg_size = size();
+m_avg_util = utilization();
+}
+
+#endif
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 23f8707..2990612 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2019-2020 ARM Limited
+# Copyright (c) 2019-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -809,6 +809,13 @@
$c_ident::regStats()
{
AbstractController::regStats();
+''')
+for var in self.objects:
+if var.type.ident == 'TBEStorage':
+vident = var.ident
+vcident = "m_%s_ptr" % var.ident
+code('$vcident->regStats(name() + ".$vident");')
+code('''
// For each type of controllers, one controller of that type is picked
// to aggregate stats of all controllers of that type.
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: intToTick helper
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41156 )
Change subject: mem-ruby: intToTick helper
..
mem-ruby: intToTick helper
Change-Id: I76635228223e9a83eef94a25d166d091315a5e96
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index 70648ec..1cf3cab 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -33,6 +33,7 @@
void assert(bool condition);
Cycles zero_time();
Cycles intToCycles(int c);
+Tick intToTick(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index f7f8a01..4337b39 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -62,6 +62,8 @@
inline Cycles intToCycles(int c) { return Cycles(c); }
+inline Tick intToTick(int c) { return c; }
+
inline NodeID
intToID(int nodenum)
{
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fixes for masked writes
t(m_outstanding_count < m_max_outstanding_requests);
Addr line_addr = makeLineAddress(paddr);
auto emplace_pair =
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 2d51f84..ab83677 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 ARM Limited
+ * Copyright (c) 2019-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -575,8 +575,7 @@
// update the data unless it is a non-data-carrying flush
if (RubySystem::getWarmupEnabled()) {
-data.setData(pkt->getConstPtr(),
- getOffset(request_address), pkt->getSize());
+data.setData(pkt);
} else if (!pkt->isFlush()) {
if ((type == RubyRequestType_LD) ||
(type == RubyRequestType_IFETCH) ||
@@ -587,6 +586,7 @@
data.getData(getOffset(request_address), pkt->getSize()));
DPRINTF(RubySequencer, "read data %s\n", data);
} else if (pkt->req->isSwap()) {
+assert(!pkt->isMaskedWrite());
std::vector overwrite_val(pkt->getSize());
pkt->writeData(&overwrite_val[0]);
pkt->setData(
@@ -597,8 +597,7 @@
} else if (type != RubyRequestType_Store_Conditional ||
llscSuccess) {
// Types of stores set the actual data here, apart from
// failed Store Conditional requests
-data.setData(pkt->getConstPtr(),
- getOffset(request_address), pkt->getSize());
+data.setData(pkt);
DPRINTF(RubySequencer, "set data %s\n", data);
}
}
--
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Gerrit-Change-Id: I9e5f70fed29edcf55fef94a4b145aa838dc60eac
Gerrit-Change-Number: 41134
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: warns on masked functional writes
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41133 )
Change subject: mem-ruby: warns on masked functional writes
..
mem-ruby: warns on masked functional writes
It's not expected to issue masked functional writes or to receive
functional writes to an address with a pending masked write.
Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41133
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/RubyRequest.cc
1 file changed, 8 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc
b/src/mem/ruby/slicc_interface/RubyRequest.cc
index f2099db..3cafabe 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019,2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -82,6 +82,13 @@
if (!data)
return false;
+if (pkt->isMaskedWrite() || m_pkt->isMaskedWrite()) {
+warn("Skiping functional write to/from a masked write packet"
+" (addr: %#x, other addr: %#x).\n", m_PhysicalAddress,
+ pkt->getAddr());
+return false;
+}
+
Addr wBase = pkt->getAddr();
Addr wTail = wBase + pkt->getSize();
Addr mBase = m_PhysicalAddress;
--
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Gerrit-Change-Id: Ibc8ba5f642ff72f897e3a50011c0da6d3000b741
Gerrit-Change-Number: 41133
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix functional reads in abstract ctrl
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41153 )
Change subject: mem-ruby: fix functional reads in abstract ctrl
..
mem-ruby: fix functional reads in abstract ctrl
When calling functionalMemoryRead we need to check the mem req. queue
first as it may have write data not yet forwarded to the memory port.
Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41153
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/AbstractController.cc
1 file changed, 4 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1222631..b7da81e 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -317,7 +317,10 @@
void
AbstractController::functionalMemoryRead(PacketPtr pkt)
{
-memoryPort.sendFunctional(pkt);
+// read from mem. req. queue if write data is pending there
+MessageBuffer *req_queue = getMemReqQueue();
+if (!req_queue || !req_queue->functionalRead(pkt))
+memoryPort.sendFunctional(pkt);
}
int
--
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Gerrit-Change-Id: Id37aa0837a3462d92ae9ac3b45ca756b2c4f7d97
Gerrit-Change-Number: 41153
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix Sequencer latency reporting
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41114 )
Change subject: mem-ruby: fix Sequencer latency reporting
..
mem-ruby: fix Sequencer latency reporting
Most protocols won't set initialRequestTime, forwardRequestTime, and
firstResponseTime, thus leading to calculated latency being always 0.
Change-Id: Id2c73314a964bf6efb262d40b3df515373023b84
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41114
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/Sequencer.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index ab83677..49c0351 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -334,7 +334,7 @@
assert(curCycle() >= issued_time);
Cycles total_lat = completion_time - issued_time;
-if (initialRequestTime < issued_time) {
+if ((initialRequestTime != 0) && (initialRequestTime < issued_time)) {
// if the request was combined in the protocol with an earlier
request
// for the same address, it is possible that it will return an
// initialRequestTime corresponding the earlier request. Since
Cycles
--
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Gerrit-Change-Number: 41114
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: more readable Ruby dot topology
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41093 )
Change subject: python: more readable Ruby dot topology
..
python: more readable Ruby dot topology
Controllers may have the same name under different parents, thus
the controller full path is used as label. To avoid long and redundant
labels, common prefixes and suffixes are removed from the path.
Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41093
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/python/m5/util/dot_writer_ruby.py
1 file changed, 17 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/util/dot_writer_ruby.py
b/src/python/m5/util/dot_writer_ruby.py
index 9356a94..4123cac 100644
--- a/src/python/m5/util/dot_writer_ruby.py
+++ b/src/python/m5/util/dot_writer_ruby.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2019 ARM Limited
+# Copyright (c) 2019,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -90,9 +90,24 @@
)
connected[link.dst_node.path()] = link.src_node.path()
+# Find common prefixes and sufixes to generate names
+paths = [link.ext_node.path() for link in network.ext_links]
+rpaths = [link.ext_node.path()[::-1] for link in network.ext_links]
+preffix = os.path.commonprefix(paths)
+suffix = os.path.commonprefix(rpaths)[::-1]
+def strip_right(text, suffix):
+if not text.endswith(suffix):
+return text
+return text[:len(text)-len(suffix)]
+def strip_left(text, prefix):
+if not text.startswith(prefix):
+return text
+return text[len(prefix):]
+
+
for link in network.ext_links:
ctrl = link.ext_node
-label = ctrl._name
+label = strip_right(strip_left(ctrl.path(), preffix), suffix)
if hasattr(ctrl, '_node_type'):
label += ' (' + ctrl._node_type + ')'
callgraph.add_node(
--
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Gerrit-Change-Id: Id793b59a4c38f3425ae5348138ae1d74c823edd7
Gerrit-Change-Number: 41093
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add andMask to WriteMask
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41154 )
Change subject: mem-ruby: add andMask to WriteMask
..
mem-ruby: add andMask to WriteMask
Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41154
Reviewed-by: Matt Sinclair
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 16 insertions(+), 1 deletion(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index f1e5f37..895584a 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020,2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -160,6 +160,20 @@
}
void
+andMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = (mMask.at(i)) & (writeMask.mMask.at(i));
+}
+
+if (writeMask.mAtomic) {
+mAtomic = true;
+mAtomicOp = writeMask.mAtomicOp;
+}
+}
+
+void
orMask(const WriteMask & writeMask)
{
assert(mSize == writeMask.mSize);
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 1b67dc6..e48cca5 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -57,6 +57,7 @@
bool isEmpty();
bool isFull();
bool isOverlap(WriteMask);
+ void andMask(WriteMask);
void orMask(WriteMask);
void setInvertedMask(WriteMask);
void fillMask();
--
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Gerrit-Change-Id: Ieeb68b405a68226077a2ffee231408f554e758a5
Gerrit-Change-Number: 41154
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: intToTick helper
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41156 )
Change subject: mem-ruby: intToTick helper
..
mem-ruby: intToTick helper
Change-Id: I76635228223e9a83eef94a25d166d091315a5e96
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41156
Reviewed-by: Jason Lowe-Power
Reviewed-by: Matt Sinclair
Maintainer: Jason Lowe-Power
Maintainer: Matt Sinclair
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 16 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index 70648ec..3079f20 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -1,5 +1,16 @@
-
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -33,6 +44,7 @@
void assert(bool condition);
Cycles zero_time();
Cycles intToCycles(int c);
+Tick intToTick(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index f7f8a01..187f5fe 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -62,6 +62,8 @@
inline Cycles intToCycles(int c) { return Cycles(c); }
+inline Tick intToTick(int c) { return c; }
+
inline NodeID
intToID(int nodenum)
{
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add wakeup_port statement
THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from slicc.ast.StatementAST import StatementAST
+
+class WakeupPortStatementAST(StatementAST):
+def __init__(self, slicc, in_port, address):
+super(StatementAST, self).__init__(slicc)
+self.in_port = in_port
+self.address = address
+
+def __repr__(self):
+return "[WakeupPortStatementAst: %r]" % self.in_port
+
+def generate(self, code, return_type):
+self.in_port.assertType("InPort")
+self.address.assertType("Addr")
+
+in_port_code = self.in_port.var.code
+address_code = self.address.var.code
+code('''
+wakeUpBuffer(&($in_port_code), $address_code);
+''')
diff --git a/src/mem/slicc/ast/__init__.py b/src/mem/slicc/ast/__init__.py
index c410104..247546f 100644
--- a/src/mem/slicc/ast/__init__.py
+++ b/src/mem/slicc/ast/__init__.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
#
@@ -60,6 +72,7 @@
from slicc.ast.PeekStatementAST import *
from slicc.ast.ReturnStatementAST import *
from slicc.ast.StallAndWaitStatementAST import *
+from slicc.ast.WakeupPortStatementAST import *
from slicc.ast.StateDeclAST import *
from slicc.ast.StatementAST import *
from slicc.ast.StatementListAST import *
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 51a68d0..73ca835 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020,2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -118,6 +118,7 @@
'state_declaration' : 'STATE_DECL',
'peek' : 'PEEK',
'stall_and_wait' : 'STALL_AND_WAIT',
+'wakeup_port' : 'WAKEUP_PORT',
'enqueue' : 'ENQUEUE',
'check_allocate' : 'CHECK_ALLOCATE',
'check_next_cycle' : 'CHECK_NEXT_CYCLE',
@@ -616,6 +617,10 @@
"statement : STALL_AND_WAIT '(' var ',' var ')' SEMI"
p[0] = ast.StallAndWaitStatementAST(self, p[3], p[5])
+def p_statement__wakeup_port(self, p):
+"statement : WAKEUP_PORT '(' var ',' var ')' SEMI"
+p[0] = ast.WakeupPortStatementAST(self, p[3], p[5])
+
def p_statement__peek(self, p):
"statement : PEEK '(' var ',' type pairs ')' statements"
p[0] = ast.PeekStatementAST(self, p[3], p[5], p[6], p[8], "peek")
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removes data ptr from RubyRequest
em/ruby/system/VIPERCoalescer.cc
+++ b/src/mem/ruby/system/VIPERCoalescer.cc
@@ -150,7 +150,6 @@
std::shared_ptr msg;
if (pkt->isAtomicOp()) {
msg = std::make_shared(clockEdge(), pkt->getAddr(),
- pkt->getPtr(),
pkt->getSize(), pc, crequest->getRubyType(),
RubyAccessMode_Supervisor, pkt,
PrefetchBit_No, proc_id, 100,
@@ -158,7 +157,6 @@
dataBlock, atomicOps, crequest->getSeqNum());
} else {
msg = std::make_shared(clockEdge(), pkt->getAddr(),
- pkt->getPtr(),
pkt->getSize(), pc, crequest->getRubyType(),
RubyAccessMode_Supervisor, pkt,
PrefetchBit_No, proc_id, 100,
@@ -288,7 +286,7 @@
// Evict Read-only data
RubyRequestType request_type = RubyRequestType_REPLACEMENT;
std::shared_ptr msg = std::make_shared(
-clockEdge(), addr, (uint8_t*) 0, 0, 0,
+clockEdge(), addr, 0, 0,
request_type, RubyAccessMode_Supervisor,
nullptr);
DPRINTF(GPUCoalescer, "Evicting addr 0x%x\n", addr);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add TBEStorage structure
capacity() const { return m_slots_used.size() +
m_slots_avail.size(); }
+
+// Returns number of slots currently reserved
+int reserved() const { return m_reserved; }
+
+// Returns the number of slots available
+int slotsAvailable() const { return m_slots_avail.size() - m_reserved;
}
+
+// Returns the TBEStorage utilization
+float utilization() const { return size() / (float)capacity(); }
+
+// Returns true if slotsAvailable() >= n; current_time is always
ignored
+// This allows this class to be used with check_allocate in SLICC to
+// trigger resource stalls when there are no slots available
+bool areNSlotsAvailable(int n, Tick current_time = 0) const;
+
+// Increase/decrease the number of reserved slots. Having reserved
slots
+// reduces the number of slots available for allocation
+void incrementReserved();
+void decrementReserved();
+
+// Assign a TBETable entry to a free slot and returns the slot number.
+// Notice we don't need any info from TBETable and just track the
number
+// of entries assigned to each slot.
+// This funcion requires slotsAvailable() > 0
+int addEntryToNewSlot();
+
+// Assign an entry to an existing non-empty slot
+void addEntryToSlot(int slot);
+
+// Remove an entry from an existing non-empty slot. The slot becomes
+// available again when the number of assigned entries == 0
+void removeEntryFromSlot(int slot);
+
+ private:
+int m_reserved;
+std::stack m_slots_avail;
+std::unordered_map m_slots_used;
+
+struct TBEStorageStats : public Stats::Group
+{
+TBEStorageStats(Stats::Group *parent);
+
+// Statistical variables
+Stats::Average avg_size;
+Stats::Average avg_util;
+Stats::Average avg_reserved;
+} m_stats;
+};
+
+inline bool
+TBEStorage::areNSlotsAvailable(int n, Tick current_time) const
+{
+return slotsAvailable() >= n;
+}
+
+inline void
+TBEStorage::incrementReserved()
+{
+++m_reserved;
+m_stats.avg_reserved = m_reserved;
+}
+
+inline void
+TBEStorage::decrementReserved()
+{
+assert(m_reserved > 0);
+--m_reserved;
+m_stats.avg_reserved = m_reserved;
+}
+
+inline int
+TBEStorage::addEntryToNewSlot()
+{
+assert(slotsAvailable() > 0);
+assert(m_slots_avail.size() > 0);
+int slot = m_slots_avail.top();
+m_slots_used[slot] = 1;
+m_slots_avail.pop();
+m_stats.avg_size = size();
+m_stats.avg_util = utilization();
+return slot;
+}
+
+inline void
+TBEStorage::addEntryToSlot(int slot)
+{
+auto iter = m_slots_used.find(slot);
+assert(iter != m_slots_used.end());
+iter->second += 1;
+}
+
+inline void
+TBEStorage::removeEntryFromSlot(int slot)
+{
+auto iter = m_slots_used.find(slot);
+assert(iter != m_slots_used.end());
+assert(iter->second > 0);
+iter->second -= 1;
+if (iter->second == 0) {
+m_slots_used.erase(iter);
+m_slots_avail.push(slot);
+}
+m_stats.avg_size = size();
+m_stats.avg_util = utilization();
+}
+
+#endif
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: extended transaction profiling
);
+
stats.inTransLatHist.emplace_back();
for (${ident}_State initial_state = ${ident}_State_FIRST;
initial_state < ${ident}_State_NUM; ++initial_state) {
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: alternative interface for func. reads
get a full copy of the line
+WriteMask bytes;
+if (ctrl_rw != nullptr) {
+ctrl_rw->functionalRead(line_address, pkt, bytes);
+// if a RW controllter has the full line that's all uptodate
+if (bytes.isFull())
+return true;
+}
+
+// Get data from RO and BS
+for (auto ctrl : ctrl_ro)
+ctrl->functionalRead(line_address, pkt, bytes);
+
+ctrl_bs->functionalRead(line_address, pkt, bytes);
+
+// if there is any busy controller or bytes still not set, then a
partial
+// and/or dirty copy of the line might be in a message buffer or the
+// network
+if (!ctrl_busy.empty() || !bytes.isFull()) {
+DPRINTF(RubySystem, "Reading from busy controllers and network\n");
+for (auto ctrl : ctrl_busy) {
+ctrl->functionalRead(line_address, pkt, bytes);
+ctrl->functionalReadBuffers(pkt, bytes);
+}
+for (auto& network : m_networks) {
+network->functionalRead(pkt, bytes);
+}
+for (auto ctrl : ctrl_others) {
+ctrl->functionalRead(line_address, pkt, bytes);
+ctrl->functionalReadBuffers(pkt, bytes);
+}
+}
+// we either got the full line or couldn't find anything at this point
+panic_if(!(bytes.isFull() || bytes.isEmpty()),
+"Inconsistent state on functional read for %#x %s\n",
+address, bytes);
+
+return bytes.isFull();
+}
+#endif
// The function searches through all the buffers that exist in different
// cache, directory and memory controllers, and in the network components
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript
index a5d2fb1..a2708ae 100644
--- a/src/mem/ruby/system/SConscript
+++ b/src/mem/ruby/system/SConscript
@@ -45,6 +45,12 @@
env.Append(CPPDEFINES=['PROTOCOL_' + env['PROTOCOL']])
+# list of protocols that require the partial functional read interface
+need_partial_func_reads = []
+
+if env['PROTOCOL'] in need_partial_func_reads:
+env.Append(CPPDEFINES=['PARTIAL_FUNC_READS'])
+
if env['BUILD_GPU']:
SimObject('GPUCoalescer.py')
SimObject('RubySystem.py')
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 012441d..59e54a8 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -328,6 +328,7 @@
GPUCoalescer* getGPUCoalescer() const;
bool functionalReadBuffers(PacketPtr&);
+bool functionalReadBuffers(PacketPtr&, WriteMask&);
int functionalWriteBuffers(PacketPtr&);
void countTransition(${ident}_State state, ${ident}_Event event);
@@ -1182,6 +1183,27 @@
code('''
return false;
}
+
+bool
+$c_ident::functionalReadBuffers(PacketPtr& pkt, WriteMask &mask)
+{
+bool read = false;
+''')
+for var in self.objects:
+vtype = var.type
+if vtype.isBuffer:
+vid = "m_%s_ptr" % var.ident
+code('if ($vid->functionalRead(pkt, mask)) read = true;')
+
+ for var in self.config_parameters:
+vtype = var.type_ast.type
+if vtype.isBuffer:
+ vid = "m_%s_ptr" % var.ident
+ code('if ($vid->functionalRead(pkt, mask)) read = true;')
+
+code('''
+return read;
+}
''')
code.write(path, "%s.cc" % c_ident)
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: RubyRequest getter for request ptr
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41814 )
Change subject: mem-ruby: RubyRequest getter for request ptr
..
mem-ruby: RubyRequest getter for request ptr
Change-Id: Ib3d12c9030d18d96388dd66f0a409b42543ee9a8
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 0eb10a7..c2f2c9d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -50,6 +50,7 @@
external_type(Addr, primitive="yes");
external_type(Cycles, primitive="yes", default="Cycles(0)");
external_type(Tick, primitive="yes", default="0");
+external_type(RequestPtr, primitive="yes", default="nullptr");
structure(WriteMask, external="yes", desc="...") {
void clear();
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 339e99a..c3a2f2d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -170,6 +170,8 @@
PacketPtr pkt, desc="Packet associated with this request";
bool htmFromTransaction, desc="Memory request originates within a HTM
transaction";
int htmTransactionUid, desc="Used to identify the unique HTM
transaction that produced this request";
+
+ RequestPtr getRequestPtr();
}
structure(AbstractCacheEntry, primitive="yes", external = "yes") {
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh
b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 55b645e..3a2f486 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -154,6 +154,7 @@
const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
const int& getSize() const { return m_Size; }
const PrefetchBit& getPrefetch() const { return m_Prefetch; }
+RequestPtr getRequestPtr() const { return m_pkt->req; }
void print(std::ostream& out) const;
bool functionalRead(Packet *pkt);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed Message copy constructors
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41813 )
Change subject: mem-ruby: removed Message copy constructors
..
mem-ruby: removed Message copy constructors
Prevents error with deprecated implicitly-declared operator= when
Message assignment operator is used.
The copy constructor in the Message class and the ones generated from
SLICC are not doing anything special so use the compiler-generated ones
instead.
Change-Id: I0edec4a44cbb7858f07ed2f2f189455994055c33
Signed-off-by: Tiago Mück
---
M src/mem/ruby/slicc_interface/Message.hh
M src/mem/slicc/symbols/Type.py
2 files changed, 3 insertions(+), 24 deletions(-)
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index d7acd2c..b8449e7 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -62,12 +62,7 @@
m_DelayedTicks(0), m_msg_counter(0)
{ }
-Message(const Message &other)
-: m_time(other.m_time),
- m_LastEnqueueTime(other.m_LastEnqueueTime),
- m_DelayedTicks(other.m_DelayedTicks),
- m_msg_counter(other.m_msg_counter)
-{ }
+Message(const Message &other) = default;
virtual ~Message() { }
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 4e064b5..85a3c41 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -259,23 +259,7 @@
code('}')
# Copy constructor
-if not self.isGlobal:
-code('${{self.c_ident}}(const ${{self.c_ident}}&other)')
-
-# Call superclass constructor
-if "interface" in self:
-code(': ${{self["interface"]}}(other)')
-
-code('{')
-code.indent()
-
-for dm in self.data_members.values():
-code('m_${{dm.ident}} = other.m_${{dm.ident}};')
-
-code.dedent()
-code('}')
-else:
-code('${{self.c_ident}}(const ${{self.c_ident}}&) = default;')
+code('${{self.c_ident}}(const ${{self.c_ident}}&) = default;')
# Assignment operator
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: renamed prefetch stats
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41816 )
Change subject: mem-ruby: renamed prefetch stats
..
mem-ruby: renamed prefetch stats
Splitting hw_prefetches into prefetch_hits and prefetch_misses so both
events can be tracked separately. Also added appropriate functions to
increment stats. Renamed m_prefetches for consistency.
sw_prefetches is not used and has been removed. The sequencer converts
SW prefetch requests into a RubyRequestType_LD/RubyRequestType_ST
which are handled as demand requests by the all current protocols.
Change-Id: Iafa6b31c84843ddd1fad98fa7e5afed02b8c4b4d
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
3 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index c3a2f2d..e5ecb00 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -215,6 +215,8 @@
void profileDemandHit();
void profileDemandMiss();
+ void profilePrefetchHit();
+ void profilePrefetchMiss();
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
diff --git a/src/mem/ruby/structures/CacheMemory.cc
b/src/mem/ruby/structures/CacheMemory.cc
index 8d98ef3..1436e9a 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -533,10 +533,10 @@
ADD_STAT(m_demand_misses, "Number of cache demand misses"),
ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
m_demand_hits + m_demand_misses),
- ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
- ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
- ADD_STAT(m_prefetches, "Number of prefetches",
- m_sw_prefetches + m_hw_prefetches),
+ ADD_STAT(m_prefetch_hits, "Number of cache prefetch hits"),
+ ADD_STAT(m_prefetch_misses, "Number of cache prefetch misses"),
+ ADD_STAT(m_prefetch_accesses, "Number of cache prefetch accesses",
+ m_prefetch_hits + m_prefetch_misses),
ADD_STAT(m_accessModeType, "")
{
numDataArrayReads
@@ -573,13 +573,13 @@
.init(8)
.flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
-m_sw_prefetches
+m_prefetch_hits
.flags(Stats::nozero);
-m_hw_prefetches
+m_prefetch_misses
.flags(Stats::nozero);
-m_prefetches
+m_prefetch_accesses
.flags(Stats::nozero);
m_accessModeType
@@ -747,3 +747,16 @@
{
cacheMemoryStats.m_demand_misses++;
}
+
+void
+CacheMemory::profilePrefetchHit()
+{
+cacheMemoryStats.m_prefetch_hits++;
+}
+
+void
+CacheMemory::profilePrefetchMiss()
+{
+cacheMemoryStats.m_prefetch_misses++;
+}
+
diff --git a/src/mem/ruby/structures/CacheMemory.hh
b/src/mem/ruby/structures/CacheMemory.hh
index 84b9d87..7b378f4 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -228,9 +228,9 @@
Stats::Scalar m_demand_misses;
Stats::Formula m_demand_accesses;
- Stats::Scalar m_sw_prefetches;
- Stats::Scalar m_hw_prefetches;
- Stats::Formula m_prefetches;
+ Stats::Scalar m_prefetch_hits;
+ Stats::Scalar m_prefetch_misses;
+ Stats::Formula m_prefetch_accesses;
Stats::Vector m_accessModeType;
} cacheMemoryStats;
@@ -240,6 +240,8 @@
// each time they are called
void profileDemandHit();
void profileDemandMiss();
+ void profilePrefetchHit();
+ void profilePrefetchMiss();
};
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: notify controller on coalescing
ach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, - const Cycles firstResponseTime); + const Cycles firstResponseTime, + const bool was_coalesced); void recordMissLatency(SequencerRequest* srequest, bool llscSuccess, const MachineType respondingMach, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41815 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia9c8d64cac2cd3ce859a76a1dc1324e3fc6a7b90 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs: Ruby fixes for SimpleMemory
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41817 ) Change subject: configs: Ruby fixes for SimpleMemory .. configs: Ruby fixes for SimpleMemory Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3 Signed-off-by: Tiago Mück --- M configs/ruby/Ruby.py 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 4779005..2bed341 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012, 2017-2018 ARM Limited +# Copyright (c) 2012, 2017-2018, 2021 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -131,13 +131,16 @@ dram_intf = MemConfig.create_mem_intf(mem_type, r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), intlv_size, options.xor_low_bit) -mem_ctrl = m5.objects.MemCtrl(dram = dram_intf) +if issubclass(mem_type, DRAMInterface): +mem_ctrl = m5.objects.MemCtrl(dram = dram_intf) +else: +mem_ctrl = dram_intf if options.access_backing_store: dram_intf.kvm_map=False mem_ctrls.append(mem_ctrl) -dir_ranges.append(mem_ctrl.dram.range) +dir_ranges.append(dram_intf.range) if crossbar != None: mem_ctrl.port = crossbar.master -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41817 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3 Gerrit-Change-Number: 41817 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: change NULL and ARM default protocol to CHI
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41819 ) Change subject: scons: change NULL and ARM default protocol to CHI .. scons: change NULL and ARM default protocol to CHI Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Signed-off-by: Tiago Mück --- M build_opts/ARM M build_opts/NULL 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build_opts/ARM b/build_opts/ARM index c473078..e4cb9a5 100644 --- a/build_opts/ARM +++ b/build_opts/ARM @@ -1,3 +1,3 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_CMP_directory' +PROTOCOL = 'CHI' diff --git a/build_opts/NULL b/build_opts/NULL index 1242fa9..de8b1dd 100644 --- a/build_opts/NULL +++ b/build_opts/NULL @@ -1,3 +1,3 @@ TARGET_ISA = 'null' CPU_MODELS = '' -PROTOCOL='MI_example' +PROTOCOL='CHI' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41819 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Gerrit-Change-Number: 41819 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: CHI-based Ruby protocol
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41818 ) Change subject: configs,mem-ruby: CHI-based Ruby protocol .. configs,mem-ruby: CHI-based Ruby protocol This patch add a new Ruby cache coherence protocol based on Arm' AMBA5 CHI specification. The CHI protocol defines and implements two state machine types: - Cache_Controller: generic cache controller that can be configured as: - Top-level L1 I/D cache - A intermediate level (L2, L3, ...) private or shared cache - A CHI home node (i.e. the point of coherence of the system and has the global directory) - A DMA requester - Memory_Controller: implements a CHI slave node and interfaces with gem5 memory controller. This controller has the functionality of a Directory_Controller on the other Ruby protocols, except it doesn't have a directory. The Cache_Controller has multiple cache allocation/deallocation parameters to control the clusivity with respect to upstream caches. Allocation can be completely disabled to use Cache_Controller as a DMA requester or as a home node without a shared LLC. The standard configuration file configs/ruby/CHI.py provides a 'create_system' compatible with configs/example/fs.py and configs/example/se.py and creates a system with private L1/L2 caches per core and a shared LLC at the home nodes. Different cache topologies can be defined by modifying 'create_system' or by creating custom scripts using the structures defined in configs/ruby/CHI.py. This patch also includes the 'CustomMesh' topology script to be used with CHI. CustomMesh generates a 2D mesh topology with the placement of components manually defined in a separate configuration file using the --noc-config parameter. The example in configs/example/noc_config/2x4.yaml creates a simple 2x4 mesh. For example, to run a SE mode simulation, with 4 cores, 4 mem ctnrls, and 4 home nodes (L3 caches): build/ARM/gem5.opt configs/example/se.py \ --cmd 'tests/test-progs/hello/bin/arm/linux/hello' \ --ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \ --topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml If one doesn't care about the component placement on the interconnect, the 'Crossbar' and 'Pt2Pt' may be used and they do not require the --noc-config option. Additional authors: Joshua Randall Pedro Benedicte Tuan Ta JIRA: https://gem5.atlassian.net/browse/GEM5-908 Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Signed-off-by: Tiago Mück --- A configs/example/noc_config/2x4.yaml A configs/ruby/CHI.py A configs/topologies/CustomMesh.py M src/mem/ruby/SConscript A src/mem/ruby/common/ExpectedMap.hh A src/mem/ruby/common/TriggerQueue.hh A src/mem/ruby/protocol/CHI-cache-actions.sm A src/mem/ruby/protocol/CHI-cache-funcs.sm A src/mem/ruby/protocol/CHI-cache-transitions.sm A src/mem/ruby/protocol/CHI-cache.sm A src/mem/ruby/protocol/CHI-mem.sm A src/mem/ruby/protocol/CHI-msg.sm A src/mem/ruby/protocol/CHI.slicc M src/mem/ruby/protocol/RubySlicc_Exports.sm M src/mem/ruby/protocol/SConsopts M src/mem/ruby/system/SConscript 16 files changed, 9,358 insertions(+), 2 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41818 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Gerrit-Change-Number: 41818 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: RubyRequest getter for request ptr
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41814 )
Change subject: mem-ruby: RubyRequest getter for request ptr
..
mem-ruby: RubyRequest getter for request ptr
Change-Id: Ib3d12c9030d18d96388dd66f0a409b42543ee9a8
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41814
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Exports.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/slicc_interface/RubyRequest.hh
3 files changed, 5 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index 0eb10a7..c2f2c9d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -50,6 +50,7 @@
external_type(Addr, primitive="yes");
external_type(Cycles, primitive="yes", default="Cycles(0)");
external_type(Tick, primitive="yes", default="0");
+external_type(RequestPtr, primitive="yes", default="nullptr");
structure(WriteMask, external="yes", desc="...") {
void clear();
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 339e99a..c3a2f2d 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -170,6 +170,8 @@
PacketPtr pkt, desc="Packet associated with this request";
bool htmFromTransaction, desc="Memory request originates within a HTM
transaction";
int htmTransactionUid, desc="Used to identify the unique HTM
transaction that produced this request";
+
+ RequestPtr getRequestPtr();
}
structure(AbstractCacheEntry, primitive="yes", external = "yes") {
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh
b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 55b645e..3a2f486 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -154,6 +154,7 @@
const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
const int& getSize() const { return m_Size; }
const PrefetchBit& getPrefetch() const { return m_Prefetch; }
+RequestPtr getRequestPtr() const { return m_pkt->req; }
void print(std::ostream& out) const;
bool functionalRead(Packet *pkt);
--
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Gerrit-Change-Id: Ib3d12c9030d18d96388dd66f0a409b42543ee9a8
Gerrit-Change-Number: 41814
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: removed Message copy constructors
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41813 )
Change subject: mem-ruby: removed Message copy constructors
..
mem-ruby: removed Message copy constructors
Prevents error with deprecated implicitly-declared operator= when
Message assignment operator is used.
The copy constructor in the Message class and the ones generated from
SLICC are not doing anything special so use the compiler-generated ones
instead.
Change-Id: I0edec4a44cbb7858f07ed2f2f189455994055c33
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41813
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/slicc_interface/Message.hh
M src/mem/slicc/symbols/Type.py
2 files changed, 3 insertions(+), 24 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/Message.hh
b/src/mem/ruby/slicc_interface/Message.hh
index d7acd2c..b8449e7 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -62,12 +62,7 @@
m_DelayedTicks(0), m_msg_counter(0)
{ }
-Message(const Message &other)
-: m_time(other.m_time),
- m_LastEnqueueTime(other.m_LastEnqueueTime),
- m_DelayedTicks(other.m_DelayedTicks),
- m_msg_counter(other.m_msg_counter)
-{ }
+Message(const Message &other) = default;
virtual ~Message() { }
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index 4e064b5..85a3c41 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020-2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -259,23 +259,7 @@
code('}')
# Copy constructor
-if not self.isGlobal:
-code('${{self.c_ident}}(const ${{self.c_ident}}&other)')
-
-# Call superclass constructor
-if "interface" in self:
-code(': ${{self["interface"]}}(other)')
-
-code('{')
-code.indent()
-
-for dm in self.data_members.values():
-code('m_${{dm.ident}} = other.m_${{dm.ident}};')
-
-code.dedent()
-code('}')
-else:
-code('${{self.c_ident}}(const ${{self.c_ident}}&) = default;')
+code('${{self.c_ident}}(const ${{self.c_ident}}&) = default;')
# Assignment operator
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I0edec4a44cbb7858f07ed2f2f189455994055c33
Gerrit-Change-Number: 41813
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: SimpleNetwork router latencies
Mask&);
uint32_t functionalWrite(Packet *);
+Cycles latency() const { return m_latency; }
+
+Tick latencyTicks() const { return cyclesToTicks(m_latency); }
+
private:
// Private copy constructor and assignment operator
Switch(const Switch& obj);
@@ -103,6 +113,8 @@
SimpleNetwork* m_network_ptr;
std::list throttles;
+const Cycles m_latency;
+
unsigned m_num_connected_buffers;
std::vector m_port_buffers;
diff --git a/src/mem/ruby/network/simple/Throttle.cc
b/src/mem/ruby/network/simple/Throttle.cc
index a6aa51b..f3dd82c 100644
--- a/src/mem/ruby/network/simple/Throttle.cc
+++ b/src/mem/ruby/network/simple/Throttle.cc
@@ -60,7 +60,7 @@
Throttle::Throttle(int sID, RubySystem *rs, NodeID node, Cycles
link_latency,
int endpoint_bandwidth, Switch *em)
-: Consumer(em),
+: Consumer(em, Switch::THROTTLE_EV_PRI),
m_switch_id(sID), m_switch(em), m_node(node),
m_physical_vnets(false), m_ruby_system(rs),
throttleStats(em, node)
--
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Gerrit-Change-Id: I6cae6a0fc22b25078c27a1e2f71744c08efd7753
Gerrit-Change-Number: 41856
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MI_example functional read
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41853 )
Change subject: mem-ruby: fix MI_example functional read
..
mem-ruby: fix MI_example functional read
Changing AccessPermission to Read_Write for transient states waiting
on memory when to or from Invalid. In all cases the memory will have
the latest data, so this also modifies functionalRead to always send
the access to memory.
Change-Id: I99f557539b4f9d0d2f99558752b7ddb7e85ab3c6
Signed-off-by: Tiago Mück
---
M src/mem/ruby/protocol/MI_example-dir.sm
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/src/mem/ruby/protocol/MI_example-dir.sm
b/src/mem/ruby/protocol/MI_example-dir.sm
index ed315e8..11d2862 100644
--- a/src/mem/ruby/protocol/MI_example-dir.sm
+++ b/src/mem/ruby/protocol/MI_example-dir.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
* Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -56,13 +68,17 @@
M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a
DMA read";
M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a
DMA write";
-M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
-M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
+M_DWRI, AccessPermission:Read_Write, desc="Intermediate state
M_DWR-->I";
+M_DRDI, AccessPermission:Read_Write, desc="Intermediate state
M_DRD-->I";
-IM, AccessPermission:Busy, desc="Intermediate state I-->M";
-MI, AccessPermission:Busy, desc="Intermediate state M-->I";
-ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when
in I";
-ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE
when in I";
+IM, AccessPermission:Read_Write, desc="Intermediate state I-->M";
+MI, AccessPermission:Read_Write, desc="Intermediate state M-->I";
+ID, AccessPermission:Read_Write, desc="Intermediate state for DMA_READ
when in I";
+ID_W, AccessPermission:Read_Write, desc="Intermediate state for
DMA_WRITE when in I";
+
+// Note: busy states when we wait for memory in transitions from or
to 'I'
+// have AccessPermission:Read_Write so this controller can get the
latest
+// data from memory during a functionalRead
}
// Events
@@ -180,12 +196,9 @@
}
void functionalRead(Addr addr, Packet *pkt) {
-TBE tbe := TBEs[addr];
-if(is_valid(tbe)) {
- testAndRead(addr, tbe.DataBlk, pkt);
-} else {
- functionalMemoryRead(pkt);
-}
+// if this is called; state is always either invalid or data was just
been WB
+// to memory (and we are waiting for an ack), so go directly to memory
+functionalMemoryRead(pkt);
}
int functionalWrite(Addr addr, Packet *pkt) {
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: dequeue rate limit for message buffers
all ready messages)") -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41862 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I3a446c7276b80a0e3f409b4fbab0ab65ff5c1f81 Gerrit-Change-Number: 41862 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Optionally set Consumer ev. priority
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41855 )
Change subject: mem-ruby: Optionally set Consumer ev. priority
..
mem-ruby: Optionally set Consumer ev. priority
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I62dc6656bbed4e7f4d575a6a82ac254382294ed1
Signed-off-by: Tiago Mück
---
M src/mem/ruby/common/Consumer.cc
M src/mem/ruby/common/Consumer.hh
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/common/Consumer.cc
b/src/mem/ruby/common/Consumer.cc
index fcaa132..bf11756 100644
--- a/src/mem/ruby/common/Consumer.cc
+++ b/src/mem/ruby/common/Consumer.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -40,9 +40,9 @@
#include "mem/ruby/common/Consumer.hh"
-Consumer::Consumer(ClockedObject *_em)
+Consumer::Consumer(ClockedObject *_em, Event::Priority ev_prio)
: m_wakeup_event([this]{ processCurrentEvent(); },
-"Consumer Event", false),
+"Consumer Event", false, ev_prio),
em(_em)
{ }
diff --git a/src/mem/ruby/common/Consumer.hh
b/src/mem/ruby/common/Consumer.hh
index 2c7065b..2d3c358 100644
--- a/src/mem/ruby/common/Consumer.hh
+++ b/src/mem/ruby/common/Consumer.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -55,7 +55,8 @@
class Consumer
{
public:
-Consumer(ClockedObject *_em);
+Consumer(ClockedObject *em,
+ Event::Priority ev_prio = Event::Default_Pri);
virtual
~Consumer()
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fixed SimpleNetwork starvation
e license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -99,11 +111,18 @@
std::vector m_link_order;
uint32_t m_virtual_networks;
-int m_round_robin_start;
int m_wakeups_wo_switch;
SimpleNetwork* m_network_ptr;
std::vector m_pending_message_count;
+
+MessageBuffer* inBuffer(int in_port, int vnet)
+{
+ if (m_in[in_port].size() <= vnet)
+ return nullptr;
+ else
+ return m_in[in_port][vnet];
+}
};
inline std::ostream&
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix SimpleNetwork WeightBased routing
dOutPort(const std::vector& out,
const NetDest& routing_table_entry,
-Cycles link_latency, int bw_multiplier,
+Cycles link_latency, int link_weight, int
bw_multiplier,
PortDirection dst_inport = "");
void resetStats();
diff --git a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
index 49140b8..830c341 100644
--- a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
+++ b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
@@ -65,7 +65,8 @@
virtual void addOutPort(LinkID link_id,
const std::vector& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction) = 0;
+ const PortDirection &direction,
+ int link_weight) = 0;
struct RouteInfo {
const NetDest m_destinations;
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.cc
b/src/mem/ruby/network/simple/routing/WeightBased.cc
index 3918642..2dd19cc 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.cc
+++ b/src/mem/ruby/network/simple/routing/WeightBased.cc
@@ -49,13 +49,15 @@
WeightBased::addOutPort(LinkID link_id,
const std::vector& m_out_buffer,
const NetDest& routing_table_entry,
-const PortDirection &direction)
+const PortDirection &direction,
+int link_weight)
{
assert(link_id == m_links.size());
m_links.push_back(new LinkInfo{link_id,
routing_table_entry,
m_out_buffer,
-(int)link_id});
+0, link_weight});
+sortLinks();
}
void
@@ -70,7 +72,7 @@
// Don't adaptively route
// Makes sure ordering is reset
for (auto link : m_links)
-link->m_order = (int) link->m_link_id;
+link->m_order = 0;
} else {
// Find how clogged each link is
for (auto link : m_links) {
@@ -85,11 +87,7 @@
link->m_order = value;
}
}
-
-std::sort(m_links.begin(), m_links.end(),
-[](const LinkInfo* a, const LinkInfo* b) {
-return a->m_order < b->m_order;
-});
+sortLinks();
}
findRoute(msg, m_links, out_links);
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.hh
b/src/mem/ruby/network/simple/routing/WeightBased.hh
index 6cb4a82..dda00df 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.hh
+++ b/src/mem/ruby/network/simple/routing/WeightBased.hh
@@ -57,7 +57,8 @@
void addOutPort(LinkID link_id,
const std::vector& m_out_buffer,
const NetDest& routing_table_entry,
-const PortDirection &direction);
+const PortDirection &direction,
+int link_weight);
void route(const Message &msg,
int vnet,
@@ -72,9 +73,24 @@
const NetDest m_routing_entry;
const std::vector m_out_buffers;
int m_order;
+int m_weight;
};
std::vector m_links;
+
+void sortLinks() {
+std::sort(m_links.begin(), m_links.end(),
+[](const LinkInfo* a, const LinkInfo* b) {
+if (a->m_order == b->m_order){
+if (a->m_weight == b->m_weight)
+return a->m_link_id < b->m_link_id;
+else
+return a->m_weight < b->m_weight;
+} else {
+return a->m_order < b->m_order;
+}
+});
+}
};
#endif // __MEM_RUBY_NETWORK_SIMPLE_WEIGHTBASEDROUTINGUNIT_HH__
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int/ext SimpleNetwork routing latency
outer(p),
-perfectSwitch(m_id, this, p.virt_nets), m_latency(p.latency),
+perfectSwitch(m_id, this, p.virt_nets),
+m_int_routing_latency(p.int_routing_latency),
+m_ext_routing_latency(p.ext_routing_latency),
m_routing_unit(*p.routing_unit), m_num_connected_buffers(0),
switchStats(this)
{
@@ -81,6 +83,7 @@
const NetDest& routing_table_entry,
Cycles link_latency, int link_weight,
int bw_multiplier,
+ bool is_external,
PortDirection dst_inport)
{
const std::vector &physical_vnets_channels =
@@ -116,9 +119,11 @@
intermediateBuffers.push_back(buffer_ptr);
}
+Tick routing_latency = is_external ?
cyclesToTicks(m_ext_routing_latency) :
+
cyclesToTicks(m_int_routing_latency);
// Hook the queues to the PerfectSwitch
perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
- dst_inport, link_weight);
+ dst_inport, routing_latency, link_weight);
// Hook the queues to the Throttle
throttles.back().addLinks(intermediateBuffers, out);
diff --git a/src/mem/ruby/network/simple/Switch.hh
b/src/mem/ruby/network/simple/Switch.hh
index 50a9eac..7a7878c 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -87,6 +87,7 @@
void addOutPort(const std::vector& out,
const NetDest& routing_table_entry,
Cycles link_latency, int link_weight, int
bw_multiplier,
+bool is_external,
PortDirection dst_inport = "");
void resetStats();
@@ -102,9 +103,8 @@
bool functionalRead(Packet *, WriteMask&);
uint32_t functionalWrite(Packet *);
-Cycles latency() const { return m_latency; }
-
-Tick latencyTicks() const { return cyclesToTicks(m_latency); }
+Cycles intRoutingLatency() const { return m_int_routing_latency; }
+Cycles extRoutingLatency() const { return m_ext_routing_latency; }
BaseRoutingUnit& getRoutingUnit() { return m_routing_unit; }
@@ -117,7 +117,8 @@
SimpleNetwork* m_network_ptr;
std::list throttles;
-const Cycles m_latency;
+const Cycles m_int_routing_latency;
+const Cycles m_ext_routing_latency;
BaseRoutingUnit &m_routing_unit;
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: refactor SimpleNetwork buffers
tworks buffers per
-# int_link port
-for i in range(int(self.number_of_virtual_networks)):
-network_buffers.append(MessageBuffer(ordered = True,
- buffer_size =
self.vnet_buffer_size(i)))
-network_buffers.append(MessageBuffer(ordered = True,
- buffer_size =
self.vnet_buffer_size(i)))
-self.int_link_buffers = network_buffers
-
-# Also add buffers for all router-link connections
+link.setup_buffers(self)
for router in self.routers:
-router_buffers = []
-# Add message buffers to routers at the end of each
-# unidirectional internal link
-for link in self.int_links:
-if link.dst_node == router:
-for i in range(int(self.number_of_virtual_networks)):
-router_buffers.append(MessageBuffer(ordered = True,
- allow_zero_latency = True,
- buffer_size =
self.vnet_buffer_size(i)))
-
-# Add message buffers to routers for each external link
connection
-for link in self.ext_links:
-# Routers can only be int_nodes on ext_links
-if link.int_node in self.routers:
-for i in range(int(self.number_of_virtual_networks)):
-router_buffers.append(MessageBuffer(ordered = True,
- allow_zero_latency = True,
- buffer_size =
self.vnet_buffer_size(i)))
-router.port_buffers = router_buffers
+router.setup_buffers(self)
class BaseRoutingUnit(SimObject):
@@ -126,8 +98,38 @@
cxx_header = 'mem/ruby/network/simple/Switch.hh'
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
+
+# Internal port buffers used between the PerfectSwitch and
+# Throttle objects. There is one buffer per virtual network
+# and per output port.
+# These are created by setup_buffers and the user should not
+# set these manually.
port_buffers = VectorParam.MessageBuffer("Port buffers")
routing_unit = Param.BaseRoutingUnit(
WeightBased(adaptive_routing = False),
"Routing strategy to be used")
+
+def setup_buffers(self, network):
+if hasattr(self, 'port_buffers') > 0:
+fatal("User should not manually set routers' port_buffers")
+router_buffers = []
+# Add message buffers to routers at the end of each
+# unidirectional internal link
+for link in network.int_links:
+if link.dst_node == self:
+for i in range(int(network.number_of_virtual_networks)):
+router_buffers.append(MessageBuffer(ordered = True,
+allow_zero_latency = True,
+buffer_size =
network.vnet_buffer_size(i)))
+
+# Add message buffers to routers for each external link connection
+for link in network.ext_links:
+# Routers can only be int_nodes on ext_links
+if link.int_node == self:
+for i in range(int(network.number_of_virtual_networks)):
+router_buffers.append(MessageBuffer(ordered = True,
+allow_zero_latency = True,
+buffer_size =
network.vnet_buffer_size(i)))
+
+self.port_buffers = router_buffers
--
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: SimpleNetwork physical channels
andwidth()));
+double ratio = 1.0 - (double(bw_remaining) /
+ double(getTotalLinkBandwidth()));
// If ratio = 0, we used no bandwidth, if ratio = 1, we used all
m_link_utilization_proxy += ratio;
-if (bw_remaining > 0 && !schedule_wakeup) {
+if (!schedule_wakeup) {
// We have extra bandwidth and our output buffer was
// available, so we must not have anything else to do until
// another message arrives.
@@ -245,7 +304,14 @@
void
Throttle::print(std::ostream& out) const
{
-ccprintf(out, "[%i bw: %i]", m_node, getLinkBandwidth());
+ccprintf(out, "[%i bw:", m_node);
+if (m_physical_vnets) {
+for (unsigned i = 0; i < m_vnets; ++i)
+ccprintf(out, " vnet%d=%i", i, getLinkBandwidth(i));
+} else {
+ccprintf(out, " %i", getTotalLinkBandwidth());
+}
+ccprintf(out, "]");
}
int
diff --git a/src/mem/ruby/network/simple/Throttle.hh
b/src/mem/ruby/network/simple/Throttle.hh
index 0d92041..9b5cfe6 100644
--- a/src/mem/ruby/network/simple/Throttle.hh
+++ b/src/mem/ruby/network/simple/Throttle.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -51,10 +63,17 @@
class Throttle : public Consumer
{
+ private:
+Throttle(int sID, RubySystem *rs, NodeID node, Cycles link_latency,
+ int endpoint_bandwidth, Switch *em);
public:
Throttle(int sID, RubySystem *rs, NodeID node, Cycles link_latency,
int link_bandwidth_multiplier, int endpoint_bandwidth,
Switch *em);
+Throttle(int sID, RubySystem *rs, NodeID node, Cycles link_latency,
+ const std::vector &vnet_channels,
+ const std::vector &vnet_bandwidth_multiplier,
+ int endpoint_bandwidth, Switch *em);
~Throttle() {}
std::string name()
@@ -70,8 +89,26 @@
const Stats::Vector & getMsgCount(unsigned int type) const
{ return *(throttleStats.m_msg_counts[type]); }
-int getLinkBandwidth() const
-{ return m_endpoint_bandwidth * m_link_bandwidth_multiplier; }
+int getLinkBandwidth(int vnet) const
+{
+return m_endpoint_bandwidth * (m_physical_vnets ?
+ m_link_bandwidth_multiplier[vnet] :
+ m_link_bandwidth_multiplier[0]);
+}
+
+int getTotalLinkBandwidth() const
+{
+int sum = getLinkBandwidth(0) * getChannelCnt(0);
+if (m_physical_vnets)
+ for (unsigned i = 1; i < m_vnets; ++i)
+sum += getLinkBandwidth(i) * getChannelCnt(i);
+return sum;
+}
+
+int getChannelCnt(int vnet) const
+{
+return m_physical_vnets ? m_vnet_channels[vnet] : 1;
+}
Cycles getLatency() const { return m_link_latency; }
@@ -83,7 +120,8 @@
private:
void init(NodeID node, Cycles link_latency, int
link_bandwidth_multiplier,
int endpoint_bandwidth);
-void operateVnet(int vnet, int &bw_remainin, bool &schedule_wakeup,
+void operateVnet(int vnet, int channel, int &total_bw_remaining,
+ bool &schedule_wakeup,
MessageBuffer *in, MessageBuffer *out);
// Private copy constructor and assignment operator
@@ -93,13 +131,15 @@
std::vector m_in;
std::vector m_out;
unsigned int m_vnets;
- std::vector m_units_remaining;
+std::vector> m_units_remaining;
const int m_switch_id;
Switch *m_switch;
NodeID m_node;
-int m_link_bandwidth_multiplier;
+bool m_physical_vnets;
+std::vector m_link_bandwidth_multiplier;
+std::vector m_vnet_channels;
Cycles m_link_latency;
int m_wakeups_wo_switch;
int m_endpoint_bandwidth;
--
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Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: refactored SimpleNetwork routing
), m_links.end(),
+[](const LinkInfo* a, const LinkInfo* b) {
+return a->m_order < b->m_order;
+});
+}
+
+findRoute(msg, m_links, out_links);
+}
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.hh
b/src/mem/ruby/network/simple/routing/WeightBased.hh
new file mode 100644
index 000..6cb4a82
--- /dev/null
+++ b/src/mem/ruby/network/simple/routing/WeightBased.hh
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_RUBY_NETWORK_SIMPLE_WEIGHTBASEDROUTINGUNIT_HH__
+#define __MEM_RUBY_NETWORK_SIMPLE_WEIGHTBASEDROUTINGUNIT_HH__
+
+#include "mem/ruby/network/simple/routing/BaseRoutingUnit.hh"
+#include "params/WeightBased.hh"
+
+class WeightBased : public BaseRoutingUnit
+{
+ public:
+typedef WeightBasedParams Params;
+
+WeightBased(const Params &p)
+ :BaseRoutingUnit(p), m_params(p)
+{
+}
+
+void addOutPort(LinkID link_id,
+const std::vector& m_out_buffer,
+ const NetDest& routing_table_entry,
+const PortDirection &direction);
+
+void route(const Message &msg,
+ int vnet,
+ bool deterministic,
+ std::vector &out_links);
+
+ private:
+const Params &m_params;
+
+struct LinkInfo {
+const LinkID m_link_id;
+const NetDest m_routing_entry;
+const std::vector m_out_buffers;
+int m_order;
+};
+
+std::vector m_links;
+};
+
+#endif // __MEM_RUBY_NETWORK_SIMPLE_WEIGHTBASEDROUTINGUNIT_HH__
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fine tunning SimpleNetwork buffers
,6 @@ for i in range(int(network.number_of_virtual_networks)): router_buffers.append(MessageBuffer(ordered = True, allow_zero_latency = True, -buffer_size = network.vnet_buffer_size(i))) +buffer_size = vnet_buffer_size(i))) self.port_buffers = router_buffers -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41863 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Id99ab745ed54686d8ffcc630d622fb07ac0fc352 Gerrit-Change-Number: 41863 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: tests: extend ruby_mem_test
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41867 )
Change subject: tests: extend ruby_mem_test
..
tests: extend ruby_mem_test
Replace ruby_mem_test by these tests which run different
configurations:
ruby_mem_test-garnet: use Garnet
ruby_mem_test-simple: use SimpleNetwork (same as original ruby_mem_test)
ruby_mem_test-simple-extra: use SimpleNetwork with
--simple-physical-channels and --simple-trace-routes options
ruby_mem_test-simple-extra-multicore: same as previous using 4 cores
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I7716cd222dd56ddbf06f53f92ec9b568ed5a182c
Signed-off-by: Tiago Mück
---
M tests/gem5/memory/test.py
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/tests/gem5/memory/test.py b/tests/gem5/memory/test.py
index db20ab5..8beca78 100644
--- a/tests/gem5/memory/test.py
+++ b/tests/gem5/memory/test.py
@@ -68,17 +68,31 @@
)
null_tests = [
-('garnet_synth_traffic', ['--sim-cycles', '500']),
-('memcheck', ['--maxtick', '20', '--prefetchers']),
-('ruby_mem_test', ['--abs-max-tick', '2000',
-'--functional', '10']),
-('ruby_random_test', ['--maxloads', '5000']),
-('ruby_direct_test', ['--requests', '5']),
+('garnet_synth_traffic', None, ['--sim-cycles', '500']),
+('memcheck', None, ['--maxtick', '20', '--prefetchers']),
+('ruby_mem_test-garnet', 'ruby_mem_test',
+['--abs-max-tick', '2000', '--functional', '10', \
+ '--network=garnet']),
+('ruby_mem_test-simple', 'ruby_mem_test',
+['--abs-max-tick', '2000', '--functional', '10', \
+ '--network=simple']),
+('ruby_mem_test-simple-extra', 'ruby_mem_test',
+['--abs-max-tick', '2000', '--functional', '10', \
+ '--network=simple', '--simple-physical-channels',
+ '--simple-trace-routes']),
+('ruby_mem_test-simple-extra-multicore', 'ruby_mem_test',
+['--abs-max-tick', '2000', '--functional', '10', \
+ '--network=simple', '--simple-physical-channels',
+ '--simple-trace-routes', '--num-cpus=4']),
+('ruby_random_test', None, ['--maxloads', '5000']),
+ ('ruby_direct_test', None, ['--requests', '5']),
]
-for basename_noext, args in null_tests:
+for test_name, basename_noext, args in null_tests:
+if basename_noext == None:
+basename_noext = test_name
gem5_verify_config(
-name=basename_noext,
+name=test_name,
fixtures=(),
verifiers=(),
config=joinpath(config.base_dir, 'configs',
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional SimpleNetwork stats
stall_cy += 1;
+
+if (!bw_saturated && !output_blocked) {
// We have extra bandwidth and our output buffer was
// available, so we must not have anything else to do until
// another message arrives.
@@ -332,7 +348,33 @@
Throttle::
ThrottleStats::ThrottleStats(Stats::Group *parent, const NodeID &nodeID)
: Stats::Group(parent, csprintf("throttle%02i", nodeID).c_str()),
- m_link_utilization(this, "link_utilization")
+ m_link_utilization(this, "link_utilization"),
+ m_total_msg_count(this, "total_msg_count",
+"Total number of messages forwarded by this switch"),
+ m_total_msg_bytes(this, "total_msg_bytes",
+"Total number of bytes forwarded by this switch"),
+ m_total_data_msg_bytes(this, "total_data_msg_bytes",
+"Total number of data bytes forwarded by this switch"),
+ m_total_msg_wait_time(this, "total_msg_wait_time",
+"Total time spend forwarding messages"),
+ m_total_stall_cy(this, "total_stall_cy",
+"Total time spent blocked on any output link"),
+ m_total_bw_sat_cy(this, "total_bw_sat_cy",
+"Total time bandwidth was saturated on any output link"),
+ m_avg_msg_wait_time(this, "avg_msg_wait_time",
+"Average time a message took to be forwarded"),
+ m_avg_bandwidth(this, "avg_bandwidth",
+"Average bandwidth (GB/s)"),
+ m_avg_useful_bandwidth(this, "avg_useful_bandwidth",
+"Average usefull (only data) bandwidth (GB/s)")
{
+m_avg_msg_wait_time = m_total_msg_wait_time / m_total_msg_count;
+m_avg_bandwidth.precision(2);
+m_avg_bandwidth = (m_total_msg_bytes / simSeconds) /
+ Stats::constant(1024*1024*1024);
+
+m_avg_useful_bandwidth.precision(2);
+m_avg_useful_bandwidth = (m_total_data_msg_bytes / simSeconds) /
+ Stats::constant(1024*1024*1024);
}
diff --git a/src/mem/ruby/network/simple/Throttle.hh
b/src/mem/ruby/network/simple/Throttle.hh
index 9b5cfe6..44da830 100644
--- a/src/mem/ruby/network/simple/Throttle.hh
+++ b/src/mem/ruby/network/simple/Throttle.hh
@@ -121,7 +121,7 @@
void init(NodeID node, Cycles link_latency, int
link_bandwidth_multiplier,
int endpoint_bandwidth);
void operateVnet(int vnet, int channel, int &total_bw_remaining,
- bool &schedule_wakeup,
+ bool &bw_saturated, bool &output_blocked,
MessageBuffer *in, MessageBuffer *out);
// Private copy constructor and assignment operator
@@ -156,6 +156,16 @@
Stats::Scalar m_link_utilization;
Stats::Vector* m_msg_counts[MessageSizeType_NUM];
Stats::Formula* m_msg_bytes[MessageSizeType_NUM];
+
+Stats::Scalar m_total_msg_count;
+Stats::Scalar m_total_msg_bytes;
+Stats::Scalar m_total_data_msg_bytes;
+Stats::Scalar m_total_msg_wait_time;
+Stats::Scalar m_total_stall_cy;
+Stats::Scalar m_total_bw_sat_cy;
+Stats::Formula m_avg_msg_wait_time;
+ Stats::Formula m_avg_bandwidth;
+Stats::Formula m_avg_useful_bandwidth;
} throttleStats;
};
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add priorities in SimpleNetwork routing
ncoming = 0;
-Tick lowest_tick = MaxTick;
-for (int counter = 0; counter < m_in.size(); ++counter) {
-MessageBuffer *buffer = inBuffer(counter, vnet);
-if (buffer == nullptr)
-continue;
-if (buffer->readyTime() < lowest_tick){
-lowest_tick = buffer->readyTime();
-incoming = counter;
+// iterate over priority levels for this vnet
+for (auto &in : m_in_prio_groups[vnet]) {
+// first check the port with the oldest message
+unsigned incoming = 0;
+Tick lowest_tick = MaxTick;
+for (int counter = 0; counter < in.size(); ++counter) {
+MessageBuffer *buffer = in[counter];
+if (buffer == nullptr)
+continue;
+if (buffer->readyTime() < lowest_tick){
+lowest_tick = buffer->readyTime();
+incoming = counter;
+}
}
-}
-DPRINTF(RubyNetwork, "vnet %d: %d pending msgs. "
- "Checking port %d first\n",
-vnet, m_pending_message_count[vnet], incoming);
-// check all ports starting with the one with the oldest message
-for (int counter = 0; counter < m_in.size();
- ++counter, incoming = (incoming + 1) % m_in.size()) {
-MessageBuffer *buffer = inBuffer(incoming, vnet);
-if (buffer == nullptr)
-continue;
-operateMessageBuffer(buffer, incoming, vnet);
+DPRINTF(RubyNetwork, "vnet %d: %d pending msgs. "
+"Checking port %d (%s) first\n",
+vnet, m_pending_message_count[vnet],
+in[incoming]->getIncomingLink(), in[incoming]);
+// check all ports starting with the one with the oldest
message
+for (int counter = 0; counter < in.size();
+++counter, incoming = (incoming + 1) % in.size()) {
+MessageBuffer *buffer = in[incoming];
+if (buffer == nullptr)
+continue;
+operateMessageBuffer(buffer, vnet);
+}
}
}
}
void
-PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
-int vnet)
+PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int vnet)
{
MsgPtr msg_ptr;
Message *net_msg_ptr = NULL;
@@ -149,7 +181,7 @@
Tick current_time = m_switch->clockEdge();
while (buffer->isReady(current_time)) {
-DPRINTF(RubyNetwork, "incoming: %d\n", incoming);
+DPRINTF(RubyNetwork, "incoming: %d\n", buffer->getIncomingLink());
// Peek at message
msg_ptr = buffer->peekMsgPtr();
@@ -219,7 +251,7 @@
// Enqeue msg
DPRINTF(RubyNetwork, "Enqueuing net msg from "
"inport[%d][%d] to outport [%d][%d].\n",
-incoming, vnet, outgoing, vnet);
+buffer->getIncomingLink(), vnet, outgoing, vnet);
m_out[outgoing][vnet]->enqueue(msg_ptr, current_time,
m_out_latencies[outgoing]);
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index d4f35e3..52af132 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -94,7 +94,7 @@
PerfectSwitch& operator=(const PerfectSwitch& obj);
void operateVnet(int vnet);
-void operateMessageBuffer(MessageBuffer *b, int incoming, int vnet);
+void operateMessageBuffer(MessageBuffer *b, int vnet);
const SwitchID m_switch_id;
Switch * const m_switch;
@@ -106,6 +106,13 @@
// latency for routing to each out port
std::vector m_out_latencies;
+// input ports ordered by priority; indexed by vnet first
+std::vector > m_in_prio;
+// input ports grouped by priority; indexed by vnet,prio_lv
+std::vector>> m_in_prio_groups;
+
+void updatePriorityGroups(int vnet, MessageBuffer* buf);
+
uint32_t m_virtual_networks;
int m_wakeups_wo_switch;
--
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[gem5-dev] Change in gem5/gem5[develop]: configs,mem-ruby: dumps network route profile
e
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -43,7 +55,7 @@
TimerTable();
void
-setConsumer(Consumer* consumer_ptr)
+setConsumer(Consumer* consumer_ptr, bool is_inport = false)
{
assert(m_consumer_ptr == NULL);
m_consumer_ptr = consumer_ptr;
diff --git a/src/mem/ruby/structures/WireBuffer.hh
b/src/mem/ruby/structures/WireBuffer.hh
index be861ec..63a1f76 100644
--- a/src/mem/ruby/structures/WireBuffer.hh
+++ b/src/mem/ruby/structures/WireBuffer.hh
@@ -64,7 +64,7 @@
void wakeup();
-void setConsumer(Consumer* consumer_ptr)
+void setConsumer(Consumer* consumer_ptr, bool is_inport = false)
{
m_consumer_ptr = consumer_ptr;
}
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 59e54a8..5a028ec 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -681,7 +681,7 @@
code()
for port in self.in_ports:
# Set the queue consumers
-code('${{port.code}}.setConsumer(this);')
+code('${{port.code}}.setConsumer(this, true);')
# Initialize the transition profiling
code()
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MI_example functional read
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41853 )
Change subject: mem-ruby: fix MI_example functional read
..
mem-ruby: fix MI_example functional read
Changing AccessPermission to Read_Write for transient states waiting
on memory when to or from Invalid. In all cases the memory will have
the latest data, so this also modifies functionalRead to always send
the access to memory.
Change-Id: I99f557539b4f9d0d2f99558752b7ddb7e85ab3c6
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41853
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/MI_example-dir.sm
1 file changed, 25 insertions(+), 12 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/MI_example-dir.sm
b/src/mem/ruby/protocol/MI_example-dir.sm
index ed315e8..11d2862 100644
--- a/src/mem/ruby/protocol/MI_example-dir.sm
+++ b/src/mem/ruby/protocol/MI_example-dir.sm
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
* Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
* All rights reserved.
@@ -56,13 +68,17 @@
M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a
DMA read";
M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a
DMA write";
-M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
-M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
+M_DWRI, AccessPermission:Read_Write, desc="Intermediate state
M_DWR-->I";
+M_DRDI, AccessPermission:Read_Write, desc="Intermediate state
M_DRD-->I";
-IM, AccessPermission:Busy, desc="Intermediate state I-->M";
-MI, AccessPermission:Busy, desc="Intermediate state M-->I";
-ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when
in I";
-ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE
when in I";
+IM, AccessPermission:Read_Write, desc="Intermediate state I-->M";
+MI, AccessPermission:Read_Write, desc="Intermediate state M-->I";
+ID, AccessPermission:Read_Write, desc="Intermediate state for DMA_READ
when in I";
+ID_W, AccessPermission:Read_Write, desc="Intermediate state for
DMA_WRITE when in I";
+
+// Note: busy states when we wait for memory in transitions from or
to 'I'
+// have AccessPermission:Read_Write so this controller can get the
latest
+// data from memory during a functionalRead
}
// Events
@@ -180,12 +196,9 @@
}
void functionalRead(Addr addr, Packet *pkt) {
-TBE tbe := TBEs[addr];
-if(is_valid(tbe)) {
- testAndRead(addr, tbe.DataBlk, pkt);
-} else {
- functionalMemoryRead(pkt);
-}
+// if this is called; state is always either invalid or data was just
been WB
+// to memory (and we are waiting for an ack), so go directly to memory
+functionalMemoryRead(pkt);
}
int functionalWrite(Addr addr, Packet *pkt) {
--
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Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: notify controller on coalescing
t (c) 2019-2020 ARM Limited + * Copyright (c) 2019-2021 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -193,7 +193,8 @@ const MachineType mach, const bool externalHit, const Cycles initialRequestTime, const Cycles forwardRequestTime, - const Cycles firstResponseTime); + const Cycles firstResponseTime, + const bool was_coalesced); void recordMissLatency(SequencerRequest* srequest, bool llscSuccess, const MachineType respondingMach, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41815 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia9c8d64cac2cd3ce859a76a1dc1324e3fc6a7b90 Gerrit-Change-Number: 41815 Gerrit-PatchSet: 2 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: renamed prefetch stats
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41816 )
Change subject: mem-ruby: renamed prefetch stats
..
mem-ruby: renamed prefetch stats
Splitting hw_prefetches into prefetch_hits and prefetch_misses so both
events can be tracked separately. Also added appropriate functions to
increment stats. Renamed m_prefetches for consistency.
sw_prefetches is not used and has been removed. The sequencer converts
SW prefetch requests into a RubyRequestType_LD/RubyRequestType_ST
which are handled as demand requests by the all current protocols.
Change-Id: Iafa6b31c84843ddd1fad98fa7e5afed02b8c4b4d
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41816
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.cc
M src/mem/ruby/structures/CacheMemory.hh
3 files changed, 29 insertions(+), 12 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index c3a2f2d..e5ecb00 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -215,6 +215,8 @@
void profileDemandHit();
void profileDemandMiss();
+ void profilePrefetchHit();
+ void profilePrefetchMiss();
}
structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
diff --git a/src/mem/ruby/structures/CacheMemory.cc
b/src/mem/ruby/structures/CacheMemory.cc
index 8d98ef3..1436e9a 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -533,10 +533,10 @@
ADD_STAT(m_demand_misses, "Number of cache demand misses"),
ADD_STAT(m_demand_accesses, "Number of cache demand accesses",
m_demand_hits + m_demand_misses),
- ADD_STAT(m_sw_prefetches, "Number of software prefetches"),
- ADD_STAT(m_hw_prefetches, "Number of hardware prefetches"),
- ADD_STAT(m_prefetches, "Number of prefetches",
- m_sw_prefetches + m_hw_prefetches),
+ ADD_STAT(m_prefetch_hits, "Number of cache prefetch hits"),
+ ADD_STAT(m_prefetch_misses, "Number of cache prefetch misses"),
+ ADD_STAT(m_prefetch_accesses, "Number of cache prefetch accesses",
+ m_prefetch_hits + m_prefetch_misses),
ADD_STAT(m_accessModeType, "")
{
numDataArrayReads
@@ -573,13 +573,13 @@
.init(8)
.flags(Stats::pdf | Stats::dist | Stats::nozero | Stats::nonan);
-m_sw_prefetches
+m_prefetch_hits
.flags(Stats::nozero);
-m_hw_prefetches
+m_prefetch_misses
.flags(Stats::nozero);
-m_prefetches
+m_prefetch_accesses
.flags(Stats::nozero);
m_accessModeType
@@ -747,3 +747,16 @@
{
cacheMemoryStats.m_demand_misses++;
}
+
+void
+CacheMemory::profilePrefetchHit()
+{
+cacheMemoryStats.m_prefetch_hits++;
+}
+
+void
+CacheMemory::profilePrefetchMiss()
+{
+cacheMemoryStats.m_prefetch_misses++;
+}
+
diff --git a/src/mem/ruby/structures/CacheMemory.hh
b/src/mem/ruby/structures/CacheMemory.hh
index 84b9d87..7b378f4 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -228,9 +228,9 @@
Stats::Scalar m_demand_misses;
Stats::Formula m_demand_accesses;
- Stats::Scalar m_sw_prefetches;
- Stats::Scalar m_hw_prefetches;
- Stats::Formula m_prefetches;
+ Stats::Scalar m_prefetch_hits;
+ Stats::Scalar m_prefetch_misses;
+ Stats::Formula m_prefetch_accesses;
Stats::Vector m_accessModeType;
} cacheMemoryStats;
@@ -240,6 +240,8 @@
// each time they are called
void profileDemandHit();
void profileDemandMiss();
+ void profilePrefetchHit();
+ void profilePrefetchMiss();
};
std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
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[gem5-dev] Change in gem5/gem5[develop]: configs: Ruby fixes for SimpleMemory
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/41817 ) Change subject: configs: Ruby fixes for SimpleMemory .. configs: Ruby fixes for SimpleMemory Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41817 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M configs/ruby/Ruby.py 1 file changed, 6 insertions(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 4779005..2bed341 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -1,4 +1,4 @@ -# Copyright (c) 2012, 2017-2018 ARM Limited +# Copyright (c) 2012, 2017-2018, 2021 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -131,13 +131,16 @@ dram_intf = MemConfig.create_mem_intf(mem_type, r, index, options.num_dirs, int(math.log(options.num_dirs, 2)), intlv_size, options.xor_low_bit) -mem_ctrl = m5.objects.MemCtrl(dram = dram_intf) +if issubclass(mem_type, DRAMInterface): +mem_ctrl = m5.objects.MemCtrl(dram = dram_intf) +else: +mem_ctrl = dram_intf if options.access_backing_store: dram_intf.kvm_map=False mem_ctrls.append(mem_ctrl) -dir_ranges.append(mem_ctrl.dram.range) +dir_ranges.append(dram_intf.range) if crossbar != None: mem_ctrl.port = crossbar.master 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41817 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Idc21c8c616ef953d161685ec459765ef21ac9bc3 Gerrit-Change-Number: 41817 Gerrit-PatchSet: 3 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Add Vega as a copy of gcn3
Alexandru Duțu has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42204 ) Change subject: arch-vega: Add Vega as a copy of gcn3 .. arch-vega: Add Vega as a copy of gcn3 Configs that looked for gcn3 are modified to look for either gcn3 or vega, this may not be the proper implementation Change-Id: I608aa6747a45594f8e1bd7802da1883cf612168b --- M src/arch/SConscript A src/arch/amdgpu/vega/SConscript A src/arch/amdgpu/vega/SConsopts A src/arch/amdgpu/vega/decoder.cc A src/arch/amdgpu/vega/gpu_decoder.hh A src/arch/amdgpu/vega/gpu_isa.hh A src/arch/amdgpu/vega/gpu_mem_helpers.hh A src/arch/amdgpu/vega/gpu_registers.hh A src/arch/amdgpu/vega/gpu_types.hh A src/arch/amdgpu/vega/insts/gpu_static_inst.cc A src/arch/amdgpu/vega/insts/gpu_static_inst.hh A src/arch/amdgpu/vega/insts/inst_util.hh A src/arch/amdgpu/vega/insts/instructions.cc A src/arch/amdgpu/vega/insts/instructions.hh A src/arch/amdgpu/vega/insts/op_encodings.cc A src/arch/amdgpu/vega/insts/op_encodings.hh A src/arch/amdgpu/vega/isa.cc A src/arch/amdgpu/vega/operand.hh A src/arch/amdgpu/vega/registers.cc 19 files changed, 144,264 insertions(+), 1 deletion(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42204 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I608aa6747a45594f8e1bd7802da1883cf612168b Gerrit-Change-Number: 42204 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandru Duțu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Remove unused functions
Alexandru Duțu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42202 )
Change subject: gpu-compute: Remove unused functions
..
gpu-compute: Remove unused functions
These functions were probably used for some stat collection,
but they're no longer used, so they're being removed
Change-Id: Ic99f22391c0d5ffb0e9963670efb35e503f9957d
---
M src/gpu-compute/gpu_dyn_inst.cc
M src/gpu-compute/gpu_dyn_inst.hh
2 files changed, 0 insertions(+), 37 deletions(-)
diff --git a/src/gpu-compute/gpu_dyn_inst.cc
b/src/gpu-compute/gpu_dyn_inst.cc
index b827632..b9b23d4 100644
--- a/src/gpu-compute/gpu_dyn_inst.cc
+++ b/src/gpu-compute/gpu_dyn_inst.cc
@@ -268,40 +268,6 @@
return _staticInst->executed_as;
}
-bool
-GPUDynInst::hasVgprRawDependence(GPUDynInstPtr s)
-{
-assert(s);
-for (int i = 0; i < getNumOperands(); ++i) {
-if (isVectorRegister(i) && isSrcOperand(i)) {
-for (int j = 0; j < s->getNumOperands(); ++j) {
-if (s->isVectorRegister(j) && s->isDstOperand(j)) {
-if (i == j)
-return true;
-}
-}
-}
-}
-return false;
-}
-
-bool
-GPUDynInst::hasSgprRawDependence(GPUDynInstPtr s)
-{
-assert(s);
-for (int i = 0; i < getNumOperands(); ++i) {
-if (isScalarRegister(i) && isSrcOperand(i)) {
-for (int j = 0; j < s->getNumOperands(); ++j) {
-if (s->isScalarRegister(j) && s->isDstOperand(j)) {
-if (i == j)
-return true;
-}
-}
-}
-}
-return false;
-}
-
// Process a memory instruction and (if necessary) submit timing request
void
GPUDynInst::initiateAcc(GPUDynInstPtr gpuDynInst)
diff --git a/src/gpu-compute/gpu_dyn_inst.hh
b/src/gpu-compute/gpu_dyn_inst.hh
index 851a46a..97eea01 100644
--- a/src/gpu-compute/gpu_dyn_inst.hh
+++ b/src/gpu-compute/gpu_dyn_inst.hh
@@ -101,9 +101,6 @@
bool hasDestinationVgpr() const;
bool hasSourceVgpr() const;
-bool hasSgprRawDependence(GPUDynInstPtr s);
-bool hasVgprRawDependence(GPUDynInstPtr s);
-
// returns true if the string "opcodeStr" is found in the
// opcode of the instruction
bool isOpcode(const std::string& opcodeStr) const;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic99f22391c0d5ffb0e9963670efb35e503f9957d
Gerrit-Change-Number: 42202
Gerrit-PatchSet: 1
Gerrit-Owner: Alexandru Duțu
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Support dynamic scratch allocations
DPRINTF(GPUCommandProc, "Not enough scratch space to launch "
+"kernel (%x available, %x requested bytes per "
+"workitem). Asking host runtime to allocate more "
+"space.\n",
+task->amdQueue.compute_tmpring_size_wavesize * 1024,
+task->privMemPerItem());
+
+updateHsaSignal(task->amdQueue.queue_inactive_signal.handle, 1,
+[ = ] (const uint64_t &dma_buffer)
+{ WaitScratchDmaEvent(task, dma_buffer);
});
+
+} else {
+DPRINTF(GPUCommandProc, "Sufficient scratch space, launching "
+"kernel (%x available, %x requested bytes per "
+"workitem).\n",
+task->amdQueue.compute_tmpring_size_wavesize * 1024,
+task->privMemPerItem());
+dispatchPkt(task);
+}
+}
+
+/**
+ * Poll on queue_inactive signal until the runtime can get around to
+ * taking care of our lack of scratch space.
+ */
+void
+WaitScratchDmaEvent(HSAQueueEntry *task, const uint64_t &dmaBuffer)
{
- public:
-MQDDmaEvent(GPUCommandProcessor &gpu_cmd_proc, HSAQueueEntry *task)
-: DmaCallback(), gpuCmdProc(gpu_cmd_proc), _task(task)
-{
-}
+if (dmaBuffer == 0) {
+DPRINTF(GPUCommandProc, "Host scratch allocation complete. "
+"Attempting to re-read MQD\n");
+/**
+* Runtime will have updated the MQD to give us more scratch
+* space. Read it out and continue to pester the runtime until
+* we get all that we need to launch.
+*
+* TODO: Technically only need to update private segment fields
+* since other MQD entries won't change since we last read them.
+*/
+auto cb = new CPDmaCallback(
+[ = ] (const int &) { MQDDmaEvent(task); });
-void
-process() override
-{
-gpuCmdProc.dispatchPkt(_task);
+dmaReadVirt(task->hostAMDQueueAddr, sizeof(_amd_queue_t), cb,
+&task->amdQueue);
+} else {
+/**
+* Poll until runtime signals us that scratch space has been
+* allocated.
+*/
+Addr value_addr = getHsaSignalValueAddr(
+task->amdQueue.queue_inactive_signal.handle);
+DPRINTF(GPUCommandProc, "Polling queue inactive signal at "
+"%p.\n", value_addr);
+auto cb = new CPDmaCallback(
+[ = ] (const uint64_t &dma_buffer)
+{ WaitScratchDmaEvent(task, dma_buffer); } );
+dmaReadVirt(value_addr, sizeof(Addr), cb, &cb->dmaBuffer);
}
-
- private:
-GPUCommandProcessor &gpuCmdProc;
- HSAQueueEntry *_task;
-};
+}
};
#endif // __DEV_HSA_GPU_COMMAND_PROCESSOR_HH__
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Gerrit-Branch: develop
Gerrit-Change-Id: Ica8a5fc8283415507544d6cc49fa748fe84d
Gerrit-Change-Number: 42201
Gerrit-PatchSet: 1
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Gerrit-CC: Michael LeBeane
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Add decodings for Flat, Global, Scratch
_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_AND(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_OR(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_INC(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2(MachInst); +GPUStaticInst* decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2(MachInst); GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst); GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst); GPUStaticInst* decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst); @@ -823,6 +881,28 @@ GPUStaticInst* decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst); GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1(MachInst); GPUStaticInst* decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_USHORT(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_DWORD(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_BYTE(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_SHORT(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_DWORD(MachInst); + GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16(MachInst); +GPUStaticInst* decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI(MachInst); GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE(MachInst); GPUStaticInst* decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst); GPUStaticInst* decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42206 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I32feab747b13bd2eff98983e3281c0d82e756221 Gerrit-Change-Number: 42206 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandru Duțu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Update instruction encodings
Alexandru Duțu has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42205 ) Change subject: arch-vega: Update instruction encodings .. arch-vega: Update instruction encodings This also renames VOP3 and VOP3_SDST_ENC to VOP3A and VOP3B, matching the ISA. Change-Id: I56f254433b1f3181d4ee6896f957a2256e3c7b29 --- M src/arch/amdgpu/vega/decoder.cc M src/arch/amdgpu/vega/gpu_decoder.hh M src/arch/amdgpu/vega/insts/inst_util.hh M src/arch/amdgpu/vega/insts/instructions.cc M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.cc M src/arch/amdgpu/vega/insts/op_encodings.hh 7 files changed, 2,111 insertions(+), 2,063 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42205 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I56f254433b1f3181d4ee6896f957a2256e3c7b29 Gerrit-Change-Number: 42205 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandru Duțu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Add operand info class to GPUDynInst
x, int num_dwords,
+const std::vector &virt_indices,
+const std::vector &phys_indices)
+: opIdx(op_idx), numDWORDs(num_dwords), virtIndices(virt_indices),
+ physIndices(phys_indices)
+{
+}
+
+/**
+ * The number of registers required to store this operand.
+ */
+int numRegisters() const { return numDWORDs /
TheGpuISA::RegSizeDWORDs; }
+int operandIdx() const { return opIdx; }
+/**
+ * We typically only need the first virtual register for the operand
+ * regardless of its size.
+ */
+int virtIdx(int reg_num=0) const { return virtIndices.at(reg_num); }
+
+ private:
+/**
+ * Index of this operand within the set of its parent instruction's
+ * operand list.
+ */
+const int opIdx;
+/**
+ * Size of this operand in DWORDs.
+ */
+const int numDWORDs;
+const std::vector virtIndices;
+const std::vector physIndices;
+};
+
class GPUDynInst : public GPUExecContext
{
public:
GPUDynInst(ComputeUnit *_cu, Wavefront *_wf, GPUStaticInst
*static_inst,
uint64_t instSeqNum);
~GPUDynInst();
+void initOperandInfo(GPUDynInstPtr &gpu_dyn_inst);
void execute(GPUDynInstPtr gpuDynInst);
+
+const std::vector&
+srcVecRegOperands() const
+{
+return srcVecRegOps;
+}
+
+const std::vector&
+dstVecRegOperands() const
+{
+return dstVecRegOps;
+}
+
+const std::vector&
+srcScalarRegOperands() const
+{
+return srcScalarRegOps;
+}
+
+const std::vector&
+dstScalarRegOperands() const
+{
+return dstScalarRegOps;
+}
+
+int numSrcVecRegOperands() const;
+int numDstVecRegOperands() const;
+int maxSrcVecRegOperandSize() const;
+int numSrcScalarRegOperands() const;
+int numDstScalarRegOperands() const;
+int maxSrcScalarRegOperandSize() const;
+
int numSrcRegOperands();
int numDstRegOperands();
-int numDstVecOperands();
-int numSrcVecOperands();
int numSrcVecDWORDs();
int numDstVecDWORDs();
int numOpdDWORDs(int operandIdx);
@@ -428,6 +496,8 @@
private:
GPUStaticInst *_staticInst;
const InstSeqNum _seqNum;
+int maxSrcVecRegOpSize;
+int maxSrcScalarRegOpSize;
// the time the request was started
Tick accessTime = -1;
@@ -439,6 +509,12 @@
// hold each cache block address for the instruction and a vector
// to hold the tick when the block arrives at certain hop points
std::map> lineAddressTime;
+
+// Operand info.
+std::vector srcVecRegOps;
+std::vector dstVecRegOps;
+std::vector srcScalarRegOps;
+std::vector dstScalarRegOps;
};
#endif // __GPU_DYN_INST_HH__
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index e442e2a..279aac7 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -904,8 +904,8 @@
}
computeUnit->srf[simdId]->waveExecuteInst(this, ii);
-computeUnit->shader->incVectorInstSrcOperand(ii->numSrcVecOperands());
-computeUnit->shader->incVectorInstDstOperand(ii->numDstVecOperands());
+
computeUnit->shader->incVectorInstSrcOperand(ii->numSrcVecRegOperands());
+
computeUnit->shader->incVectorInstDstOperand(ii->numDstVecRegOperands());
computeUnit->stats.numInstrExecuted++;
stats.numInstrExecuted++;
computeUnit->instExecPerSimd[simdId]++;
--
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Gerrit-Change-Id: I3cf267942e54fe60fcb4224d3b88da08a1a0226e
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3, gpu-compute: Update getRegisterIndex() API
; ii->getNumOperands(); i++) {
if (ii->isScalarRegister(i) && ii->isDstOperand(i)) {
-int sgprIdx = ii->getRegisterIndex(i, ii);
+int sgprIdx = ii->getRegisterIndex(i);
int nRegs = ii->getOperandSize(i) <= 4 ? 1
: ii->getOperandSize(i) / 4;
for (int j = 0; j < nRegs; j++) {
@@ -139,7 +139,7 @@
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isScalarRegister(i) && ii->isDstOperand(i)) {
-int sgprIdx = ii->getRegisterIndex(i, ii);
+int sgprIdx = ii->getRegisterIndex(i);
int nRegs = ii->getOperandSize(i) <= 4 ? 1 :
ii->getOperandSize(i) / 4;
diff --git a/src/gpu-compute/vector_register_file.cc
b/src/gpu-compute/vector_register_file.cc
index 40ce281..f162279 100644
--- a/src/gpu-compute/vector_register_file.cc
+++ b/src/gpu-compute/vector_register_file.cc
@@ -59,7 +59,7 @@
{
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i) && ii->isSrcOperand(i)) {
-int vgprIdx = ii->getRegisterIndex(i, ii);
+int vgprIdx = ii->getRegisterIndex(i);
// determine number of registers
int nRegs =
@@ -89,7 +89,7 @@
// iterate over all register destination operands
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
-int vgprIdx = ii->getRegisterIndex(i, ii);
+int vgprIdx = ii->getRegisterIndex(i);
int nRegs = ii->getOperandSize(i) <= 4 ? 1 :
ii->getOperandSize(i) / 4;
@@ -150,7 +150,7 @@
for (int i = 0; i < ii->getNumOperands(); i++) {
if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
-int vgprIdx = ii->getRegisterIndex(i, ii);
+int vgprIdx = ii->getRegisterIndex(i);
int nRegs = ii->getOperandSize(i) <= 4 ? 1
: ii->getOperandSize(i) / 4;
for (int j = 0; j < nRegs; j++) {
@@ -183,7 +183,7 @@
assert(ii->isLoad() || ii->isAtomicRet());
for (int i = 0; i < ii->getNumOperands(); ++i) {
if (ii->isVectorRegister(i) && ii->isDstOperand(i)) {
-int vgprIdx = ii->getRegisterIndex(i, ii);
+int vgprIdx = ii->getRegisterIndex(i);
int nRegs = ii->getOperandSize(i) <= 4 ? 1 :
ii->getOperandSize(i) / 4;
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
index 279aac7..0cb6675 100644
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -927,7 +927,7 @@
// vector RAW dependency tracking
for (int i = 0; i < ii->getNumOperands(); i++) {
if (ii->isVectorRegister(i)) {
-int vgpr = ii->getRegisterIndex(i, ii);
+int vgpr = ii->getRegisterIndex(i);
int nReg = ii->getOperandSize(i) <= 4 ? 1 :
ii->getOperandSize(i) / 4;
for (int n = 0; n < nReg; n++) {
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Update FLAT instructions to use offset
alcAddr(gpuDynInst, addr);
+calcAddr(gpuDynInst, addr, instData.OFFSET);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh
b/src/arch/amdgpu/vega/insts/op_encodings.hh
index bfff12d..39bfc65 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -791,11 +791,12 @@
}
void
-calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr)
+calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr,
+ ScalarRegU32 offset)
{
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
-gpuDynInst->addr.at(lane) = addr[lane];
+gpuDynInst->addr.at(lane) = addr[lane] + offset;
}
}
gpuDynInst->resolveFlatSegment(gpuDynInst->exec_mask);
--
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[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Fix doorbell mmap for APU
Alexandru Duțu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42218 )
Change subject: dev-hsa: Fix doorbell mmap for APU
..
dev-hsa: Fix doorbell mmap for APU
Commit id ef44dc9a removed mmap-based doorbell allocation since dGPUs
use ioctl's instead. However, APUs still need this to work correctly.
Add that logic back in as well as some new logic to distinguish doorbells
mmaps from other types. Also add some additional commentary regarding
Event page mmaps.
Change-Id: I8507ac85c8f07886d0fb4f95bde5e18a7790eab8
---
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/kfd_event_defines.h
2 files changed, 46 insertions(+), 15 deletions(-)
diff --git a/src/dev/hsa/hsa_driver.cc b/src/dev/hsa/hsa_driver.cc
index decd488..f17638b 100644
--- a/src/dev/hsa/hsa_driver.cc
+++ b/src/dev/hsa/hsa_driver.cc
@@ -70,21 +70,41 @@
HSADriver::mmap(ThreadContext *tc, Addr start, uint64_t length, int prot,
int tgt_flags, int tgt_fd, off_t offset)
{
- // Check if mmap is for signal events first
- if (((offset >> PAGE_SHIFT) & KFD_MMAP_TYPE_MASK) ==
- KFD_MMAP_TYPE_EVENTS) {
- DPRINTF(HSADriver, "amdkfd mmap for events(start: %p, length:
0x%x,"
- "offset: 0x%x, )\n", start, length, offset);
- panic_if(start != 0,
- "Start address should be provided by KFD\n");
- panic_if(length != 8 * KFD_SIGNAL_EVENT_LIMIT,
- "Requested length %d, expected length %d; length
mismatch\n",
- length, 8 * KFD_SIGNAL_EVENT_LIMIT);
- // For signal event, do mmap only is eventPage is uninitialized
- if (!eventPage)
-eventPage = start;
-} else {
-DPRINTF(HSADriver, "Non-event amdkfd mmap. IGNORING\n");
+auto process = tc->getProcessPtr();
+auto mem_state = process->memState;
+
+Addr pg_off = offset >> PAGE_SHIFT;
+Addr mmap_type = pg_off & KFD_MMAP_TYPE_MASK;
+DPRINTF(HSADriver, "amdkfd mmap (start: %p, length: 0x%x,"
+"offset: 0x%x)\n", start, length, offset);
+
+switch (mmap_type) {
+case KFD_MMAP_TYPE_DOORBELL:
+DPRINTF(HSADriver, "amdkfd mmap type DOORBELL offset\n");
+start = mem_state->extendMmap(length);
+process->pTable->map(start, device->hsaPacketProc().pioAddr,
+length, false);
+break;
+case KFD_MMAP_TYPE_EVENTS:
+DPRINTF(HSADriver, "amdkfd mmap type EVENTS offset\n");
+panic_if(start != 0,
+ "Start address should be provided by KFD\n");
+panic_if(length != 8 * KFD_SIGNAL_EVENT_LIMIT,
+ "Requested length %d, expected length %d; length "
+ "mismatch\n", length, 8 * KFD_SIGNAL_EVENT_LIMIT);
+/**
+ * We don't actually access these pages. We just need to
reserve
+ * some VA space. See commit id 5ce8abce for details on how
+ * events are currently implemented.
+ */
+ if (!eventPage) {
+eventPage = mem_state->extendMmap(length);
+start = eventPage;
+ }
+ break;
+default:
+warn_once("Unrecognized kfd mmap type %llx\n", mmap_type);
+break;
}
return start;
@@ -106,6 +126,9 @@
fatal("%s: Exceeded maximum number of HSA queues allowed\n",
name());
}
+args->doorbell_offset = (KFD_MMAP_TYPE_DOORBELL |
+KFD_MMAP_GPU_ID(args->gpu_id)) << PAGE_SHIFT;
+
args->queue_id = queueId++;
auto &hsa_pp = device->hsaPacketProc();
hsa_pp.setDeviceQueueDesc(args->read_pointer_address,
diff --git a/src/dev/hsa/kfd_event_defines.h
b/src/dev/hsa/kfd_event_defines.h
index 0202b3b..f52bb59 100644
--- a/src/dev/hsa/kfd_event_defines.h
+++ b/src/dev/hsa/kfd_event_defines.h
@@ -35,6 +35,8 @@
#include "dev/hsa/kfd_ioctl.h"
+#define KFD_GPU_ID_HASH_WIDTH 16
+
#define PAGE_SHIFT 12
#define KFD_MMAP_TYPE_SHIFT (62 - PAGE_SHIFT)
#define KFD_MMAP_TYPE_MASK (0x3ULL << KFD_MMAP_TYPE_SHIFT)
@@ -42,4 +44,10 @@
#define KFD_MMAP_TYPE_EVENTS(0x2ULL << KFD_MMAP_TYPE_SHIFT)
#define SLOTS_PER_PAGE KFD_SIGNAL_EVENT_LIMIT
+#define KFD_MMAP_GPU_ID_SHIFT (46 - PAGE_SHIFT)
+#define KFD_MMAP_GPU_ID_MASK (((1ULL << KFD_GPU_ID_HASH_WIDTH) - 1) \
+<< KFD_MMAP_GPU_ID_SHIFT)
+#define KFD_MMAP_GPU_ID(gpu_id) \
+uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT) & KFD_MMAP_GPU_ID_MASK)
+
#endif
--
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Topology and driver changes for dGPU
et = args->va_addr;
+// VRAM allocations are device memory mapped into GPUVM
+// space.
+//
+// We can't rely on the lazy host allocator (fixupFault) to
+// handle this mapping since it needs to be placed in dGPU
+// framebuffer memory. The lazy allocator will try to
place
+// this in host memory.
+//
+// TODO: We don't have the appropriate bifurcation of the
+// physical address space with different memory controllers
+// yet. This is where we will explicitly add the PT maps
to
+// dGPU memory in the future.
+} else if (KFD_IOC_ALLOC_MEM_FLAGS_USERPTR & args->flags) {
+DPRINTF(GPUDriver, "amdkfd allocation type: USERPTR\n");
+mmap_offset = args->mmap_offset;
+// USERPTR allocations are system memory mapped into GPUVM
+// space. The user provides the driver with the pointer.
+//
+// No action needs to be taken for this memory type. We
will
+// lazily map it into host memory on first touch.
+} else if (KFD_IOC_ALLOC_MEM_FLAGS_GTT & args->flags) {
+DPRINTF(GPUDriver, "amdkfd allocation type: GTT\n");
+args->mmap_offset = args->va_addr;
+// GTT allocations are system memory mapped into GPUVM
space.
+// It's different than a USERPTR allocation since the
driver
+// itself allocates the physical memory on the host.
+//
+// No action needs to be taken for this memory type. We
will
+// lazily map it into host memory on first touch. The
+// fixupFault will find the original SVM aperture mapped
to the
+// host.
+//
+// Note that for GTT the thunk layer needs to call mmap on
the
+// driver FD later if it wants the host to have access to
this
+// memory (which it probably does).
+} else if (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL & args->flags) {
+DPRINTF(GPUDriver, "amdkfd allocation type: DOORBELL\n");
+// DOORBELL allocations are the queue doorbells that are
+// memory mapped into GPUVM space.
+//
+// Explicitly map this virtual address to our PIO doorbell
+// interface in the page tables (non-cacheable)
+tc->getProcessPtr()->pTable->map(args->va_addr,
+device->hsaPacketProc().pioAddr,
+args->size, false);
+break;
+}
+
+DPRINTF(GPUDriver, "amdkfd allocation arguments: va_addr %p "
+"size %lu, mmap_offset %p, gpu_id %d\n",
+args->va_addr, args->size, mmap_offset, args->gpu_id);
+
+// TODO: Not sure where the handle is used yet. Set it to an
+// easily trackable value.
+args->handle= 0xdeadbeef;
+args.copyOut(virt_proxy);
}
break;
case AMDKFD_IOC_FREE_MEMORY_OF_GPU:
@@ -361,6 +460,13 @@
warn("unimplemented ioctl: AMDKFD_IOC_FREE_MEMORY_OF_GPU\n");
}
break;
+/**
+ * Called to map an already allocated region of memory to this
GPU's
+ * GPUVM VA space. We don't need to implement this in the
simulator
+ * since we only have a single VM system. If the region has
already
+ * been allocated somewhere like the CPU, then it's already visible
+ * to the device.
+ */
case AMDKFD_IOC_MAP_MEMORY_TO_GPU:
{
warn("unimplemented ioctl: AMDKFD_IOC_MAP_MEMORY_TO_GPU\n");
@@ -415,7 +521,11 @@
ape_args->gpuvm_base = gpuVmApeBase(i + 1);
ape_args->gpuvm_limit =
gpuVmApeLimit(ape_args->gpuvm_base);
-ape_args->gpu_id = 2765;
+// NOTE: Must match ID populated by hsaTopology.py
+if (isdGPU)
+ape_args->gpu_id = 50156;
+else
+ape_args->gpu_id = 2765;
assert(bits(ape_args->scratch_base, 63, 47) !=
0x1);
assert(bits(ape_args->scratch_base, 63, 47) != 0);
diff --git a/src/gpu-compute/gpu_compute_driver.hh
b/src/gpu-compute/gpu_compute_driver.hh
index d2c822d..f8c02b2 100644
--- a/src/gpu-compute/gpu_compute_driver.hh
+++ b/src/gpu-compute/gpu_compute_driver.hh
@@ -55,6 +55,7 @@
void sleepCPU(ThreadContext *tc, uint32_t milliSecTimeout);
private:
+bool isdGPU;
/**
* The aperture (APE) base/limit pairs are set
* statically at startup by the real KFD. AMD
--
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[gem5-dev] Change in gem5/gem5[develop]: configs, gpu-compute: Add option to specify gfx version
UVM base for node[%i] = %#x\n", i,
args->process_apertures[i].gpuvm_base);
@@ -610,10 +627,26 @@
ape_args->gpuvm_limit =
gpuVmApeLimit(ape_args->gpuvm_base);
// NOTE: Must match ID populated by hsaTopology.py
-if (isdGPU)
-ape_args->gpu_id = 50156;
-else
-ape_args->gpu_id = 2765;
+if (isdGPU) {
+switch (gfxVersion) {
+ case GfxVersion::gfx803:
+ape_args->gpu_id = 50156;
+break;
+ case GfxVersion::gfx900:
+ape_args->gpu_id = 22124;
+break;
+ default:
+fatal("Invalid gfx version for dGPU\n");
+}
+} else {
+switch (gfxVersion) {
+ case GfxVersion::gfx801:
+ape_args->gpu_id = 2765;
+break;
+ default:
+fatal("Invalid gfx version for APU\n");
+}
+}
assert(bits(ape_args->scratch_base, 63, 47) !=
0x1);
assert(bits(ape_args->scratch_base, 63, 47) != 0);
diff --git a/src/gpu-compute/gpu_compute_driver.hh
b/src/gpu-compute/gpu_compute_driver.hh
index 7f94acc..7f13461 100644
--- a/src/gpu-compute/gpu_compute_driver.hh
+++ b/src/gpu-compute/gpu_compute_driver.hh
@@ -44,6 +44,7 @@
#include "base/addr_range_map.hh"
#include "dev/hsa/hsa_driver.hh"
+#include "enums/GfxVersion.hh"
#include "mem/request.hh"
struct GPUComputeDriverParams;
@@ -68,6 +69,7 @@
private:
bool isdGPU;
+GfxVersion gfxVersion;
int dGPUPoolID;
/**
--
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Implement per-request MTYPEs
= 1,
+CACHED = 2
+};
+
+Request::CacheCoherenceFlags defaultMtype;
+
+/**
+ * Register a region of host memory as uncacheable from the perspective
+ * of the dGPU.
+ */
+void registerUncacheableMemory(Addr start, Addr length);
+
/**
* The aperture (APE) base/limit pairs are set
* statically at startup by the real KFD. AMD
@@ -77,6 +113,16 @@
Addr scratchApeLimit(Addr apeBase) const;
Addr ldsApeBase(int gpuNum) const;
Addr ldsApeLimit(Addr apeBase) const;
+
+/**
+ * Allocate/deallocate GPUVM VMAs for tracking virtual address
allocations
+ * and properties on DGPUs. For now, we use these to track MTYPE and
to
+ * be able to select which pages to unmap when the user provides us
with
+ * a handle during the free ioctl.
+ */
+void allocateGpuVma(Request::CacheCoherenceFlags mtype, Addr start,
+Addr length);
+Addr deallocateGpuVma(Addr start);
};
#endif // __GPU_COMPUTE_GPU_COMPUTE_DRIVER_HH__
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 38b64fd..2e9e914 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -292,11 +292,23 @@
*/
enum : CacheCoherenceFlagsType {
/** mem_sync_op flags */
-INV_L1 = 0x0001,
+I_CACHE_INV = 0x0001,
+INV_L1 = I_CACHE_INV,
+V_CACHE_INV = 0x0002,
+K_CACHE_INV = 0x0004,
+GL1_CACHE_INV = 0x0008,
+K_CACHE_WB = 0x0010,
FLUSH_L2= 0x0020,
+GL2_CACHE_INV = 0x0040,
/** user-policy flags */
SLC_BIT = 0x0080,
-GLC_BIT = 0x0100,
+DLC_BIT = 0x0100,
+GLC_BIT = 0x00000200,
+/** mtype flags */
+CACHED = 0x0400,
+ READ_WRITE = 0x0800,
+ SHARED = 0x1000,
+
};
using LocalAccessor =
diff --git a/src/sim/mem_state.hh b/src/sim/mem_state.hh
index c052389..1f4f325 100644
--- a/src/sim/mem_state.hh
+++ b/src/sim/mem_state.hh
@@ -235,6 +235,17 @@
private:
/**
+ * @param
+ */
+void replicatePage(const MemState &in, Addr vaddr, Addr new_paddr,
+ bool alloc_page);
+
+/**
+ * @param
+ */
+System * system() const;
+
+/**
* Owner process of MemState. Used to manipulate page tables.
*/
Process * _ownerProcess;
--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Add pool specific allocators to SE mode
system.hh
@@ -310,7 +310,21 @@
bool schedule(PCEvent *event) override;
bool remove(PCEvent *event) override;
-Addr pagePtr;
+/** Structure that keeps track of physical frame allocations in SE
mode. */
+struct PhysMemInfo
+{
+/** Current physical frame pointer from which we allocate memory.
*/
+Addr physFramePtr;
+
+/** Physical memory limits for this node, in number of frames. */
+Addr physMemLimit;
+
+PhysMemInfo(Addr ptr, Addr limit)
+: physFramePtr(ptr), physMemLimit(limit) { }
+};
+
+/** PhysMemInfos for each node */
+std::vector physMemInfos;
uint64_t init_param;
@@ -337,10 +351,10 @@
PhysicalMemory& getPhysMem() { return physmem; }
/** Amount of physical memory that is still free */
-Addr freeMemSize() const;
+Addr freeMemSize(int poolID = 0) const;
/** Amount of physical memory that exists */
-Addr memSize() const;
+Addr memSize(int poolID = 0) const;
/**
* Check if a physical address is within a range of a memory that
@@ -583,7 +597,7 @@
/// Allocate npages contiguous unused physical pages
/// @return Starting address of first page
-Addr allocPhysPages(int npages);
+Addr allocPhysPages(int npages, int poolID = 0);
ContextID registerThreadContext(
ThreadContext *tc, ContextID assigned=InvalidContextID);
--
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute, dev-hsa: Fix doorbell for gfx900
-// `(Addr)(VOID_PRT_ADD32(0, queue_id))`
-//
-// Originally
-// #define VOID_PTR_ADD32(ptr,n)
-// (void*)((uint32_t*)(ptr) + n)/*ptr + offset*/
-// (Addr)VOID_PTR_ADD32(0, queue_id)
-Addr db_offset = sizeof(uint32_t)*queue_id;
+Addr db_offset = queue_id * doorbellSize;
auto dbmap_iter = dbMap.find(db_offset);
if (dbmap_iter == dbMap.end()) {
panic("Destroying a non-existing queue (db_offset %x)",
diff --git a/src/dev/hsa/hw_scheduler.hh b/src/dev/hsa/hw_scheduler.hh
index 4669c89..0ec41ed 100644
--- a/src/dev/hsa/hw_scheduler.hh
+++ b/src/dev/hsa/hw_scheduler.hh
@@ -47,12 +47,12 @@
: hsaPP(hsa_pp), nextALId(0), nextRLId(0),
wakeupDelay(wakeup_delay), schedWakeupEvent(this)
{}
-void write(Addr db_addr, uint32_t doorbell_reg);
+void write(Addr db_addr, uint64_t doorbell_reg);
void registerNewQueue(uint64_t hostReadIndexPointer,
uint64_t basePointer,
uint64_t queue_id,
- uint32_t size);
-void unregisterQueue(uint64_t queue_id);
+ uint32_t size, int doorbellSize);
+void unregisterQueue(uint64_t queue_id, int doorbellSize);
void wakeup();
void schedWakeup();
class SchedulerWakeupEvent : public Event
diff --git a/src/gpu-compute/gpu_compute_driver.cc
b/src/gpu-compute/gpu_compute_driver.cc
index d91b174..e113a5a 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -144,18 +144,22 @@
TypedBufferArg args(ioc_buf);
args.copyIn(mem_proxy);
-if ((sizeof(uint32_t) * queueId) > 4096) {
+if ((doorbellSize() * queueId) > 4096) {
fatal("%s: Exceeded maximum number of HSA queues allowed\n",
name());
}
args->doorbell_offset = (KFD_MMAP_TYPE_DOORBELL |
KFD_MMAP_GPU_ID(args->gpu_id)) << PAGE_SHIFT;
+// for vega offset needs to include exact value of doorbell
+if (doorbellSize())
+args->doorbell_offset += queueId * doorbellSize();
+
args->queue_id = queueId++;
auto &hsa_pp = device->hsaPacketProc();
hsa_pp.setDeviceQueueDesc(args->read_pointer_address,
args->ring_base_address, args->queue_id,
- args->ring_size);
+ args->ring_size, doorbellSize());
args.copyOut(mem_proxy);
}
@@ -238,7 +242,8 @@
args.copyIn(virt_proxy);
DPRINTF(GPUDriver, "ioctl: AMDKFD_IOC_DESTROY_QUEUE;" \
"queue offset %d\n", args->queue_id);
-device->hsaPacketProc().unsetDeviceQueueDesc(args->queue_id);
+device->hsaPacketProc().unsetDeviceQueueDesc(args->queue_id,
+ doorbellSize());
}
break;
case AMDKFD_IOC_SET_MEMORY_POLICY:
diff --git a/src/gpu-compute/gpu_compute_driver.hh
b/src/gpu-compute/gpu_compute_driver.hh
index d4813a1..83e5717 100644
--- a/src/gpu-compute/gpu_compute_driver.hh
+++ b/src/gpu-compute/gpu_compute_driver.hh
@@ -78,6 +78,21 @@
*/
void setMtype(RequestPtr req);
+int
+doorbellSize()
+{
+switch (gfxVersion) {
+ case GfxVersion::gfx801:
+ case GfxVersion::gfx803:
+return 4;
+ case GfxVersion::gfx900:
+return 8;
+ default:
+fatal("Invalid GPU type\n");
+}
+return 4;
+}
+
class DriverWakeupEvent : public Event
{
public:
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega, gpu-compute: Add vectors to hold op info
Alexandru Duțu has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42211 ) Change subject: arch-vega, gpu-compute: Add vectors to hold op info .. arch-vega, gpu-compute: Add vectors to hold op info This removes the need for redundant functions like isScalarRegister/isVectorRegister, as well as isSrcOperand/isDstOperand. Also, the op info is only generated once this way instead of every time it's needed. Change-Id: I8af5080502ed08ed9107a441e2728828f86496f4 --- M MAINTAINERS.yaml M src/arch/amdgpu/gcn3/insts/gpu_static_inst.hh M src/arch/amdgpu/gcn3/insts/instructions.hh M src/arch/amdgpu/gcn3/insts/op_encodings.cc M src/arch/amdgpu/gcn3/insts/op_encodings.hh M src/arch/amdgpu/vega/insts/gpu_static_inst.hh M src/arch/amdgpu/vega/insts/instructions.hh M src/arch/amdgpu/vega/insts/op_encodings.cc M src/arch/amdgpu/vega/insts/op_encodings.hh M src/gpu-compute/gpu_dyn_inst.cc M src/gpu-compute/gpu_static_inst.hh A src/gpu-compute/operand_info.hh 12 files changed, 1,241 insertions(+), 80,257 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42211 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8af5080502ed08ed9107a441e2728828f86496f4 Gerrit-Change-Number: 42211 Gerrit-PatchSet: 1 Gerrit-Owner: Alexandru Duțu Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: configs,mem-ruby: CHI-based Ruby protocol
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42563 ) Change subject: configs,mem-ruby: CHI-based Ruby protocol .. configs,mem-ruby: CHI-based Ruby protocol This patch add a new Ruby cache coherence protocol based on Arm' AMBA5 CHI specification. The CHI protocol defines and implements two state machine types: - Cache_Controller: generic cache controller that can be configured as: - Top-level L1 I/D cache - A intermediate level (L2, L3, ...) private or shared cache - A CHI home node (i.e. the point of coherence of the system and has the global directory) - A DMA requester - Memory_Controller: implements a CHI slave node and interfaces with gem5 memory controller. This controller has the functionality of a Directory_Controller on the other Ruby protocols, except it doesn't have a directory. The Cache_Controller has multiple cache allocation/deallocation parameters to control the clusivity with respect to upstream caches. Allocation can be completely disabled to use Cache_Controller as a DMA requester or as a home node without a shared LLC. The standard configuration file configs/ruby/CHI.py provides a 'create_system' compatible with configs/example/fs.py and configs/example/se.py and creates a system with private L1/L2 caches per core and a shared LLC at the home nodes. Different cache topologies can be defined by modifying 'create_system' or by creating custom scripts using the structures defined in configs/ruby/CHI.py. This patch also includes the 'CustomMesh' topology script to be used with CHI. CustomMesh generates a 2D mesh topology with the placement of components manually defined in a separate configuration file using the --noc-config parameter. The example in configs/example/noc_config/2x4.yaml creates a simple 2x4 mesh. For example, to run a SE mode simulation, with 4 cores, 4 mem ctnrls, and 4 home nodes (L3 caches): build/ARM/gem5.opt configs/example/se.py \ --cmd 'tests/test-progs/hello/bin/arm/linux/hello' \ --ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \ --topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml If one doesn't care about the component placement on the interconnect, the 'Crossbar' and 'Pt2Pt' may be used and they do not require the --noc-config option. Additional authors: Joshua Randall Pedro Benedicte Tuan Ta JIRA: https://gem5.atlassian.net/browse/GEM5-908 Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Signed-off-by: Tiago Mück --- A configs/example/noc_config/2x4.yaml A configs/ruby/CHI.py A configs/topologies/CustomMesh.py M src/mem/ruby/SConscript A src/mem/ruby/common/ExpectedMap.hh A src/mem/ruby/common/TriggerQueue.hh A src/mem/ruby/protocol/CHI-cache-actions.sm A src/mem/ruby/protocol/CHI-cache-funcs.sm A src/mem/ruby/protocol/CHI-cache-transitions.sm A src/mem/ruby/protocol/CHI-cache.sm A src/mem/ruby/protocol/CHI-mem.sm A src/mem/ruby/protocol/CHI-msg.sm A src/mem/ruby/protocol/CHI.slicc M src/mem/ruby/protocol/RubySlicc_Exports.sm M src/mem/ruby/protocol/SConsopts M src/mem/ruby/system/SConscript 16 files changed, 9,403 insertions(+), 2 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42563 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v21-0 Gerrit-Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Gerrit-Change-Number: 42563 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons: change NULL and ARM default protocol to CHI
Tiago Mück has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/42564 ) Change subject: scons: change NULL and ARM default protocol to CHI .. scons: change NULL and ARM default protocol to CHI Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Signed-off-by: Tiago Mück --- M build_opts/ARM M build_opts/NULL 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/build_opts/ARM b/build_opts/ARM index c473078..e4cb9a5 100644 --- a/build_opts/ARM +++ b/build_opts/ARM @@ -1,3 +1,3 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_CMP_directory' +PROTOCOL = 'CHI' diff --git a/build_opts/NULL b/build_opts/NULL index 1242fa9..de8b1dd 100644 --- a/build_opts/NULL +++ b/build_opts/NULL @@ -1,3 +1,3 @@ TARGET_ISA = 'null' CPU_MODELS = '' -PROTOCOL='MI_example' +PROTOCOL='CHI' -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42564 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v21-0 Gerrit-Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Gerrit-Change-Number: 42564 Gerrit-PatchSet: 1 Gerrit-Owner: Tiago Mück Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons,mem-ruby: export need_partial_func_reads in SConstruct
Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/43043 )
Change subject: scons,mem-ruby: export need_partial_func_reads in SConstruct
..
scons,mem-ruby: export need_partial_func_reads in SConstruct
need_partial_func_reads should now be modified from protocol specific
files (e.g. src/learning_gem5/part3/SConsopts)
Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
---
M SConstruct
M src/mem/ruby/system/SConscript
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/SConstruct b/SConstruct
index beaf9ae..fb3421c 100755
--- a/SConstruct
+++ b/SConstruct
@@ -764,6 +764,9 @@
Export('protocol_dirs')
slicc_includes = []
Export('slicc_includes')
+# list of protocols that require the partial functional read interface
+need_partial_func_reads = []
+Export('need_partial_func_reads')
# Walk the tree and execute all SConsopts scripts that wil add to the
# above variables
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript
index a2708ae..e87cd24 100644
--- a/src/mem/ruby/system/SConscript
+++ b/src/mem/ruby/system/SConscript
@@ -45,9 +45,6 @@
env.Append(CPPDEFINES=['PROTOCOL_' + env['PROTOCOL']])
-# list of protocols that require the partial functional read interface
-need_partial_func_reads = []
-
if env['PROTOCOL'] in need_partial_func_reads:
env.Append(CPPDEFINES=['PARTIAL_FUNC_READS'])
--
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Gerrit-Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
Gerrit-Change-Number: 43043
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons,mem-ruby: export need_partial_func_reads in SConstruct
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/43043 )
Change subject: scons,mem-ruby: export need_partial_func_reads in SConstruct
..
scons,mem-ruby: export need_partial_func_reads in SConstruct
need_partial_func_reads should now be modified from protocol specific
files (e.g. src/learning_gem5/part3/SConsopts)
Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43043
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M SConstruct
M src/mem/ruby/system/SConscript
2 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index beaf9ae..fb3421c 100755
--- a/SConstruct
+++ b/SConstruct
@@ -764,6 +764,9 @@
Export('protocol_dirs')
slicc_includes = []
Export('slicc_includes')
+# list of protocols that require the partial functional read interface
+need_partial_func_reads = []
+Export('need_partial_func_reads')
# Walk the tree and execute all SConsopts scripts that wil add to the
# above variables
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript
index a2708ae..e87cd24 100644
--- a/src/mem/ruby/system/SConscript
+++ b/src/mem/ruby/system/SConscript
@@ -45,9 +45,6 @@
env.Append(CPPDEFINES=['PROTOCOL_' + env['PROTOCOL']])
-# list of protocols that require the partial functional read interface
-need_partial_func_reads = []
-
if env['PROTOCOL'] in need_partial_func_reads:
env.Append(CPPDEFINES=['PARTIAL_FUNC_READS'])
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-0
Gerrit-Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
Gerrit-Change-Number: 43043
Gerrit-PatchSet: 2
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: configs,mem-ruby: CHI-based Ruby protocol
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/42563 ) Change subject: configs,mem-ruby: CHI-based Ruby protocol .. configs,mem-ruby: CHI-based Ruby protocol This patch add a new Ruby cache coherence protocol based on Arm' AMBA5 CHI specification. The CHI protocol defines and implements two state machine types: - Cache_Controller: generic cache controller that can be configured as: - Top-level L1 I/D cache - A intermediate level (L2, L3, ...) private or shared cache - A CHI home node (i.e. the point of coherence of the system and has the global directory) - A DMA requester - Memory_Controller: implements a CHI slave node and interfaces with gem5 memory controller. This controller has the functionality of a Directory_Controller on the other Ruby protocols, except it doesn't have a directory. The Cache_Controller has multiple cache allocation/deallocation parameters to control the clusivity with respect to upstream caches. Allocation can be completely disabled to use Cache_Controller as a DMA requester or as a home node without a shared LLC. The standard configuration file configs/ruby/CHI.py provides a 'create_system' compatible with configs/example/fs.py and configs/example/se.py and creates a system with private L1/L2 caches per core and a shared LLC at the home nodes. Different cache topologies can be defined by modifying 'create_system' or by creating custom scripts using the structures defined in configs/ruby/CHI.py. This patch also includes the 'CustomMesh' topology script to be used with CHI. CustomMesh generates a 2D mesh topology with the placement of components manually defined in a separate configuration file using the --noc-config parameter. The example in configs/example/noc_config/2x4.yaml creates a simple 2x4 mesh. For example, to run a SE mode simulation, with 4 cores, 4 mem ctnrls, and 4 home nodes (L3 caches): build/ARM/gem5.opt configs/example/se.py \ --cmd 'tests/test-progs/hello/bin/arm/linux/hello' \ --ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \ --topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml If one doesn't care about the component placement on the interconnect, the 'Crossbar' and 'Pt2Pt' may be used and they do not require the --noc-config option. Additional authors: Joshua Randall Pedro Benedicte Tuan Ta JIRA: https://gem5.atlassian.net/browse/GEM5-908 Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42563 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A configs/example/noc_config/2x4.yaml A configs/ruby/CHI.py A configs/topologies/CustomMesh.py M src/mem/ruby/SConscript A src/mem/ruby/common/ExpectedMap.hh A src/mem/ruby/common/TriggerQueue.hh M src/mem/ruby/protocol/RubySlicc_Exports.sm A src/mem/ruby/protocol/chi/CHI-cache-actions.sm A src/mem/ruby/protocol/chi/CHI-cache-funcs.sm A src/mem/ruby/protocol/chi/CHI-cache-ports.sm A src/mem/ruby/protocol/chi/CHI-cache-transitions.sm A src/mem/ruby/protocol/chi/CHI-cache.sm A src/mem/ruby/protocol/chi/CHI-mem.sm A src/mem/ruby/protocol/chi/CHI-msg.sm A src/mem/ruby/protocol/chi/CHI.slicc A src/mem/ruby/protocol/chi/SConsopts 16 files changed, 9,498 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42563 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v21-0 Gerrit-Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0 Gerrit-Change-Number: 42563 Gerrit-PatchSet: 3 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: configs: changed CHI --noc-config format
-# CHI_SNF_IO (applies to CHI_SNF_Bootmem)
-noc_params.CHI_SNF_IO = config['CHI_SNF_IO']
+def noc_params_from_config_file(noc_config_file, noc_params):
+from importlib.machinery import SourceFileLoader
+loader = SourceFileLoader('chi_noc_configs', noc_config_file)
+config = loader.load_module()
+# required configuration functions
+required = ['setup_NoC_Params', 'setup_CHI_RNF', 'setup_CHI_HNF',
+'setup_CHI_SNF_MainMem', 'setup_CHI_SNF_BootMem',
+'setup_CHI_RNI_DMA', 'setup_CHI_RNI_IO']
+for func in required:
+if not hasattr(config, func):
+m5.fatal('Configuration function %s undefined in %s' % \
+ (func, noc_config_file))
+noc_params_from_config(config, noc_params)
def create_system(options, full_system, system, dma_ports, bootmem,
@@ -668,12 +707,13 @@
self.router_buffer_size = 4
self.cntrl_msg_size = 8
self.data_width = 32
+self.cross_links = []
+self.cross_link_latency = 0
params = NoC_Params()
-# read additional configurations from yaml file if provided
+# read additional configurations from noc config file if provided
if options.noc_config:
-with open(options.noc_config, 'r') as file:
-noc_params_from_config(yaml.load(file), params)
+noc_params_from_config_file(options.noc_config, params)
elif params.topology == 'CustomMesh':
m5.fatal('--noc-config must be provided if topology is CustomMesh')
diff --git a/configs/topologies/CustomMesh.py
b/configs/topologies/CustomMesh.py
index 73793e4..43a55d8 100644
--- a/configs/topologies/CustomMesh.py
+++ b/configs/topologies/CustomMesh.py
@@ -163,8 +163,9 @@
return node_router
-def distributeNodes(self, num_nodes_per_router, router_idx_list,
-node_list):
+def distributeNodes(self, node_placement_config, node_list):
+num_nodes_per_router = node_placement_config.num_nodes_per_router
+router_idx_list = node_placement_config.router_list
if num_nodes_per_router:
# evenly distribute nodes to all listed routers
@@ -237,7 +238,8 @@
hnf_list = []
mem_ctrls = []
io_mem_ctrls = []
-io_rni_ctrls = []
+rni_dma_ctrls = []
+rni_io_ctrls = []
for n in self.nodes:
if isinstance(n, CHI.CHI_RNF):
@@ -249,9 +251,9 @@
elif isinstance(n, CHI.CHI_SNF_BootMem):
io_mem_ctrls.append(n)
elif isinstance(n, CHI.CHI_RNI_DMA):
-io_rni_ctrls.append(n)
+rni_dma_ctrls.append(n)
elif isinstance(n, CHI.CHI_RNI_IO):
-io_rni_ctrls.append(n)
+rni_io_ctrls.append(n)
else:
fatal('topologies.CustomMesh: {} not supported'
.format(n.__class__.__name__))
@@ -269,39 +271,20 @@
options.cross_links, options.cross_link_latency)
# Place CHI_RNF on the mesh
-num_nodes_per_router = options.CHI_RNF['num_nodes_per_router'] \
-if 'num_nodes_per_router' in options.CHI_RNF else None
-self.distributeNodes(num_nodes_per_router,
- options.CHI_RNF['router_list'],
- rnf_list)
+self.distributeNodes(CHI.CHI_RNF.noc_params(), rnf_list)
# Place CHI_HNF on the mesh
-num_nodes_per_router = options.CHI_HNF['num_nodes_per_router'] \
-if 'num_nodes_per_router' in options.CHI_HNF else None
-self.distributeNodes(num_nodes_per_router,
- options.CHI_HNF['router_list'],
- hnf_list)
+self.distributeNodes(CHI.CHI_HNF.noc_params(), hnf_list)
# Place CHI_SNF_MainMem on the mesh
-num_nodes_per_router =
options.CHI_SNF_MainMem['num_nodes_per_router']\
-if 'num_nodes_per_router' in options.CHI_SNF_MainMem else
None
-self.distributeNodes(num_nodes_per_router,
- options.CHI_SNF_MainMem['router_list'],
- mem_ctrls)
+self.distributeNodes(CHI.CHI_SNF_MainMem.noc_params(), mem_ctrls)
# Place all IO mem nodes on the mesh
-num_nodes_per_router = options.CHI_SNF_IO['num_nodes_per_router'] \
-if 'num_nodes_per_router' in options.CHI_SNF_IO else None
-self.distributeNodes(num_nodes_per_router,
- options.CHI_SNF_IO['router_list'],
- io_mem_ctrls)
+self.distributeNodes(CHI.CHI_SNF_BootMem.noc_par
[gem5-dev] Change in gem5/gem5[release-staging-v21-0]: scons: change ARM default protocol to CHI
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/42564 ) Change subject: scons: change ARM default protocol to CHI .. scons: change ARM default protocol to CHI Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42564 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Giacomo Travaglini Maintainer: Jason Lowe-Power Maintainer: Giacomo Travaglini --- M build_opts/ARM 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/build_opts/ARM b/build_opts/ARM index c473078..e4cb9a5 100644 --- a/build_opts/ARM +++ b/build_opts/ARM @@ -1,3 +1,3 @@ TARGET_ISA = 'arm' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_CMP_directory' +PROTOCOL = 'CHI' 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42564 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v21-0 Gerrit-Change-Id: Ic05f96b84a4e61e93bc12e48381c6a809f260021 Gerrit-Change-Number: 42564 Gerrit-PatchSet: 5 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-CC: Bobby R. Bruce Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed locked cmpxchg8b allows reordering
Eduardo José Gómez Hernández has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44166 )
Change subject: arch-x86: Fixed locked cmpxchg8b allows reordering
..
arch-x86: Fixed locked cmpxchg8b allows reordering
Locked versions of cmpxcgh8b (and cmpxcgh16b) should
be guarded by mfences to prevent reordering from
surrounding memory instructions.
Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236
---
M src/arch/x86/isa/insts/general_purpose/semaphores.py
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py
b/src/arch/x86/isa/insts/general_purpose/semaphores.py
index de7c6ef..ba17541 100644
--- a/src/arch/x86/isa/insts/general_purpose/semaphores.py
+++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py
@@ -159,10 +159,37 @@
microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
"l": "", "ul": "",
"suffix": "P"}
-microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
+
+cmpxchg8bLockedCode = '''
+def macroop CMPXCHG8B_%(suffix)s {
+.adjust_env clampOsz
+%(rdip)s
+mfence
+lea t1, seg, %(sib)s, disp, dataSize=asz
+ldsplit%(l)s (t2, t3), seg, [1, t0, t1], disp=0
+
+sub t0, rax, t2, flags=(ZF,)
+br label("doneComparing"), flags=(nCZF,)
+sub t0, rdx, t3, flags=(ZF,)
+doneComparing:
+
+# If they're equal, set t3:t2 to rbx:rcx to write to memory
+mov t2, t2, rbx, flags=(CZF,)
+mov t3, t3, rcx, flags=(CZF,)
+
+# If they're not equal, set rdx:rax to the value from memory.
+mov rax, rax, t2, flags=(nCZF,)
+mov rdx, rdx, t3, flags=(nCZF,)
+
+# Write to memory
+stsplit%(ul)s (t2, t3), seg, [1, t0, t1], disp=0
+mfence
+};
+'''
+microcode += cmpxchg8bLockedCode % {"rdip": "", "sib": "sib",
"l": "l", "ul": "ul",
"suffix": "LOCKED_M"}
-microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
+microcode += cmpxchg8bLockedCode % {"rdip": "rdip t7", "sib": "riprel",
"l": "l", "ul": "ul",
"suffix": "LOCKED_P"}
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236
Gerrit-Change-Number: 44166
Gerrit-PatchSet: 1
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed locked cmpxchg8b allows reordering
Eduardo José Gómez Hernández has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44166 )
Change subject: arch-x86: Fixed locked cmpxchg8b allows reordering
..
arch-x86: Fixed locked cmpxchg8b allows reordering
Locked versions of cmpxcgh8b (and cmpxcgh16b) should
be guarded by mfences to prevent reordering from
surrounding memory instructions.
Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44166
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa/insts/general_purpose/semaphores.py
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/insts/general_purpose/semaphores.py
b/src/arch/x86/isa/insts/general_purpose/semaphores.py
index de7c6ef..aae67fa 100644
--- a/src/arch/x86/isa/insts/general_purpose/semaphores.py
+++ b/src/arch/x86/isa/insts/general_purpose/semaphores.py
@@ -132,6 +132,7 @@
def macroop CMPXCHG8B_%(suffix)s {
.adjust_env clampOsz
%(rdip)s
+%(mfence)s
lea t1, seg, %(sib)s, disp, dataSize=asz
ldsplit%(l)s (t2, t3), seg, [1, t0, t1], disp=0
@@ -150,20 +151,25 @@
# Write to memory
stsplit%(ul)s (t2, t3), seg, [1, t0, t1], disp=0
+%(mfence)s
};
'''
microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
"l": "", "ul": "",
+ "mfence": "",
"suffix": "M"}
microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
"l": "", "ul": "",
+ "mfence": "",
"suffix": "P"}
microcode += cmpxchg8bCode % {"rdip": "", "sib": "sib",
"l": "l", "ul": "ul",
+ "mfence": "mfence",
"suffix": "LOCKED_M"}
microcode += cmpxchg8bCode % {"rdip": "rdip t7", "sib": "riprel",
"l": "l", "ul": "ul",
+ "mfence": "mfence",
"suffix": "LOCKED_P"}
#let {{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236
Gerrit-Change-Number: 44166
Gerrit-PatchSet: 3
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-Reviewer: Eduardo José Gómez Hernández
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: queued prefetcher bug fix
Burak Öçalan has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46759 )
Change subject: mem-cache: queued prefetcher bug fix
..
mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.
Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan
Reported-by: Burak Öçalan
Tested-by: Burak Öçalan
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 2a74a17..221542a 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -475,6 +475,13 @@
if (queue.size() == 0) {
queue.emplace_back(dpp);
} else {
+/* Handle the case where the element should be added to end of
queue
+ separately */
+if (dpp <= queue.back()) {
+queue.insert(queue.end(), dpp);
+return;
+}
+
iterator it = queue.end();
do {
--it;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Gerrit-Change-Number: 46759
Gerrit-PatchSet: 1
Gerrit-Owner: Burak Öçalan
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: queued prefetcher bug fix
Burak Öçalan has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/46759 )
Change subject: mem-cache: queued prefetcher bug fix
..
mem-cache: queued prefetcher bug fix
In queued prefetcher, addToQueue function doesn't behave
correctly where the element must be added to the end of queue.
I fixed this bug.
Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Signed-off-by: Burak Öçalan
Reported-by: Burak Öçalan
Tested-by: Burak Öçalan
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46759
Reviewed-by: Daniel Carvalho
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/cache/prefetch/queued.cc
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/queued.cc
b/src/mem/cache/prefetch/queued.cc
index 2a74a17..db3ba2f 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -472,7 +472,7 @@
queue.erase(it);
}
-if (queue.size() == 0) {
+if ((queue.size() == 0) || (dpp <= queue.back())) {
queue.emplace_back(dpp);
} else {
iterator it = queue.end();
--
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Gerrit-Change-Id: I1eec129f827b6465e7cef874c551d96acbf18d5b
Gerrit-Change-Number: 46759
Gerrit-PatchSet: 6
Gerrit-Owner: Burak Öçalan
Gerrit-Reviewer: Burak Öçalan
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed M5InternalError when decoding certain bytes
Eduardo José Gómez Hernández has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49990 )
Change subject: arch-x86: Fixed M5InternalError when decoding certain bytes
..
arch-x86: Fixed M5InternalError when decoding certain bytes
0F38 is the two bytes prefixes to decode a three-byte opcode.
To prevent error, the two_bytes_opcode decoder will complain
if it tries to decode 38 as the opcode, because it is a prefix.
The decoder, will treat 38 as a prefix, preventing it to
end in the two_byte_opcode decoder.
However, using the VEX prefix is possible to reach this
forbidden state.
The set of bytes C4 01 01 38 00 will trigger the mentioned
M5InternalError.
The previous instruction is not valid, but it could be
decoded from an speculative path. In its place, a UD2
instructtion should be emitted.
Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
---
M src/arch/x86/decoder.cc
1 file changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 015a504..3020b1d 100644
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -362,6 +362,16 @@
switch (emi.opcode.type) {
case TwoByteOpcode:
+ // Decoding garbage could lead in invalid instructions
+// that will never commit. This prevent certain 3 VEX opcodes
+// from reaching the decoder 'panic' of decoding 3 opcode
+// instructions using the 2 opcode decoder.
+if (emi.opcode.op == 0x38 || emi.opcode.op == 0x3A) {
+DPRINTF(Decoder, "Found VEX opcode redirecting to " \
+"TwoByteOpcode a reserved opcode for ThreeByteOpcode. "
+"Now, it will be converted into UD2.\n");
+emi.opcode.op = 0x39;
+}
return processOpcode(ImmediateTypeTwoByte, UsesModRMTwoByte);
case ThreeByte0F38Opcode:
return processOpcode(ImmediateTypeThreeByte0F38,
--
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Gerrit-Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
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Gerrit-PatchSet: 1
Gerrit-Owner: Eduardo José Gómez Hernández
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fixed M5InternalError when decoding certain bytes
Eduardo José Gómez Hernández has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49990 )
Change subject: arch-x86: Fixed M5InternalError when decoding certain bytes
..
arch-x86: Fixed M5InternalError when decoding certain bytes
0F 38 is the two bytes prefixes to decode a three-byte opcode.
To prevent errors, the two_bytes_opcode decoder will complain
if it tries to decode 38 as the opcode, because it is a prefix.
The decoder, will treat 38 as a prefix, preventing it to
end in the two_byte_opcode decoder.
However, using the VEX prefix is possible to reach this
forbidden state.
The set of bytes C4 01 01 38 00 will trigger the mentioned
M5InternalError.
The previous instruction is not valid, but it could be
decoded from an speculative path. In its place, a UD2
instructtion should be emitted if the VEX prefix is
present.
Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49990
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/bitfields.isa
2 files changed, 42 insertions(+), 8 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa
index 9522a8d..0404afc 100644
--- a/src/arch/x86/isa/bitfields.isa
+++ b/src/arch/x86/isa/bitfields.isa
@@ -86,5 +86,6 @@
def bitfield MODE_MODE mode.mode;
def bitfield MODE_SUBMODE mode.submode;
+def bitfield VEX_PRESENT vex.present;
def bitfield VEX_V vex.v;
def bitfield VEX_L vex.l;
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 48f46d4..549db47 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -354,14 +354,17 @@
0x6: Inst::UD2();
0x7: getsec();
}
-0x07: decode OPCODE_OP_BOTTOM3 {
-0x0: M5InternalError::error(
-{{"Three byte opcode shouldn't be handled by "
- "two_byte_opcodes.isa!"}});
-0x2: M5InternalError::error(
-{{"Three byte opcode shouldn't be handled by "
- "two_byte_opcodes.isa!"}});
-default: UD2();
+0x07: decode VEX_PRESENT {
+0x0: decode OPCODE_OP_BOTTOM3 {
+0x0: M5InternalError::error(
+{{"Three byte opcode shouldn't be handled by "
+ "two_byte_opcodes.isa!"}});
+0x2: M5InternalError::error(
+{{"Three byte opcode shouldn't be handled by "
+ "two_byte_opcodes.isa!"}});
+default: UD2();
+}
+0x1: UD2();
}
format Inst {
0x08: decode OPCODE_OP_BOTTOM3 {
--
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Gerrit-Change-Id: I6b7c4b3593dd8e6e8ac99aaf306b8feeb7784b56
Gerrit-Change-Number: 49990
Gerrit-PatchSet: 3
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-Reviewer: Eduardo José Gómez Hernández
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix rcl implementation triggers "bits" assert
Eduardo José Gómez Hernández has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/52803 )
Change subject: arch-x86: Fix rcl implementation triggers "bits" assert
..
arch-x86: Fix rcl implementation triggers "bits" assert
With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.
This was not detected before because:
1 - The assert triggered in "bits" is from a recent commit
2 - The result is correct.
Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index e5f9e3d..338ded9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -990,7 +990,7 @@
CCFlagBits flags = cfofBits;
uint64_t top = PSrcReg1 << realShiftAmt;
uint64_t bottom = flags.cf << (realShiftAmt - 1);
-if(shiftAmt > 1) {
+if(realShiftAmt > 1) {
bottom |= bits(PSrcReg1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
}
--
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Gerrit-Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Gerrit-Change-Number: 52803
Gerrit-PatchSet: 1
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix rcl implementation triggers "bits" assert
Eduardo José Gómez Hernández has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/52803 )
Change subject: arch-x86: Fix rcl implementation triggers "bits" assert
..
arch-x86: Fix rcl implementation triggers "bits" assert
With some values of rotations and datasizes, is it possible to call
"bits" with first being smaller than seccond. To prevent it, rcl,
similar to other rotations had an if to check if the value to rotate
is bigger than 1, however, rcl was checking for 'shiftAmt' instead
of 'realShiftAmt'.
This was not detected before because:
1 - The assert triggered in "bits" is from a recent commit
2 - The result is correct.
Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52803
Reviewed-by: Jason Lowe-Power
Reviewed-by: Gabe Black
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 25 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index e5f9e3d..338ded9 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -990,7 +990,7 @@
CCFlagBits flags = cfofBits;
uint64_t top = PSrcReg1 << realShiftAmt;
uint64_t bottom = flags.cf << (realShiftAmt - 1);
-if(shiftAmt > 1) {
+if(realShiftAmt > 1) {
bottom |= bits(PSrcReg1, dataSize * 8 - 1,
dataSize * 8 - realShiftAmt + 1);
}
--
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Gerrit-Change-Id: I669f4e064e12b035538e5dd0cc61eb4546603512
Gerrit-Change-Number: 52803
Gerrit-PatchSet: 2
Gerrit-Owner: Eduardo José Gómez Hernández
Gerrit-Reviewer: Eduardo José Gómez Hernández
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega,arch-gcn3: Implement S_MEMTIME instruction
Alexandru Duțu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53603 )
Change subject: arch-vega,arch-gcn3: Implement S_MEMTIME instruction
..
arch-vega,arch-gcn3: Implement S_MEMTIME instruction
Change-Id: I3e286eb6ff8af4097ad03d4066be79f73d938cea
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/gpu-compute/gpu_static_inst.hh
M src/arch/amdgpu/gcn3/insts/instructions.cc
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc
b/src/arch/amdgpu/gcn3/insts/instructions.cc
index bb15957..9bc0369 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -5318,6 +5318,11 @@
Inst_SMEM__S_MEMTIME::Inst_SMEM__S_MEMTIME(InFmt_SMEM *iFmt)
: Inst_SMEM(iFmt, "s_memtime")
{
+// Unlike other SMEM instructions, S_MEMTIME does not actually
issue a
+// request to memory. To simplify the implementation, we model it
as an
+// ALU instruction.
+unsetFlag(SMEM);
+setFlag(ALU);
} // Inst_SMEM__S_MEMTIME
Inst_SMEM__S_MEMTIME::~Inst_SMEM__S_MEMTIME()
@@ -5328,7 +5333,10 @@
void
Inst_SMEM__S_MEMTIME::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+ScalarOperandU64 sdst(gpuDynInst, instData.SDATA);
+sdst = (ScalarRegU64) curTick() /
+ gpuDynInst->computeUnit()->clockPeriod();
+sdst.write();
}
Inst_SMEM__S_MEMREALTIME::Inst_SMEM__S_MEMREALTIME(InFmt_SMEM *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 1e07f0b..4650aa8 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -5841,6 +5841,11 @@
Inst_SMEM__S_MEMTIME::Inst_SMEM__S_MEMTIME(InFmt_SMEM *iFmt)
: Inst_SMEM(iFmt, "s_memtime")
{
+// Unlike other SMEM instructions, S_MEMTIME does not actually
issue a
+// request to memory. To simplify the implementation, we model it
as an
+// ALU instruction.
+unsetFlag(SMEM);
+setFlag(ALU);
} // Inst_SMEM__S_MEMTIME
Inst_SMEM__S_MEMTIME::~Inst_SMEM__S_MEMTIME()
@@ -5852,7 +5857,10 @@
void
Inst_SMEM__S_MEMTIME::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+ScalarOperandU64 sdst(gpuDynInst, instData.SDATA);
+sdst = (ScalarRegU64) curTick() /
+ gpuDynInst->computeUnit()->clockPeriod();
+sdst.write();
} // execute
// --- Inst_SMEM__S_MEMREALTIME class methods ---
diff --git a/src/gpu-compute/gpu_static_inst.hh
b/src/gpu-compute/gpu_static_inst.hh
index 8de6c89..a15e912 100644
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -262,6 +262,7 @@
executed_as = enums::SC_ARG;
}
}
+void unsetFlag(Flags flag) { _flags[flag] = false; }
const std::string& opcode() const { return _opcode; }
const std::vector& srcOperands() const { return srcOps; }
--
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Gerrit-Change-Id: I3e286eb6ff8af4097ad03d4066be79f73d938cea
Gerrit-Change-Number: 53603
Gerrit-PatchSet: 1
Gerrit-Owner: Alexandru Duțu
Gerrit-CC: Michael Boyer
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache,python: Allow custom TLB and events in each prefetcher.
Isaac Sánchez Barrera has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32394 )
Change subject: mem-cache,python: Allow custom TLB and events in each
prefetcher.
..
mem-cache,python: Allow custom TLB and events in each prefetcher.
The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object. This change redefines them as `None` by default and sets the
value to a per-object empty list before inserting the first element.
Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off by: Isaac Sánchez Barrera
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index f131ccf..d6a01b9 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -80,17 +80,21 @@
use_virtual_addresses = Param.Bool(False,
"Use virtual addresses for prefetching")
-_events = []
+_events = None
def addEvent(self, newObject):
+if not self._events:
+self._events = []
self._events.append(newObject)
# Override the normal SimObject::regProbeListeners method and
# register deferred event handlers.
def regProbeListeners(self):
-for tlb in self._tlbs:
-self.getCCObject().addTLB(tlb.getCCObject())
-for event in self._events:
- event.register()
+if self._tlbs:
+for tlb in self._tlbs:
+self.getCCObject().addTLB(tlb.getCCObject())
+if self._events:
+for event in self._events:
+event.register()
self.getCCObject().regProbeListeners()
def listenFromProbe(self, simObj, *probeNames):
@@ -99,10 +103,13 @@
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
-_tlbs = []
+
+_tlbs = None
def registerTLB(self, simObj):
if not isinstance(simObj, SimObject):
raise TypeError("argument must be a SimObject type")
+if not self._tlbs:
+self._tlbs = []
self._tlbs.append(simObj)
class MultiPrefetcher(BasePrefetcher):
--
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Gerrit-Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Gerrit-Change-Number: 32394
Gerrit-PatchSet: 1
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache,python: Allow custom TLB and events in each prefetcher.
Isaac Sánchez Barrera has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32394 )
Change subject: mem-cache,python: Allow custom TLB and events in each
prefetcher.
..
mem-cache,python: Allow custom TLB and events in each prefetcher.
The `BasePrefetcher` python class had members `_events` and `_tlbs`
defined as lists, meaning that any call to `list.append` on them would
affect `_events` and `_tlbs` for all prefetchers, not just the calling
object. This change redefines them as instance members to fix the
problem.
Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Signed-off-by: Isaac Sánchez Barrera
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32394
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
---
M src/mem/cache/prefetch/Prefetcher.py
1 file changed, 7 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index f131ccf..c163028 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -80,7 +80,11 @@
use_virtual_addresses = Param.Bool(False,
"Use virtual addresses for prefetching")
-_events = []
+def __init__(self, **kwargs):
+super(BasePrefetcher, self).__init__(**kwargs)
+self._events = []
+self._tlbs = []
+
def addEvent(self, newObject):
self._events.append(newObject)
@@ -90,7 +94,7 @@
for tlb in self._tlbs:
self.getCCObject().addTLB(tlb.getCCObject())
for event in self._events:
- event.register()
+event.register()
self.getCCObject().regProbeListeners()
def listenFromProbe(self, simObj, *probeNames):
@@ -99,7 +103,7 @@
if len(probeNames) <= 0:
raise TypeError("probeNames must have at least one element")
self.addEvent(HWPProbeEvent(self, simObj, *probeNames))
-_tlbs = []
+
def registerTLB(self, simObj):
if not isinstance(simObj, SimObject):
raise TypeError("argument must be a SimObject type")
--
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Gerrit-Change-Id: I68feb1d6d78e2fa5e8775afba8c81c6dd0de6c60
Gerrit-Change-Number: 32394
Gerrit-PatchSet: 4
Gerrit-Owner: Isaac Sánchez Barrera
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Isaac Sánchez Barrera
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: ZHENGRONG WANG
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86,cpu: Fix bpred by annotating branch instructions in x86
branchTarget
+using StaticInst::branchTarget;
};
}};
@@ -101,6 +107,17 @@
%(constructor)s;
%(cond_control_flag_init)s;
}
+
+X86ISA::PCState
+%(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
+{
+X86ISA::PCState pcs = branchPC;
+DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
+pcs, (int16_t)target);
+pcs.nupc(target);
+pcs.uAdvance();
+return pcs;
+}
}};
output decoder {{
@@ -173,7 +190,8 @@
"else_code": "nuIP = nuIP;",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": "flags[IsCondControl] = true"})
+ "cond_control_flag_init": "flags[IsCondControl] = true; \
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
@@ -191,7 +209,8 @@
{"code": "", "else_code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
ecfBit | ezfBit, cc)",
- "cond_control_flag_init": ""})
+ "cond_control_flag_init": "flags[IsUncondControl] = true;\
+ flags[IsDirectControl] = true;"})
exec_output += SeqOpExecute.subst(iop)
header_output += SeqOpDeclare.subst(iop)
decoder_output += SeqOpConstructor.subst(iop)
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index 968bbc7..cf3d601 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -747,8 +747,9 @@
DPRINTF(Decode,
"[tid:%i] [sn:%llu] "
-"Updating predictions: PredPC: %s\n",
-tid, inst->seqNum, target);
+ "Updating predictions: Wrong predicted target: %s \
+PredPC: %s\n",
+ tid, inst->seqNum, inst->readPredTarg(), target);
//The micro pc after an instruction level branch should be
0
inst->setPredTarg(target);
break;
--
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Gerrit-Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
Gerrit-Change-Number: 29154
Gerrit-PatchSet: 2
Gerrit-Owner: Juan Manuel Cebrián González
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Juan Manuel Cebrián González
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Network can use custom data msg size
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31256 )
Change subject: mem-ruby: Network can use custom data msg size
..
mem-ruby: Network can use custom data msg size
The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.
Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31256
Reviewed-by: Jason Lowe-Power
Reviewed-by: Srikant Bharadwaj
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/Network.cc
M src/mem/ruby/network/Network.hh
M src/mem/ruby/network/Network.py
3 files changed, 10 insertions(+), 7 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Srikant Bharadwaj: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/Network.cc
b/src/mem/ruby/network/Network.cc
index cda99b1..a676a38 100644
--- a/src/mem/ruby/network/Network.cc
+++ b/src/mem/ruby/network/Network.cc
@@ -55,6 +55,10 @@
m_virtual_networks = p->number_of_virtual_networks;
m_control_msg_size = p->control_msg_size;
+fatal_if(p->data_msg_size > p->ruby_system->getBlockSizeBytes(),
+ "%s: data message size > cache line size", name());
+m_data_msg_size = p->data_msg_size + m_control_msg_size;
+
params()->ruby_system->registerNetwork(this);
// Populate localNodeVersions with the version of each MachineType in
@@ -150,12 +154,6 @@
delete m_topology_ptr;
}
-void
-Network::init()
-{
-m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size;
-}
-
uint32_t
Network::MessageSizeType_to_int(MessageSizeType size_type)
{
diff --git a/src/mem/ruby/network/Network.hh
b/src/mem/ruby/network/Network.hh
index f151aed..371ceb8 100644
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -82,7 +82,6 @@
{ return dynamic_cast(_params); }
virtual ~Network();
-void init() override;
static uint32_t getNumberOfVirtualNetworks() { return
m_virtual_networks; }
int getNumNodes() const { return m_nodes; }
diff --git a/src/mem/ruby/network/Network.py
b/src/mem/ruby/network/Network.py
index 8999ff1..5febaad 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
+from m5.proxy import *
from m5.objects.ClockedObject import ClockedObject
from m5.objects.BasicLink import BasicLink
@@ -53,3 +54,8 @@
slave = DeprecatedParam(in_port, '`slave` is now called `in_port`')
out_port = VectorRequestPort("CPU output port")
master = DeprecatedParam(out_port, '`master` is now called `out_port`')
+
+data_msg_size = Param.Int(Parent.block_size_bytes,
+"Size of data messages. Defaults to the
parent "
+"RubySystem cache line size.")
+
--
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Gerrit-Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Gerrit-Change-Number: 31256
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Bradford Beckmann
Gerrit-CC: Matthew Poremba
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix include dependency
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31258 )
Change subject: mem-ruby: fix include dependency
..
mem-ruby: fix include dependency
Removed include dependency between WriteMask and RubySystem.
Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31258
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/WriteMask.cc
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
3 files changed, 9 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/WriteMask.cc
b/src/mem/ruby/common/WriteMask.cc
index 4585077..54ba8ff 100644
--- a/src/mem/ruby/common/WriteMask.cc
+++ b/src/mem/ruby/common/WriteMask.cc
@@ -32,6 +32,11 @@
#include "mem/ruby/system/RubySystem.hh"
+WriteMask::WriteMask()
+: mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
+ mAtomic(false)
+{}
+
void
WriteMask::print(std::ostream& out) const
{
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 6e3ea29..f1e5f37 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -46,18 +46,16 @@
#include
#include
+#include "base/amo.hh"
+#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
-#include "mem/ruby/system/RubySystem.hh"
class WriteMask
{
public:
typedef std::vector> AtomicOpVector;
-WriteMask()
- : mSize(RubySystem::getBlockSizeBytes()), mMask(mSize, false),
-mAtomic(false)
-{}
+WriteMask();
WriteMask(int size)
: mSize(size), mMask(size, false), mAtomic(false)
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 155d134..a5a18ff 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -55,6 +55,7 @@
#include "mem/ruby/common/DataBlock.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/common/WriteMask.hh"
+#include "mem/ruby/protocol/RubyRequestType.hh"
inline Cycles zero_time() { return Cycles(0); }
--
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Gerrit-Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Gerrit-Change-Number: 31258
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MessageBuffer capacity check
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31254 ) Change subject: mem-ruby: MessageBuffer capacity check .. mem-ruby: MessageBuffer capacity check Trip assert if call enqueue on a full message buffer. Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31254 Maintainer: Jason Lowe-Power Tested-by: kokoro Reviewed-by: Jason Lowe-Power Reviewed-by: Matthew Poremba --- M src/mem/ruby/network/MessageBuffer.cc 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Matthew Poremba: Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc index 3db8515..fb1d734 100644 --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -225,6 +225,9 @@ // Increment the number of messages statistic m_buf_msgs++; +assert((m_max_size == 0) || + ((m_prio_heap.size() + m_stall_map_size) <= m_max_size)); + DPRINTF(RubyQueue, "Enqueue arrival_time: %lld, Message: %s\n", arrival_time, *(message.get())); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31254 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d Gerrit-Change-Number: 31254 Gerrit-PatchSet: 4 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Allow same-cycle enqueue
ot;)
out_port = RequestPort("Request port to MessageBuffer receiver")
master = DeprecatedParam(out_port, '`master` is now called `out_port`')
--
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Gerrit-Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Gerrit-Change-Number: 31255
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: additional WriteMask methods
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31257 )
Change subject: mem-ruby: additional WriteMask methods
..
mem-ruby: additional WriteMask methods
Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31257
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/common/WriteMask.hh
M src/mem/ruby/protocol/RubySlicc_Exports.sm
2 files changed, 51 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/common/WriteMask.hh
b/src/mem/ruby/common/WriteMask.hh
index 6a0a041..6e3ea29 100644
--- a/src/mem/ruby/common/WriteMask.hh
+++ b/src/mem/ruby/common/WriteMask.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2012-15 Advanced Micro Devices, Inc.
* All rights reserved.
*
@@ -69,18 +81,18 @@
}
bool
-test(int offset)
+test(int offset) const
{
assert(offset < mSize);
return mMask[offset];
}
void
-setMask(int offset, int len)
+setMask(int offset, int len, bool val = true)
{
assert(mSize >= (offset + len));
for (int i = 0; i < len; i++) {
-mMask[offset + i] = true;
+mMask[offset + i] = val;
}
}
void
@@ -163,6 +175,33 @@
}
}
+void
+setInvertedMask(const WriteMask & writeMask)
+{
+assert(mSize == writeMask.mSize);
+for (int i = 0; i < mSize; i++) {
+mMask[i] = !writeMask.mMask.at(i);
+}
+}
+
+int
+firstBitSet(bool val, int offset = 0) const
+{
+for (int i = offset; i < mSize; ++i)
+if (mMask[i] == val)
+return i;
+return mSize;
+}
+
+int
+count(int offset = 0) const
+{
+int count = 0;
+for (int i = offset; i < mSize; ++i)
+count += mMask[i];
+return count;
+}
+
void print(std::ostream& out) const;
void
diff --git a/src/mem/ruby/protocol/RubySlicc_Exports.sm
b/src/mem/ruby/protocol/RubySlicc_Exports.sm
index ea61350..1b67dc6 100644
--- a/src/mem/ruby/protocol/RubySlicc_Exports.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Exports.sm
@@ -58,7 +58,16 @@
bool isFull();
bool isOverlap(WriteMask);
void orMask(WriteMask);
+ void setInvertedMask(WriteMask);
void fillMask();
+ void setMask(int,int);
+ bool getMask(int,int);
+ void setMask(int,int,bool);
+ int firstBitSet(bool);
+ int firstBitSet(bool,int);
+ int count();
+ int count(int);
+ bool test(int);
}
structure(DataBlock, external = "yes", desc="..."){
--
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Gerrit-Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Gerrit-Change-Number: 31257
Gerrit-PatchSet: 4
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: move AddrRange propagation to RubyPort
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31268 )
Change subject: mem-ruby: move AddrRange propagation to RubyPort
..
mem-ruby: move AddrRange propagation to RubyPort
Doing the master address range notification from the RubyPort.
This allows us the DMASequencer to be replaced by Sequencer in future
protocols.
Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31268
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/system/DMASequencer.cc
M src/mem/ruby/system/RubyPort.cc
2 files changed, 2 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/system/DMASequencer.cc
b/src/mem/ruby/system/DMASequencer.cc
index 938044a..4c61dd2 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -56,9 +56,6 @@
{
RubyPort::init();
m_data_block_mask = mask(RubySystem::getBlockSizeBits());
-
-for (const auto &response_port : response_ports)
-response_port->sendRangeChange();
}
RequestStatus
diff --git a/src/mem/ruby/system/RubyPort.cc
b/src/mem/ruby/system/RubyPort.cc
index 116f04f..2469710 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -86,6 +86,8 @@
{
assert(m_controller != NULL);
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
+for (const auto &response_port : response_ports)
+response_port->sendRangeChange();
}
Port &
--
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Gerrit-Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Gerrit-Change-Number: 31268
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: sequencer callback for unique writes
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31269 )
Change subject: mem-ruby: sequencer callback for unique writes
..
mem-ruby: sequencer callback for unique writes
A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.
Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31269
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
---
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/system/Sequencer.cc
M src/mem/ruby/system/Sequencer.hh
3 files changed, 21 insertions(+), 2 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index b4854d4..a7b9d34 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -129,6 +129,7 @@
void writeCallback(Addr, DataBlock, bool, MachineType);
void writeCallback(Addr, DataBlock, bool, MachineType,
Cycles, Cycles, Cycles);
+ void writeUniqueCallback(Addr, DataBlock);
// ll/sc support
void writeCallbackScFail(Addr, DataBlock);
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index 0614c11..6b50636 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -352,7 +352,8 @@
const bool externalHit, const MachineType mach,
const Cycles initialRequestTime,
const Cycles forwardRequestTime,
- const Cycles firstResponseTime)
+ const Cycles firstResponseTime,
+ const bool noCoales)
{
//
// Free the whole list as we assume we have had the exclusive access
@@ -370,6 +371,15 @@
int aliased_loads = 0;
while (!seq_req_list.empty()) {
SequencerRequest &seq_req = seq_req_list.front();
+
+if (noCoales && !ruby_request) {
+// Do not process follow-up requests
+// (e.g. if full line no present)
+// Reissue to the cache hierarchy
+issueRequest(seq_req.pkt, seq_req.m_second_type);
+break;
+}
+
if (ruby_request) {
assert(seq_req.m_type != RubyRequestType_LD);
assert(seq_req.m_type != RubyRequestType_Load_Linked);
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 4a5e281..e1a3c2d 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -103,7 +103,15 @@
const MachineType mach = MachineType_NUM,
const Cycles initialRequestTime = Cycles(0),
const Cycles forwardRequestTime = Cycles(0),
- const Cycles firstResponseTime = Cycles(0));
+ const Cycles firstResponseTime = Cycles(0),
+ const bool noCoales = false);
+
+// Write callback that prevents coalescing
+void writeUniqueCallback(Addr address, DataBlock& data)
+{
+writeCallback(address, data, true, MachineType_NUM, Cycles(0),
+ Cycles(0), Cycles(0), true);
+}
void readCallback(Addr address,
DataBlock& data,
--
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Gerrit-Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Gerrit-Change-Number: 31269
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Alexandru Duțu
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: change MessageBuffer randomization param
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31419 )
Change subject: mem-ruby: change MessageBuffer randomization param
..
mem-ruby: change MessageBuffer randomization param
There are cases in which we need to prevent randomization for a
specific buffer when enabled at the RubySystem level (e.g. a internal
trigger queue that requires zero latency enqueue, while other buffers
can be randomized).
This changes the randomization parameter to support enabling and
disabling randomization regardless of the RubySystem setting.
Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31419
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
M src/mem/ruby/network/MessageBuffer.py
3 files changed, 15 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/MessageBuffer.cc
b/src/mem/ruby/network/MessageBuffer.cc
index 8843694..00e8fea 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -176,9 +176,11 @@
assert((delta > 0) || m_allow_zero_latency);
Tick arrival_time = 0;
-// random delays are inserted if either RubySystem level randomization
flag
-// is turned on, or the buffer level randomization is set
-if (!RubySystem::getRandomization() && !m_randomization) {
+// random delays are inserted if the RubySystem level randomization
flag
+// is turned on and this buffer allows it
+if ((m_randomization == MessageRandomization::disabled) ||
+((m_randomization == MessageRandomization::ruby_system) &&
+ !RubySystem::getRandomization())) {
// No randomization
arrival_time = current_time + delta;
} else {
diff --git a/src/mem/ruby/network/MessageBuffer.hh
b/src/mem/ruby/network/MessageBuffer.hh
index 3887340..fc69d34 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -248,7 +248,7 @@
uint64_t m_msg_counter;
int m_priority_rank;
const bool m_strict_fifo;
-const bool m_randomization;
+const MessageRandomization m_randomization;
const bool m_allow_zero_latency;
int m_input_link_id;
diff --git a/src/mem/ruby/network/MessageBuffer.py
b/src/mem/ruby/network/MessageBuffer.py
index 297835f..807ffb4 100644
--- a/src/mem/ruby/network/MessageBuffer.py
+++ b/src/mem/ruby/network/MessageBuffer.py
@@ -40,6 +40,13 @@
from m5.proxy import *
from m5.SimObject import SimObject
+# A MessageBuffer inserts random delays to enqueued messages when the
+# randomization param is set to 'enabled' or when globally enabled for the
+# RubySystem and the param is set to 'ruby_system' (default). 'disabled'
+# completely prevents randomization.
+class MessageRandomization(ScopedEnum):
+vals = ['disabled', 'enabled', 'ruby_system']
+
class MessageBuffer(SimObject):
type = 'MessageBuffer'
cxx_class = 'MessageBuffer'
@@ -47,10 +54,8 @@
ordered = Param.Bool(False, "Whether the buffer is ordered")
buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \
(0 allows infinite entries)")
-randomization = Param.Bool(False, "Insert random delays on message \
- enqueue times (enforced to have \
- random delays if RubySystem \
- randomization flag is True)")
+randomization = Param.MessageRandomization('ruby_system',
+ "Randomization parameter")
allow_zero_latency = Param.Bool(False, "Allows messages to be enqueued
\
with zero latency. This is
useful \
for internall trigger queues
and \
--
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Gerrit-Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Gerrit-Change-Number: 31419
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: expose transition info to actions
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31420 )
Change subject: mem-ruby: expose transition info to actions
..
mem-ruby: expose transition info to actions
SLICC compiler generates the curTransitionEvent and
curTransitionNextState functions, which allows actions to check which
event triggered the current transition and what's the next state.
Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31420
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/slicc/symbols/StateMachine.py
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/slicc/symbols/StateMachine.py
b/src/mem/slicc/symbols/StateMachine.py
index 1399d00..c019e1b 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -380,6 +380,12 @@
code('''
Addr addr);
+${ident}_Event m_curTransitionEvent;
+${ident}_State m_curTransitionNextState;
+
+${ident}_Event curTransitionEvent() { return m_curTransitionEvent; }
+${ident}_State curTransitionNextState() { return m_curTransitionNextState;
}
+
int m_counters[${ident}_State_NUM][${ident}_Event_NUM];
int m_event_counters[${ident}_Event_NUM];
bool m_possible[${ident}_State_NUM][${ident}_Event_NUM];
@@ -1407,6 +1413,8 @@
code('''
Addr addr)
{
+m_curTransitionEvent = event;
+m_curTransitionNextState = next_state;
switch(HASH_FUN(state, event)) {
''')
@@ -1427,10 +1435,12 @@
# is determined before any actions of the transition
# execute, and therefore the next state calculation
cannot
# depend on any of the transitionactions.
-case('next_state = getNextState(addr);')
+case('next_state = getNextState(addr); '
+ 'm_curTransitionNextState = next_state;')
else:
ns_ident = trans.nextState.ident
-case('next_state = ${ident}_State_${ns_ident};')
+case('next_state = ${ident}_State_${ns_ident}; '
+ 'm_curTransitionNextState = next_state;')
actions = trans.actions
request_types = trans.request_types
--
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Gerrit-Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Gerrit-Change-Number: 31420
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-CC: Bradford Beckmann
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: missing method in NetDest interface
Tiago Mück has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31262 ) Change subject: mem-ruby: missing method in NetDest interface .. mem-ruby: missing method in NetDest interface Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Signed-off-by: Tiago Mück Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31262 Reviewed-by: Matthew Poremba Maintainer: Bradford Beckmann Tested-by: kokoro --- M src/mem/ruby/protocol/RubySlicc_Types.sm 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Matthew Poremba: Looks good to me, approved Bradford Beckmann: Looks good to me, approved kokoro: Regressions pass diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm index 9c64732..b4854d4 100644 --- a/src/mem/ruby/protocol/RubySlicc_Types.sm +++ b/src/mem/ruby/protocol/RubySlicc_Types.sm @@ -111,6 +111,7 @@ bool isEmpty(); bool intersectionIsEmpty(Set); bool intersectionIsEmpty(NetDest); + MachineID smallestElement(); MachineID smallestElement(MachineType); NetDest OR(NetDest); NetDest AND(NetDest); -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31262 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33 Gerrit-Change-Number: 31262 Gerrit-PatchSet: 5 Gerrit-Owner: Tiago Mück Gerrit-Reviewer: Bradford Beckmann Gerrit-Reviewer: Matthew Poremba Gerrit-Reviewer: Tiago Mück Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: int to Cycle converter
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31266 )
Change subject: mem-ruby: int to Cycle converter
..
mem-ruby: int to Cycle converter
Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31266
Reviewed-by: Jason Lowe-Power
Reviewed-by: Matthew Poremba
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/ruby/protocol/RubySlicc_Util.sm
M src/mem/ruby/slicc_interface/RubySlicc_Util.hh
2 files changed, 3 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/RubySlicc_Util.sm
b/src/mem/ruby/protocol/RubySlicc_Util.sm
index f509d09..b8b005a 100644
--- a/src/mem/ruby/protocol/RubySlicc_Util.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Util.sm
@@ -32,6 +32,7 @@
void error(std::string msg);
void assert(bool condition);
Cycles zero_time();
+Cycles intToCycles(int c);
NodeID intToID(int nodenum);
int IDToInt(NodeID id);
int addressToInt(Addr addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index a5a18ff..b51b30c 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -59,6 +59,8 @@
inline Cycles zero_time() { return Cycles(0); }
+inline Cycles intToCycles(int c) { return Cycles(c); }
+
inline NodeID
intToID(int nodenum)
{
--
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Gerrit-Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Gerrit-Change-Number: 31266
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added function to check addr range
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31263 )
Change subject: mem-ruby: added function to check addr range
..
mem-ruby: added function to check addr range
respondsTo checks if a controller address ranges includes a given
address.
Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31263
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Bradford Beckmann
---
M src/mem/ruby/slicc_interface/AbstractController.hh
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 98cb0a7..cbe92c0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -153,6 +153,13 @@
Stats::Histogram& getDelayVCHist(uint32_t index)
{ return *(m_delayVCHistogram[index]); }
+bool respondsTo(Addr addr)
+{
+for (auto &range: addrRanges)
+if (range.contains(addr)) return true;
+return false;
+}
+
/**
* Map an address to the correct MachineID
*
--
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Gerrit-Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Gerrit-Change-Number: 31263
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Sequencer can be used without cache
/ruby/MOESI_CMP_token.py
@@ -117,7 +117,7 @@
clk_domain=clk_domain,
ruby_system=ruby_system)
-cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+cpu_seq = RubySequencer(version=i,
dcache=l1d_cache, clk_domain=clk_domain,
ruby_system=ruby_system)
diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index c83bb72..1e00f0f 100644
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -109,7 +109,7 @@
clk_domain=clk_domain,
ruby_system=ruby_system)
-cpu_seq = RubySequencer(version=i, icache=l1i_cache,
+cpu_seq = RubySequencer(version=i,
dcache=l1d_cache,clk_domain=clk_domain,
ruby_system=ruby_system)
diff --git a/src/mem/ruby/system/Sequencer.cc
b/src/mem/ruby/system/Sequencer.cc
index dbc85c4..0614c11 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -73,7 +73,6 @@
{
m_outstanding_count = 0;
-m_instCache_ptr = p->icache;
m_dataCache_ptr = p->dcache;
m_max_outstanding_requests = p->max_outstanding_requests;
m_deadlock_threshold = p->deadlock_threshold;
@@ -81,8 +80,6 @@
m_coreId = p->coreid; // for tracking the two CorePair sequencers
assert(m_max_outstanding_requests > 0);
assert(m_deadlock_threshold > 0);
-assert(m_instCache_ptr != NULL);
-assert(m_dataCache_ptr != NULL);
m_runningGarnetStandalone = p->garnet_standalone;
}
@@ -94,6 +91,8 @@
void
Sequencer::llscLoadLinked(const Addr claddr)
{
+fatal_if(m_dataCache_ptr == NULL,
+"%s must have a dcache object to support LLSC requests.", name());
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line) {
line->setLocked(m_version);
@@ -105,6 +104,9 @@
void
Sequencer::llscClearMonitor(const Addr claddr)
{
+// clear monitor is called for all stores and evictions
+if (m_dataCache_ptr == NULL)
+return;
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (line && line->isLocked(m_version)) {
line->clearLocked();
@@ -116,6 +118,8 @@
bool
Sequencer::llscStoreConditional(const Addr claddr)
{
+fatal_if(m_dataCache_ptr == NULL,
+"%s must have a dcache object to support LLSC requests.", name());
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
return false;
@@ -137,6 +141,7 @@
bool
Sequencer::llscCheckMonitor(const Addr address)
{
+assert(m_dataCache_ptr != NULL);
const Addr claddr = makeLineAddress(address);
AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
if (!line)
diff --git a/src/mem/ruby/system/Sequencer.hh
b/src/mem/ruby/system/Sequencer.hh
index 92fdab6..4a5e281 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -212,7 +212,6 @@
int m_max_outstanding_requests;
CacheMemory* m_dataCache_ptr;
-CacheMemory* m_instCache_ptr;
// The cache access latency for top-level caches (L0/L1). These are
// currently assessed at the beginning of each memory access through
the
diff --git a/src/mem/ruby/system/Sequencer.py
b/src/mem/ruby/system/Sequencer.py
index 0a28d36..0acd87a 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2009 Advanced Micro Devices, Inc.
# Copyright (c) 2020 ARM Limited
# All rights reserved.
@@ -76,7 +88,6 @@
cxx_class = 'Sequencer'
cxx_header = "mem/ruby/system/Sequencer.hh"
- icache = Param.RubyCache("")
dcache = Param.RubyCache("")
max_outstanding_requests = Param.Int(16,
--
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Gerrit-Change-Number: 31267
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerri
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: support for template types in structs
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31264 )
Change subject: mem-ruby: support for template types in structs
..
mem-ruby: support for template types in structs
Templated types can now be used within structures defined in SLICC.
Usage is similar to the TBETable: the templated type must have all
possible methods in it's SLICC definition. Eg.:
structure(Map, desc="Template map definition") {
MachineID lookup(Addr);
MachineID lookup(int);
}
structure(SomeType, desc="Some other struct definition") {
MachineID addrMap, template="";
MachineID intMap, template="";
}
Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31264
Reviewed-by: Matthew Poremba
Reviewed-by: Bradford Beckmann
Maintainer: Bradford Beckmann
Tested-by: kokoro
---
M src/mem/slicc/symbols/Type.py
1 file changed, 23 insertions(+), 7 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
index fa5e79a..ee319cb 100644
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
# Copyright (c) 2009 The Hewlett-Packard Development Company
# All rights reserved.
@@ -37,6 +49,9 @@
super(DataMember, self).__init__(symtab, ident, location, type,
code, pairs, machine)
self.init_code = init_code
+self.real_c_type = self.type.c_ident
+if "template" in pairs:
+self.real_c_type += pairs["template"]
class Enumeration(PairContainer):
def __init__(self, ident, pairs):
@@ -235,8 +250,9 @@
code('m_$ident = ${{dm["default"]}}; // default for
this field')
elif "default" in dm.type:
# Look for the type default
-tid = dm.type.c_ident
-code('m_$ident = ${{dm.type["default"]}}; // default
value of $tid')
+tid = dm.real_c_type
+code('m_$ident = ${{dm.type["default"]}};')
+code(' // default value of $tid')
else:
code('// m_$ident has no default')
code.dedent()
@@ -268,7 +284,7 @@
# Full init constructor
if not self.isGlobal:
-params = [ 'const %s& local_%s' % (dm.type.c_ident, dm.ident) \
+params = [ 'const %s& local_%s' % (dm.real_c_type, dm.ident) \
for dm in self.data_members.values() ]
params = ', '.join(params)
@@ -318,7 +334,7 @@
/** \\brief Const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-const ${{dm.type.c_ident}}&
+const ${{dm.real_c_type}}&
get${{dm.ident}}() const
{
return m_${{dm.ident}};
@@ -332,7 +348,7 @@
/** \\brief Non-const accessor method for ${{dm.ident}} field.
* \\return ${{dm.ident}} field
*/
-${{dm.type.c_ident}}&
+${{dm.real_c_type}}&
get${{dm.ident}}()
{
return m_${{dm.ident}};
@@ -345,7 +361,7 @@
code('''
/** \\brief Mutator method for ${{dm.ident}} field */
void
-set${{dm.ident}}(const ${{dm.type.c_ident}}& local_${{dm.ident}})
+set${{dm.ident}}(const ${{dm.real_c_type}}& local_${{dm.ident}})
{
m_${{dm.ident}} = local_${{dm.ident}};
}
@@ -375,7 +391,7 @@
if "desc" in dm:
code('/** ${{dm["desc"]}} */')
-code('$const${{dm.type.c_ident}} m_${{dm.ident}}$init;')
+code('$const${{dm.real_c_type}} m_${{dm.ident}}$init;')
# Prototypes for methods defined for the Type
for item in self.methods:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: added %(mod) operator to SLICC
Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31260 )
Change subject: mem-ruby: added %(mod) operator to SLICC
..
mem-ruby: added %(mod) operator to SLICC
Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Signed-off-by: Tiago Mück
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31260
Reviewed-by: Jason Lowe-Power
Reviewed-by: John Alsop
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/mem/slicc/ast/OperatorExprAST.py
M src/mem/slicc/parser.py
2 files changed, 5 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
John Alsop: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/mem/slicc/ast/OperatorExprAST.py
b/src/mem/slicc/ast/OperatorExprAST.py
index 7752e9c..cab1369 100644
--- a/src/mem/slicc/ast/OperatorExprAST.py
+++ b/src/mem/slicc/ast/OperatorExprAST.py
@@ -64,7 +64,7 @@
elif self.op in ("<<", ">>"):
expected_types = [("int", "int", "int"),
("Cycles", "int", "Cycles")]
-elif self.op in ("+", "-", "*", "/"):
+elif self.op in ("+", "-", "*", "/", "%"):
expected_types = [("int", "int", "int"),
("Cycles", "Cycles", "Cycles"),
("Tick", "Tick", "Tick"),
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 643eec6..13dde9a 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -128,7 +128,7 @@
tokens = [ 'EQ', 'NE', 'LT', 'GT', 'LE', 'GE',
'LEFTSHIFT', 'RIGHTSHIFT',
'NOT', 'AND', 'OR',
- 'PLUS', 'DASH', 'STAR', 'SLASH',
+ 'PLUS', 'DASH', 'STAR', 'SLASH', 'MOD',
'INCR', 'DECR',
'DOUBLE_COLON', 'SEMI',
'ASSIGN', 'DOT',
@@ -150,6 +150,7 @@
t_DASH = r'-'
t_STAR = r'\*'
t_SLASH = r'/'
+t_MOD = r'%'
t_DOUBLE_COLON = r'::'
t_SEMI = r';'
t_ASSIGN = r':='
@@ -165,7 +166,7 @@
('left', 'LT', 'GT', 'LE', 'GE'),
('left', 'RIGHTSHIFT', 'LEFTSHIFT'),
('left', 'PLUS', 'DASH'),
- ('left', 'STAR', 'SLASH'),
+('left', 'STAR', 'SLASH', 'MOD'),
('right', 'NOT', 'UMINUS'),
)
@@ -695,6 +696,7 @@
def p_expr__binary_op(self, p):
"""expr : expr STAR expr
| expr SLASH expr
+| expr MOD expr
| expr PLUS expr
| expr DASH expr
| expr LTexpr
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31260
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Gerrit-Change-Number: 31260
Gerrit-PatchSet: 5
Gerrit-Owner: Tiago Mück
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: John Alsop
Gerrit-Reviewer: Tiago Mück
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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