[gem5-dev] Change in gem5/gem5[master]: arch-arm: Implement ARMv8.1 TTBR1_EL2 register

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add E2H bit to HCR_EL2 System register

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[gem5-dev] Change in gem5/gem5[master]: cpu: Avoid unnecessary dynamic_pointer_cast in atomic model

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: MPIDR.MT = 1 in a multithreaded system

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

.unimplemented() + .warnNotFail(impdefAsNop); // Register mappings for some unimplemented registers: // ESR_EL1 -> DFSR -- To view, visit https://gem5-review.googlesource.com/10504 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/setting

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Remove unusued MISCREG_A64_UNIMPL

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: S3____ are Implementation defined

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

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[gem5-dev] Change in gem5/gem5[master]: python: Include hasattr helper for SimObjects

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add Illegal Execution flag to PCState

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adapting IllegalExecution fault for AArch32

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[gem5-dev] Change in gem5/gem5[master]: misc: Substitute pointer to Request with aliased RequestPtr

etch/queued.cc +++ b/src/mem/cache/prefetch/queued.cc @@ -223,7 +223,7 @@ } /* Create a prefetch memory request */ -Request *pf_req = +RequestPtr pf_req = new Request(pf_info.first, blkSize, 0, masterId); if (is_secure) { -- To view, visit https://gem5-review.google

[gem5-dev] Change in gem5/gem5[master]: misc: Using smart pointers for memory Requests

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[gem5-dev] Change in gem5/gem5[master]: misc: Using smart pointers for memory Requests

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[gem5-dev] Change in gem5/gem5[master]: misc: Substitute pointer to Request with aliased RequestPtr

7 +223,7 @@ } /* Create a prefetch memory request */ - Request *pf_req = +RequestPtr pf_req = new Request(pf_info.first, blkSize, 0, masterId); if (is_secure) { -- To view, visit https://gem5-review.googlesource.com/10995 To unsubscribe

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix missing Request allocation

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Fix missing Request allocation

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Read APSR in User Mode

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Adapting IllegalExecution fault for AArch32

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Add Illegal Execution flag to PCState

); +UNSERIALIZE_SCALAR(_illegalExec); } }; -- To view, visit https://gem5-review.googlesource.com/10813 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I9c1c4e9c6b

[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

c; +result = coro(result).get(); +} + +ASSERT_STREQ(result.c_str(), expected.c_str()); +} -- To view, visit https://gem5-review.googlesource.com/11195 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7bb673a954d4a456997afd45b696933534f3e239 Gerrit-Change-Number: 11195 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: base: Add a class which encapsulates Fibers.

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: BadMode checking if corresponding EL is implemented

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

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[gem5-dev] Change in gem5/gem5[master]: cpu: Fix bug introduced by RequestPtr type change

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[gem5-dev] Change in gem5/gem5[master]: cpu: Fix bug introduced by RequestPtr type change

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: BadMode checking if corresponding EL is implemented

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: AArch32 execution triggering AArch64 SW Break

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

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[gem5-dev] Change in gem5/gem5[master]: base: Add an asymmetrical Coroutine class

mp;callee, &valid_return] +(Coroutine::CallerType& yield) +{ +callee(); +valid_return = true; +yield(); +}}; + +ASSERT_TRUE(valid_return); +} -- To view, visit https://gem5-review.googlesource.com/11195 To unsubscribe, or for help writing mail filters, visit

[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce ARMv8.1 Virtual Timer System Registers

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce RAS System Registers

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce RAS System Registers

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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Introduce ARMv8.1 Virtual Timer System Registers

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[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

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[gem5-dev] Change in gem5/gem5[master]: cpu: Allow creation of traffic gen from generic SimObjects

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[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

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[gem5-dev] Change in gem5/gem5[master]: cpu: Warn when (un)serializing a traffic generator

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[gem5-dev] Change in gem5/gem5[master]: cpu: Turn BaseTrafficGen numSuppressed into a stat

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[gem5-dev] Change in gem5/gem5[master]: cpu: Warn when (un)serializing a traffic generator

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[gem5-dev] Change in gem5/gem5[master]: cpu: Allow creation of traffic gen from generic SimObjects

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[gem5-dev] Change in gem5/gem5[master]: base: Fix ucontext compilation error for macOS

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

27;s not time to send the response yet. The - * responses are stored seperately mostly to keep the code clean + * responses are stored separately mostly to keep the code clean * and help with events scheduling. For all logical purposes such * as sizing the r

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

false otherwise + */ +inline bool writeQueueFull(const uint64_t packets) const; + +/** + * Receive a Packet in Atomic mode + * + * @param pkt pointer to memory packet + * @return packet access latency in ticks + */ +Tick recvAtomic(PacketPtr pkt); + +

[gem5-dev] Change in gem5/gem5[master]: sim: Add System method for MasterID lookup

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

t Params*); + +virtual ~TurnaroundPolicyIdeal(); + +/** + * Bus Selection function. + * + * @return selected bus state + */ + virtual MemCtrl::BusState selectBusState() override; +}; + +} // namespace QoS + +#endif /* __MEM_QOS_TURNAROUND_POLICY_IDEAL_HH_ */ -- To view, visit h

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/11970 Change subject: mem: Add a QoS-aware Memory Controller type .. mem: Add a QoS-aware Memory Controller type

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for RCpc load-acquire instructions (ARMv8.3)

;, 1, flavor="acquire").emit() + class LoadImmU64(LoadImm64): decConstBase = 'LoadStoreImmU64' micro = True -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11989 To unsubscribe, or for help writing mail filters, visit https:/

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for RCpc load-acquire instructions (ARMv8.3)

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

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[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0b611f13fce54dd1dd444eb806f8e98afd248bd5 Gerrit-Change-Number: 11970 Gerrit-PatchSet: 7 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Re

[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Add StreamID and SubstreamID

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[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

eset Stream or Substream ID */ +uint32_t randomPick(const std::vector &svec); +}; + +#endif // __CPU_TRAFFIC_GEN_STREAM_GEN_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12188 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49 Gerrit-Change-Number: 12188 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem: Add StreamID and SubstreamID

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[gem5-dev] Change in gem5/gem5[master]: cpu: Turn BaseTrafficGen numSuppressed into a stat

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[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

tings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iea068de581ae7125a9d49314124a08c045c75b49 Gerrit-Change-Number: 12188 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Anthony Gutierrez Gerrit-Reviewer: Giacomo Trava

[gem5-dev] Change in gem5/gem5[master]: cpu: Stream/SubstreamID support in TrafficGen

amIds); } + +uint32_t pickSubStreamID() override +{ return randomPick(substreamIds); } + + protected: +/** Function to pick one of the preset Stream or Substream ID */ +uint32_t randomPick(const std::vector &svec); +}; + +#endif // __CPU_TRAFFIC_GEN_STREAM_GEN_HH__ -- To view,

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

errit-Change-Number: 11972 Gerrit-PatchSet: 8 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Matthew Poremba Gerrit-Messag

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Create a getter for ArmInterruptPin ID number

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

std::vector history; +}; + +} // namespace QoS + +#endif // __MEM_QOS_POLICY_PF_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12359 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I7679e234b916c57ebed06cec0ff3cff3cf2aef22 Gerrit-Change-Number: 12359 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Round Robin policy

+uint64_t quantumCounter; + +std::set::iterator selector; + +std::set masters; +}; + +} // namespace QoS + +#endif // __MEM_QOS_POLICY_ROUND_ROBIN_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12358 To unsubscribe, or for help writing mail filters, visit

[gem5-dev] Change in gem5/gem5[master]: dev, arm: Add misc reg tracing to the generic timer

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[gem5-dev] Change in gem5/gem5[master]: arm: Add support for tracking TCs in ISA devices

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[gem5-dev] Change in gem5/gem5[master]: arm: Use the interrupt adaptor in the PMU

rruptPin *const interrupt; /** * List of event types supported by this PMU. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12400 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 G

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Factory SimObject for generating ArmInterruptPin

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Make GenericTimer use standard ArmInterruptPin

stem; - -/// Pointer to the GIC, needed to trigger timer interrupts. -BaseGic *const gic; - -/// Physical timer interrupt (S) -const unsigned irqPhysS; -/// Physical timer interrupt (NS) -const unsigned irqPhysNS; - -/// Virtual timer interrupt -const unsigne

[gem5-dev] Change in gem5/gem5[master]: mem: Implement base QoS Policies.

ic: +TurnaroundPolicyIdeal(const Params*); + +virtual ~TurnaroundPolicyIdeal(); + +/** + * Bus Selection function. + * + * @return selected bus state + */ + virtual MemCtrl::BusState selectBusState() override; +}; + +} // namespace QoS + +#endif /* __MEM_QOS_TURNAROU

[gem5-dev] Change in gem5/gem5[master]: mem: Add a simple QoS-aware Memory Controller

turn true if write queue is full, false otherwise + */ +inline bool writeQueueFull(const uint64_t packets) const; + +/** + * Receive a Packet in Atomic mode + * + * @param pkt pointer to memory packet + * @return packet access latency in ticks + */ +Tick rec

[gem5-dev] Change in gem5/gem5[master]: sim: Add System method for MasterID lookup

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[gem5-dev] Change in gem5/gem5[master]: mem: Make DRAMCtrl a QoS-aware Memory Controller

working * with them, but it's not time to send the response yet. The - * responses are stored seperately mostly to keep the code clean + * responses are stored separately mostly to keep the code clean * and help with events scheduling. For all logical purposes such * as s

[gem5-dev] Change in gem5/gem5[master]: mem: Add a QoS-aware Memory Controller type

Giacomo Travaglini has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/11970 ) Change subject: mem: Add a QoS-aware Memory Controller type .. mem: Add a QoS-aware Memory Controll

[gem5-dev] Change in gem5/gem5[master]: arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Create a getter for ArmInterruptPin ID number

: I095393d4d25efe13eb2a75a0b0b055d386c2c126 Gerrit-Change-Number: 12298 Gerrit-PatchSet: 2 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Ciro Santilli Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev

[gem5-dev] Change in gem5/gem5[master]: arm: Add support for tracking TCs in ISA devices

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[gem5-dev] Change in gem5/gem5[master]: dev, arm: Add misc reg tracing to the generic timer

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[gem5-dev] Change in gem5/gem5[master]: arm: Use the interrupt adaptor in the PMU

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Factory SimObject for generating ArmInterruptPin

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[gem5-dev] Change in gem5/gem5[master]: dev-arm: Make GenericTimer use standard ArmInterruptPin

hysical timer interrupt (NS) -const unsigned irqPhysNS; - -/// Virtual timer interrupt -const unsigned irqVirt; - -/// Hypervisor timer interrupt -const unsigned irqHyp; }; class GenericTimerISA : public ArmISA::BaseISADevice -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12402 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I5aa5661e48834398bd7aae15df9578b8db5c8da3 Gerrit-Change-Number: 12402 Gerrit-PatchSet: 3 Gerrit-Owner: Giacomo Travaglini Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Giacomo Travaglini Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Take into account PPI enable bit

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

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[gem5-dev] Change in gem5/gem5[master]: mem: Implement QoS Proportional Fair policy

le weight; + +/** history is keeping track of every master's score */ +using MasterHistory = std::pair; +std::vector history; +}; + +} // namespace QoS + +#endif // __MEM_QOS_POLICY_PF_HH__ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12359 To unsubscribe

[gem5-dev] Change in gem5/gem5[master]: dev-arm: Make CpuLocalTimer use standard ArmInterruptPin

or> localTimer; public: typedef CpuLocalTimerParams Params; @@ -172,6 +171,9 @@ */ CpuLocalTimer(Params *p); +/** Inits the local timers */ +void init() override; + /** * Handle a read to the device * @param pkt The memory request. -- To view, visit ht

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