[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Remove the A9GlobalTimer

2021-02-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev
LITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __DEV_ARM_GLOBAL_TIMER_HH__
-#define __DEV_ARM_GLOBAL_TIMER_HH__
-
-#include 
-
-#include "base/types.hh"
-#include "base/bitunion.hh"
-#include "base/types.hh"
-#include "dev/io_device.hh"
-#include "params/A9GlobalTimer.hh"
-#include "sim/eventq.hh"
-#include "sim/serialize.hh"
-
-/** @file
- * This implements the Cortex A9-MPCore global timer from TRM rev r4p1.
- * The global timer is an incrementing timer.
- */
-
-class BaseGic;
-
-class A9GlobalTimer : public BasicPioDevice
-{
-  protected:
-class Timer : public Serializable
-{
-
-  public:
-/* TODO: IntStatusReg, CmpValRegLow32, CmpValRegHigh32,
- * and AutoIncrementReg are banked per-cpu. Some bits of
- * ControlReg are also banked per-cpu, see below. */
-enum {
-CounterRegLow32  = 0x00,
-CounterRegHigh32 = 0x04,
-ControlReg   = 0x08,
-IntStatusReg = 0x0C,
-CmpValRegLow32   = 0x10,
-CmpValRegHigh32  = 0x14,
-AutoIncrementReg = 0x18,
-Size = 0x1C
-};
-
-/* TODO: bits 1--3 are banked per-cpu */
-BitUnion32(CTRL)
-Bitfield<0>enable;
-Bitfield<1>cmpEnable;
-Bitfield<2>intEnable;
-Bitfield<3>autoIncrement;
-Bitfield<7,4>  reserved;
-Bitfield<15,8> prescalar;
-EndBitUnion(CTRL)
-
-  protected:
-std::string _name;
-
-/** Pointer to parent class */
-A9GlobalTimer *parent;
-
-/** Number of interrupt to cause/clear */
-const uint32_t intNum;
-
-/** Control register as specified above */
-/* TODO: one per-cpu? */
-CTRL control;
-
-/** If timer has caused an interrupt. This is irrespective of
- * interrupt enable */
-/* TODO: one per-cpu */
-bool rawInt;
-
-/** If an interrupt is currently pending. Logical and of  
CTRL.intEnable

- * and rawInt */
-bool pendingInt;
-
-/** Value of the comparator */
-uint64_t cmpVal;
-
-/** Value to add to comparator when counter reaches comparator */
-/* TODO: one per-cpu */
-uint32_t autoIncValue;
-
-/** Called when the counter reaches the comparator */
-void counterAtCmpVal();
-EventWrapper cmpValEvent;
-
-  public:
-/** Restart the counter ticking */
-void restartCounter();
-/**
-  * Convert a number of ticks into the time counter format
-  * @param ticks number of ticks
-  */
-uint64_t getTimeCounterFromTicks(Tick ticks);
-Timer(std::string __name, A9GlobalTimer *parent, int int_num);
-
-std::string name() const { return _name; }
-
-/** Handle read for a single timer */
-void read(PacketPtr pkt, Addr daddr);
-
-/** Handle write for a single timer */
-void write(PacketPtr pkt, Addr daddr);
-
-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-};
-
-/** Pointer to the GIC for causing an interrupt */
-BaseGic *gic;
-
-/** Timer that does the actual work */
-Timer global_timer;
-
-  public:
-using Params = A9GlobalTimerParams;
-
-/**
-  * The constructor for RealView just registers itself with the MMU.
-  * @param p params structure
-  */
-A9GlobalTimer(const Params );
-
-/**
- * Handle a read to the device
- * @param pkt The memory request.
- * @return Returns latency of device read
- */
-Tick read(PacketPtr pkt) override;
-
-/**
- * Handle a write to the device.
-     * @param pkt The memory request.
- * @return Returns latency of device write
- */
-Tick write(PacketPtr pkt) override;
-
-void serialize(CheckpointOut ) const override;
-void unserialize(CheckpointIn ) override;
-};
-
-#endif // __DEV_ARM_GLOBAL_TIMER_HH__

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia25921cfe47e7f6b895450031abb740f94dc032d
Gerrit-Change-Number: 31937
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove unused params() definitions

2021-02-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
  public:
-PARAMS(FaultModel);
+using Params = FaultModelParams;
 FaultModel(const Params );

  
//

diff --git a/src/sim/clocked_object.hh b/src/sim/clocked_object.hh
index 12204c3..23ace92 100644
--- a/src/sim/clocked_object.hh
+++ b/src/sim/clocked_object.hh
@@ -234,7 +234,7 @@
 ClockedObject(const ClockedObjectParams );

 /** Parameters of ClockedObject */
-PARAMS(ClockedObject);
+using Params = ClockedObjectParams;

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index dc3a3d3..50c35dd 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -34,7 +34,7 @@
 class SEWorkload : public Workload
 {
   public:
-PARAMS(SEWorkload);
+using Params = SEWorkloadParams;

 SEWorkload(const Params );


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Gerrit-Change-Id: Id71829aca71341d46964d8f071099342b946b62f
Gerrit-Change-Number: 41613
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove duplicate isPow2 helper

2021-02-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41533 )


Change subject: base: Remove duplicate isPow2 helper
..

base: Remove duplicate isPow2 helper

This is already defined as isPowerOf2 in src/base/intmath.hh and it
is currently unused

Change-Id: I50b5d344e234fe1d4f1f85186686440773a209e3
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41533
Tested-by: kokoro 
---
M src/base/bitfield.hh
M src/base/bitfield.test.cc
M src/base/intmath.test.cc
3 files changed, 2 insertions(+), 26 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 470941a..9dc7722 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -304,14 +304,6 @@
 }

 /**
- * Checks if a number is a power of two, or zero.
- *
- * @ingroup api_bitfield
- */
-template 
-constexpr inline bool isPow2(T v) { return (v & (v - 1)) == (T)0; }
-
-/**
  * Returns the number of set ones in the provided value.
  * PD algorithm from
  * http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 51c316e..8097415 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -290,24 +290,6 @@
 EXPECT_EQ(64, findLsbSet(0));
 }

-/* The following tests a simple function that verifies whether a value is a
- * a power of two or not.
- */
-TEST(BitfieldTest, IsPow2)
-{
-EXPECT_TRUE(isPow2(32));
-}
-
-TEST(BitfieldTest, IsNotPow2)
-{
-EXPECT_FALSE(isPow2(36));
-}
-
-TEST(BitfieldTest, IsPow2Zero)
-{
-EXPECT_TRUE(isPow2(0));
-}
-
 /*
  * The following tests "popCount(X)". popCount counts the number of bits  
set to

  * one.
diff --git a/src/base/intmath.test.cc b/src/base/intmath.test.cc
index 4e88b00..e985a1b 100644
--- a/src/base/intmath.test.cc
+++ b/src/base/intmath.test.cc
@@ -33,10 +33,12 @@
 TEST(IntmathTest, isPowerOf2)
 {
 EXPECT_TRUE(isPowerOf2(1));
+EXPECT_TRUE(isPowerOf2(32));
 EXPECT_TRUE(isPowerOf2(65536));
 EXPECT_TRUE(isPowerOf2(131072));
 EXPECT_TRUE(isPowerOf2(262144));
 EXPECT_FALSE(isPowerOf2(0));
+EXPECT_FALSE(isPowerOf2(36));
 EXPECT_FALSE(isPowerOf2(2521));
 EXPECT_FALSE(isPowerOf2(1679616));
 }

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Gerrit-Change-Id: I50b5d344e234fe1d4f1f85186686440773a209e3
Gerrit-Change-Number: 41533
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: base: Exclude the end of ChannelAddrRange

2021-02-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41653 )


Change subject: base: Exclude the end of ChannelAddrRange
..

base: Exclude the end of ChannelAddrRange

Since [1] has changed the end of AddrRange to be excluded from the
range, we need to do the same for ChannelAddrRange.

[1] Idd1e75d5771d198c4b8142b28de0f3a6e9007a52

Change-Id: I901a03409f2204a502133a1d763d8112b1d08f8f
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41653
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/base/channel_addr.hh
M src/base/channel_addr.test.cc
2 files changed, 7 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 55d227b..ad32d04 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -154,6 +154,7 @@
 /**
  * The ChanneelAddrRange class describes a contiguous range of
  * addresses in a contiguous channel-local address space.
+ * The start is inclusive, the end is not.
  */
 class ChannelAddrRange
 {
@@ -173,15 +174,15 @@

 constexpr ChannelAddrRange(const ChannelAddrRange &) = default;

-constexpr ChannelAddr size() const { return _end - _start + 1; }
+constexpr ChannelAddr size() const { return _end - _start; }

-constexpr bool valid() const { return _start <= _end; }
+constexpr bool valid() const { return _start < _end; }

 constexpr ChannelAddr start() const { return _start; }
 constexpr ChannelAddr end() const { return _end; }

 constexpr bool contains(ChannelAddr a) const {
-return a >= _start && a <= _end;
+return a >= _start && a < _end;
 }

 /** @} */ // end of api_channel_addr
diff --git a/src/base/channel_addr.test.cc b/src/base/channel_addr.test.cc
index 47ec0ab..01aa8b7 100644
--- a/src/base/channel_addr.test.cc
+++ b/src/base/channel_addr.test.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,7 +50,7 @@
 /* Ensure that range bounds are inclusive */
 TEST(ChannelAddrRange, Range)
 {
-ChannelAddrRange range(ChannelAddr(1), ChannelAddr(3));
+ChannelAddrRange range(ChannelAddr(1), ChannelAddr(4));

 EXPECT_FALSE(range.contains(ChannelAddr(0)));
 EXPECT_TRUE(range.contains(ChannelAddr(1)));
@@ -59,6 +59,6 @@
 EXPECT_FALSE(range.contains(ChannelAddr(4)));

 EXPECT_EQ(range.start(), ChannelAddr(1));
-EXPECT_EQ(range.end(), ChannelAddr(3));
+EXPECT_EQ(range.end(), ChannelAddr(4));
 EXPECT_EQ(range.size(), ChannelAddr(3));
 }

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Gerrit-Change-Id: I901a03409f2204a502133a1d763d8112b1d08f8f
Gerrit-Change-Number: 41653
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: base: Exclude the end of ChannelAddrRange

2021-02-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Attention is currently required from: Nikos Nikoleris.
Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/41653

to review the following change.


Change subject: base: Exclude the end of ChannelAddrRange
..

base: Exclude the end of ChannelAddrRange

Since [1] has changed the end of AddrRange to be excluded from the
range, we need to do the same for ChannelAddrRange.

[1] Idd1e75d5771d198c4b8142b28de0f3a6e9007a52

Change-Id: I901a03409f2204a502133a1d763d8112b1d08f8f
Reviewed-by: Nikos Nikoleris 
---
M src/base/channel_addr.hh
M src/base/channel_addr.test.cc
2 files changed, 8 insertions(+), 7 deletions(-)



diff --git a/src/base/channel_addr.hh b/src/base/channel_addr.hh
index 55d227b..9384a39 100644
--- a/src/base/channel_addr.hh
+++ b/src/base/channel_addr.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, 2021 ARM Limited
+ * Copyright (c) 2019, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -154,6 +154,7 @@
 /**
  * The ChanneelAddrRange class describes a contiguous range of
  * addresses in a contiguous channel-local address space.
+ * The start is inclusive, the end is not.
  */
 class ChannelAddrRange
 {
@@ -173,15 +174,15 @@

 constexpr ChannelAddrRange(const ChannelAddrRange &) = default;

-constexpr ChannelAddr size() const { return _end - _start + 1; }
+constexpr ChannelAddr size() const { return _end - _start; }

-constexpr bool valid() const { return _start <= _end; }
+constexpr bool valid() const { return _start < _end; }

 constexpr ChannelAddr start() const { return _start; }
 constexpr ChannelAddr end() const { return _end; }

 constexpr bool contains(ChannelAddr a) const {
-return a >= _start && a <= _end;
+return a >= _start && a < _end;
 }

 /** @} */ // end of api_channel_addr
diff --git a/src/base/channel_addr.test.cc b/src/base/channel_addr.test.cc
index 47ec0ab..c166b542 100644
--- a/src/base/channel_addr.test.cc
+++ b/src/base/channel_addr.test.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -50,7 +50,7 @@
 /* Ensure that range bounds are inclusive */
 TEST(ChannelAddrRange, Range)
 {
-ChannelAddrRange range(ChannelAddr(1), ChannelAddr(3));
+ChannelAddrRange range(ChannelAddr(1), ChannelAddr(4));

 EXPECT_FALSE(range.contains(ChannelAddr(0)));
 EXPECT_TRUE(range.contains(ChannelAddr(1)));
@@ -59,6 +59,6 @@
 EXPECT_FALSE(range.contains(ChannelAddr(4)));

 EXPECT_EQ(range.start(), ChannelAddr(1));
-EXPECT_EQ(range.end(), ChannelAddr(3));
+EXPECT_EQ(range.end(), ChannelAddr(4));
 EXPECT_EQ(range.size(), ChannelAddr(3));
 }

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Gerrit-Change-Id: I901a03409f2204a502133a1d763d8112b1d08f8f
Gerrit-Change-Number: 41653
Gerrit-PatchSet: 1
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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove unused params() definitions

2021-02-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
ms;
 FaultModel(const Params );

  
//

diff --git a/src/sim/clocked_object.hh b/src/sim/clocked_object.hh
index 12204c3..23ace92 100644
--- a/src/sim/clocked_object.hh
+++ b/src/sim/clocked_object.hh
@@ -234,7 +234,7 @@
 ClockedObject(const ClockedObjectParams );

 /** Parameters of ClockedObject */
-PARAMS(ClockedObject);
+using Params = ClockedObjectParams;

 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index dc3a3d3..50c35dd 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -34,7 +34,7 @@
 class SEWorkload : public Workload
 {
   public:
-PARAMS(SEWorkload);
+using Params = SEWorkloadParams;

 SEWorkload(const Params );


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[gem5-dev] Change in gem5/gem5[develop]: sim: Define PARAMS macro utility

2021-02-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39898 )


Change subject: sim: Define PARAMS macro utility
..

sim: Define PARAMS macro utility

To reduce code duplication and to ensure that the result of [1] will not
deteriorate, define a macro to be used in every descendant of SimObject
that needs its own params().

[1] 91d83cc8a12883f2d7493b37f50487cd7f03a9e6

Change-Id: I1a1a0dedf91ae228ea27b8ed324577ee3439ea68
Signed-off-by: Alexander Klimov 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39898
Reviewed-by: Daniel Carvalho 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/sim_object.hh
1 file changed, 36 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index a75f8dd..9bab952 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -117,6 +117,26 @@
  * If you don't have a constructor with that signature at all, then you  
must

  * implement the create method with that signature which will build your
  * object in some other way.
+ *
+ * A reference to the SimObjectParams will be returned via the params()
+ * API. It is quite common for a derived class (DerivSimObject) to access  
its
+ * derived parameters by downcasting the SimObjectParam to  
DerivSimObjectParams

+ *
+ * \code{.cpp}
+ * using Params = DerivSimObjectParams;
+ * const Params &
+ * params() const
+ * {
+ * return reinterpret_cast(_params);
+ * }
+ * \endcode
+ *
+ * We provide the PARAMS(..) macro as syntactic sugar to replace the code
+ * above with a much simpler:
+ *
+ * \code{.cpp}
+ * PARAMS(DerivSimObject);
+ * \endcode
  */
 class SimObject : public EventManager, public Serializable, public  
Drainable,

   public Stats::Group
@@ -314,6 +334,21 @@
 static SimObject *find(const char *name);
 };

+/* Add PARAMS(ClassName) to every descendant of SimObject that needs
+ * params.
+ *
+ * Strictly speaking, we need static_cast here, because the types are
+ * related by inheritance, but since the target type may be
+ * incomplete, the compiler does not know the relation.
+ */
+#define PARAMS(type) \
+using Params = type ## Params;   \
+const Params &   \
+params() const   \
+{\
+return reinterpret_cast(_params); \
+}
+
 /**
  * Base class to wrap object resolving functionality.
  *

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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I1a1a0dedf91ae228ea27b8ed324577ee3439ea68
Gerrit-Change-Number: 39898
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Remove duplicate isPow2 helper

2021-02-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41533 )



Change subject: base: Remove duplicate isPow2 helper
..

base: Remove duplicate isPow2 helper

This is already defined as isPowerOf2 in src/base/intmath.hh and it
is currently unused

Change-Id: I50b5d344e234fe1d4f1f85186686440773a209e3
Signed-off-by: Giacomo Travaglini 
---
M src/base/bitfield.hh
M src/base/bitfield.test.cc
M src/base/intmath.test.cc
3 files changed, 2 insertions(+), 29 deletions(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 98a93d4..2aea2b7 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -264,17 +264,6 @@
 }

 /**
- * Checks if a number is a power of two, or zero.
- *
- * @ingroup api_bitfield
- */
-template 
-inline bool
-isPow2(T v) {
-   return (v & (v - 1)) == (T)0;
-}
-
-/**
  * Returns the number of set ones in the provided value.
  * PD algorithm from
  * http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 3d07e69..909b111 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -290,24 +290,6 @@
 EXPECT_EQ(64, findLsbSet(0));
 }

-/* The following tests a simple function that verifies whether a value is a
- * a power of two or not.
- */
-TEST(BitfieldTest, IsPow2)
-{
-EXPECT_TRUE(isPow2(32));
-}
-
-TEST(BitfieldTest, IsNotPow2)
-{
-EXPECT_FALSE(isPow2(36));
-}
-
-TEST(BitfieldTest, IsPow2Zero)
-{
-EXPECT_TRUE(isPow2(0));
-}
-
 /*
  * The following tests "popCount(X)". popCount counts the number of bits  
set to

  * one.
diff --git a/src/base/intmath.test.cc b/src/base/intmath.test.cc
index 4e88b00..e985a1b 100644
--- a/src/base/intmath.test.cc
+++ b/src/base/intmath.test.cc
@@ -33,10 +33,12 @@
 TEST(IntmathTest, isPowerOf2)
 {
 EXPECT_TRUE(isPowerOf2(1));
+EXPECT_TRUE(isPowerOf2(32));
 EXPECT_TRUE(isPowerOf2(65536));
 EXPECT_TRUE(isPowerOf2(131072));
 EXPECT_TRUE(isPowerOf2(262144));
 EXPECT_FALSE(isPowerOf2(0));
+EXPECT_FALSE(isPowerOf2(36));
 EXPECT_FALSE(isPowerOf2(2521));
 EXPECT_FALSE(isPowerOf2(1679616));
 }

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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix initialization of ticksClkGated distribution

2021-02-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41413 )


Change subject: sim: Fix initialization of ticksClkGated distribution
..

sim: Fix initialization of ticksClkGated distribution

The third init argument is the bucket size. This should be evaluated
according to the following formula:

bucket size = (max - min + 1.0) / #buckets

Current initialization is not taking into considering the minimum value
(and the +1 offset)

Change-Id: Ie4b8dd7e26d3db60288ab1715ff1b7f0f4fe419e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41413
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/sim/power_state.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index a12e247..8281d2f 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -245,7 +245,8 @@
 // Each sample is time in ticks
 unsigned num_bins = std::max(p.clk_gate_bins, 10U);
 ticksClkGated
-.init(p.clk_gate_min, p.clk_gate_max, (p.clk_gate_max / num_bins))
+.init(p.clk_gate_min, p.clk_gate_max,
+(p.clk_gate_max - p.clk_gate_min + 1.0) / num_bins)
 .flags(pdf | nozero | nonan)
 ;


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Gerrit-Change-Id: Ie4b8dd7e26d3db60288ab1715ff1b7f0f4fe419e
Gerrit-Change-Number: 41413
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Anouk Van Laer 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base: Fix coding style in bitfield.hh

2021-02-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41493 )



Change subject: base: Fix coding style in bitfield.hh
..

base: Fix coding style in bitfield.hh

Change-Id: I4d571a14f297efcd776c5e47ecb50289b9c1
Signed-off-by: Giacomo Travaglini 
---
M src/base/bitfield.hh
1 file changed, 6 insertions(+), 3 deletions(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 98a93d4..13282f2 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -313,7 +313,8 @@
  *
  * @ingroup api_bitfield
  */
-inline uint64_t alignToPowerOfTwo(uint64_t val)
+inline uint64_t
+alignToPowerOfTwo(uint64_t val)
 {
 val--;
 val |= val >> 1;
@@ -335,7 +336,8 @@
  *
  * @ingroup api_bitfield
  */
-inline int ctz32(uint32_t value)
+inline int
+ctz32(uint32_t value)
 {
 return value ? __builtin_ctzl(value) : 32;
 }
@@ -348,7 +350,8 @@
  *
  * @ingroup api_bitfield
  */
-inline int ctz64(uint64_t value)
+inline int
+ctz64(uint64_t value)
 {
 return value ? __builtin_ctzll(value) : 64;
 }

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Gerrit-Change-Id: I4d571a14f297efcd776c5e47ecb50289b9c1
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Turn flash1 into a CFI Flash Memory

2021-02-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41496 )



Change subject: dev-arm: Turn flash1 into a CFI Flash Memory
..

dev-arm: Turn flash1 into a CFI Flash Memory

Change-Id: I21bdc165fba88d6366ea500a8a662fe0dcc02dab
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 7caa203..a433e62 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -66,6 +66,8 @@
 from m5.objects.SMMUv3 import SMMUv3
 from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar

+from m5.objects.CfiMemory import CfiMemory
+
 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
 # gem5's GIC model and KVM's GIC model if KVM is available.
@@ -1172,8 +1174,8 @@
 ]

 # NOR flash, flash1
-flash1 = SimpleMemory(range=AddrRange(0x0c00, 0x1000),
-  conf_table_reported=False)
+flash1 = CfiMemory(range=AddrRange(0x0c00, 0x1000),
+   conf_table_reported=False)

 # VRAM
 vram = SimpleMemory(range=AddrRange(0x1800, size='32MB'),

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[gem5-dev] Change in gem5/gem5[develop]: base: Add log2i to calculate log2 for integers

2021-02-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41494 )



Change subject: base: Add log2i to calculate log2 for integers
..

base: Add log2i to calculate log2 for integers

This is meant to evaluate the log2 for power of 2 integers

Change-Id: Iaa110cce4d36c578a201c8a45e9e2e3a369ffb30
Signed-off-by: Giacomo Travaglini 
---
M src/base/bitfield.hh
M src/base/bitfield.test.cc
2 files changed, 62 insertions(+), 1 deletion(-)



diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh
index 13282f2..79e14f5 100644
--- a/src/base/bitfield.hh
+++ b/src/base/bitfield.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, 2019 ARM Limited
+ * Copyright (c) 2017, 2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -356,4 +356,19 @@
 return value ? __builtin_ctzll(value) : 64;
 }

+/**
+ * Calculate the log2 of a power of 2 integer
+ *
+ * @param An input value
+ * @return The base 2 log of value
+ *
+ * @ingroup api_bitfield
+ */
+inline int
+log2i(int value)
+{
+assert(isPow2(value) && value > 0);
+return sizeof(int) * 8 - __builtin_clz(value) - 1;
+}
+
 #endif // __BASE_BITFIELD_HH__
diff --git a/src/base/bitfield.test.cc b/src/base/bitfield.test.cc
index 3d07e69..38acd15 100644
--- a/src/base/bitfield.test.cc
+++ b/src/base/bitfield.test.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2021 ARM Limited
  * Copyright (c) 2019 The Regents of the University of California
  * All rights reserved
  *
@@ -405,3 +406,48 @@
 uint64_t value = 0;
 EXPECT_EQ(64, ctz64(value));
 }
+
+/** This is testing the assertions: what if invalid arguments are
+ * provided to log2i:
+ *
+ * 1) value = 0
+ * 2) value < 0
+ * 3) value is not a poower of 2
+ */
+TEST(BitfieldTest, Log2iDeath)
+{
+// 1) value = 0
+EXPECT_DEATH({
+const int value = 0;
+log2i(value);
+}, "value > 0.*failed");
+
+// 2) value < 0
+EXPECT_DEATH({
+const int value = -1;
+log2i(value);
+}, "value > 0.*failed");
+
+// 3) value is not a power of 2
+EXPECT_DEATH({
+const int pow2_value = 1 << 2;
+const int value = pow2_value + 1;
+log2i(value);
+}, "isPow2");
+}
+
+/** This is testing if log2i actually works.
+ * at every iteration value is multiplied by 2 (left shift) and expected
+ * is incremented by one. This until value reaches becomes negative (by
+ * left shifting) which is when expected points to the MSB
+ */
+TEST(BitfieldTest, Log2i)
+{
+int expected = 0;
+for (int value = 1; value > 0; expected++, value <<= 1) {
+EXPECT_EQ(expected, log2i(value));
+}
+
+// Just as a sanity check for expected to point to the MSB
+EXPECT_EQ(expected, sizeof(int) * 8 - 1);
+}

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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: python: Sort py sources in alphabetical order

2021-02-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41313 )


Change subject: python: Sort py sources in alphabetical order
..

python: Sort py sources in alphabetical order

Signed-off-by: Giacomo Travaglini 
Change-Id: Id61b47389fdd72573c0a450eb86f802d05667e93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41313
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/SConscript
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/SConscript b/src/python/SConscript
index 9c02f53..19f260a 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -50,12 +50,12 @@
 PySource('m5.util', 'm5/util/convert.py')
 PySource('m5.util', 'm5/util/dot_writer.py')
 PySource('m5.util', 'm5/util/dot_writer_ruby.py')
+PySource('m5.util', 'm5/util/fdthelper.py')
 PySource('m5.util', 'm5/util/grammar.py')
 PySource('m5.util', 'm5/util/jobfile.py')
 PySource('m5.util', 'm5/util/multidict.py')
-PySource('m5.util', 'm5/util/terminal.py')
 PySource('m5.util', 'm5/util/pybind.py')
-PySource('m5.util', 'm5/util/fdthelper.py')
+PySource('m5.util', 'm5/util/terminal.py')
 PySource('m5.util', 'm5/util/terminal_formatter.py')

 PySource('m5.internal', 'm5/internal/__init__.py')

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Gerrit-Change-Id: Id61b47389fdd72573c0a450eb86f802d05667e93
Gerrit-Change-Number: 41313
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix PL111 address range

2021-02-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41293 )


Change subject: dev-arm: Fix PL111 address range
..

dev-arm: Fix PL111 address range

The device was using an incorrect range size (0x) instead of
0x1

Signed-off-by: Giacomo Travaglini 
Change-Id: I57ddfdb171351b606c63fcc90bcf0126c9ae76da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41293
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/pl111.cc
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 3847f3a..be3ff5e 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -54,7 +54,7 @@

 // initialize clcd registers
 Pl111::Pl111(const Params )
-: AmbaDmaDevice(p), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
+: AmbaDmaDevice(p, 0x1), lcdTiming0(0), lcdTiming1(0),  
lcdTiming2(0),

   lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0),
   lcdRis(0), lcdMis(0),
   clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
@@ -73,8 +73,6 @@
   intEvent([this]{ generateInterrupt(); }, name()),
   enableCapture(p.enable_capture)
 {
-pioSize = 0x;
-
 dmaBuffer = new uint8_t[buffer_size];

 memset(lcdPalette, 0, sizeof(lcdPalette));



The change was submitted with unreviewed changes in the following files:

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Gerrit-Change-Id: I57ddfdb171351b606c63fcc90bcf0126c9ae76da
Gerrit-Change-Number: 41293
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: sim: Fix initialization of ticksClkGated distribution

2021-02-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41413 )



Change subject: sim: Fix initialization of ticksClkGated distribution
..

sim: Fix initialization of ticksClkGated distribution

The third init argument is the bucket size. This should be evaluated
according to the following formula:

bucket size = (max - min + 1.0) / #buckets

Current initialization is taking into considering the minimum value (and
the +1 offset)

Change-Id: Ie4b8dd7e26d3db60288ab1715ff1b7f0f4fe419e
Signed-off-by: Giacomo Travaglini 
---
M src/sim/power_state.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/sim/power_state.cc b/src/sim/power_state.cc
index a12e247..8281d2f 100644
--- a/src/sim/power_state.cc
+++ b/src/sim/power_state.cc
@@ -245,7 +245,8 @@
 // Each sample is time in ticks
 unsigned num_bins = std::max(p.clk_gate_bins, 10U);
 ticksClkGated
-.init(p.clk_gate_min, p.clk_gate_max, (p.clk_gate_max / num_bins))
+.init(p.clk_gate_min, p.clk_gate_max,
+(p.clk_gate_max - p.clk_gate_min + 1.0) / num_bins)
 .flags(pdf | nozero | nonan)
 ;


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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix GICv3 address range

2021-02-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41294 )


Change subject: dev-arm: Fix GICv3 address range
..

dev-arm: Fix GICv3 address range

Distributor and Redistributor sizes should be 64KiB and 128KiB (gicv4)

Signed-off-by: Giacomo Travaglini 
Change-Id: I7f9696c5911840d88f4db10379f8cd62fa06a718
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41294
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/gic_v3.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index ef27d80..1f74209 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -74,10 +74,10 @@
 }

 distRange = RangeSize(params().dist_addr,
-Gicv3Distributor::ADDR_RANGE_SIZE - 1);
+Gicv3Distributor::ADDR_RANGE_SIZE);

 redistSize = redistributors[0]->addrRangeSize;
-redistRange = RangeSize(params().redist_addr, redistSize * threads -  
1);

+redistRange = RangeSize(params().redist_addr, redistSize * threads);

 addrRanges = {distRange, redistRange};




The change was submitted with unreviewed changes in the following files:

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[gem5-dev] Change in gem5/gem5[develop]: mem: XBar drawing mem_side ranges with MemMap Dflag

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41317 )



Change subject: mem: XBar drawing mem_side ranges with MemMap Dflag
..

mem: XBar drawing mem_side ranges with MemMap Dflag

With this commit we allow a XBar to print the memory map of the
address ranges it responds to.

This can be switched on via the new MemMap debug flag.

A new image is drawn every time there is a change in the memory
map during simulation (for example with PCI devices their
address ranges are setup via PCI Bars during the enumeration
phase / system bringup, and those are not available at construction
time)

These images are hence printed in the outdir (m5out) with the
following name

.curTick().jpg

So a single simulation might end up with different pictures of
the same xbar, showing the evolution of the xbar memory map
throughout time

Signed-off-by: Giacomo Travaglini 
Change-Id: Ife9174bc2904dcf44663fbc31db831019dc68749
---
M src/mem/SConscript
M src/mem/xbar.cc
M src/mem/xbar.hh
3 files changed, 38 insertions(+), 2 deletions(-)



diff --git a/src/mem/SConscript b/src/mem/SConscript
index cf7adc8..bd3cf47 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -122,6 +122,7 @@
 DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 DebugFlag('LLSC')
 DebugFlag('MemCtrl')
+DebugFlag('MemMap')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
diff --git a/src/mem/xbar.cc b/src/mem/xbar.cc
index 41ad585..7fe6955 100644
--- a/src/mem/xbar.cc
+++ b/src/mem/xbar.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -46,11 +46,15 @@
 #include "mem/xbar.hh"

 #include "base/logging.hh"
+#include "base/output.hh"
 #include "base/trace.hh"
 #include "debug/AddrRanges.hh"
 #include "debug/Drain.hh"
+#include "debug/MemMap.hh"
 #include "debug/XBar.hh"

+#include "python/pybind11/mem.hh"
+
 BaseXBar::BaseXBar(const BaseXBarParams )
 : ClockedObject(p),
   frontendLatency(p.frontend_latency),
@@ -511,6 +515,11 @@
 }
 }

+// Draw the xbar memory ranges if debug flag is set
+if (DTRACE(MemMap)) {
+drawMemRanges();
+}
+
 // tell all our neighbouring memory-side ports that our address
 // ranges have changed
 for (const auto& port: cpuSidePorts)
@@ -518,6 +527,30 @@
 }
 }

+void
+BaseXBar::drawMemRanges() const
+{
+const std::string filename = simout.resolve(
+csprintf("%s.%d.jpg", name(), curTick()));
+
+std::vector ranges;
+std::vector names;
+for (const auto& port: memSidePorts) {
+if (port->getId() == defaultPortID)
+continue;
+
+auto range_owner = static_cast(
+port->getPeer()).ownerName();
+
+for (const auto& range: port->getAddrRanges()) {
+ranges.push_back(range);
+names.push_back(range_owner);
+}
+}
+
+drawRanges(filename, ranges, names);
+}
+
 AddrRangeList
 BaseXBar::getAddrRanges() const
 {
diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh
index 88be87f..544d2ba 100644
--- a/src/mem/xbar.hh
+++ b/src/mem/xbar.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2015, 2018-2020 ARM Limited
+ * Copyright (c) 2011-2015, 2018-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -352,6 +352,8 @@
  */
 AddrRangeList getAddrRanges() const;

+void drawMemRanges() const;
+
 /**
  * Calculate the timing parameters for the packet. Updates the
  * headerDelay and payloadDelay fields of the packet

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[gem5-dev] Change in gem5/gem5[develop]: python: Add Range Writer utility

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
ange[0].end()
+
+return full_list
+
+def create_boxes(memory_ranges):
+return BoxSet(memory_ranges)
+
+def draw_ranges(filename, addr_ranges, names):
+"""
+Draw a list of memory ranges into an image file
+This is used to print the memory map of a system
+
+@param filename: name of the image file
+@param addr_ranges: list of AddrRange
+@param names: list of AddrRange names
+"""
+try:
+from PIL import Image, ImageDraw, ImageFont
+except:
+# python package not present: do nothing
+return
+else:
+# Aggregate range names and slots in a single list
+# Sort the ranges if necessary and introduce unnamed
+# ranges to fill the gaps
+combined_list = create_list(addr_ranges, names)
+
+with create_boxes(combined_list) as bset:
+im = Image.new('RGB', (1080, 1080), (128, 128, 128))
+draw = ImageDraw.Draw(im)
+
+    bset.draw(draw)
+
+im.save(filename, quality=95)

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[gem5-dev] Change in gem5/gem5[develop]: python: Use pybind11 to expose draw_ranges to C++

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41315 )



Change subject: python: Use pybind11 to expose draw_ranges to C++
..

python: Use pybind11 to expose draw_ranges to C++

Signed-off-by: Giacomo Travaglini 
Change-Id: I2208805c23d89cee55a06cfbf5c6fe0d8697a520
---
A src/python/pybind11/mem.hh
1 file changed, 53 insertions(+), 0 deletions(-)



diff --git a/src/python/pybind11/mem.hh b/src/python/pybind11/mem.hh
new file mode 100644
index 000..364a2b5
--- /dev/null
+++ b/src/python/pybind11/mem.hh
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2021 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "pybind11/pybind11.h"
+#include "pybind11/stl.h"
+#include "pybind11/stl_bind.h"
+
+namespace py = pybind11;
+
+static void
+drawRanges(const std::string ,
+const std::vector _ranges,
+const std::vector )
+{
+py::module_ m = py::module_::import("m5.util.range_writer");
+auto draw_ranges = m.attr("draw_ranges");
+
+draw_ranges(filename, addr_ranges, names);
+}

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[gem5-dev] Change in gem5/gem5[develop]: python: Sort py sources in alphabetical order

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41313 )



Change subject: python: Sort py sources in alphabetical order
..

python: Sort py sources in alphabetical order

Signed-off-by: Giacomo Travaglini 
Change-Id: Id61b47389fdd72573c0a450eb86f802d05667e93
---
M src/python/SConscript
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index 9c02f53..19f260a 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -50,12 +50,12 @@
 PySource('m5.util', 'm5/util/convert.py')
 PySource('m5.util', 'm5/util/dot_writer.py')
 PySource('m5.util', 'm5/util/dot_writer_ruby.py')
+PySource('m5.util', 'm5/util/fdthelper.py')
 PySource('m5.util', 'm5/util/grammar.py')
 PySource('m5.util', 'm5/util/jobfile.py')
 PySource('m5.util', 'm5/util/multidict.py')
-PySource('m5.util', 'm5/util/terminal.py')
 PySource('m5.util', 'm5/util/pybind.py')
-PySource('m5.util', 'm5/util/fdthelper.py')
+PySource('m5.util', 'm5/util/terminal.py')
 PySource('m5.util', 'm5/util/terminal_formatter.py')

 PySource('m5.internal', 'm5/internal/__init__.py')

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[gem5-dev] Change in gem5/gem5[develop]: mem: Port returning name of SimObject owner via ownerName

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41316 )



Change subject: mem: Port returning name of SimObject owner via ownerName
..

mem: Port returning name of SimObject owner via ownerName

Signed-off-by: Giacomo Travaglini 
Change-Id: Ie43b7b0567f9025dcdb36c7d6b86fb0e6f93f85d
---
M src/mem/port.cc
M src/mem/port.hh
2 files changed, 20 insertions(+), 2 deletions(-)



diff --git a/src/mem/port.cc b/src/mem/port.cc
index e5d8308..4a55a0b 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012,2015,2017 ARM Limited
+ * Copyright (c) 2012,2015,2017,2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -144,6 +144,12 @@
 Port::unbind();
 }

+const std::string
+RequestPort::ownerName() const
+{
+return owner.name();
+}
+
 AddrRangeList
 RequestPort::getAddrRanges() const
 {
@@ -176,6 +182,12 @@
 {
 }

+const std::string
+ResponsePort::ownerName() const
+{
+return owner.name();
+}
+
 void
 ResponsePort::responderUnbind()
 {
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 357a10e..e2f2f8a 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012,2015,2017 ARM Limited
+ * Copyright (c) 2011-2012,2015,2017,2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -120,6 +120,9 @@
  */
 void printAddr(Addr a);

+/** Return the SimObject's name owning the request port */
+const std::string ownerName() const;
+
   public:
 /* The atomic protocol. */

@@ -307,6 +310,9 @@
 void unbind() override {}
 void bind(Port ) override {}

+/** Return the SimObject's name owning the request port */
+const std::string ownerName() const;
+
   public:
 /* The atomic protocol. */


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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix GICv3 address range

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41294 )



Change subject: dev-arm: Fix GICv3 address range
..

dev-arm: Fix GICv3 address range

Distributor and Redistributor sizes should be 64KiB and 128KiB (gicv4)

Signed-off-by: Giacomo Travaglini 
Change-Id: I7f9696c5911840d88f4db10379f8cd62fa06a718
---
M src/dev/arm/gic_v3.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index ef27d80..1f74209 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -74,10 +74,10 @@
 }

 distRange = RangeSize(params().dist_addr,
-Gicv3Distributor::ADDR_RANGE_SIZE - 1);
+Gicv3Distributor::ADDR_RANGE_SIZE);

 redistSize = redistributors[0]->addrRangeSize;
-redistRange = RangeSize(params().redist_addr, redistSize * threads -  
1);

+redistRange = RangeSize(params().redist_addr, redistSize * threads);

 addrRanges = {distRange, redistRange};


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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix PL111 address range

2021-02-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/41293 )



Change subject: dev-arm: Fix PL111 address range
..

dev-arm: Fix PL111 address range

The device was using an incorrect range size (0x) instead of
0x1

Signed-off-by: Giacomo Travaglini 
Change-Id: I57ddfdb171351b606c63fcc90bcf0126c9ae76da
---
M src/dev/arm/pl111.cc
1 file changed, 1 insertion(+), 3 deletions(-)



diff --git a/src/dev/arm/pl111.cc b/src/dev/arm/pl111.cc
index 3847f3a..be3ff5e 100644
--- a/src/dev/arm/pl111.cc
+++ b/src/dev/arm/pl111.cc
@@ -54,7 +54,7 @@

 // initialize clcd registers
 Pl111::Pl111(const Params )
-: AmbaDmaDevice(p), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
+: AmbaDmaDevice(p, 0x1), lcdTiming0(0), lcdTiming1(0),  
lcdTiming2(0),

   lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0),
   lcdRis(0), lcdMis(0),
   clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
@@ -73,8 +73,6 @@
   intEvent([this]{ generateInterrupt(); }, name()),
   enableCapture(p.enable_capture)
 {
-pioSize = 0x;
-
 dmaBuffer = new uint8_t[buffer_size];

 memset(lcdPalette, 0, sizeof(lcdPalette));

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix CPTR_EL2 writes

2021-02-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39702 )


Change subject: arch-arm: Fix CPTR_EL2 writes
..

arch-arm: Fix CPTR_EL2 writes

* If E2H==1, CPTR_EL2.ZEN bits are not RES0.
* If E2H==1, CPTR_EL2.FPEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39702
Reviewed-by: Ciro Santilli 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2429e5c..447eb60 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -936,6 +936,7 @@
 break;
   case MISCREG_CPTR_EL2:
 {
+const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
 const uint32_t ones = (uint32_t)(-1);
 CPTR cptrMask = 0;
 cptrMask.tcpac = ones;
@@ -943,7 +944,9 @@
 cptrMask.tfp = ones;
 if (haveSVE) {
 cptrMask.tz = ones;
+cptrMask.zen = hcr.e2h ? ones : 0;
 }
+cptrMask.fpen = hcr.e2h ? ones : 0;
 newVal &= cptrMask;
 cptrMask = 0;
 cptrMask.res1_13_12_el2 = ones;

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Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add VRAM to VExpress_GEM5_Base

2021-02-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40973 )


Change subject: dev-arm: Add VRAM to VExpress_GEM5_Base
..

dev-arm: Add VRAM to VExpress_GEM5_Base

Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40973
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 10 insertions(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8969bc0..7caa203 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -964,7 +964,11 @@
0x1002-0x1002: gem5 MHU

0x1400-0x17ff: Reserved (Off-chip, PSRAM, CS1)
-   0x1800-0x1bff: Reserved (Off-chip, Peripherals, CS2)
+
+   0x1800-0x1bff: Off-chip, Peripherals, CS2
+   0x1800-0x19ff: VRAM
+   0x1a00-0x1bff: Reserved
+
0x1c00-0x1fff: Peripheral block 1 (Off-chip, CS3):
0x1c01-0x1c01: realview_io (VE system control regs.)
0x1c06-0x1c06: KMI0 (keyboard)
@@ -1171,6 +1175,10 @@
 flash1 = SimpleMemory(range=AddrRange(0x0c00, 0x1000),
   conf_table_reported=False)

+# VRAM
+vram = SimpleMemory(range=AddrRange(0x1800, size='32MB'),
+conf_table_reported=False)
+
 def _off_chip_devices(self):
 return [
 self.realview_io,
@@ -1190,6 +1198,7 @@
 def _off_chip_memory(self):
 return [
 self.flash1,
+self.vram,
 ]

 def __init__(self, **kwargs):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Gerrit-Change-Number: 40973
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Reduce boilerplate when read/writing to Pio devices

2021-02-08 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40775 )


Change subject: dev-arm: Reduce boilerplate when read/writing to Pio devices
..

dev-arm: Reduce boilerplate when read/writing to Pio devices

Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40775
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/pl011.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/ufs_device.cc
3 files changed, 9 insertions(+), 70 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index ea76416..cfe241d 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -64,6 +64,7 @@
 Pl011::read(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

+assert(pkt->getSize() <= 4);

 Addr daddr = pkt->getAddr() - pioAddr;

@@ -145,22 +146,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->setLE(data);
-break;
-  case 2:
-pkt->setLE(data);
-break;
-  case 4:
-pkt->setLE(data);
-break;
-  default:
-panic("Uart read size too big?\n");
-break;
-}
-
-
+pkt->setUintX(data, ByteOrder::little);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -170,6 +156,7 @@
 {

 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

+assert(pkt->getSize() <= 4);

 Addr daddr = pkt->getAddr() - pioAddr;

@@ -179,23 +166,7 @@
 // use a temporary data since the uart registers are read/written with
 // different size operations
 //
-uint32_t data = 0;
-
-switch(pkt->getSize()) {
-  case 1:
-data = pkt->getLE();
-break;
-  case 2:
-data = pkt->getLE();
-break;
-  case 4:
-data = pkt->getLE();
-break;
-  default:
-panic("Uart write size too big?\n");
-break;
-}
-
+const uint32_t data = pkt->getUintX(ByteOrder::little);

 switch (daddr) {
 case UART_DR:
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index a6cdc7d..de84384 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -61,7 +61,7 @@
 PL031::read(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

-assert(pkt->getSize() == 4);
+assert(pkt->getSize() <= 4);
 Addr daddr = pkt->getAddr() - pioAddr;
 uint32_t data;

@@ -99,22 +99,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->setLE(data);
-break;
-  case 2:
-pkt->setLE(data);
-break;
-  case 4:
-pkt->setLE(data);
-break;
-  default:
-panic("Uart read size too big?\n");
-break;
-}
-
-
+pkt->setUintX(data, ByteOrder::little);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -123,7 +108,7 @@
 PL031::write(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

-assert(pkt->getSize() == 4);
+assert(pkt->getSize() <= 4);
 Addr daddr = pkt->getAddr() - pioAddr;
 DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);

diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 1406e4a..e04cb39 100644
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -1029,26 +1029,9 @@
 Tick
 UFSHostDevice::write(PacketPtr pkt)
 {
-uint32_t data = 0;
+assert(pkt->getSize() <= 4);

-switch (pkt->getSize()) {
-
-  case 1:
-data = pkt->getLE();
-break;
-
-  case 2:
-data = pkt->getLE();
-break;
-
-  case 4:
-data = pkt->getLE();
-break;
-
-  default:
-panic("Undefined UFSHCD controller write size!\n");
-break;
-}
+const uint32_t data = pkt->getUintX(ByteOrder::little);

 switch (pkt->getAddr() & 0xFF)
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Gerrit-Change-Number: 40775
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add VRAM to VExpress_GEM5_Base

2021-02-08 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40973 )



Change subject: dev-arm: Add VRAM to VExpress_GEM5_Base
..

dev-arm: Add VRAM to VExpress_GEM5_Base

Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
1 file changed, 10 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 8969bc0..755cfa5 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -964,7 +964,11 @@
0x1002-0x1002: gem5 MHU

0x1400-0x17ff: Reserved (Off-chip, PSRAM, CS1)
-   0x1800-0x1bff: Reserved (Off-chip, Peripherals, CS2)
+
+   0x1800-0x1bff: Off-chip, Peripherals, CS2
+   0x1800-0x19ff: VRAM
+   0x1a00-0x1bff: Reserved
+
0x1c00-0x1fff: Peripheral block 1 (Off-chip, CS3):
0x1c01-0x1c01: realview_io (VE system control regs.)
0x1c06-0x1c06: KMI0 (keyboard)
@@ -1171,6 +1175,10 @@
 flash1 = SimpleMemory(range=AddrRange(0x0c00, 0x1000),
   conf_table_reported=False)

+# VRAM
+vram = SimpleMemory(range = AddrRange(0x1800, size='32MB'),
+conf_table_reported = False)
+
 def _off_chip_devices(self):
 return [
 self.realview_io,
@@ -1190,6 +1198,7 @@
 def _off_chip_memory(self):
 return [
 self.flash1,
+self.vram,
 ]

 def __init__(self, **kwargs):

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibd3ae59730c6d00a6bd8b129f973b79a565f66e4
Gerrit-Change-Number: 40973
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Reduce boilerplate when read/writing to Pio devices

2021-02-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40775 )



Change subject: dev-arm: Reduce boilerplate when read/writing to Pio devices
..

dev-arm: Reduce boilerplate when read/writing to Pio devices

Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/pl011.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/ufs_device.cc
3 files changed, 9 insertions(+), 70 deletions(-)



diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index ea76416..cfe241d 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -64,6 +64,7 @@
 Pl011::read(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

+assert(pkt->getSize() <= 4);

 Addr daddr = pkt->getAddr() - pioAddr;

@@ -145,22 +146,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->setLE(data);
-break;
-  case 2:
-pkt->setLE(data);
-break;
-  case 4:
-pkt->setLE(data);
-break;
-  default:
-panic("Uart read size too big?\n");
-break;
-}
-
-
+pkt->setUintX(data, ByteOrder::little);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -170,6 +156,7 @@
 {

 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

+assert(pkt->getSize() <= 4);

 Addr daddr = pkt->getAddr() - pioAddr;

@@ -179,23 +166,7 @@
 // use a temporary data since the uart registers are read/written with
 // different size operations
 //
-uint32_t data = 0;
-
-switch(pkt->getSize()) {
-  case 1:
-data = pkt->getLE();
-break;
-  case 2:
-data = pkt->getLE();
-break;
-  case 4:
-data = pkt->getLE();
-break;
-  default:
-panic("Uart write size too big?\n");
-break;
-}
-
+const uint32_t data = pkt->getUintX(ByteOrder::little);

 switch (daddr) {
 case UART_DR:
diff --git a/src/dev/arm/rtc_pl031.cc b/src/dev/arm/rtc_pl031.cc
index a6cdc7d..de84384 100644
--- a/src/dev/arm/rtc_pl031.cc
+++ b/src/dev/arm/rtc_pl031.cc
@@ -61,7 +61,7 @@
 PL031::read(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

-assert(pkt->getSize() == 4);
+assert(pkt->getSize() <= 4);
 Addr daddr = pkt->getAddr() - pioAddr;
 uint32_t data;

@@ -99,22 +99,7 @@
 break;
 }

-switch(pkt->getSize()) {
-  case 1:
-pkt->setLE(data);
-break;
-  case 2:
-pkt->setLE(data);
-break;
-  case 4:
-pkt->setLE(data);
-break;
-  default:
-panic("Uart read size too big?\n");
-break;
-}
-
-
+pkt->setUintX(data, ByteOrder::little);
 pkt->makeAtomicResponse();
 return pioDelay;
 }
@@ -123,7 +108,7 @@
 PL031::write(PacketPtr pkt)
 {
 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +  
pioSize);

-assert(pkt->getSize() == 4);
+assert(pkt->getSize() <= 4);
 Addr daddr = pkt->getAddr() - pioAddr;
 DPRINTF(Timer, "Writing to RTC at offset: %#x\n", daddr);

diff --git a/src/dev/arm/ufs_device.cc b/src/dev/arm/ufs_device.cc
index 1406e4a..e04cb39 100644
--- a/src/dev/arm/ufs_device.cc
+++ b/src/dev/arm/ufs_device.cc
@@ -1029,26 +1029,9 @@
 Tick
 UFSHostDevice::write(PacketPtr pkt)
 {
-uint32_t data = 0;
+assert(pkt->getSize() <= 4);

-switch (pkt->getSize()) {
-
-  case 1:
-data = pkt->getLE();
-break;
-
-  case 2:
-data = pkt->getLE();
-break;
-
-  case 4:
-data = pkt->getLE();
-break;
-
-  default:
-panic("Undefined UFSHCD controller write size!\n");
-break;
-}
+const uint32_t data = pkt->getUintX(ByteOrder::little);

 switch (pkt->getAddr() & 0xFF)
 {

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Id59ac950f37d7f4f2642daf324d501da1ee622de
Gerrit-Change-Number: 40775
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add destRegIdxArr arrays to TME instructions

2021-02-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40375 )


Change subject: arch-arm: Add destRegIdxArr arrays to TME instructions
..

arch-arm: Add destRegIdxArr arrays to TME instructions

This is needed as the base StaticInst class is no longer holding the
index array and it is up to the derived class to allocate the
storage depending on the number of registers used

Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40375
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
2 files changed, 20 insertions(+), 2 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index d32e8c9..85ffd6d 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -116,6 +116,12 @@
 Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("tstart", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
@@ -144,6 +150,12 @@
 Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("ttest", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index b75adc1..0a1e02c 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -97,6 +97,9 @@

 class Tstart64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

@@ -107,6 +110,9 @@

 class Ttest64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Gerrit-Change-Number: 40375
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add destRegIdxArr arrays to TME instructions

2021-02-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40375 )



Change subject: arch-arm: Add destRegIdxArr arrays to TME instructions
..

arch-arm: Add destRegIdxArr arrays to TME instructions

This is needed as the base StaticInst class is no longer holding the
index array and it is up to the derived class to allocate the
storage depending on the number of registers used

Change-Id: I389e39a7e09d31f370d63a6e61fe6ee3faaac7db
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/insts/tme64.cc
M src/arch/arm/insts/tme64.hh
2 files changed, 20 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index d32e8c9..85ffd6d 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -116,6 +116,12 @@
 Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("tstart", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
@@ -144,6 +150,12 @@
 Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
 : TmeRegNone64("ttest", machInst, MemReadOp, _dest)
 {
+setRegIdxArrays(
+nullptr,
+reinterpret_cast(
+::remove_pointer_t::destRegIdxArr));
+;
+
 _numSrcRegs = 0;
 _numDestRegs = 0;
 _numFPDestRegs = 0;
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index b75adc1..0a1e02c 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 ARM Limited
+ * Copyright (c) 2020-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -97,6 +97,9 @@

 class Tstart64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);

@@ -107,6 +110,9 @@

 class Ttest64 : public TmeRegNone64
 {
+  private:
+RegId destRegIdxArr[1];
+
   public:
 Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);


--
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[gem5-dev] Change in gem5/gem5[develop]: ext: testlib loading tests from multiple directories

2021-02-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40136 )


Change subject: ext: testlib loading tests from multiple directories
..

ext: testlib loading tests from multiple directories

We currently run regressions with the following command line

./main.py run [...] 

Where  is the positional argument pointing to the tests root
directory: Testlib will walk through the directory and load every
testsuite it encounters in its path.

./main.py run [...]   ...

Allowing testlib to load tests from multiple directories will make it
possible to load out of tree regressions (living in an EXTRAS repository
for example)

JIRA: https://gem5.atlassian.net/browse/GEM5-905

Change-Id: I802d8753a18f4dfb00347252f031b5438e9be672
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40136
Reviewed-by: Bobby R. Bruce 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M TESTING.md
M ext/testlib/configuration.py
M ext/testlib/main.py
3 files changed, 27 insertions(+), 9 deletions(-)

Approvals:
  Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/TESTING.md b/TESTING.md
index 17aeff9..88d1f29 100644
--- a/TESTING.md
+++ b/TESTING.md
@@ -63,6 +63,20 @@
 The above is the *minumum* you should run before posting a patch to
 https://gem5-review.googlesource.com

+## Running tests from multiple directories
+
+The command line above will walk the directory tree starting from the cwd
+(tests), and it will run every test it encounters in its path. It is  
possible

+to specify multiple root directories by providing several positional
+arguments:
+
+```shell
+./main.py run   [...]
+```
+
+This will load every test in directory1 and directory2 (and their
+subdirectories).
+
 ## Specifying a subset of tests to run

 You can use the tag query interface to specify the exact tests you want to  
run.

diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index f2d93d6..1fffab4 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020-2021 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -493,10 +493,11 @@
 # A list of common arguments/flags used across cli parsers.
 common_args = [
 Argument(
-'directory',
-nargs='?',
-default=os.getcwd(),
-help='Directory to start searching for tests in'),
+'directories',
+nargs='*',
+default=[os.getcwd()],
+help='Space separated list of directories to start searching '
+ 'for tests in'),
 Argument(
 '--exclude-tags',
 action=StorePositionalTagsAction,
@@ -646,7 +647,7 @@

 common_args.uid.add_to(parser)
 common_args.skip_build.add_to(parser)
-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.build_dir.add_to(parser)
 common_args.base_dir.add_to(parser)
 common_args.bin_path.add_to(parser)
@@ -703,7 +704,7 @@
 help='Quiet output (machine readable).'
 ).add_to(parser)

-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.bin_path.add_to(parser)
 common_args.isa.add_to(parser)
 common_args.variant.add_to(parser)
@@ -722,7 +723,7 @@
 super(RerunParser, self).__init__(parser)

 common_args.skip_build.add_to(parser)
-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.build_dir.add_to(parser)
 common_args.base_dir.add_to(parser)
 common_args.bin_path.add_to(parser)
diff --git a/ext/testlib/main.py b/ext/testlib/main.py
index d2ae5a9..6087a8e 100644
--- a/ext/testlib/main.py
+++ b/ext/testlib/main.py
@@ -205,7 +205,10 @@
 testloader = loader_mod.Loader()
 log.test_log.message(terminal.separator())
 log.test_log.message('Loading Tests', bold=True)
-testloader.load_root(configuration.config.directory)
+
+for root in configuration.config.directories:
+testloader.load_root(root)
+
 return testloader

 def do_list():

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Gerrit-Change-Id: I802d8753a18f4dfb00347252f031b5438e9be672
Gerrit-Change-Number: 40136
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged

[gem5-dev] Change in gem5/gem5[develop]: configs: Use MmioVirtIO for disk image in baremetal.py

2021-01-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39995 )


Change subject: configs: Use MmioVirtIO for disk image in baremetal.py
..

configs: Use MmioVirtIO for disk image in baremetal.py

The baremetal platform is the platform we use for running
user supplied binaries on baremetal hardware.
(simply put, it runs provided binaries without adding
a gem5 bootloader)

Some layers of this software stack might not have a pci driver.
This might be the case for firmware images like edkII
which needs to use a block device to extract the bootloader
and/or the kernel image. Those can use the memory mapped
(in host domain) virtio block device which is already
part of the VExpress_GEM5 platforms

Change-Id: I9c6ba7e1b4566a3999fd9ba20a2bebe191dc3ef8
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39995
Reviewed-by: Andreas Sandberg 
Reviewed-by: Richard Cooper 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
1 file changed, 3 insertions(+), 14 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 011883b..29e9b48 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019-2020 ARM Limited
+# Copyright (c) 2016-2017,2019-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -113,24 +113,13 @@
 cmd_line = " ".join([ object_file ] + args.args)
 )

-# Add the PCI devices we need for this system. The base system
-# doesn't have any PCI devices by default since they are assumed
-# to be added by the configurastion scripts needin them.
-pci_devices = []
 if args.disk_image:
 # Create a VirtIO block device for the system's boot
 # disk. Attach the disk image using gem5's Copy-on-Write
 # functionality to avoid writing changes to the stored copy of
 # the disk image.
-system.disk = PciVirtIO(vio=VirtIOBlock(
-image=create_cow_image(args.disk_image)))
-pci_devices.append(system.disk)
-
-# Attach the PCI devices to the system. The helper method in the
-# system assigns a unique PCI bus ID to each of the devices and
-# connects them to the IO bus.
-for dev in pci_devices:
-system.attach_pci(dev)
+system.realview.vio[0].vio = VirtIOBlock(
+image=create_cow_image(args.disk_image))

 # Wire up the system's memory system
 system.connect()

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Gerrit-Change-Number: 39995
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: ext: testlib loading tests from multiple directories

2021-01-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40136 )



Change subject: ext: testlib loading tests from multiple directories
..

ext: testlib loading tests from multiple directories

We currently run regressions with the following command line

./main.py run [...] 

Where  is the positional argument pointing to the tests root
directory: Testlib will walk through the directory and load every
testsuite it encounters in its path.

./main.py run [...]   ...

Allowing testlib to load tests from multiple directories will make it
possible to load out of tree regressions (living in an EXTRAS repository
for example)

JIRA: https://gem5.atlassian.net/browse/GEM5-905

Change-Id: I802d8753a18f4dfb00347252f031b5438e9be672
Signed-off-by: Giacomo Travaglini 
---
M TESTING.md
M ext/testlib/configuration.py
M ext/testlib/main.py
3 files changed, 27 insertions(+), 9 deletions(-)



diff --git a/TESTING.md b/TESTING.md
index 17aeff9..88d1f29 100644
--- a/TESTING.md
+++ b/TESTING.md
@@ -63,6 +63,20 @@
 The above is the *minumum* you should run before posting a patch to
 https://gem5-review.googlesource.com

+## Running tests from multiple directories
+
+The command line above will walk the directory tree starting from the cwd
+(tests), and it will run every test it encounters in its path. It is  
possible

+to specify multiple root directories by providing several positional
+arguments:
+
+```shell
+./main.py run   [...]
+```
+
+This will load every test in directory1 and directory2 (and their
+subdirectories).
+
 ## Specifying a subset of tests to run

 You can use the tag query interface to specify the exact tests you want to  
run.

diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index f2d93d6..1fffab4 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2020 ARM Limited
+# Copyright (c) 2020-2021 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -493,10 +493,11 @@
 # A list of common arguments/flags used across cli parsers.
 common_args = [
 Argument(
-'directory',
-nargs='?',
-default=os.getcwd(),
-help='Directory to start searching for tests in'),
+'directories',
+nargs='*',
+default=[os.getcwd()],
+help='Space separated list of directories to start searching '
+ 'for tests in'),
 Argument(
 '--exclude-tags',
 action=StorePositionalTagsAction,
@@ -646,7 +647,7 @@

 common_args.uid.add_to(parser)
 common_args.skip_build.add_to(parser)
-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.build_dir.add_to(parser)
 common_args.base_dir.add_to(parser)
 common_args.bin_path.add_to(parser)
@@ -703,7 +704,7 @@
 help='Quiet output (machine readable).'
 ).add_to(parser)

-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.bin_path.add_to(parser)
 common_args.isa.add_to(parser)
 common_args.variant.add_to(parser)
@@ -722,7 +723,7 @@
 super(RerunParser, self).__init__(parser)

 common_args.skip_build.add_to(parser)
-common_args.directory.add_to(parser)
+common_args.directories.add_to(parser)
 common_args.build_dir.add_to(parser)
 common_args.base_dir.add_to(parser)
 common_args.bin_path.add_to(parser)
diff --git a/ext/testlib/main.py b/ext/testlib/main.py
index d2ae5a9..6087a8e 100644
--- a/ext/testlib/main.py
+++ b/ext/testlib/main.py
@@ -205,7 +205,10 @@
 testloader = loader_mod.Loader()
 log.test_log.message(terminal.separator())
 log.test_log.message('Loading Tests', bold=True)
-testloader.load_root(configuration.config.directory)
+
+for root in configuration.config.directories:
+testloader.load_root(root)
+
 return testloader

 def do_list():

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[gem5-dev] Change in gem5/gem5[develop]: ext: Replace Queue.Empty with queue.empty

2021-01-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40135 )



Change subject: ext: Replace Queue.Empty with queue.empty
..

ext: Replace Queue.Empty with queue.empty

Queue.Empty is not an exception in python3
(Queue has been renamed to queue)

Change-Id: I82555d96608094fa47990f888fd11663379547bc
Signed-off-by: Giacomo Travaglini 
---
M ext/testlib/handlers.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/ext/testlib/handlers.py b/ext/testlib/handlers.py
index b62322f..fa7aea9 100644
--- a/ext/testlib/handlers.py
+++ b/ext/testlib/handlers.py
@@ -44,7 +44,7 @@
 import testlib.state as state
 import testlib.terminal as terminal

-from queue import Queue
+from queue import Queue, Empty
 from testlib.configuration import constants


@@ -383,7 +383,7 @@
 raise
 except EOFError:
 return
-except Queue.Empty:
+except Empty:
 continue

 def _drain(self):
@@ -395,7 +395,7 @@
 raise
 except EOFError:
 return
-except Queue.Empty:
+except Empty:
 return

 def _handle(self, record):

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[gem5-dev] Change in gem5/gem5[develop]: configs: Use MmioVirtIO for disk image in baremetal.py

2021-01-28 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39995 )



Change subject: configs: Use MmioVirtIO for disk image in baremetal.py
..

configs: Use MmioVirtIO for disk image in baremetal.py

The baremetal platform is the platform we use for running
user supplied binaries on baremetal hardware.
(simply put, it runs provided binaries without adding
a gem5 bootloader)

Some layers of this software stack might not have a pci driver.
This might be the case for firmware images like edkII
which needs to use a block device to extract the bootloader
and/or the kernel image. Those can use the memory mapped
(in host domain) virtio block device which is already
part of the VExpress_GEM5 platforms

Change-Id: I9c6ba7e1b4566a3999fd9ba20a2bebe191dc3ef8
Signed-off-by: Giacomo Travaglini 
---
M configs/example/arm/baremetal.py
1 file changed, 2 insertions(+), 13 deletions(-)



diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 011883b..317be8f 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -113,24 +113,13 @@
 cmd_line = " ".join([ object_file ] + args.args)
 )

-# Add the PCI devices we need for this system. The base system
-# doesn't have any PCI devices by default since they are assumed
-# to be added by the configurastion scripts needin them.
-pci_devices = []
 if args.disk_image:
 # Create a VirtIO block device for the system's boot
 # disk. Attach the disk image using gem5's Copy-on-Write
 # functionality to avoid writing changes to the stored copy of
 # the disk image.
-system.disk = PciVirtIO(vio=VirtIOBlock(
-image=create_cow_image(args.disk_image)))
-pci_devices.append(system.disk)
-
-# Attach the PCI devices to the system. The helper method in the
-# system assigns a unique PCI bus ID to each of the devices and
-# connects them to the IO bus.
-for dev in pci_devices:
-system.attach_pci(dev)
+system.realview.vio[0].vio = VirtIOBlock(
+image=create_cow_image(args.disk_image))

 # Wire up the system's memory system
 system.connect()

--
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[gem5-dev] Change in gem5/gem5[develop]: system: Fix PCI Mem range for VExpress_GEM5_VX DTS

2021-01-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39915 )



Change subject: system: Fix PCI Mem range for VExpress_GEM5_VX DTS
..

system: Fix PCI Mem range for VExpress_GEM5_VX DTS

This is addressing an issue raised in the mailing list [1]
where setting up a PCI mem bar for an ethernet device
resulted into an overlap of memory ranges:

fatal: system.iobus has two ports responding within range
[0x8000:0x8002]:
system.realview.ethernet.pio
system.iobridge.cpu_side_port

The reason for this is the following:

The PCI mem range in the DTB is using 0x4000 (3rd word) as a
starting address in the PCI domain, which is linked to 0x4000 in the
host domain.

<0x0200 0x0 0x4000  0x0 0x4000  0x0 0x4000>;

However the current mapping scheme works with simple fixed translation
So address 0x4000 in the PCI domain will be mapped to 0x4000 +
0x4000 = 0x8000, which is where DRAM starts

This is aligning with DTB autogeneration, which is setting up a
PCI mem range starting at PCI address = 0 [2]

[1]: https://www.mail-archive.com/gem5-users@gem5.org/msg18941.html
[2]:  
https://github.com/gem5/gem5/blob/v20.1.0.0/src/dev/arm/RealView.py#L161


Change-Id: I4538511453cfd5143fb4613a080780dc86b2244c
Signed-off-by: Giacomo Travaglini 
---
M system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi

index a84e8e3..2a56150 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_base.dtsi
@@ -66,8 +66,8 @@

reg = <0x0 0x3000 0x0 0x1000>;

-   ranges = <0x0100 0x0 0x  0x0 0x2f00  0x0 
0x0001>,
-<0x0200 0x0 0x4000  0x0 0x4000  0x0 
0x4000>;
+   ranges = <0x0100 0x0 0x0  0x0 0x2f00  0x0 0x0001>,
+<0x0200 0x0 0x0  0x0 0x4000  0x0 0x4000>;

interrupt-map = <0x00 0x0 0x0 0  0 68 1>,
<0x000800 0x0 0x0 0  0 69 1>,
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi

index 2ea94ac..6dbaa2c 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_base.dtsi
@@ -76,8 +76,8 @@

reg = <0x0 0x3000 0x0 0x1000>;

-   ranges = <0x0100 0x0 0x  0x0 0x2f00  0x0 
0x0001>,
-<0x0200 0x0 0x4000  0x0 0x4000  0x0 
0x4000>;
+   ranges = <0x0100 0x0 0x0  0x0 0x2f00  0x0 0x0001>,
+<0x0200 0x0 0x0  0x0 0x4000  0x0 0x4000>;

/*
  child unit address, #cells = #address-cells

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[gem5-dev] Change in gem5/gem5[develop]: misc: Remove redundant _params

2021-01-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev
p;_params) : SimObject(_params),  
stats(this)

+Workload(const WorkloadParams ) : SimObject(params), stats(this)
 {}

 void recordQuiesce() { stats.instStats.quiesce++; }

--
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[gem5-dev] Change in gem5/gem5[develop]: sim: Define PARAMS macro utility

2021-01-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39898 )



Change subject: sim: Define PARAMS macro utility
..

sim: Define PARAMS macro utility

To reduce code duplication and to ensure that the result of [1] will not
deteriorate, define a macro to be used in every descendant of SimObject
that needs its own params().

[1] 91d83cc8a12883f2d7493b37f50487cd7f03a9e6

Change-Id: I1a1a0dedf91ae228ea27b8ed324577ee3439ea68
Signed-off-by: Alexander Klimov 
---
M src/sim/sim_object.hh
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index a75f8dd..1e1d553 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2015, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -314,6 +314,21 @@
 static SimObject *find(const char *name);
 };

+/* Add PARAMS(ClassName) to every descendant of SimObject that needs
+ * params.
+ *
+ * Strictly speaking, we need static_cast here, because the types are
+ * related by inheritance, but since the target type may be
+ * incomplete, the compiler does not know the relation.
+ */
+#define PARAMS(type) \
+using Params = type ## Params;   \
+const Params &   \
+params() const   \
+{\
+return reinterpret_cast(_params); \
+}
+
 /**
  * Base class to wrap object resolving functionality.
  *

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[gem5-dev] Change in gem5/gem5[develop]: dev: Fix reset of virtio devices

2021-01-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39701 )


Change subject: dev: Fix reset of virtio devices
..

dev: Fix reset of virtio devices

The VirtualQueue reset was just resetting the queue address but
it was not touching other cached state and its associated
ring buffers (used and avail)

Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39701
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
2 files changed, 29 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 0624c7e..c19cf92 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -256,6 +256,16 @@
 }

 void
+VirtQueue::reset()
+{
+_address = 0;
+_last_avail = 0;
+
+avail.reset();
+used.reset();
+}
+
+void
 VirtQueue::setAddress(Addr address)
 {
 const Addr addr_avail(address + _size * sizeof(struct vring_desc));
@@ -366,7 +376,7 @@
 _deviceStatus = 0;

 for (QueueID i = 0; i < _queues.size(); ++i)
-_queues[i]->setAddress(0);
+_queues[i]->reset();
 }

 void
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index d9ade7f..72ad02e 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2017 ARM Limited
+ * Copyright (c) 2014, 2016-2017, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -305,6 +305,14 @@
 /** @{
  * @name Low-level Device Interface
  */
+
+/**
+ * Reset cached state in this queue and in the associated
+ * ring buffers. A client of this method should be the
+ * VirtIODeviceBase::reset.
+ */
+void reset();
+
 /**
  * Set the base address of this queue.
  *
@@ -464,6 +472,14 @@
 header{0, 0}, ring(size), _proxy(proxy), _base(0),  
byteOrder(bo)

 {}

+/** Reset any state in the ring buffer. */
+void
+reset()
+{
+header = {0, 0};
+_base = 0;
+};
+
 /**
  * Set the base address of the VirtIO ring buffer.
  *

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Gerrit-Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Gerrit-Change-Number: 39701
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Generic Watchdog

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
   W_IIDR = 0xfcc, // Watchdog Interface Identification Register
+};
+
+BitUnion32(WCTRLS)
+Bitfield<2> ws1; // Watchdog Signal 1 Status
+Bitfield<1> ws0; // Watchdog Signal 0 Status
+Bitfield<0> enabled; // Watchdog Enable
+EndBitUnion(WCTRLS)
+
+/** Control and Status Register */
+WCTRLS controlStatus;
+
+/** Offset Register */
+uint32_t offset;
+
+/** Compare Register */
+uint64_t compare;
+
+/** Interface Identification Register */
+const uint32_t iidr;
+
+const AddrRange refreshFrame;
+const AddrRange controlFrame;
+
+const Tick pioLatency;
+
+SystemCounter 
+Listener cntListener;
+
+/** Watchdog Signals (IRQs) */
+ArmInterruptPin * const ws0;
+ArmInterruptPin * const ws1;
+};
+
+#endif // __DEV_ARM_WATCHDOG_GENERIC_HH__

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Instantiate Generic Watchdog in Foundation platform

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39700 )


Change subject: dev-arm: Instantiate Generic Watchdog in Foundation platform
..

dev-arm: Instantiate Generic Watchdog in Foundation platform

Change-Id: I75496eeabeabb81804d4055f8257309324d6476a
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39700
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 588e4a9..0b5fdda 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1085,6 +1085,11 @@

 ### On-chip devices ###

+el2_watchdog = GenericWatchdog(
+control_start=0x2a44,
+refresh_start=0x2a45,
+ws0=ArmSPI(num=59), ws1=ArmSPI(num=60))
+
 # Trusted Watchdog, SP805
 trusted_watchdog = Sp805(pio_addr=0x2a49, interrupt=ArmSPI(num=56))

@@ -1109,6 +1114,7 @@
 def _on_chip_devices(self):
 return [
 self.generic_timer_mem,
+self.el2_watchdog,
 self.trusted_watchdog,
 self.system_watchdog
 ] + self.generic_timer_mem.frames

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Gerrit-Change-Number: 39700
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
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Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39696 )


Change subject: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation
..

dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation Platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I81c11312f29d8e59ac5f8ce2fe165d9474027d82
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39696
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index c168cfd..0c65ff2 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1363,6 +1363,8 @@
 AddrRange(0x4000, 0x8000),
 ]

+sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1378,6 +1380,11 @@
 self.gic
 ]

+def _off_chip_devices(self):
+return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.sp810_fake,
+]
+
 def setupBootLoader(self, cur_sys, loc, boot_loader=None):
 if boot_loader is None:
 boot_loader = [ loc('boot_v2.arm64') ]

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Gerrit-Change-Number: 39696
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39697 )


Change subject: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation
..

dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I91226cb10a3be50c59e32288b3643c550e8b538d
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39697
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/RealView.py
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 0c65ff2..7d90111 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1365,6 +1365,8 @@

 sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)

+clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1382,6 +1384,7 @@

 def _off_chip_devices(self):
 return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.clcd,
 self.sp810_fake,
 ]


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Gerrit-Change-Number: 39697
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: A SystemCounterListener doesn't have to be Serializable

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39698 )


Change subject: dev-arm: A SystemCounterListener doesn't have to be  
Serializable

..

dev-arm: A SystemCounterListener doesn't have to be Serializable

The class is not making use of any Serializable utility.
By removing this dependency we can extend it more easilly

Change-Id: Ia321b8f0deeb92adde008551eb921dcfd365e675
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39698
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/dev/arm/generic_timer.hh
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 16d2ce3..9a6663c 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -71,7 +71,7 @@

 /// Abstract class for elements whose events depend on the counting speed
 /// of the System Counter
-class SystemCounterListener : public Serializable
+class SystemCounterListener
 {
   public:
 /// Called from the SystemCounter when a change in counting speed  
occurred

@@ -174,7 +174,8 @@
 };

 /// Per-CPU architected timer.
-class ArchTimer : public SystemCounterListener, public Drainable
+class ArchTimer : public SystemCounterListener, public Drainable,
+  public Serializable
 {
   protected:
 /// Control register.
@@ -297,7 +298,7 @@
 RegVal readMiscReg(int misc_reg, unsigned cpu);

   protected:
-class CoreTimers : public SystemCounterListener
+class CoreTimers : public SystemCounterListener, public Serializable
 {
   public:
 CoreTimers(GenericTimer &_parent, ArmSystem , unsigned cpu,

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Gerrit-Change-Number: 39698
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
s/vexpress_gem5_v1_base.dtsi
+
+VEXPRESS_GEM5_V1_HDLCD_DTSIS=\
+   platforms/vexpress_gem5_v1_hdlcd.dtsi \
platforms/vexpress_gem5_v1_base.dtsi

 VEXPRESS_GEM5_V2_DTSIS=\
-   platforms/vexpress_gem5_v2.dtsi \
+   platforms/vexpress_gem5_v2_base.dtsi
+
+VEXPRESS_GEM5_V2_HDLCD_DTSIS=\
+   platforms/vexpress_gem5_v2_hdlcd.dtsi \
platforms/vexpress_gem5_v2_base.dtsi

 GEN_DTS=mkdir -p .gen; \
@@ -62,22 +75,45 @@

 all: $(TARGETS)

-.gen/armv7_gem5_v1_%cpu.dts: armv7.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)

-.gen/armv8_gem5_v1_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_hdlcd_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

-.gen/armv8_gem5_v2_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+.gen/armv8_gem5_v1_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)
+
+.gen/armv8_gem5_v2_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v1_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v2_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 %.dtb: .gen/%.dts
$(DTC) -I dts -O dtb -o $@ $<
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v1.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v2.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

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Gerrit-Change-Id: I4b1920efe764080115a57f52d8a3df2e6e2386a0
Gerrit-Change-Number: 38796
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Adrian Herrera 
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Gerrit-Reviewer: Gabe Black 
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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Enabled HDLcd by default in DTS

2021-01-26 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38797 )


Change subject: system-arm: Enabled HDLcd by default in DTS
..

system-arm: Enabled HDLcd by default in DTS

This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

JIRA: https://gem5.atlassian.net/browse/GEM5-866

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38797
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M system/arm/dt/platforms/display.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
3 files changed, 4 insertions(+), 15 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

index 16a029a..64c41e6 100644
--- a/system/arm/dt/platforms/display.dtsi
+++ b/system/arm/dt/platforms/display.dtsi
@@ -55,8 +55,6 @@
 };

  {
-   status = "ok";
-
port {
dp0_output: endpoint@0 {
remote-endpoint = <_virt_input>;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

index efca66d..a11dcb6 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,13 @@
 /include/ "vexpress_gem5_v1_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
- * output ports. Disable it by default in the platform until the
- * DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-
-   status = "disabled";
+   status = "ok";
};
 };

diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

index 6775727..3e8003a 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,17 +29,13 @@
 /include/ "vexpress_gem5_v2_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
-* output ports. Disable it by default in the platform until the
-* DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-   status = "disabled";
+   status = "ok";
};
 };


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Gerrit-Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Gerrit-Change-Number: 38797
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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[gem5-dev] Change in gem5/gem5[develop]: configs: Do not assume single mem range in RealView

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39636 )



Change subject: configs: Do not assume single mem range in RealView
..

configs: Do not assume single mem range in RealView

The SimpleSystem was assuming a single memory range for RealView
platforms by selecting the first element of the list only:

mem_range = self.realview._mem_regions[0]

This patch is fixing this by evaluating the entire list of platform
ranges.

Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Signed-off-by: Giacomo Travaglini 
---
M configs/example/arm/devices.py
1 file changed, 26 insertions(+), 8 deletions(-)



diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 9ef4d70..3b55be8 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019 ARM Limited
+# Copyright (c) 2016-2017, 2019, 2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -312,21 +312,39 @@
 # CPUs->PIO
 self.iobridge = Bridge(delay='50ns')
 # Device DMA -> MEM
-mem_range = self.realview._mem_regions[0]
-assert int(mem_range.size()) >= int(Addr(mem_size))
-self.mem_ranges = [
-AddrRange(start=mem_range.start, size=mem_size) ]
+self.memoryRanges(int(Addr(mem_size)))

 self._caches = caches
 if self._caches:
-self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
+self.iocache = IOCache(addr_ranges=self.mem_ranges)
 else:
-self.dmabridge = Bridge(delay='50ns',
-ranges=[self.mem_ranges[0]])
+self.dmabridge = Bridge(delay='50ns',  
ranges=self.mem_ranges)


 self._clusters = []
 self._num_cpus = 0

+def memoryRanges(self, mem_size):
+"""
+Define system memory ranges. This depends on the physical
+memory map provided by the realview platform and by the memory
+size provided by the user (mem_size argument).
+The method is iterating over all platform ranges until they  
cover

+the entire user's memory requirements.
+"""
+self.mem_ranges = []
+for mem_range in self.realview._mem_regions:
+if int(mem_range.size()) >= mem_size:
+# The platform range is bigger than selected mem size
+# We can stop iterating
+self.mem_ranges.append(
+AddrRange(start=mem_range.start, size=mem_size))
+mem_size = 0
+break
+else:
+self.mem_ranges.append(mem_range)
+mem_size -= mem_range.size()
+assert mem_size == 0
+
 def attach_pci(self, dev):
 self.realview.attachPciDevice(dev, self.iobus)


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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix CPTR_EL2 writes

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39702 )



Change subject: arch-arm: Fix CPTR_EL2 writes
..

arch-arm: Fix CPTR_EL2 writes

If E2H==1, CPTR_EL2.ZEN bits are not RES0.

Change-Id: Ic82b266975d89056d7c2f55464bd8a0c18a43e03
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f4fabc1..07b85a4 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2020 ARM Limited
+ * Copyright (c) 2010-2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -930,6 +930,7 @@
 break;
   case MISCREG_CPTR_EL2:
 {
+const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
 const uint32_t ones = (uint32_t)(-1);
 CPTR cptrMask = 0;
 cptrMask.tcpac = ones;
@@ -937,6 +938,8 @@
 cptrMask.tfp = ones;
 if (haveSVE) {
 cptrMask.tz = ones;
+if (hcr.e2h)
+cptrMask.zen = ones;
 }
 newVal &= cptrMask;
 cptrMask = 0;

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[gem5-dev] Change in gem5/gem5[develop]: dev: Fix reset of virtio devices

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39701 )



Change subject: dev: Fix reset of virtio devices
..

dev: Fix reset of virtio devices

Change-Id: I55cc767d791825899d62c4cd88b84809527f3f22
Signed-off-by: Giacomo Travaglini 
---
M src/dev/virtio/base.cc
M src/dev/virtio/base.hh
2 files changed, 29 insertions(+), 3 deletions(-)



diff --git a/src/dev/virtio/base.cc b/src/dev/virtio/base.cc
index 0624c7e..c19cf92 100644
--- a/src/dev/virtio/base.cc
+++ b/src/dev/virtio/base.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016 ARM Limited
+ * Copyright (c) 2014, 2016, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -256,6 +256,16 @@
 }

 void
+VirtQueue::reset()
+{
+_address = 0;
+_last_avail = 0;
+
+avail.reset();
+used.reset();
+}
+
+void
 VirtQueue::setAddress(Addr address)
 {
 const Addr addr_avail(address + _size * sizeof(struct vring_desc));
@@ -366,7 +376,7 @@
 _deviceStatus = 0;

 for (QueueID i = 0; i < _queues.size(); ++i)
-_queues[i]->setAddress(0);
+_queues[i]->reset();
 }

 void
diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh
index d9ade7f..72ad02e 100644
--- a/src/dev/virtio/base.hh
+++ b/src/dev/virtio/base.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2016-2017 ARM Limited
+ * Copyright (c) 2014, 2016-2017, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -305,6 +305,14 @@
 /** @{
  * @name Low-level Device Interface
  */
+
+/**
+ * Reset cached state in this queue and in the associated
+ * ring buffers. A client of this method should be the
+ * VirtIODeviceBase::reset.
+ */
+void reset();
+
 /**
  * Set the base address of this queue.
  *
@@ -464,6 +472,14 @@
 header{0, 0}, ring(size), _proxy(proxy), _base(0),  
byteOrder(bo)

 {}

+/** Reset any state in the ring buffer. */
+void
+reset()
+{
+header = {0, 0};
+_base = 0;
+};
+
 /**
  * Set the base address of the VirtIO ring buffer.
  *

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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Move display node into a shared DTS file

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
   /* 1920x1080-60 */
-   clock-frequency = <14850>;
-   hactive = <1920>;
-   vactive = <1080>;
-   hfront-porch = <148>;
-   hback-porch = <88>;
-   hsync-len = <44>;
-   vfront-porch = <36>;
-   vback-porch = <4>;
-   vsync-len = <5>;
-   };
-   };
-   };
 };
-
- {
-   status = "ok";
-
-   port {
-   dp0_output: endpoint@0 {
-   remote-endpoint = <_virt_input>;
-   };
-   };
-};
-
-
diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

new file mode 100644
index 000..16a029a
--- /dev/null
+++ b/system/arm/dt/platforms/display.dtsi
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015-2016, 2019, 2021 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+   virt-encoder {
+   compatible = "drm,virtual-encoder";
+   port {
+   dp0_virt_input: endpoint@0 {
+   remote-endpoint = <_output>;
+   };
+   };
+
+   display-timings {
+   native-mode = <>;
+
+   timing0: timing_1080p60 {
+   /* 1920x1080-60 */
+   clock-frequency = <14850>;
+   hactive = <1920>;
+   vactive = <1080>;
+   hfront-porch = <148>;
+   hback-porch = <88>;
+   hsync-len = <44>;
+   vfront-porch = <36>;
+   vback-porch = <4>;
+   vsync-len = <5>;
+   };
+   };
+   };
+};
+
+ {
+   status = "ok";
+
+   port {
+   dp0_output: endpoint@0 {
+   remote-endpoint = <_virt_input>;
+   };
+   };
+};
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index 91e82c0..efca66d 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -43,3 +43,5 @@
status = "disabled";
};
 };
+
+/include/ "display.dtsi"
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi

index 6c4dddc..6775727 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
@@ -42,3 +42,5 @@
status = "disabled";
};
 };
+
+/include/ "display.dtsi"

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Generic Watchdog

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
// Watchdog Enable
+EndBitUnion(WCTRLS)
+
+/** Control and Status Register */
+WCTRLS controlStatus;
+
+/** Offset Register */
+uint32_t offset;
+
+/** Compare Register */
+uint64_t compare;
+
+/** Interface Identification Register */
+const uint32_t iidr;
+
+const AddrRange refreshFrame;
+const AddrRange controlFrame;
+
+const Tick pioLatency;
+
+SystemCounter 
+Listener cntListener;
+
+/** Watchdog Signals (IRQs) */
+ArmInterruptPin * const ws0;
+ArmInterruptPin * const ws1;
+};
+
+#endif // __DEV_ARM_WATCHDOG_GENERIC_HH__

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Instantiate Generic Watchdog in Foundation platform

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39700 )



Change subject: dev-arm: Instantiate Generic Watchdog in Foundation platform
..

dev-arm: Instantiate Generic Watchdog in Foundation platform

Change-Id: I75496eeabeabb81804d4055f8257309324d6476a
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
1 file changed, 6 insertions(+), 0 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 6375d47..4a8cd99 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1085,6 +1085,11 @@

 ### On-chip devices ###

+el2_watchdog = GenericWatchdog(
+control_start=0x2a44,
+refresh_start=0x2a45,
+ws0=ArmSPI(num=59), ws1=ArmSPI(num=60))
+
 # Trusted Watchdog, SP805
 trusted_watchdog = Sp805(pio_addr=0x2a49, interrupt=ArmSPI(num=56))

@@ -1109,6 +1114,7 @@
 def _on_chip_devices(self):
 return [
 self.generic_timer_mem,
+self.el2_watchdog,
 self.trusted_watchdog,
 self.system_watchdog
 ] + self.generic_timer_mem.frames

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: A SystemCounterListener doesn't have to be Serializable

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39698 )



Change subject: dev-arm: A SystemCounterListener doesn't have to be  
Serializable

..

dev-arm: A SystemCounterListener doesn't have to be Serializable

The class is not making use of any Serializable utility.
By removing this dependency we can extend it more easilly

Change-Id: Ia321b8f0deeb92adde008551eb921dcfd365e675
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/generic_timer.hh
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh
index 16d2ce3..9a6663c 100644
--- a/src/dev/arm/generic_timer.hh
+++ b/src/dev/arm/generic_timer.hh
@@ -71,7 +71,7 @@

 /// Abstract class for elements whose events depend on the counting speed
 /// of the System Counter
-class SystemCounterListener : public Serializable
+class SystemCounterListener
 {
   public:
 /// Called from the SystemCounter when a change in counting speed  
occurred

@@ -174,7 +174,8 @@
 };

 /// Per-CPU architected timer.
-class ArchTimer : public SystemCounterListener, public Drainable
+class ArchTimer : public SystemCounterListener, public Drainable,
+  public Serializable
 {
   protected:
 /// Control register.
@@ -297,7 +298,7 @@
 RegVal readMiscReg(int misc_reg, unsigned cpu);

   protected:
-class CoreTimers : public SystemCounterListener
+class CoreTimers : public SystemCounterListener, public Serializable
 {
   public:
 CoreTimers(GenericTimer &_parent, ArmSystem , unsigned cpu,

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39696 )



Change subject: dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation
..

dev-arm: Add a fake SP810 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation Platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I81c11312f29d8e59ac5f8ce2fe165d9474027d82
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
1 file changed, 8 insertions(+), 1 deletion(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index f988452..1053c12 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2009-2020 ARM Limited
+# Copyright (c) 2009-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -1349,6 +1349,8 @@
 AddrRange(0x4000, 0x8000),
 ]

+sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1364,6 +1366,11 @@
 self.gic
 ]

+def _off_chip_devices(self):
+return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.sp810_fake,
+]
+
 def setupBootLoader(self, cur_sys, loc, boot_loader=None):
 if boot_loader is None:
 boot_loader = [ loc('boot_v2.arm64') ]

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39697 )



Change subject: dev-arm: Add a PL111 to the VExpress_GEM5_Foundation
..

dev-arm: Add a PL111 to the VExpress_GEM5_Foundation

The device is part of the FVP Foundation platform:

https://static.docs.arm.com/100961/1190/armv8_a_fp_ug_100961_1190_00_en.pdf

Change-Id: I91226cb10a3be50c59e32288b3643c550e8b538d
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/RealView.py
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 1053c12..6a064c6 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -1351,6 +1351,8 @@

 sp810_fake = AmbaFake(pio_addr=0x1C02, ignore_access=True)

+clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
+
 gic = Gicv3(dist_addr=0x2f00, redist_addr=0x2f10,
 maint_int=ArmPPI(num=25), gicv4=False,
 its=NULL)
@@ -1368,6 +1370,7 @@

 def _off_chip_devices(self):
 return super(VExpress_GEM5_Foundation, self)._off_chip_devices() +  
[

+self.clcd,
 self.sp810_fake,
 ]


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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

2021-01-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39635 )


Change subject: arch-arm: Add set_reg_idx_arr to  
SveStructMemSIMicroopDeclare

..

arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

This should have been part of:

https://gem5-review.googlesource.com/c/public/gem5/+/38381

Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39635
Reviewed-by: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/isa/templates/sve_mem.isa
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/isa/templates/sve_mem.isa  
b/src/arch/arm/isa/templates/sve_mem.isa

index 8bfb423..f635870 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -911,6 +911,7 @@
 numRegs(_numRegs), regIndex(_regIndex),
 memAccessFlags(ArmISA::TLB::AllowUnaligned)
 {
+%(set_reg_idx_arr)s;
 %(constructor)s;
 baseIsSP = isSP(_base);
 }

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Gerrit-Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Gerrit-Change-Number: 39635
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

2021-01-24 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39635 )



Change subject: arch-arm: Add set_reg_idx_arr to  
SveStructMemSIMicroopDeclare

..

arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

This should have been part of:

https://gem5-review.googlesource.com/c/public/gem5/+/38381

Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/isa/templates/sve_mem.isa
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/src/arch/arm/isa/templates/sve_mem.isa  
b/src/arch/arm/isa/templates/sve_mem.isa

index 8bfb423..f635870 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -911,6 +911,7 @@
 numRegs(_numRegs), regIndex(_regIndex),
 memAccessFlags(ArmISA::TLB::AllowUnaligned)
 {
+%(set_reg_idx_arr)s;
 %(constructor)s;
 baseIsSP = isSP(_base);
 }

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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Compare and Swap Pair instructions

2021-01-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev
class_name)s(ExtMachInst machInst,
-IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) :
- %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
-_dest,  _base, _result)
-{
-%(set_reg_idx_arr)s;
-%(constructor)s;
-
-uint32_t d2 = RegId(IntRegClass, dest).index() + 1 ;
-uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
-
-d2_src = _numSrcRegs ;
-setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, d2));
-r2_src = _numSrcRegs ;
-setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, r2));
-r2_dst = _numDestRegs ;
-setDestRegIdx(_numDestRegs++, RegId(IntRegClass, r2));
-flags[IsStore] = false;
-flags[IsLoad] = false;
-}
-}};
-
 def template AmoArithmeticOpDeclare {{
 class %(class_name)s : public %(base_class)s
 {

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Gerrit-Change-Id: Ie35c26256f42459805e007847896ac58b178fd42
Gerrit-Change-Number: 39456
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Compare and Swap Pair instructions

2021-01-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev
(IntRegClass, dest).index() + 1 ;
-uint32_t r2 = RegId(IntRegClass, result).index() + 1 ;
-
-d2_src = _numSrcRegs ;
-setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, d2));
-r2_src = _numSrcRegs ;
-setSrcRegIdx(_numSrcRegs++, RegId(IntRegClass, r2));
-r2_dst = _numDestRegs ;
-setDestRegIdx(_numDestRegs++, RegId(IntRegClass, r2));
-flags[IsStore] = false;
-flags[IsLoad] = false;
-}
-}};
-
 def template AmoArithmeticOpDeclare {{
 class %(class_name)s : public %(base_class)s
 {

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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix syntax error in cpu_tests/test.py

2021-01-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39295 )


Change subject: tests: Fix syntax error in cpu_tests/test.py
..

tests: Fix syntax error in cpu_tests/test.py

The testsuite was not loaded with the following error:

Exception thrown while loading
/tests/gem5/cpu_tests/test.py

Signed-off-by: Giacomo Travaglini 
Change-Id: I1e88b8957bb24471e1bb6113ffc7c78886b6ed70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39295
Reviewed-by: Hoa Nguyen 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/cpu_tests/test.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Hoa Nguyen: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index 393ff26..ee56400 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -60,9 +60,9 @@
 base_url = config.resource_url + '/gem5/cpu_tests/benchmarks/bin/'

 isa_url = {
-constants.gcn3_x86_tag : base_url + "x86"
-constants.arm_tag : base_url + "arm"
-constants.riscv_tag : base_url + "riscv"
+constants.gcn3_x86_tag : base_url + "x86",
+constants.arm_tag : base_url + "arm",
+constants.riscv_tag : base_url + "riscv",
 }

 for isa in valid_isas:

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Gerrit-Change-Id: I1e88b8957bb24471e1bb6113ffc7c78886b6ed70
Gerrit-Change-Number: 39295
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: dtb_addr is already encoding the loadAddrOffset

2021-01-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39216 )


Change subject: arch-arm: dtb_addr is already encoding the loadAddrOffset
..

arch-arm: dtb_addr is already encoding the loadAddrOffset

This fixes a bug in AArch32 where the dtb_address is
adding the loadAddrOffset twice to the dtb base address
after

https://gem5-review.googlesource.com/c/public/gem5/+/35076

Change-Id: Ia8bd35a02d998c54fbc3a889739c9abbeb506d96
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39216
Reviewed-by: Ciro Santilli 
Tested-by: kokoro 
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
2 files changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 8eb3c70..cc0151b 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -95,7 +95,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
-params().dtb_addr + _loadAddrOffset);
+params().dtb_addr);

 auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);

@@ -108,7 +108,7 @@
 bootReleaseAddr = ra & ~ULL(0x7F);

 dtb_file->buildImage().
-offset(params().dtb_addr + _loadAddrOffset).
+offset(params().dtb_addr).
 write(system->physProxy);
 delete dtb_file;

@@ -116,7 +116,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }

diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index f05fd6f..b296b68 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -151,7 +151,7 @@
 DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
 DDUMP(Loader, boot_data, size << 2);

-system->physProxy.writeBlob(params().dtb_addr + _loadAddrOffset,
+system->physProxy.writeBlob(params().dtb_addr,
 boot_data, size << 2);

 delete[] boot_data;
@@ -170,7 +170,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }
 }

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Gerrit-Change-Id: Ia8bd35a02d998c54fbc3a889739c9abbeb506d96
Gerrit-Change-Number: 39216
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: dtb_addr is already encoding the loadAddrOffset

2021-01-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39216 )



Change subject: arch-arm: dtb_addr is already encoding the loadAddrOffset
..

arch-arm: dtb_addr is already encoding the loadAddrOffset

This fixes a bug in AArch32 where the dtb_address is
adding the loadAddrOffset twice to the dtb base address
after

https://gem5-review.googlesource.com/c/public/gem5/+/35076

Change-Id: Ia8bd35a02d998c54fbc3a889739c9abbeb506d96
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
2 files changed, 5 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 8eb3c70..cc0151b 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -95,7 +95,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
-params().dtb_addr + _loadAddrOffset);
+params().dtb_addr);

 auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);

@@ -108,7 +108,7 @@
 bootReleaseAddr = ra & ~ULL(0x7F);

 dtb_file->buildImage().
-offset(params().dtb_addr + _loadAddrOffset).
+offset(params().dtb_addr).
 write(system->physProxy);
 delete dtb_file;

@@ -116,7 +116,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }

diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index f05fd6f..b296b68 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -151,7 +151,7 @@
 DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
 DDUMP(Loader, boot_data, size << 2);

-system->physProxy.writeBlob(params().dtb_addr + _loadAddrOffset,
+system->physProxy.writeBlob(params().dtb_addr,
 boot_data, size << 2);

 delete[] boot_data;
@@ -170,7 +170,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params().machine_type);
-tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
+tc->setIntReg(2, params().dtb_addr);
 }
 }
 }

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[gem5-dev] Change in gem5/gem5[develop]: tests: Fix syntax error in cpu_tests/test.py

2021-01-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/39295 )



Change subject: tests: Fix syntax error in cpu_tests/test.py
..

tests: Fix syntax error in cpu_tests/test.py

The testsuite was not loaded with the following error:

Exception thrown while loading
/scratch/jactra01/GEM/external/reviews/gem5/tests/gem5/cpu_tests/test.py

Signed-off-by: Giacomo Travaglini 
Change-Id: I1e88b8957bb24471e1bb6113ffc7c78886b6ed70
---
M tests/gem5/cpu_tests/test.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index 393ff26..ee56400 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -60,9 +60,9 @@
 base_url = config.resource_url + '/gem5/cpu_tests/benchmarks/bin/'

 isa_url = {
-constants.gcn3_x86_tag : base_url + "x86"
-constants.arm_tag : base_url + "arm"
-constants.riscv_tag : base_url + "riscv"
+constants.gcn3_x86_tag : base_url + "x86",
+constants.arm_tag : base_url + "arm",
+constants.riscv_tag : base_url + "riscv",
 }

 for isa in valid_isas:

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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove default bootscript option for fs_bigLITTLE.py

2021-01-07 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38815 )


Change subject: configs: Remove default bootscript option for  
fs_bigLITTLE.py

..

configs: Remove default bootscript option for fs_bigLITTLE.py

Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38815
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 76de0eb..090e071 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019-2020 ARM Limited
+# Copyright (c) 2016-2017, 2019-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -60,7 +60,6 @@


 default_disk = 'aarch64-ubuntu-trusty-headless.img'
-default_rcs = 'bootscript.rcS'

 default_mem_size= "2GB"

@@ -175,7 +174,7 @@
 help="Hardware platform class")
 parser.add_argument("--disk", action="append", type=str, default=[],
 help="Disks to instantiate")
-parser.add_argument("--bootscript", type=str, default=default_rcs,
+parser.add_argument("--bootscript", type=str, default="",
 help="Linux bootscript")
 parser.add_argument("--cpu-type", type=str,  
choices=list(cpu_types.keys()),

 default="timing",

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Gerrit-Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Gerrit-Change-Number: 38815
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Remove default bootscript option for fs_bigLITTLE.py

2021-01-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38815 )



Change subject: configs: Remove default bootscript option for  
fs_bigLITTLE.py

..

configs: Remove default bootscript option for fs_bigLITTLE.py

Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini 
---
M configs/example/arm/fs_bigLITTLE.py
1 file changed, 2 insertions(+), 3 deletions(-)



diff --git a/configs/example/arm/fs_bigLITTLE.py  
b/configs/example/arm/fs_bigLITTLE.py

index 76de0eb..090e071 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019-2020 ARM Limited
+# Copyright (c) 2016-2017, 2019-2021 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -60,7 +60,6 @@


 default_disk = 'aarch64-ubuntu-trusty-headless.img'
-default_rcs = 'bootscript.rcS'

 default_mem_size= "2GB"

@@ -175,7 +174,7 @@
 help="Hardware platform class")
 parser.add_argument("--disk", action="append", type=str, default=[],
 help="Disks to instantiate")
-parser.add_argument("--bootscript", type=str, default=default_rcs,
+parser.add_argument("--bootscript", type=str, default="",
 help="Linux bootscript")
 parser.add_argument("--cpu-type", type=str,  
choices=list(cpu_types.keys()),

 default="timing",

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[gem5-dev] Change in gem5/gem5[develop]: dev-arm, system-arm: Remove HDLcd from VExpress_GEM5_VX platforms

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
em5_v2_hdlcd.dtsi \
platforms/vexpress_gem5_v2_base.dtsi

 GEN_DTS=mkdir -p .gen; \
@@ -62,22 +75,45 @@

 all: $(TARGETS)

-.gen/armv7_gem5_v1_%cpu.dts: armv7.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)

-.gen/armv8_gem5_v1_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+.gen/armv7_gem5_v1_hdlcd_%cpu.dts: armv7.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

-.gen/armv8_gem5_v2_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+.gen/armv8_gem5_v1_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)
+
+.gen/armv8_gem5_v2_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_%cpu.dts: armv8.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v1_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V1_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v1.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v1_base.dtsi,$*)
+
+.gen/armv8_gem5_v1_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V1_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v1_hdlcd.dtsi,$*)

 .gen/armv8_gem5_v2_big_little%.dts: armv8_big_little.dts \
$(VEXPRESS_GEM5_V2_DTSIS)
-   $(call GEN_DTS,vexpress_gem5_v2.dtsi,$*)
+   $(call GEN_DTS,vexpress_gem5_v2_base.dtsi,$*)
+
+.gen/armv8_gem5_v2_hdlcd_big_little%.dts: armv8_big_little.dts \
+   $(VEXPRESS_GEM5_V2_HDLCD_DTSIS)
+   $(call GEN_DTS,vexpress_gem5_v2_hdlcd.dtsi,$*)

 %.dtb: .gen/%.dts
$(DTC) -I dts -O dtb -o $@ $<
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v1.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

similarity index 100%
rename from system/arm/dt/platforms/vexpress_gem5_v2.dtsi
rename to system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Enabled HDLcd by default in DTS

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38797 )



Change subject: system-arm: Enabled HDLcd by default in DTS
..

system-arm: Enabled HDLcd by default in DTS

This is fine as people using *_hdlcd.dtsi are willing to simulate
an HDLcd

Change-Id: Ifd5d6ecc81de920dbc29a05b07f30c13dcee3aa4
Signed-off-by: Giacomo Travaglini 
---
M system/arm/dt/platforms/display.dtsi
M system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
M system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
3 files changed, 4 insertions(+), 15 deletions(-)



diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

index 16a029a..64c41e6 100644
--- a/system/arm/dt/platforms/display.dtsi
+++ b/system/arm/dt/platforms/display.dtsi
@@ -55,8 +55,6 @@
 };

  {
-   status = "ok";
-
port {
dp0_output: endpoint@0 {
remote-endpoint = <_virt_input>;
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi

index efca66d..a11dcb6 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,18 +29,13 @@
 /include/ "vexpress_gem5_v1_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
- * output ports. Disable it by default in the platform until the
- * DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-
-   status = "disabled";
+   status = "ok";
};
 };

diff --git a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi

index 6775727..3e8003a 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2_hdlcd.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019 ARM Limited
+ * Copyright (c) 2015-2019, 2021 ARM Limited
  * All rights reserved
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,17 +29,13 @@
 /include/ "vexpress_gem5_v2_base.dtsi"

 / {
-   /* The display processor needs custom configuration to setup its
-* output ports. Disable it by default in the platform until the
-* DT bindings have stabilize.
-*/
dp0: hdlcd@2b00 {
compatible = "arm,hdlcd";
reg = <0x0 0x2b00 0x0 0x1000>;
interrupts = <0 63 4>;
clocks = <_pxl>;
clock-names = "pxlclk";
-   status = "disabled";
+   status = "ok";
};
 };


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[gem5-dev] Change in gem5/gem5[develop]: system-arm: Move display node into a shared DTS file

2021-01-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev
front-porch = <148>;
-   hback-porch = <88>;
-   hsync-len = <44>;
-   vfront-porch = <36>;
-   vback-porch = <4>;
-   vsync-len = <5>;
-   };
-   };
-   };
 };
-
- {
-   status = "ok";
-
-   port {
-   dp0_output: endpoint@0 {
-   remote-endpoint = <_virt_input>;
-   };
-   };
-};
-
-
diff --git a/system/arm/dt/platforms/display.dtsi  
b/system/arm/dt/platforms/display.dtsi

new file mode 100644
index 000..16a029a
--- /dev/null
+++ b/system/arm/dt/platforms/display.dtsi
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2015-2016, 2019, 2021 ARM Limited
+ * All rights reserved
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/ {
+   virt-encoder {
+   compatible = "drm,virtual-encoder";
+   port {
+   dp0_virt_input: endpoint@0 {
+   remote-endpoint = <_output>;
+   };
+   };
+
+   display-timings {
+   native-mode = <>;
+
+   timing0: timing_1080p60 {
+   /* 1920x1080-60 */
+   clock-frequency = <14850>;
+   hactive = <1920>;
+   vactive = <1080>;
+   hfront-porch = <148>;
+   hback-porch = <88>;
+   hsync-len = <44>;
+   vfront-porch = <36>;
+   vback-porch = <4>;
+   vsync-len = <5>;
+   };
+   };
+   };
+};
+
+ {
+   status = "ok";
+
+   port {
+   dp0_output: endpoint@0 {
+   remote-endpoint = <_virt_input>;
+   };
+   };
+};
diff --git a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi

index 91e82c0..efca66d 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v1.dtsi
@@ -43,3 +43,5 @@
status = "disabled";
};
 };
+
+/include/ "display.dtsi"
diff --git a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi  
b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi

index 6c4dddc..6775727 100644
--- a/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
+++ b/system/arm/dt/platforms/vexpress_gem5_v2.dtsi
@@ -42,3 +42,5 @@
status = "disabled";
};
 };
+
+/include/ "display.dtsi"

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[gem5-dev] Change in gem5/gem5[develop]: cpu: MinorCPU not updating cycle counter value

2020-12-08 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38095 )


Change subject: cpu: MinorCPU not updating cycle counter value
..

cpu: MinorCPU not updating cycle counter value

By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.

For more info check the following email thread in gem5-users:

https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html

Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38095
Tested-by: kokoro 
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/pipeline.cc
2 files changed, 11 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 0e919f33..1e846565 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -181,6 +181,12 @@
 return prio_list;
 }

+/** The tick method in the MinorCPU is simply updating the cycle
+ * counters as the ticking of the pipeline stages is already
+ * handled by the Pipeline object.
+ */
+void tick() { updateCycleCounters(BaseCPU::CPU_STATE_ON); }
+
 /** Interface for stages to signal that they have become active after
  *  a callback or eventq event where the pipeline itself may have
  *  already been idled.  The stage argument should be from the
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 78c2020..3997c89 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -121,6 +121,9 @@
 void
 Pipeline::evaluate()
 {
+/** We tick the CPU to update the BaseCPU cycle counters */
+cpu.tick();
+
 /* Note that it's important to evaluate the stages in order to allow
  *  'immediate', 0-time-offset TimeBuffer activity to be visible from
  *  later stages to earlier ones in the same cycle */

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Gerrit-Branch: develop
Gerrit-Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Gerrit-Change-Number: 38095
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: cpu, sim: Remove unused System::totalNumInst

2020-12-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/25305 )


Change subject: cpu, sim: Remove unused System::totalNumInst
..

cpu, sim: Remove unused System::totalNumInst

This counter gets augmented for every executed instruction but it
is not used. It is also overlapping with the

BaseCPU::numSimulatedInsts

A client willing to know the number of simulated instruction should rely
on the interface above.

Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25305
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/cpu/kvm/base.cc
M src/cpu/minor/execute.cc
M src/cpu/o3/cpu.cc
M src/cpu/simple/base.cc
M src/cpu/simple/timing.cc
M src/sim/system.cc
M src/sim/system.hh
7 files changed, 0 insertions(+), 16 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index cb0b4bb..b364d4f 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -766,7 +766,6 @@
 baseStats.numCycles += simCyclesExecuted;;
 stats.committedInsts += instsExecuted;
 ctrInsts += instsExecuted;
-system->totalNumInsts += instsExecuted;

 DPRINTF(KvmRun,
 "KVM: Executed %i instructions in %i cycles "
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 52708ab..3eb7811 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -866,7 +866,6 @@
 thread->numInst++;
 thread->threadStats.numInsts++;
 cpu.stats.numInsts++;
-cpu.system->totalNumInsts++;

 /* Act on events related to instruction counts */
 thread->comInstEventQueue.serviceEvents(thread->numInst);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c67ee64..c910cc4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1474,7 +1474,6 @@
 thread[tid]->numInst++;
 thread[tid]->threadStats.numInsts++;
 cpuStats.committedInsts[tid]++;
-system->totalNumInsts++;

 // Check for instruction-count-based events.
 thread[tid]->comInstEventQueue.serviceEvents(thread[tid]->numInst);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index dc58e0a..7f4797b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -166,7 +166,6 @@
 t_info.numInst++;
 t_info.execContextStats.numInsts++;

-system->totalNumInsts++;
 t_info.thread->funcExeInst++;
 }
 t_info.numOp++;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5e9eb92..0fd83ca 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -148,8 +148,6 @@

 // Reschedule any power gating event (if any)
 schedulePowerGatingEvent();
-
-system->totalNumInsts = 0;
 }

 bool
diff --git a/src/sim/system.cc b/src/sim/system.cc
index d31238c..de4744a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -229,7 +229,6 @@
   _m5opRange(p.m5ops_base ?
  RangeSize(p.m5ops_base, 0x1) :
  AddrRange(1, 0)), // Create an empty range if disabled
-  totalNumInsts(0),
   redirectPaths(p.redirect_paths)
 {
 if (workload)
@@ -440,12 +439,6 @@
 }

 void
-System::drainResume()
-{
-totalNumInsts = 0;
-}
-
-void
 System::serialize(CheckpointOut ) const
 {
 SERIALIZE_SCALAR(pagePtr);
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 4954af6..ce77f0a 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -592,10 +592,7 @@
 void serialize(CheckpointOut ) const override;
 void unserialize(CheckpointIn ) override;

-void drainResume() override;
-
   public:
-Counter totalNumInsts;
 std::map, Tick>  lastWorkItemStarted;
 std::map workItemStats;


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Gerrit-Change-Id: Ic5c805ac3b2e87bbacb365108d4060f53e044b4e
Gerrit-Change-Number: 25305
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: MinorCPU not updating cycle counter value

2020-11-27 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38095 )



Change subject: cpu: MinorCPU not updating cycle counter value
..

cpu: MinorCPU not updating cycle counter value

By not updating the cycle counter value for every tick in the
MinorCPU meant that a read to the associated performance counter
was always returning 0.

For more info check the following email thread in gem5-users:

https://www.mail-archive.com/gem5-users@gem5.org/msg18742.html

Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Signed-off-by: Giacomo Travaglini 
---
M src/cpu/minor/cpu.hh
M src/cpu/minor/pipeline.cc
2 files changed, 11 insertions(+), 2 deletions(-)



diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 0e919f33..1e846565 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014 ARM Limited
+ * Copyright (c) 2012-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -181,6 +181,12 @@
 return prio_list;
 }

+/** The tick method in the MinorCPU is simply updating the cycle
+ * counters as the ticking of the pipeline stages is already
+ * handled by the Pipeline object.
+ */
+void tick() { updateCycleCounters(BaseCPU::CPU_STATE_ON); }
+
 /** Interface for stages to signal that they have become active after
  *  a callback or eventq event where the pipeline itself may have
  *  already been idled.  The stage argument should be from the
diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc
index 78c2020..3997c89 100644
--- a/src/cpu/minor/pipeline.cc
+++ b/src/cpu/minor/pipeline.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -121,6 +121,9 @@
 void
 Pipeline::evaluate()
 {
+/** We tick the CPU to update the BaseCPU cycle counters */
+cpu.tick();
+
 /* Note that it's important to evaluate the stages in order to allow
  *  'immediate', 0-time-offset TimeBuffer activity to be visible from
  *  later stages to earlier ones in the same cycle */

--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibc033b536669cbb43d40c8a7c0659eb5565bdf93
Gerrit-Change-Number: 38095
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add SECURE_RD/WR flags to miscRegInfo

2020-11-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
];
+} else {
+return secure ? miscRegInfo[reg][MISCREG_HYP_S_RD] :
+miscRegInfo[reg][MISCREG_HYP_NS_RD];
+}
   case EL3:
 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
 secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
@@ -1428,8 +1433,13 @@
 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
 miscRegInfo[reg][MISCREG_PRI_NS_WR];
   case EL2:
-return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
-miscRegInfo[reg][MISCREG_HYP_WR];
+if (el2_host) {
+return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
+miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
+} else {
+return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
+miscRegInfo[reg][MISCREG_HYP_NS_WR];
+}
   case EL3:
 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
 secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index cc29c03..26ca9b1 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1121,11 +1121,15 @@
 MISCREG_PRI_S_RD,
 MISCREG_PRI_S_WR,
 // Hypervisor mode
-MISCREG_HYP_RD,
-MISCREG_HYP_WR,
+MISCREG_HYP_NS_RD,
+MISCREG_HYP_NS_WR,
+MISCREG_HYP_S_RD,
+MISCREG_HYP_S_WR,
 // Hypervisor mode, HCR_EL2.E2H == 1
-MISCREG_HYP_E2H_RD,
-MISCREG_HYP_E2H_WR,
+MISCREG_HYP_E2H_NS_RD,
+MISCREG_HYP_E2H_NS_WR,
+MISCREG_HYP_E2H_S_RD,
+MISCREG_HYP_E2H_S_WR,
 // Monitor mode, SCR.NS == 0
 MISCREG_MON_NS0_RD,
 MISCREG_MON_NS0_WR,

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Gerrit-Branch: develop
Gerrit-Change-Id: Ib1f0633ed23ea2364670d37c1fefd345ab2363ae
Gerrit-Change-Number: 37615
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

2020-11-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37616 )


Change subject: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode  
only

..

arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode

Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37616
Tested-by: kokoro 
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 8110a19..825811f 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4907,9 +4907,9 @@
   .hyp().mon()
   .mapsTo(MISCREG_VTCR);
 InitReg(MISCREG_VSTTBR_EL2)
-  .hyp().mon();
+  .hypSecure().mon();
 InitReg(MISCREG_VSTCR_EL2)
-  .hyp().mon();
+  .hypSecure().mon();
 InitReg(MISCREG_TTBR0_EL3)
   .mon();
 InitReg(MISCREG_TCR_EL3)

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Gerrit-Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Gerrit-Change-Number: 37616
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev: -Wdeprecated-copy not available on all supported compilers

2020-11-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37795 )


Change subject: dev: -Wdeprecated-copy not available on all supported  
compilers

..

dev: -Wdeprecated-copy not available on all supported compilers

This option has been introduced in:
1) gcc/9.0 [1]
2) clang/10.0.0 [2]

[1]: https://gcc.gnu.org/gcc-9/changes.html
[2]: https://releases.llvm.org/10.0.0/tools/clang/docs/ReleaseNotes.html

Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37795
Reviewed-by: Richard Cooper 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/reg_bank.test.cc
1 file changed, 22 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, but someone else must approve
  kokoro: Regressions pass



diff --git a/src/dev/reg_bank.test.cc b/src/dev/reg_bank.test.cc
index 348900b..6e655e2 100644
--- a/src/dev/reg_bank.test.cc
+++ b/src/dev/reg_bank.test.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright 2020 Google, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,7 +38,16 @@
  */

 #pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+
+// __GNUC__ defined for both clang and gcc
+// -Wdeprecated-copy has been added in clang10.0.0 and gcc9.0
+#if defined(__GNUC__)
+#if (defined(__clang__) && __GNUC__ >= 10) || \
+(!defined(__clang__) && __GNUC__ >= 9)
+#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+#endif
+#endif
+
 #include 
 #include 


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Gerrit-Change-Number: 37795
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Make TLB misses from a sw prefetch visible

2020-11-24 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37955 )



Change subject: arch-arm: Make TLB misses from a sw prefetch visible
..

arch-arm: Make TLB misses from a sw prefetch visible

While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.

This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss

Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/tlb.cc
1 file changed, 8 insertions(+), 7 deletions(-)



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5d2ed90..7564ca4 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1570,6 +1570,14 @@
 *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false,  
target_el,

  false);
 if (*te == NULL) {
+// Note, we are updating the stats for sw prefetching misses as  
well

+if (is_fetch)
+stats.instMisses++;
+else if (is_write)
+stats.writeMisses++;
+else
+stats.readMisses++;
+
 if (req->isPrefetch()) {
 // if the request is a prefetch don't attempt to fill the TLB  
or go
 // any further with the memory access (here we can safely use  
the

@@ -1579,13 +1587,6 @@
vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2);
 }

-if (is_fetch)
-stats.instMisses++;
-else if (is_write)
-stats.writeMisses++;
-else
-stats.readMisses++;
-
 // start translation table walk, pass variables rather than
 // re-retreaving in table walker for speed
 DPRINTF(TLB, "TLB Miss: Starting hardware table walker  
for %#x(%d:%d)\n",


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Gerrit-Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Gerrit-Change-Number: 37955
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove SortedDict from python utilities

2020-11-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev
 index - 1
-raise KeyError(key)
-
-def _left_gt(self, key):
-index = bisect_right(self._keys, key)
-if index != len(self._keys):
-return index
-raise KeyError(key)
-
-def _left_ge(self, key):
-index = bisect_left(self._keys, key)
-if index != len(self._keys):
-return index
-raise KeyError(key)
-
-def _del_keys(self):
-try:
-del self._sorted_keys
-except AttributeError:
-pass
-
-def __repr__(self):
-return 'SortedDict({%s})' % ', '.join('%r: %r' % item
-  for item in self.items())
-def __setitem__(self, key, item):
-dict.__setitem__(self, key, item)
-self._del_keys()
-
-def __delitem__(self, key):
-dict.__delitem__(self, key)
-self._del_keys()
-
-def clear(self):
-self.data.clear()
-self._del_keys()
-
-def copy(self):
-t = type(self)
-return t(self)
-
-def keys(self):
-return self._keys
-
-def values(self):
-for k in self._keys:
-yield self[k]
-
-def items(self):
-for k in self._keys:
-yield k, self[k]
-
-def keyrange(self, start=None, end=None, inclusive=False):
-if start is not None:
-start = self._left_ge(start)
-
-if end is not None:
-if inclusive:
-end = self._right_le(end)
-else:
-end = self._right_lt(end)
-
-return iter(self._keys[start:end+1])
-
-def valuerange(self, *args, **kwargs):
-for k in self.keyrange(*args, **kwargs):
-yield self[k]
-
-def itemrange(self, *args, **kwargs):
-for k in self.keyrange(*args, **kwargs):
-yield k, self[k]
-
-def update(self, *args, **kwargs):
-dict.update(self, *args, **kwargs)
-self._del_keys()
-
-def setdefault(self, key, _failobj=None):
-try:
-return self[key]
-except KeyError:
-self[key] = _failobj
-
-def pop(self, key, *args):
-try:
-dict.pop(self, key)
-self._del_keys()
-except KeyError:
-if not args:
-raise
-return args[0]
-
-def popitem(self):
-try:
-key = self._keys[0]
-self._del_keys()
-except IndexError:
-raise KeyError('popitem(): dictionary is empty')
-else:
-return key, dict.pop(self, key)
-
-@classmethod
-def fromkeys(cls, seq, value=None):
-d = cls()
-for key in seq:
-d[key] = value
-return d
-
-if __name__ == '__main__':
-def display(d):
-print(d)
-print(list(d.keys()))
-print(list(d.keys()))
-print(list(d.values()))
-print(list(d.values()))
-print(list(d.items()))
-print(list(d.items()))
-
-d = SortedDict(x=24,e=5,j=4,b=2,z=26,d=4)
-display(d)
-
-print('popitem', d.popitem())
-display(d)
-
-print('pop j')
-d.pop('j')
-display(d)
-
-d.setdefault('a', 1)
-d.setdefault('g', 7)
-d.setdefault('_')
-display(d)
-
-d.update({'b' : 2, 'h' : 8})
-display(d)
-
-del d['x']
-display(d)
-d['y'] = 26
-display(d)
-
-print(repr(d))
-
-print(d.copy())
-
-for k,v in d.itemrange('d', 'z', inclusive=True):
-print(k, v)

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Gerrit-Change-Id: Ia2cc664eb01e59b197218ccf40ff9c680a410fb2
Gerrit-Change-Number: 37796
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons, python: Remove SmartDict from python utilities

2020-11-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev
-return UndefinedVariable()
-
-def __setitem__(self, key, item):
-"""intercept the setting of any variable so that we always
-store strings in the dict"""
-dict.__setitem__(self, key, str(item))
-
-def values(self):
-for value in dict.values(self):
-yield Variable(value)
-
-def items(self):
-for key,value in dict.items(self):
-yield key, Variable(value)
-
-def get(self, key, default='False'):
-return Variable(dict.get(self, key, str(default)))
-
-def setdefault(self, key, default='False'):
-return Variable(dict.setdefault(self, key, str(default)))
-
-__all__ = [ 'SmartDict' ]

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Gerrit-Change-Id: I960fbfb1ec0f703e1e372dd752ee75f00632acac
Gerrit-Change-Number: 37775
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: python: Fix toBool converter

2020-11-20 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37755 )


Change subject: python: Fix toBool converter
..

python: Fix toBool converter

It was using an undefined variable (result) which was mistakenly left
there after its latest refactor

Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37755
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/util/convert.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 077b6b4..d3088f6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -145,7 +145,7 @@
 return True
 if value in ('false', 'f', 'no', 'n', '0'):
 return False
-return result
+raise ValueError("cannot convert '%s' to bool" % value)

 def toFrequency(value):
 return toMetricFloat(value, 'frequency', 'Hz')

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Gerrit-Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Gerrit-Change-Number: 37755
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Remove unusued SortedDict

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
 raise KeyError(key)
-
-def _del_keys(self):
-try:
-del self._sorted_keys
-except AttributeError:
-pass
-
-def __repr__(self):
-return 'SortedDict({%s})' % ', '.join('%r: %r' % item
-  for item in self.items())
-def __setitem__(self, key, item):
-dict.__setitem__(self, key, item)
-self._del_keys()
-
-def __delitem__(self, key):
-dict.__delitem__(self, key)
-self._del_keys()
-
-def clear(self):
-self.data.clear()
-self._del_keys()
-
-def copy(self):
-t = type(self)
-return t(self)
-
-def keys(self):
-return self._keys
-
-def values(self):
-for k in self._keys:
-yield self[k]
-
-def items(self):
-for k in self._keys:
-yield k, self[k]
-
-def keyrange(self, start=None, end=None, inclusive=False):
-if start is not None:
-start = self._left_ge(start)
-
-if end is not None:
-if inclusive:
-end = self._right_le(end)
-else:
-end = self._right_lt(end)
-
-return iter(self._keys[start:end+1])
-
-def valuerange(self, *args, **kwargs):
-for k in self.keyrange(*args, **kwargs):
-yield self[k]
-
-def itemrange(self, *args, **kwargs):
-for k in self.keyrange(*args, **kwargs):
-yield k, self[k]
-
-def update(self, *args, **kwargs):
-dict.update(self, *args, **kwargs)
-self._del_keys()
-
-def setdefault(self, key, _failobj=None):
-try:
-return self[key]
-except KeyError:
-self[key] = _failobj
-
-def pop(self, key, *args):
-try:
-dict.pop(self, key)
-self._del_keys()
-except KeyError:
-if not args:
-raise
-return args[0]
-
-def popitem(self):
-try:
-key = self._keys[0]
-self._del_keys()
-except IndexError:
-raise KeyError('popitem(): dictionary is empty')
-else:
-return key, dict.pop(self, key)
-
-@classmethod
-def fromkeys(cls, seq, value=None):
-d = cls()
-for key in seq:
-d[key] = value
-return d
-
-if __name__ == '__main__':
-def display(d):
-print(d)
-print(list(d.keys()))
-print(list(d.keys()))
-print(list(d.values()))
-print(list(d.values()))
-print(list(d.items()))
-print(list(d.items()))
-
-d = SortedDict(x=24,e=5,j=4,b=2,z=26,d=4)
-display(d)
-
-print('popitem', d.popitem())
-display(d)
-
-print('pop j')
-d.pop('j')
-display(d)
-
-d.setdefault('a', 1)
-d.setdefault('g', 7)
-d.setdefault('_')
-display(d)
-
-d.update({'b' : 2, 'h' : 8})
-display(d)
-
-del d['x']
-display(d)
-d['y'] = 26
-display(d)
-
-print(repr(d))
-
-print(d.copy())
-
-for k,v in d.itemrange('d', 'z', inclusive=True):
-print(k, v)

--
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Gerrit-Change-Id: Ia2cc664eb01e59b197218ccf40ff9c680a410fb2
Gerrit-Change-Number: 37796
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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: dev: -Wdeprecated-copy not available on all supported compilers

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37795 )



Change subject: dev: -Wdeprecated-copy not available on all supported  
compilers

..

dev: -Wdeprecated-copy not available on all supported compilers

This option has been introduced in:
1) gcc/9.0 [1]
2) clang/10.0.0 [2]

[1]: https://gcc.gnu.org/gcc-9/changes.html
[2]: https://releases.llvm.org/10.0.0/tools/clang/docs/ReleaseNotes.html

Change-Id: Iee9de40ca462107ec78603ffe5bc0891d6904730
Signed-off-by: Giacomo Travaglini 
---
M src/dev/reg_bank.test.cc
1 file changed, 22 insertions(+), 1 deletion(-)



diff --git a/src/dev/reg_bank.test.cc b/src/dev/reg_bank.test.cc
index 348900b..6e655e2 100644
--- a/src/dev/reg_bank.test.cc
+++ b/src/dev/reg_bank.test.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright 2020 Google, Inc.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -26,7 +38,16 @@
  */

 #pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+
+// __GNUC__ defined for both clang and gcc
+// -Wdeprecated-copy has been added in clang10.0.0 and gcc9.0
+#if defined(__GNUC__)
+#if (defined(__clang__) && __GNUC__ >= 10) || \
+(!defined(__clang__) && __GNUC__ >= 9)
+#pragma GCC diagnostic ignored "-Wdeprecated-copy"
+#endif
+#endif
+
 #include 
 #include 


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Gerrit-Owner: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Replace xrange with range to be python3 compliant

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37716 )


Change subject: fastmodel: Replace xrange with range to be python3 compliant
..

fastmodel: Replace xrange with range to be python3 compliant

Change-Id: I69ef5d744e2642af95383fbda920464178380757
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37716
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py  
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py

index 3298be9..ac81de5 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -509,7 +509,7 @@
 ]
 ranges += [
 AddrRange(its_bases[i], size=2 * gic_frame_size)
-for i in xrange(sc_gic.its_count)
+for i in range(sc_gic.its_count)
 ]

 return ranges

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Gerrit-Branch: develop
Gerrit-Change-Id: I69ef5d744e2642af95383fbda920464178380757
Gerrit-Change-Number: 37716
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Use BaseMMU in the CortexR52 wrapper

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37715 )


Change subject: fastmodel: Use BaseMMU in the CortexR52 wrapper
..

fastmodel: Use BaseMMU in the CortexR52 wrapper

Signed-off-by: Giacomo Travaglini 
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37715
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc  
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc

index 648a39a..e8e0aa7 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -36,10 +36,10 @@
 {

 CortexR52TC::CortexR52TC(
-::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB  
*itb,

+::BaseCPU *cpu, int id, System *system, ::BaseMMU *mmu,
 ::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
 const std::string _path) :
-ThreadContext(cpu, id, system, dtb, itb, isa, iris_if, iris_path)
+ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
 {}

 bool
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh  
b/src/arch/arm/fastmodel/CortexR52/thread_context.hh

index 74ac1a0..41223c9 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -44,7 +44,7 @@

   public:
 CortexR52TC(::BaseCPU *cpu, int id, System *system,
-::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa,
+::BaseMMU *mmu, ::BaseISA *isa,
 iris::IrisConnectionInterface *iris_if,
 const std::string _path);


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Gerrit-Branch: develop
Gerrit-Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Gerrit-Change-Number: 37715
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Earl Ou 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons, python: Remove SmartDict from python utilities

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
  for key,value in dict.items(self):
-yield key, Variable(value)
-
-def get(self, key, default='False'):
-return Variable(dict.get(self, key, str(default)))
-
-def setdefault(self, key, default='False'):
-return Variable(dict.setdefault(self, key, str(default)))
-
-__all__ = [ 'SmartDict' ]

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[gem5-dev] Change in gem5/gem5[develop]: python: Fix toBool converter

2020-11-19 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37755 )



Change subject: python: Fix toBool converter
..

python: Fix toBool converter

It was using an undefined variable (result) which was mistakenly left
there after its latest refactor

Change-Id: I50bb9b1e7793045556a29306faea5f455b29819d
Signed-off-by: Giacomo Travaglini 
---
M src/python/m5/util/convert.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/python/m5/util/convert.py b/src/python/m5/util/convert.py
index 077b6b4..d3088f6 100644
--- a/src/python/m5/util/convert.py
+++ b/src/python/m5/util/convert.py
@@ -145,7 +145,7 @@
 return True
 if value in ('false', 'f', 'no', 'n', '0'):
 return False
-return result
+raise ValueError("cannot convert '%s' to bool" % value)

 def toFrequency(value):
 return toMetricFloat(value, 'frequency', 'Hz')

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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Replace xrange with range to be python3 compliant

2020-11-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Attention is currently required from: Nikos Nikoleris.
Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/37716

to review the following change.


Change subject: fastmodel: Replace xrange with range to be python3 compliant
..

fastmodel: Replace xrange with range to be python3 compliant

Change-Id: I69ef5d744e2642af95383fbda920464178380757
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py  
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py

index 3298be9..ac81de5 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -509,7 +509,7 @@
 ]
 ranges += [
 AddrRange(its_bases[i], size=2 * gic_frame_size)
-for i in xrange(sc_gic.its_count)
+for i in range(sc_gic.its_count)
 ]

 return ranges

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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Use BaseMMU in the CortexR52 wrapper

2020-11-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Attention is currently required from: Nikos Nikoleris.
Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/37715

to review the following change.


Change subject: fastmodel: Use BaseMMU in the CortexR52 wrapper
..

fastmodel: Use BaseMMU in the CortexR52 wrapper

Signed-off-by: Giacomo Travaglini 
Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/fastmodel/CortexR52/thread_context.cc
M src/arch/arm/fastmodel/CortexR52/thread_context.hh
2 files changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc  
b/src/arch/arm/fastmodel/CortexR52/thread_context.cc

index 648a39a..e8e0aa7 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -36,10 +36,10 @@
 {

 CortexR52TC::CortexR52TC(
-::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB  
*itb,

+::BaseCPU *cpu, int id, System *system, ::BaseMMU *mmu,
 ::BaseISA *isa, iris::IrisConnectionInterface *iris_if,
 const std::string _path) :
-ThreadContext(cpu, id, system, dtb, itb, isa, iris_if, iris_path)
+ThreadContext(cpu, id, system, mmu, isa, iris_if, iris_path)
 {}

 bool
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.hh  
b/src/arch/arm/fastmodel/CortexR52/thread_context.hh

index 74ac1a0..41223c9 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.hh
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.hh
@@ -44,7 +44,7 @@

   public:
 CortexR52TC(::BaseCPU *cpu, int id, System *system,
-::BaseTLB *dtb, ::BaseTLB *itb, ::BaseISA *isa,
+::BaseMMU *mmu, ::BaseISA *isa,
 iris::IrisConnectionInterface *iris_if,
 const std::string _path);


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Gerrit-Change-Id: I569dc66a9dad54a374b0864ef2ffabd114aede7b
Gerrit-Change-Number: 37715
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add SECURE_RD/WR flags to miscRegInfo

2020-11-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev
] :
+miscRegInfo[reg][MISCREG_HYP_NS_RD];
+}
   case EL3:
 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_RD] :
 secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] :
@@ -1427,8 +1432,13 @@
 return secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] :
 miscRegInfo[reg][MISCREG_PRI_NS_WR];
   case EL2:
-return el2_host ? miscRegInfo[reg][MISCREG_HYP_E2H_WR] :
-miscRegInfo[reg][MISCREG_HYP_WR];
+if (el2_host) {
+return secure ? miscRegInfo[reg][MISCREG_HYP_E2H_S_WR] :
+miscRegInfo[reg][MISCREG_HYP_E2H_NS_WR];
+} else {
+return secure ? miscRegInfo[reg][MISCREG_HYP_S_WR] :
+miscRegInfo[reg][MISCREG_HYP_NS_WR];
+}
   case EL3:
 return el2_host ? miscRegInfo[reg][MISCREG_MON_E2H_WR] :
 secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] :
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index f683297..f6188a0 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1119,11 +1119,15 @@
 MISCREG_PRI_S_RD,
 MISCREG_PRI_S_WR,
 // Hypervisor mode
-MISCREG_HYP_RD,
-MISCREG_HYP_WR,
+MISCREG_HYP_NS_RD,
+MISCREG_HYP_NS_WR,
+MISCREG_HYP_S_RD,
+MISCREG_HYP_S_WR,
 // Hypervisor mode, HCR_EL2.E2H == 1
-MISCREG_HYP_E2H_RD,
-MISCREG_HYP_E2H_WR,
+MISCREG_HYP_E2H_NS_RD,
+MISCREG_HYP_E2H_NS_WR,
+MISCREG_HYP_E2H_S_RD,
+MISCREG_HYP_E2H_S_WR,
 // Monitor mode, SCR.NS == 0
 MISCREG_MON_NS0_RD,
 MISCREG_MON_NS0_WR,

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Gerrit-Reviewer: Ciro Santilli 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

2020-11-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Attention is currently required from: Ciro Santilli, Nikos Nikoleris.
Hello Ciro Santilli, Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/37616

to review the following change.


Change subject: arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode  
only

..

arch-arm: VSTCR_EL2/VSTTBR_EL2 accessible in secure mode only

We should trigger an Undefined Instruction if those registers
are accessed in non-secure mode

Change-Id: I45ec01e9e4ae9a38d59e56a51e198b4199a7d814
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Ciro Santilli 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/miscregs.cc
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 5b97b07..82a8217 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4899,9 +4899,9 @@
   .hyp().mon()
   .mapsTo(MISCREG_VTCR);
 InitReg(MISCREG_VSTTBR_EL2)
-  .hyp().mon();
+  .hypSecure().mon();
 InitReg(MISCREG_VSTCR_EL2)
-  .hyp().mon();
+  .hypSecure().mon();
 InitReg(MISCREG_TTBR0_EL3)
   .mon();
 InitReg(MISCREG_TCR_EL3)

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[gem5-dev] Change in gem5/gem5[develop]: tests: Update guest binaries used by regressions

2020-11-09 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37177 )


Change subject: tests: Update guest binaries used by regressions
..

tests: Update guest binaries used by regressions

The new tarball (aarch-system-20200611.tar.bz2) contains the
m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions

This disk image is based on a memory mapped m5 exit

Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37177
Reviewed-by: Ciro Santilli 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Ciro Santilli: Looks good to me, approved
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 33ca33e..482dd1d 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -88,7 +88,7 @@
 #'realview64-o3-checker',
 ]

-tarball = 'aarch-system-201901106.tar.bz2'
+tarball = 'aarch-system-20200611.tar.bz2'
 url = config.resource_url + "/arm/" + tarball
 filepath = os.path.dirname(os.path.abspath(__file__))
 path = joinpath(config.bin_path, 'arm')

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Gerrit-Change-Number: 37177
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
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Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add realview64-kvm.py test to quick regressions

2020-11-09 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31219 )


Change subject: tests: Add realview64-kvm.py test to quick regressions
..

tests: Add realview64-kvm.py test to quick regressions

By using the valid_host parameter we can make sure the test is
run on a aarch64 host only

Signed-off-by: Giacomo Travaglini 
Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31219
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 20 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 482dd1d..b02d1af 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -41,6 +41,10 @@

 from testlib import *

+arm_fs_kvm_tests = [
+'realview64-kvm',
+]
+
 arm_fs_quick_tests = [
 'realview64-simple-atomic',
 'realview64-simple-atomic-dual',
@@ -49,7 +53,7 @@
 'realview64-simple-timing-dual',
 'realview64-switcheroo-atomic',
 'realview64-switcheroo-timing',
-]
+] + arm_fs_kvm_tests

 arm_fs_long_tests = [
 'realview-simple-atomic',
@@ -94,7 +98,21 @@
 path = joinpath(config.bin_path, 'arm')
 arm_fs_binaries = DownloadedArchive(url, path, tarball)

+def support_kvm():
+return os.access("/dev/kvm", os.R_OK | os.W_OK)
+
 for name in arm_fs_quick_tests:
+if name in arm_fs_kvm_tests:
+# The current host might not be supporting KVM
+# Skip the test if that's the case
+if not support_kvm():
+continue
+
+# Run KVM test if we are on an arm host only
+valid_hosts = (constants.host_arm_tag,)
+else:
+valid_hosts = constants.supported_hosts
+
 args = [
 joinpath(config.base_dir, 'tests', 'gem5', 'configs', name  
+ '.py'),

 path,
@@ -107,6 +125,7 @@
 config_args=args,
 valid_isas=(constants.arm_tag,),
 length=constants.quick_tag,
+valid_hosts=valid_hosts,
 fixtures=(arm_fs_binaries,)
 )


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Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add realview64-kvm.py testing platform

2020-11-09 Thread Giacomo Travaglini (Gerrit) via gem5-dev
class=ArmV8KvmCPU).create_root()

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Gerrit-Change-Number: 31218
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] Change in gem5/gem5[develop]: tests: Update guest binaries used by regressions

2020-11-06 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/37177 )



Change subject: tests: Update guest binaries used by regressions
..

tests: Update guest binaries used by regressions

The new tarball (aarch-system-20200611.tar.bz2) contains the
m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions

This disk image is based on a memory mapped m5 exit

Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890
Signed-off-by: Giacomo Travaglini 
---
M tests/gem5/fs/linux/arm/test.py
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/tests/gem5/fs/linux/arm/test.py  
b/tests/gem5/fs/linux/arm/test.py

index 33ca33e..482dd1d 100644
--- a/tests/gem5/fs/linux/arm/test.py
+++ b/tests/gem5/fs/linux/arm/test.py
@@ -88,7 +88,7 @@
 #'realview64-o3-checker',
 ]

-tarball = 'aarch-system-201901106.tar.bz2'
+tarball = 'aarch-system-20200611.tar.bz2'
 url = config.resource_url + "/arm/" + tarball
 filepath = os.path.dirname(os.path.abspath(__file__))
 path = joinpath(config.bin_path, 'arm')

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Do not use _flushMva for TLBI IPA

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35246 )


Change subject: arch-arm: Do not use _flushMva for TLBI IPA
..

arch-arm: Do not use _flushMva for TLBI IPA

This is just a cosmetic change

Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35246
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlbi_op.hh
2 files changed, 10 insertions(+), 2 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 04b5cd4..5d2ed90 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -463,8 +463,9 @@
 TLB::flush(const TLBIIPA _op)
 {
 assert(!isStage2);
-stage2Tlb->_flushMva(tlbi_op.addr, 0xbeef, tlbi_op.secureLookup,
-true, tlbi_op.targetEL, false);
+
+// Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
+stage2Tlb->flush(tlbi_op.makeStage2());
 }

 void
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index cab0e52..ce72dfb 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -292,6 +292,13 @@

 void operator()(ThreadContext* tc) override;

+/** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
+TLBIMVAA
+makeStage2() const
+{
+return TLBIMVAA(EL1, secureLookup, addr);
+}
+
 Addr addr;
 };


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Gerrit-Change-Number: 35246
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add el2Enabled cached variable

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
asid), inHost(false),
+el2Enabled(false)
 {}

 void operator()(ThreadContext* tc) override;

 uint16_t asid;
 bool inHost;
+bool el2Enabled;
 };

 /** Instruction TLB Invalidate by ASID match */

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Gerrit-Change-Number: 35242
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix implementation of TLBI_VMALL instructions

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
LBIVMALL _op);
+
 /** Remove all entries in the non secure world, depending on whether  
they

  *  were allocated in hyp mode or not
  */
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index bb5153d..bd784ce 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -87,6 +87,21 @@
 }

 void
+TLBIVMALL::operator()(ThreadContext* tc)
+{
+HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+inHost = (hcr.tge == 1 && hcr.e2h == 1);
+
+getMMUPtr(tc)->flush(*this);
+
+// If CheckerCPU is connected, need to notify it of a flush
+CheckerCPU *checker = tc->getCheckerCpuPtr();
+if (checker) {
+getMMUPtr(checker)->flush(*this);
+}
+}
+
+void
 TLBIASID::operator()(ThreadContext* tc)
 {
 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 888cd99..cab0e52 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -141,6 +141,28 @@
 bool inHost;
 };

+/** Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions  
*/

+class TLBIVMALL : public TLBIOp
+{
+  public:
+TLBIVMALL(ExceptionLevel _targetEL, bool _secure, bool _stage2)
+  : TLBIOp(_targetEL, _secure), inHost(false), el2Enabled(false),
+stage2(_stage2)
+{}
+
+void operator()(ThreadContext* tc) override;
+
+TLBIVMALL
+makeStage2() const
+{
+return TLBIVMALL(EL1, secureLookup, false);
+}
+
+bool inHost;
+bool el2Enabled;
+bool stage2;
+};
+
 /** TLB Invalidate by ASID match */
 class TLBIASID : public TLBIOp
 {

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fede4d9cb82e4bae9163326d38db9351d2a3880
Gerrit-Change-Number: 35243
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: TlbEntry flush to be considered as functional lookup

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35244 )


Change subject: arch-arm: TlbEntry flush to be considered as functional  
lookup

..

arch-arm: TlbEntry flush to be considered as functional lookup

Otherwise we are unnecessarily shifting the TLB entry to the
MRU position before invalidating it

Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35244
Reviewed-by: Nikos Nikoleris 
Tested-by: kokoro 
---
M src/arch/arm/tlb.cc
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index bad16d8..04b5cd4 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -446,7 +446,7 @@

 bool hyp = target_el == EL2;

-te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
+te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
 target_el, in_host);
 while (te != NULL) {
 if (secure_lookup == !te->nstid) {
@@ -454,7 +454,7 @@
 te->valid = false;
 stats.flushedEntries++;
 }
-te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
+te = lookup(mva, asn, vmid, hyp, secure_lookup, true, ignore_asn,
 target_el, in_host);
 }
 }

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Gerrit-Branch: develop
Gerrit-Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Gerrit-Change-Number: 35244
Gerrit-PatchSet: 10
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual methods

2020-11-03 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34984 )


Change subject: cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual  
methods

..

cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual methods

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I6c6cdeaa3ae1433624e4e5b30b031d49e822f0e0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34984
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Anthony Gutierrez 
---
M src/arch/arm/fastmodel/iris/thread_context.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 0 insertions(+), 31 deletions(-)

Approvals:
  Anthony Gutierrez: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh  
b/src/arch/arm/fastmodel/iris/thread_context.hh

index 5e5d783..b7ea0b5 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -191,16 +191,6 @@
 int contextId() const override { return _contextId; }
 void setContextId(int id) override { _contextId = id; }

-BaseTLB *
-getITBPtr() override
-{
-return _itb;
-}
-BaseTLB *
-getDTBPtr() override
-{
-return _dtb;
-}
 BaseMMU *
 getMMUPtr() override
 {
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 5213026..7eabe57 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -152,9 +152,6 @@
 // Primary thread being run.
 SimpleThread *thread;

-BaseTLB* getITBPtr() { return mmu->itb; }
-BaseTLB* getDTBPtr() { return mmu->dtb; }
-
 BaseMMU* getMMUPtr() { return mmu; }

 virtual Counter totalInsts() const override
diff --git a/src/cpu/checker/thread_context.hh  
b/src/cpu/checker/thread_context.hh

index 5a68be4..b9442e8 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -127,10 +127,6 @@
 actualTC->setThreadId(id);
 }

-BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); }
-
-BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
-
 BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }

 CheckerCPU *
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index d4353d1..11de927 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -98,12 +98,6 @@
 /** Pointer to the thread state that this TC corrseponds to. */
 O3ThreadState *thread;

-/** Returns a pointer to the ITB. */
-BaseTLB *getITBPtr() override { return cpu->mmu->itb; }
-
-/** Returns a pointer to the DTB. */
-BaseTLB *getDTBPtr() override { return cpu->mmu->dtb; }
-
 /** Returns a pointer to the MMU. */
 BaseMMU *getMMUPtr() override { return cpu->mmu; }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e2f8070..b17f29a 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -206,10 +206,6 @@
 ContextID contextId() const override { return  
ThreadState::contextId(); }
 void setContextId(ContextID id) override {  
ThreadState::setContextId(id); }


-BaseTLB *getITBPtr() override { return mmu->itb; }
-
-BaseTLB *getDTBPtr() override { return mmu->dtb; }
-
 BaseMMU *getMMUPtr() override { return mmu; }

 CheckerCPU *getCheckerCpuPtr() override { return NULL; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 9bd5cf5..c50eb26 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -130,10 +130,6 @@

 virtual void setContextId(ContextID id) = 0;

-virtual BaseTLB *getITBPtr() = 0;
-
-virtual BaseTLB *getDTBPtr() = 0;
-
 virtual BaseMMU *getMMUPtr() = 0;

 virtual CheckerCPU *getCheckerCpuPtr() = 0;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6c6cdeaa3ae1433624e4e5b30b031d49e822f0e0
Gerrit-Change-Number: 34984
Gerrit-PatchSet: 17
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Alexandru Duțu 
Gerrit-Reviewer: Anthony Gutierrez 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Matt Sinclair 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement Arm MHU (Message Handling Unit)

2020-11-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev
in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __DEV_ARM_CSS_SCP_H__
+#define __DEV_ARM_CSS_SCP_H__
+
+#include "sim/clocked_object.hh"
+
+class Doorbell;
+
+class Scp : public ClockedObject
+{
+  public:
+Scp(const ClockedObjectParams )
+  : ClockedObject(p)
+{}
+
+virtual ~Scp() {}
+
+virtual void raiseInterrupt(const Doorbell *doorbell) = 0;
+virtual void clearInterrupt(const Doorbell *doorbell) = 0;
+};
+
+#endif // __DEV_ARM_CSS_SCP_H__

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Gerrit-Change-Id: I895eba1a3421746a602e6a4f88916da9054169a8
Gerrit-Change-Number: 34378
Gerrit-PatchSet: 9
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Instantiate SCMI in VExpress_GEM5 platforms

2020-11-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34380 )


Change subject: dev-arm: Instantiate SCMI in VExpress_GEM5 platforms
..

dev-arm: Instantiate SCMI in VExpress_GEM5 platforms

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34380
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
---
M src/dev/arm/RealView.py
1 file changed, 39 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index d35f7ce..bf8e0e6 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -53,6 +53,7 @@
 from m5.objects.SimpleMemory import SimpleMemory
 from m5.objects.GenericTimer import *
 from m5.objects.Gic import *
+from m5.objects.MHU import MHU, Scp2ApDoorbell, Ap2ScpDoorbell
 from m5.objects.EnergyCtrl import EnergyCtrl
 from m5.objects.ClockedObject import ClockedObject
 from m5.objects.SubSystem import SubSystem
@@ -61,6 +62,7 @@
 from m5.objects.PS2 import *
 from m5.objects.VirtIOMMIO import MmioVirtIO
 from m5.objects.Display import Display, Display1080p
+from m5.objects.Scmi import *
 from m5.objects.SMMUv3 import SMMUv3
 from m5.objects.PciDevice import PciLegacyIoBar, PciIoBar

@@ -607,6 +609,23 @@
 type = 'FVPBasePwrCtrl'
 cxx_header = 'dev/arm/fvp_base_pwr_ctrl.hh'

+class GenericMHU(MHU):
+lowp_scp2ap = Scp2ApDoorbell(
+set_address=0x10020008, clear_address=0x10020010,
+interrupt=ArmSPI(num=68))
+highp_scp2ap = Scp2ApDoorbell(
+set_address=0x10020028, clear_address=0x10020030,
+interrupt=ArmSPI(num=67))
+sec_scp2ap = Scp2ApDoorbell(
+set_address=0x10020208, clear_address=0x10020210,
+interrupt=ArmSPI(num=69))
+lowp_ap2scp = Ap2ScpDoorbell(
+set_address=0x10020108, clear_address=0x10020110)
+highp_ap2scp = Ap2ScpDoorbell(
+set_address=0x10020128, clear_address=0x10020130)
+sec_ap2scp = Ap2ScpDoorbell(
+set_address=0x10020308, clear_address=0x10020310)
+
 class RealView(Platform):
 type = 'RealView'
 cxx_header = "dev/arm/realview.hh"
@@ -912,6 +931,7 @@
0x1000-0x13ff: gem5-specific peripherals (Off-chip, CS5)
0x1000-0x1000: gem5 energy controller
0x1001-0x1001: gem5 pseudo-ops
+   0x1002-0x1002: gem5 MHU

0x1400-0x17ff: Reserved (Off-chip, PSRAM, CS1)
0x1800-0x1bff: Reserved (Off-chip, Peripherals, CS2)
@@ -1188,6 +1208,25 @@
 #  system.
 cur_sys.m5ops_base = 0x1001

+def attachScmi(self, bus):
+# Generate and attach the mailbox
+self.mailbox = GenericMHU(pio_addr=0x1002)
+self._attach_device(self.mailbox, bus)
+
+# Generate and attach the SCMI platform
+_scmi_comm = ScmiCommunication(
+agent_channel = ScmiAgentChannel(
+shmem=self.non_trusted_sram,
+shmem_range=AddrRange(0x2e00, size=0x200),
+doorbell=self.mailbox.highp_ap2scp),
+platform_channel = ScmiPlatformChannel(
+shmem=self.non_trusted_sram,
+shmem_range=AddrRange(0x2e00, size=0x200),
+doorbell=self.mailbox.highp_scp2ap))
+
+self.scmi = ScmiPlatform(comms=[ _scmi_comm ])
+self._attach_device(self.scmi, bus)
+
 def generateDeviceTree(self, state):
 # Generate using standard RealView function
 dt = list(super(VExpress_GEM5_Base,  
self).generateDeviceTree(state))


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Gerrit-Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413
Gerrit-Change-Number: 34380
Gerrit-PatchSet: 11
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: System is expecting a kvm_vm param for KvmVM

2020-11-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/31217 )


Change subject: tests: System is expecting a kvm_vm param for KvmVM
..

tests: System is expecting a kvm_vm param for KvmVM

Signed-off-by: Giacomo Travaglini 
Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31217
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M tests/gem5/configs/base_config.py
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/configs/base_config.py  
b/tests/gem5/configs/base_config.py

index fbedbaf..5623db8 100644
--- a/tests/gem5/configs/base_config.py
+++ b/tests/gem5/configs/base_config.py
@@ -133,7 +133,7 @@
 Arguments:
   system -- System to work on.
 """
-system.vm = KvmVM()
+system.kvm_vm = KvmVM()

 def init_system(self, system):
 """Initialize a system.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16
Gerrit-Change-Number: 31217
Gerrit-PatchSet: 6
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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