from:"Giacomo Travaglini \(Gerrit\)"

[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to missing ID registers

2023-06-07 Thread Giacomo Travaglini (Gerrit) via gem5-dev

(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_MVFR1);
 InitReg(MISCREG_MVFR2_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64PFR0_EL1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I19bddf67ecc379a14f91cfede385692536982101
Gerrit-Change-Number: 71178
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0

2023-06-05 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email )


Change subject: dev-arm: Treat GICv3 reserved addresses as RES0
..

dev-arm: Treat GICv3 reserved addresses as RES0

According to the GIC specification (IHI0069) reserved addresses in the
GIC memory map are treated as RES0.  We allow to disable this behaviour
and panic instead (reserved_res0 = False, which is what we have been
doing so far) to catch development bugs (in gem5 and in the guest SW)

Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71138
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/dev/arm/Gic.py
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_redistributor.cc
4 files changed, 26 insertions(+), 6 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Giacomo Travaglini: Looks good to me, approved




diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 41d602b..6fd8eb2 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -315,6 +315,15 @@

 gicv4 = Param.Bool(False, "GIC is GICv4 compatible")

+reserved_is_res0 = Param.Bool(
+True,
+"According to the GIC specification (IHI0069) "
+"reserved addresses in the GIC memory map are treated as RES0. "
+"We allow to disable this behaviour and panic instead "
+"(reserved_res0 = False) to catch development bugs "
+"(in gem5 and in the guest SW)",
+)
+
 def interruptCells(self, int_type, int_num, int_trigger,  
partition=None):

 """
 Interupt cells generation helper:
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 2ea6a98..7adb1d0 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -167,6 +167,17 @@
 Tick write(PacketPtr pkt) override;
 bool supportsVersion(GicVersion version) override;

+template
+void
+reserved(const char* fmt, Args... args) const
+{
+if (params().reserved_is_res0) {
+warn(fmt, args...);
+} else {
+panic(fmt, args...);
+}
+}
+
   public:

 Gicv3(const Params &p);
diff --git a/src/dev/arm/gic_v3_distributor.cc  
b/src/dev/arm/gic_v3_distributor.cc

index 1cb485c..af30692 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -505,8 +505,8 @@
 return 0; // RES0

   default:
-panic("Gicv3Distributor::read(): invalid offset %#x\n", addr);
-break;
+gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n",  
addr);

+return 0; // RES0
 }
 }

@@ -999,7 +999,7 @@
   }

   default:
-panic("Gicv3Distributor::write(): invalid offset %#x\n", addr);
+gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n",  
addr);

 break;
 }
 }
diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index e4380ef..67d6e42 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -377,8 +377,8 @@
 return 0;

   default:
-panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
-break;
+gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n",  
addr);

+return 0; // RES0
 }
 }

@@ -704,7 +704,7 @@
   }

   default:
-panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
+gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n",  
addr);

 break;
 }
 }

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Gerrit-Change-Number: 71138
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Bobby Bruce 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-arm: Apply FEAT_IDST to AArch32 state registers

2023-06-02 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email )



Change subject: arch-arm: Apply FEAT_IDST to AArch32 state registers
..

arch-arm: Apply FEAT_IDST to AArch32 state registers

When FEAT_IDST got implemented [1], we forgot to add the
logic for ID registers tracking AArch32 state/capabilities

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/70723

Signed-off-by: Giacomo Travaglini 
Change-Id: I19bddf67ecc379a14f91cfede385692536982101
---
M src/arch/arm/regs/misc.cc
1 file changed, 21 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index f32aa72..f1c69cc 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3911,83 +3911,104 @@
   .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .mapsTo(MISCREG_MPIDR);
 InitReg(MISCREG_REVIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid1))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_PFR0);
 InitReg(MISCREG_ID_PFR1_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_PFR1);
 InitReg(MISCREG_ID_DFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_DFR0);
 InitReg(MISCREG_ID_AFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_AFR0);
 InitReg(MISCREG_ID_MMFR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_MMFR0);
 InitReg(MISCREG_ID_MMFR1_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_MMFR1);
 InitReg(MISCREG_ID_MMFR2_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_MMFR2);
 InitReg(MISCREG_ID_MMFR3_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_MMFR3);
 InitReg(MISCREG_ID_MMFR4_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_MMFR4);
 InitReg(MISCREG_ID_ISAR0_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR0);
 InitReg(MISCREG_ID_ISAR1_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR1);
 InitReg(MISCREG_ID_ISAR2_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR2);
 InitReg(MISCREG_ID_ISAR3_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR3);
 InitReg(MISCREG_ID_ISAR4_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR4);
 InitReg(MISCREG_ID_ISAR5_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR5);
 InitReg(MISCREG_ID_ISAR6_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .mapsTo(MISCREG_ID_ISAR6);
 InitReg(MISCREG_MVFR0_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_MVFR0);
 InitReg(MISCREG_MVFR1_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_MVFR1);
 InitReg(MISCREG_MVFR2_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64PFR0_EL1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71178?usp=email
To unsubscribe, or for help writing mail filters, visit

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Treat GICv3 reserved addresses as RES0

2023-05-31 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email )



Change subject: dev-arm: Treat GICv3 reserved addresses as RES0
..

dev-arm: Treat GICv3 reserved addresses as RES0

According to the GIC specification (IHI0069) reserved addresses in the
GIC memory map are treated as RES0.  We allow to disable this behaviour
and panic instead (reserved_res0 = False, which is what we have been
doing so far) to catch development bugs (in gem5 and in the guest SW)

Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Signed-off-by: Giacomo Travaglini 
---
M src/dev/arm/Gic.py
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_redistributor.cc
4 files changed, 26 insertions(+), 6 deletions(-)



diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 41d602b..02df33f 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -315,6 +315,15 @@

 gicv4 = Param.Bool(False, "GIC is GICv4 compatible")

+reserved_res0 = Param.Bool(
+True,
+"According to the GIC specification (IHI0069) "
+"reserved addresses in the GIC memory map are treated as RES0. "
+"We allow to disable this behaviour and panic instead "
+"(reserved_res0 = False) to catch development bugs "
+"(in gem5 and in the guest SW)",
+)
+
 def interruptCells(self, int_type, int_num, int_trigger,  
partition=None):

 """
 Interupt cells generation helper:
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 2ea6a98..80c5afd 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -167,6 +167,17 @@
 Tick write(PacketPtr pkt) override;
 bool supportsVersion(GicVersion version) override;

+template
+void
+reserved(const char* fmt, Args... args) const
+{
+if (params().reserved_res0) {
+warn(fmt, args...);
+} else {
+panic(fmt, args...);
+}
+}
+
   public:

 Gicv3(const Params &p);
diff --git a/src/dev/arm/gic_v3_distributor.cc  
b/src/dev/arm/gic_v3_distributor.cc

index 1cb485c..af30692 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -505,8 +505,8 @@
 return 0; // RES0

   default:
-panic("Gicv3Distributor::read(): invalid offset %#x\n", addr);
-break;
+gic->reserved("Gicv3Distributor::read(): invalid offset %#x\n",  
addr);

+return 0; // RES0
 }
 }

@@ -999,7 +999,7 @@
   }

   default:
-panic("Gicv3Distributor::write(): invalid offset %#x\n", addr);
+gic->reserved("Gicv3Distributor::write(): invalid offset %#x\n",  
addr);

 break;
 }
 }
diff --git a/src/dev/arm/gic_v3_redistributor.cc  
b/src/dev/arm/gic_v3_redistributor.cc

index e4380ef..67d6e42 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -377,8 +377,8 @@
 return 0;

   default:
-panic("Gicv3Redistributor::read(): invalid offset %#x\n", addr);
-break;
+gic->reserved("Gicv3Redistributor::read(): invalid offset %#x\n",  
addr);

+return 0; // RES0
 }
 }

@@ -704,7 +704,7 @@
   }

   default:
-panic("Gicv3Redistributor::write(): invalid offset %#x\n", addr);
+gic->reserved("Gicv3Redistributor::write(): invalid offset %#x\n",  
addr);

 break;
 }
 }

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/71138?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I23f98519c2f256c092a52425735b8792bae7a2c7
Gerrit-Change-Number: 71138
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension

2023-05-25 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email )


Change subject: arch-arm: Add an ArmAllRelease containing every defined  
extension

..

arch-arm: Add an ArmAllRelease containing every defined extension

This is probably the easiest way to instantiate a release containing
any implemented extension. It is alternatively possible to use the
latest release (e.g. Armv92 as of now).
This could be preferrable for consistency across simulations.
However if users want to always be up to date with development,
using ArmAllRelease will allow them to do so without the need
to change their configuration script

Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70958
Tested-by: kokoro 
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/ArmSystem.py
1 file changed, 12 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index b826f0d..c1f5e9f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -224,6 +224,18 @@
 extensions = Armv85.extensions + ["FEAT_SME"]


+class ArmAllRelease(ArmRelease):
+"""
+A release containing any implemented extension.  It is alternatively
+possible to use the latest release (e.g. Armv92 as of now).  This  
could be
+preferrable for consistency across simulations.  However if users want  
to
+always be up to date with development, using ArmAllRelease will allow  
them

+to do so without the need to change their configuration script
+"""
+
+extensions = ArmExtension.vals
+
+
 class ArmSystem(System):
 type = "ArmSystem"
 cxx_header = "arch/arm/system.hh"

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99
Gerrit-Change-Number: 70958
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an ArmAllRelease containing every defined extension

2023-05-24 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email )



Change subject: arch-arm: Add an ArmAllRelease containing every defined  
extension

..

arch-arm: Add an ArmAllRelease containing every defined extension

This is probably the easiest way to instantiate a release containing
any implemented extension. It is alternatively possible to use the
latest release (e.g. Armv92 as of now).
This could be preferrable for consistency across simulations.
However if users want to always be up to date with development,
using ArmAllRelease will allow them to do so without the need
to change their configuration script

Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index b826f0d..c1f5e9f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -224,6 +224,18 @@
 extensions = Armv85.extensions + ["FEAT_SME"]


+class ArmAllRelease(ArmRelease):
+"""
+A release containing any implemented extension.  It is alternatively
+possible to use the latest release (e.g. Armv92 as of now).  This  
could be
+preferrable for consistency across simulations.  However if users want  
to
+always be up to date with development, using ArmAllRelease will allow  
them

+to do so without the need to change their configuration script
+"""
+
+extensions = ArmExtension.vals
+
+
 class ArmSystem(System):
 type = "ArmSystem"
 cxx_header = "arch/arm/system.hh"

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70958?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibca629e99da9b571f233de9d05a5a9186d02aa99
Gerrit-Change-Number: 70958
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_EVT

2023-05-24 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70938?usp=email )



Change subject: arch-arm: Implement FEAT_EVT
..

arch-arm: Implement FEAT_EVT

This extension is optional in Armv8.2 but mandatory since Armv8.5
We only implement this for AArch64

Change-Id: I063642ac24d27f0a81ba79b1d38f72468bb130eb
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 73 insertions(+), 18 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index b826f0d..5e45fe4 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -91,6 +91,7 @@
 "FEAT_FLAGM2",
 "FEAT_RNG",
 "FEAT_RNG_TRAP",
+"FEAT_EVT",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -174,6 +175,7 @@
 "FEAT_IDST",
 # Armv8.5
 "FEAT_FLAGM2",
+"FEAT_EVT",
 # Armv9.2
 "FEAT_SME",
 ]
@@ -217,6 +219,7 @@
 "FEAT_FLAGM2",
 "FEAT_RNG",
 "FEAT_RNG_TRAP",
+"FEAT_EVT",
 ]


diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 53e9268..c8ea1f2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1445,7 +1445,8 @@
 }
 } else if (el2_enabled && !in_host && hcr.tpu) {
 return inst.generateTrap(EL2);
-} else if (el2_enabled && !in_host && hcr.tocu) {
+} else if (el2_enabled && !in_host &&
+   HaveExt(tc, ArmExtension::FEAT_EVT) && hcr.tocu) {
 return inst.generateTrap(EL2);
 } else if (el2_enabled && in_host && !sctlr2.uci) {
 return inst.generateTrap(EL2);
@@ -1462,7 +1463,8 @@
 const bool el2_enabled = EL2Enabled(tc);
 if (el2_enabled && hcr.tpu) {
 return inst.generateTrap(EL2);
-} else if (el2_enabled && hcr.tocu) {
+} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+   hcr.tocu) {
 return inst.generateTrap(EL2);
 } else {
 return NoFault;
@@ -1477,7 +1479,8 @@
 const bool el2_enabled = EL2Enabled(tc);
 if (el2_enabled && hcr.tpu) {
 return inst.generateTrap(EL2);
-} else if (el2_enabled && hcr.ticab) {
+} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+   hcr.ticab) {
 return inst.generateTrap(EL2);
 } else {
 return NoFault;
@@ -1750,6 +1753,54 @@
 }

 Fault
+faultTlbiOsEL1(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const bool el2_enabled = EL2Enabled(tc);
+if (el2_enabled && hcr.ttlb) {
+return inst.generateTrap(EL2);
+} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+   hcr.ttlbos) {
+return inst.generateTrap(EL2);
+} else {
+return NoFault;
+}
+}
+
+Fault
+faultTlbiIsEL1(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const bool el2_enabled = EL2Enabled(tc);
+if (el2_enabled && hcr.ttlb) {
+return inst.generateTrap(EL2);
+} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+   hcr.ttlbis) {
+return inst.generateTrap(EL2);
+} else {
+return NoFault;
+}
+}
+
+Fault
+faultCacheEL1(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const bool el2_enabled = EL2Enabled(tc);
+if (el2_enabled && hcr.tid2) {
+return inst.generateTrap(EL2);
+} else if (el2_enabled && HaveExt(tc, ArmExtension::FEAT_EVT) &&
+   hcr.tid4) {
+return inst.generateTrap(EL2);
+} else {
+return NoFault;
+}
+}
+
+Fault
 faultPauthEL1(const MiscRegLUTEntry &entry,
 ThreadContext *tc, const MiscRegOp64 &inst)
 {
@@ -4041,6 +4092,7 @@
   mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
   mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 :  
0x0;
   mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 :  
0x0;

+  mmfr2_el1.evt = release->has(ArmExtension::FEAT_EVT) ? 0x2 : 0x0;
   return mmfr2_el1;
   }())
   .faultRead(EL0, faultIdst)
@@ -4090,11 +4142,11 @@

 InitReg(MISCREG_CCSIDR_EL1)
   .faultRead(EL0, faultIdst)
-  .faultRead(EL1, HCR_TRAP(tid2))
+  .faultRead(EL1, faultCacheEL1)
   .allPrivileges().writes(0);
 InitReg(MISCREG_CLIDR_EL1)
   .faultRead(EL0, faultIdst)
-  .faultRead(EL1, HCR_TRAP(tid2))
+  .faultRead(EL1, faultCacheEL1)
   .allPrivileges().writes(0);
 InitReg(MISCREG_AIDR_EL1)
   .faultRead(EL0, faultIdst)
@@ -4102,7 +4154,7 @@
   .allPriv

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_HCX

2023-05-24 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70939?usp=email )



Change subject: arch-arm: Implement FEAT_HCX
..

arch-arm: Implement FEAT_HCX

This is just making the HCRX_EL2 register read/writable;
trapping behaviour will be implemented with further extensions

Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
4 files changed, 32 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5e45fe4..d57fe80 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -92,6 +92,8 @@
 "FEAT_RNG",
 "FEAT_RNG_TRAP",
 "FEAT_EVT",
+# Armv8.7
+"FEAT_HCX",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -176,6 +178,8 @@
 # Armv8.5
 "FEAT_FLAGM2",
 "FEAT_EVT",
+# Armv8.7
+"FEAT_HCX",
 # Armv9.2
 "FEAT_SME",
 ]
@@ -223,8 +227,14 @@
 ]


-class Armv92(Armv85):
-extensions = Armv85.extensions + ["FEAT_SME"]
+class Armv87(Armv85):
+extensions = Armv85.extensions + [
+"FEAT_HCX",
+]
+
+
+class Armv92(Armv87):
+extensions = Armv87.extensions + ["FEAT_SME"]


 class ArmSystem(System):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index c8ea1f2..375e01a 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1600,6 +1600,18 @@
 }

 Fault
+faultHcrxEL2(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+if (ArmSystem::haveEL(tc, EL3) && !scr.hxen) {
+return inst.generateTrap(EL3);
+} else {
+return NoFault;
+}
+}
+
+Fault
 faultZcrEL1(const MiscRegLUTEntry &entry,
 ThreadContext *tc, const MiscRegOp64 &inst)
 {
@@ -4081,6 +4093,7 @@
   mmfr1_el1.vh = release->has(ArmExtension::FEAT_VHE) ? 0x1 : 0x0;
   mmfr1_el1.hpds = release->has(ArmExtension::FEAT_HPDS) ? 0x1 :  
0x0;

   mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
+  mmfr1_el1.hcx = release->has(ArmExtension::FEAT_HCX) ? 0x1 : 0x0;
   return mmfr1_el1;
   }())
   .faultRead(EL0, faultIdst)
@@ -4225,6 +4238,9 @@
 InitReg(MISCREG_HCR_EL2)
   .hyp().mon()
   .mapsTo(MISCREG_HCR, MISCREG_HCR2);
+InitReg(MISCREG_HCRX_EL2)
+  .hyp().mon()
+  .fault(EL2, faultHcrxEL2);
 InitReg(MISCREG_MDCR_EL2)
   .hyp().mon()
   .fault(EL2, faultDebugEL2)
@@ -5645,11 +5661,6 @@
   .warnNotFail()
   .fault(faultUnimplemented);

-// HCX extension (unimplemented)
-InitReg(MISCREG_HCRX_EL2)
-  .unimplemented()
-  .warnNotFail();
-
 // FGT extension (unimplemented)
 InitReg(MISCREG_HFGRTR_EL2)
   .unimplemented()
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 429fcb5..cb03841 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -589,6 +589,7 @@
 MISCREG_SCTLR_EL2,
 MISCREG_ACTLR_EL2,
 MISCREG_HCR_EL2,
+MISCREG_HCRX_EL2,
 MISCREG_MDCR_EL2,
 MISCREG_CPTR_EL2,
 MISCREG_HSTR_EL2,
@@ -1125,9 +1126,6 @@
 MISCREG_VSESR_EL2,
 MISCREG_VDISR_EL2,

-// HCX extension (unimplemented)
-MISCREG_HCRX_EL2,
-
 // FGT extension (unimplemented)
 MISCREG_HFGRTR_EL2,
 MISCREG_HFGWTR_EL2,
@@ -2272,6 +2270,7 @@
 "sctlr_el2",
 "actlr_el2",
 "hcr_el2",
+"hcrx_el2",
 "mdcr_el2",
 "cptr_el2",
 "hstr_el2",
@@ -2785,7 +2784,6 @@
 "disr_el1",
 "vsesr_el2",
 "vdisr_el2",
-"hcrx_el2",
 "hfgrtr_el2",
 "hfgwtr_el2",

diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index b7a1207..d8391d9 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -157,6 +157,7 @@
 EndBitUnion(AA64MMFR0)

 BitUnion64(AA64MMFR1)
+Bitfield<43, 40> hcx;
 Bitfield<31, 28> xnx;
 Bitfield<27, 24> specsei;
 Bitfield<23, 20> pan;
@@ -360,6 +361,7 @@

 BitUnion64(SCR)
 Bitfield<40> trndr;
+Bitfield<38> hxen;
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70939?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id1ec42a754b7d999782edde3a8ec6c6099e3331e
Gerrit-Change-Number: 70939
Gerrit-PatchSet: 1

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers

2023-05-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email )


Change subject: arch-arm: Fix printing of VecElemClass registers
..

arch-arm: Fix printing of VecElemClass registers

At the moment it is not possible to trace the value of VecElemClass
registers. If a AArch32 SIMD binary is run with tracing on,
simulation will fail the following assertion [1].

std::string
valString(const void *val, size_t size) const override
{
assert(size == sizeof(ValueType));

The problem is that Arm VecElems are stored in RegVal (uint64_t),
but the VecElem data type (ValueType above) per se is a uint32_t.

So valString is getting called with size = 8 (coming from RegVal)
but ValueType has size = 4. We fix this problem by using RegVal as
a VecElemRegClassOps template parameter to make them match.
This is not changing anything from a functionality perspective.
The result will be that we will be able to print VecElems as 64bit
values.

This solution is the most simple one but a bit dirty. I believe
in the long term we should make the VecElemClass use the void* interface
rather than the RegVal one. In this way we will be able to correctly
print the VecElem size as 32bit value.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362

Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70697
Tested-by: kokoro 
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/vec.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 00ab87f..19f37c9 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -93,7 +93,7 @@
 const int PREDREG_FFR = 16;
 const int PREDREG_UREG0 = 17;

-static inline VecElemRegClassOps
+static inline VecElemRegClassOps
 vecRegElemClassOps(NumVecElemPerVecReg);
 static inline TypedRegClassOps vecRegClassOps;
 static inline TypedRegClassOps  
vecPredRegClassOps;


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57
Gerrit-Change-Number: 70697
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Rename AdvSIMD instruction pool
..

arch-arm: Rename AdvSIMD instruction pool

The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool

This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension

Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/neon64.isa
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 9ad2de2..47d509e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2461,7 +2461,7 @@
 return new Unknown64(machInst);
 }
 } else if (bits(machInst, 15) == 1) {
-return decodeNeon3SameExtra(machInst);
+return decodeNeon3RegExtension(machInst);
 } else if (bits(machInst, 10) == 1) {
 if (bits(machInst, 23, 22))
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 72b7e28..c200da7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -39,9 +39,9 @@
 // AdvSIMD three same
 template 
 StaticInstPtr decodeNeon3Same(ExtMachInst machInst);
-// AdvSIMD three same Extra
+// AdvSIMD three register extension
 template 
-StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst);
+StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst);
 // AdvSIMD three different
 inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst);
 // AdvSIMD two-reg misc
@@ -507,7 +507,7 @@

 template 
 StaticInstPtr
-decodeNeon3SameExtra(ExtMachInst machInst)
+decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
 uint8_t size   = bits(machInst, 23, 22);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Gerrit-Change-Number: 70724
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Improve debugging of CC regs accesses
..

arch-arm: Improve debugging of CC regs accesses

As of now we are simply printing the CC reg index which is
not particularly helpful. With this patch we actually print
the (NZ|C|V) reg name.

Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70718
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/cc.hh
1 file changed, 23 insertions(+), 11 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index ba75527..474e48e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -61,10 +61,31 @@
 NumRegs
 };

+const char * const RegName[NumRegs] = {
+"nz",
+"c",
+"v",
+"ge",
+"fp",
+"zero"
+};
+
 } // namespace cc_reg

-inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
-cc_reg::NumRegs, debug::CCRegs);
+class CCRegClassOps : public RegClassOps
+{
+  public:
+std::string
+regName(const RegId &id) const override
+{
+return cc_reg::RegName[id.index()];
+}
+};
+
+static inline CCRegClassOps ccRegClassOps;
+
+inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName,
+cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps);

 namespace cc_reg
 {
@@ -77,15 +98,6 @@
 Fp = ccRegClass[_FpIdx],
 Zero = ccRegClass[_ZeroIdx];

-const char * const RegName[NumRegs] = {
-"nz",
-"c",
-"v",
-"ge",
-"fp",
-"zero"
-};
-
 } // namespace cc_reg

 enum ConditionCode

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Gerrit-Change-Number: 70718
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Define a AA64ZFR0 data type
..

arch-arm: Define a AA64ZFR0 data type

Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70725
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 214d418..b7a1207 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -203,6 +203,19 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64ZFR0)
+Bitfield<59, 56> f64mm;
+Bitfield<55, 52> f32mm;
+Bitfield<47, 44> i8mm;
+Bitfield<43, 40> sm4;
+Bitfield<35, 32> sha3;
+Bitfield<27, 24> b16b16;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> bitPerm;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sveVer;
+EndBitUnion(AA64ZFR0)
+
 BitUnion64(AA64SMFR0)
 Bitfield<63> fa64;
 Bitfield<59, 56> smEver;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Gerrit-Change-Number: 70725
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email )


Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP  
entry

..

arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70758
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/process.cc
1 file changed, 6 insertions(+), 2 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 9770ea6..6b5f69e 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012, 2017-2018, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -207,7 +207,11 @@
 Arm_Dit = 1 << 24,
 Arm_Uscat = 1 << 25,
 Arm_Ilrcpc = 1 << 26,
-Arm_Flagm = 1 << 27
+Arm_Flagm = 1 << 27,
+Arm_Sbss = 1 << 28,
+Arm_Sb = 1 << 29,
+Arm_Paca = 1 << 30,
+Arm_Pacg = 1 << 31
 };

 uint32_t hwcap = 0;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Gerrit-Change-Number: 70758
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

urn new Unknown64(machInst);
-}
-uint8_t switchVal = bits(machInst, 15, 10);
-switch (switchVal) {
-  case 0x0:
-return new Rbit64(machInst, rdzr, rn);
-  case 0x1:
-return new Rev1664(machInst, rdzr, rn);
-  case 0x2:
-if (bits(machInst, 31) == 0)
-return new Rev64(machInst, rdzr, rn);
-else
-return new Rev3264(machInst, rdzr, rn);
-  case 0x3:
-if (bits(machInst, 31) != 1)
-return new Unknown64(machInst);
-return new Rev64(machInst, rdzr, rn);
-  case 0x4:
-return new Clz64(machInst, rdzr, rn);
-  case 0x5:
-return new Cls64(machInst, rdzr, rn);
-  default:
-return new Unknown64(machInst);
-}
+return decodeDataProcOneS(machInst);
 }
   default:
 GEM5_UNREACHABLE;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Gerrit-Change-Number: 70717
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

s, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Gerrit-Change-Number: 70760
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Extend SCR to be 64-bit wide
..

arch-arm: Extend SCR to be 64-bit wide

Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70720
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index c139f1a..71fdd60 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -345,7 +345,7 @@
 Bitfield<0>  cp0;
 EndBitUnion(NSACR)

-BitUnion32(SCR)
+BitUnion64(SCR)
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Gerrit-Change-Number: 70720
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email )


Change subject: arch-arm: Enable FEAT_PAuth in SE mode
..

arch-arm: Enable FEAT_PAuth in SE mode

It was in theory already possible to use FEAT_PAuth instructions in
SE mode, however its presence was hidden to userspace code as
the cpu feature was not listed in the auxiliary vectors

Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70759
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/process.cc
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6b5f69e..02771ae 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -251,6 +251,8 @@
 hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
 hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
 hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
+hwcap |= (isa_r1.apa >= 1 || isa_r1.api >= 1) ? Arm_Paca : 0;
+hwcap |= (isa_r1.gpa >= 1 || isa_r1.gpi >= 1) ? Arm_Pacg : 0;

 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Gerrit-Change-Number: 70759
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

uot;RegImmImmOp64",
+   flagmCheckCode + rmifCode)
+header_output += RegImmImmOp64Declare.subst(rmifIop)
+decoder_output += RegImmImmOp64Constructor.subst(rmifIop)
+exec_output += BasicExecute.subst(rmifIop)
+
+setfCode = '''
+const int msb = %d;
+RegVal tmp = Op1;
+CondCodesNZ = (bits(tmp, msb) << 1) | (bits(tmp, msb, 0) ? 0 : 1);
+CondCodesV = bits(tmp, msb) ^ bits(tmp, msb + 1);
+'''
+setf8Iop = ArmInstObjParams("setf8", "Setf8", "RegOp64",
+flagmCheckCode + setfCode % 7)
+header_output += RegOp64Declare.subst(setf8Iop)
+decoder_output += RegOp64Constructor.subst(setf8Iop)
+exec_output += BasicExecute.subst(setf8Iop)
+
+setf16Iop = ArmInstObjParams("setf16", "Setf16", "RegOp64",
+ flagmCheckCode + setfCode % 15)
+header_output += RegOp64Declare.subst(setf16Iop)
+decoder_output += RegOp64Constructor.subst(setf16Iop)
+exec_output += BasicExecute.subst(setf16Iop)
 }};
diff --git a/src/arch/arm/isa/templates/misc64.isa  
b/src/arch/arm/isa/templates/misc64.isa

index af6b4c6..a2024f7 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -58,6 +58,56 @@
 }
 }};

+def template RegOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+  private:
+%(reg_idx_arr_decl)s;
+
+  public:
+// Constructor
+%(class_name)s(ExtMachInst machInst, RegIndex _op1);
+
+Fault execute(ExecContext *, trace::InstRecord *) const override;
+};
+}};
+
+def template RegOp64Constructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
+}};
+
+def template RegImmImmOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+  private:
+%(reg_idx_arr_decl)s;
+
+  public:
+// Constructor
+%(class_name)s(ExtMachInst machInst,
+   RegIndex _op1,
+   uint64_t _imm1, uint64_t _imm2);
+Fault execute(ExecContext *, trace::InstRecord *) const override;
+};
+}};
+
+def template RegImmImmOp64Constructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+   RegIndex _op1,
+   uint64_t _imm1, uint64_t _imm2) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+   _op1, _imm1, _imm2)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
+}};
+
 def template RegRegImmImmOp64Declare {{
 class %(class_name)s : public %(base_class)s
 {
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 9b0f3b2..b2378cc 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -314,6 +314,11 @@

 uint64_t hwcap = 0;

+ThreadContext *tc = system->threads[contextIds[0]];
+
+const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
+hwcap |= (isa_r0.ts >= 2) ? Arm_Flagm2 : Arm_None;
+
 return hwcap;
 }

diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index ec5670e..9e633c0 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3891,6 +3891,9 @@
   isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
   isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
   isar0_el1.tlb = release->has(ArmExtension::FEAT_TLBIOS) ? 0x1 :  
0x0;

+      isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
+  0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
+  0x1 : 0x0;
   return isar0_el1;
   }())
   .faultRead(EL1, HCR_TRAP(tid3))

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Gerrit-Change-Number: 70719
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

 .fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .hyp().mon();
 InitReg(MISCREG_SMCR_EL12)
 .allPrivileges().exceptUserMode();
@@ -5411,6 +5487,9 @@
 smcr_el1.len = smeVL - 1;
 return smcr_el1;
 }())
+.fault(EL1, faultSmenEL1)
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .allPrivileges().exceptUserMode();
 InitReg(MISCREG_TPIDR2_EL0)
 .allPrivileges();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Gerrit-Change-Number: 70722
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

3986,8 +4010,9 @@
   isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :  
0x0;

   return isar1_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR0_EL1)
   .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
   AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
@@ -3995,8 +4020,9 @@
   mmfr0_el1.parange = encodePhysAddrRange64(parange);
   return mmfr0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR1_EL1)
   .reset([p,release=release](){
   AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
@@ -4006,17 +4032,20 @@
   mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
   return mmfr1_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR2_EL1)
   .reset([p,release=release](){
   AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
   mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
   mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 :  
0x0;
+  mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 :  
0x0;

   return mmfr2_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);

 InitReg(MISCREG_APDAKeyHi_EL1)
   .fault(EL1, faultPauthEL1)
@@ -4060,14 +4089,17 @@
   .allPrivileges().exceptUserMode();

 InitReg(MISCREG_CCSIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_CLIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_AIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid1))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_CSSELR_EL1)
   .allPrivileges().exceptUserMode()
   .fault(EL1, HCR_TRAP(tid2))
@@ -5371,6 +5403,7 @@

 // SVE
 InitReg(MISCREG_ID_AA64ZFR0_EL1)
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid3))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ZCR_EL3)
@@ -5410,8 +5443,9 @@
 smfr0_el1.fa64 = 0x1;
 return smfr0_el1;
 }())
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid3))
-.allPrivileges().exceptUserMode().writes(0);
+.allPrivileges().writes(0);
 InitReg(MISCREG_SVCR)
 .res0([](){
 SVCR svcr_mask = 0;
@@ -5432,8 +5466,9 @@
 smidr_el1.implementer = 0x41;
 return smidr_el1;
 }())
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid1))
-.allPrivileges().exceptUserMode().writes(0);
+.allPrivileges().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
 .res0(mask(63, 4))
 .fault(EL1, faultEsm)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Gerrit-Change-Number: 70723
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

+.unverifiable()
+.allPrivileges().writes(0);
+InitReg(MISCREG_RNDRRS)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+
 // Dummy registers
 InitReg(MISCREG_NOP)
   .allPrivileges();
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index c43cf74..429fcb5 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1091,6 +1091,10 @@
 MISCREG_TPIDR2_EL0,
 MISCREG_MPAMSM_EL1,

+// FEAT_RNG
+MISCREG_RNDR,
+MISCREG_RNDRRS,
+
 // NUM_PHYS_MISCREGS specifies the number of actual physical
 // registers, not considering the following pseudo-registers
 // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -2760,6 +2764,9 @@
 "tpidr2_el0",
 "mpamsm_el1",

+"rndr",
+"rndrrs",
+
 "num_phys_regs",

 // Dummy registers
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 71fdd60..214d418 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -346,6 +346,7 @@
 EndBitUnion(NSACR)

 BitUnion64(SCR)
+Bitfield<40> trndr;
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Gerrit-Change-Number: 70721
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

2023-05-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email )



Change subject: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry
..

arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

The presence of some of the new extensions is reported via
the AT_HWCAP2 entry

Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/process.cc
M src/arch/arm/process.hh
2 files changed, 69 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 02771ae..9b0f3b2 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -261,6 +261,62 @@
 return hwcap;
 }

+uint64_t
+ArmProcess64::armHwcapImpl2() const
+{
+enum ArmCpuFeature : uint64_t
+{
+Arm_None = 0,
+Arm_Dcpodp = 1ULL << 0,
+Arm_Sve2 = 1ULL<< 1,
+Arm_Sveaes = 1ULL << 2,
+Arm_Svepmull = 1ULL << 3,
+Arm_Svebitperm = 1ULL << 4,
+Arm_Svesha3 = 1ULL << 5,
+Arm_Svesm4 = 1ULL << 6,
+Arm_Flagm2 = 1ULL << 7,
+Arm_Frint = 1ULL << 8,
+Arm_Svei8mm = 1ULL << 9,
+Arm_Svef32mm = 1ULL << 10,
+Arm_Svef64mm = 1ULL << 11,
+Arm_Svebf16 = 1ULL << 12,
+Arm_I8mm = 1ULL << 13,
+Arm_Bf16 = 1ULL << 14,
+Arm_Dgh = 1ULL << 15,
+Arm_Rng = 1ULL << 16,
+Arm_Bti = 1ULL << 17,
+Arm_Mte = 1ULL << 18,
+Arm_Ecv = 1ULL << 19,
+Arm_Afp = 1ULL << 20,
+Arm_Rpres = 1ULL << 21,
+Arm_Mte3 = 1ULL << 22,
+Arm_Sme = 1ULL << 23,
+Arm_Sme_I16i64 = 1ULL << 24,
+Arm_Sme_F64f64 = 1ULL << 25,
+Arm_Sme_I8i32 = 1ULL << 26,
+Arm_Sme_F16f32 = 1ULL << 27,
+Arm_Sme_B16f32 = 1ULL << 28,
+Arm_Sme_F32f32 = 1ULL << 29,
+Arm_Sme_Fa64 = 1ULL << 30,
+Arm_Wfxt = 1ULL << 31,
+Arm_Ebf16 = 1ULL << 32,
+Arm_Sve_Ebf16 = 1ULL << 33,
+Arm_Cssc = 1ULL << 34,
+Arm_Rprfm = 1ULL << 35,
+Arm_Sve2p1 = 1ULL << 36,
+Arm_Sme2 = 1ULL << 37,
+Arm_Sme2p1 = 1ULL << 38,
+Arm_Sme_I16i32 = 1ULL << 39,
+Arm_Sme_Bi32i32 = 1ULL << 40,
+Arm_Sme_B16b16 = 1ULL << 41,
+Arm_Sme_F16f16 = 1ULL << 42
+};
+
+uint64_t hwcap = 0;
+
+return hwcap;
+}
+
 template 
 void
 ArmProcess::argsInit(int pageSize, const RegId &spId)
@@ -284,11 +340,10 @@
 if (elfObject) {

 if (objFile->getOpSys() == loader::Linux) {
-IntType features = armHwcap();
-
 //Bits which describe the system hardware capabilities
 //XXX Figure out what these should be
-auxv.emplace_back(gem5::auxv::Hwcap, features);
+auxv.emplace_back(gem5::auxv::Hwcap, armHwcap());
+auxv.emplace_back(gem5::auxv::Hwcap2, armHwcap2());
 //Frequency at which times() increments
 auxv.emplace_back(gem5::auxv::Clktck, 0x64);
 //Whether to enable "secure mode" in the executable
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index 6bdabef..0aee6dc 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2012, 2018 ARM Limited
+* Copyright (c) 2012, 2018, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -69,10 +69,18 @@
 return static_cast(armHwcapImpl());
 }

+template
+IntType
+armHwcap2() const
+{
+return static_cast(armHwcapImpl2());
+}
+
 /**
  * AT_HWCAP is 32-bit wide on AArch64 as well so we can
  * safely return an uint32_t */
 virtual uint32_t armHwcapImpl() const = 0;
+virtual uint64_t armHwcapImpl2() const = 0;
 };

 class ArmProcess32 : public ArmProcess
@@ -86,6 +94,7 @@

 /** AArch32 AT_HWCAP */
 uint32_t armHwcapImpl() const override;
+uint64_t armHwcapImpl2() const override { return 0; }
 };

 class ArmProcess64 : public ArmProcess
@@ -99,6 +108,7 @@

 /** AArch64 AT_HWCAP */
 uint32_t armHwcapImpl() const override;
+uint64_t armHwcapImpl2() const override;
 };

 } // namespace gem5

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Gerrit-Change-Number: 70760
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

2023-05-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email )



Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP  
entry

..

arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/process.cc
1 file changed, 6 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 9770ea6..6b5f69e 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012, 2017-2018, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -207,7 +207,11 @@
 Arm_Dit = 1 << 24,
 Arm_Uscat = 1 << 25,
 Arm_Ilrcpc = 1 << 26,
-Arm_Flagm = 1 << 27
+Arm_Flagm = 1 << 27,
+Arm_Sbss = 1 << 28,
+Arm_Sb = 1 << 29,
+Arm_Paca = 1 << 30,
+Arm_Pacg = 1 << 31
 };

 uint32_t hwcap = 0;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Gerrit-Change-Number: 70758
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode

2023-05-18 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email )



Change subject: arch-arm: Enable FEAT_PAuth in SE mode
..

arch-arm: Enable FEAT_PAuth in SE mode

It was in theory already possible to use FEAT_PAuth instructions in
SE mode, however its presence was hidden to userspace code as
the cpu feature was not listed in the auxiliary vectors

Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/process.cc
1 file changed, 2 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6b5f69e..02771ae 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -251,6 +251,8 @@
 hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
 hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
 hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
+hwcap |= (isa_r1.apa >= 1 || isa_r1.api >= 1) ? Arm_Paca : 0;
+hwcap |= (isa_r1.gpa >= 1 || isa_r1.gpi >= 1) ? Arm_Pacg : 0;

 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Gerrit-Change-Number: 70759
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Re-factor Arm decoder for SVE mixed-sign DOT insts.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

   return decodeSveIntegerDotProductIndexed(machInst);
+  case 0b11:
+return decodeSveMixedSignDotProductIndexed(machInst);
+  default:
+return new Unknown64(machInst);
+}
+} else {
+return new Unknown64(machInst);
+}
+return new Unknown64(machInst);
+}

 }  // namespace Aarch64
 }};
diff --git a/src/arch/arm/isa/formats/sve_top_level.isa  
b/src/arch/arm/isa/formats/sve_top_level.isa

index 0699637..d4c2a13 100644
--- a/src/arch/arm/isa/formats/sve_top_level.isa
+++ b/src/arch/arm/isa/formats/sve_top_level.isa
@@ -71,8 +71,10 @@
 StaticInstPtr decodeSveIntWideImmUnpred(ExtMachInst machInst);
 StaticInstPtr decodeSveClamp(ExtMachInst machInst);

-StaticInstPtr decodeSveMultiplyAddUnpred(ExtMachInst machInst);
-StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);
+StaticInstPtr decodeSveIntegerDotProductUnpred(ExtMachInst machInst);
+StaticInstPtr decodeSveIntegerDotProductIndexed(ExtMachInst machInst);
+StaticInstPtr decodeSveMixedSignDotProduct(ExtMachInst machInst);
+StaticInstPtr decodeSveMixedSignDotProductIndexed(ExtMachInst  
machInst);


 StaticInstPtr decodeSveFpFastReduc(ExtMachInst machInst);
 StaticInstPtr decodeSveFpUnaryUnpred(ExtMachInst machInst);
@@ -96,6 +98,8 @@
 StaticInstPtr decodeSveMemStore(ExtMachInst machInst);

 StaticInstPtr decodeSveMisc(ExtMachInst machInst);
+StaticInstPtr decodeSveIntegerMulAddUnpred(ExtMachInst machInst);
+StaticInstPtr decodeSveMultiplyIndexed(ExtMachInst machInst);
 }
 }};

@@ -107,10 +111,31 @@
 decodeSveInt(ExtMachInst machInst)
 {
 if (bits(machInst, 31, 29) == 0b010) {
-if (bits(machInst, 24) == 0b1 &&
-bits(machInst, 21) == 0b0 &&
-bits(machInst, 15, 14)==0b10) {
-return decodeSveMisc(machInst);
+uint8_t op1 = bits(machInst, 24, 23);
+switch (op1) {
+  case 0b00:
+  case 0b01:
+  if (bits(machInst, 21) == 0b0) {
+  if (bits(machInst, 15) == 0b0) {
+  return decodeSveIntegerMulAddUnpred(machInst);
+  } else {
+  return new Unknown64(machInst);
+  }
+  } else {
+  return decodeSveMultiplyIndexed(machInst);
+  }
+  break;
+  case 0b10:
+  case 0b11:
+  if (bits(machInst, 21) == 0b0 &&
+  bits(machInst, 15, 14) == 0b10) {
+  return decodeSveMisc(machInst);
+  } else {
+  return new Unknown64(machInst);
+  }
+  break;
+  default:
+  return new Unknown64(machInst);
 }
 }

@@ -130,11 +155,10 @@
   bits(machInst, 13);
 switch (b_15_13) {
   case 0x0:
-if (bits(machInst, 30)) {
-return decodeSveMultiplyAddUnpred(machInst);
-} else {
+if (!bits(machInst, 30)) {
 return decodeSveIntArithBinPred(machInst);
 }
+break;
   case 0x1:
 return decodeSveIntReduc(machInst);
   case 0x2:
@@ -155,12 +179,11 @@
 if (b_13) {
 return decodeSveIntLogUnpred(machInst);
 } else {
-if (bits(machInst, 30)) {
-return decodeSveMultiplyIndexed(machInst);
-} else {
+if (!bits(machInst, 30)) {
 return decodeSveIntArithUnpred(machInst);
 }
 }
+break;
   case 0x1:
 if (b_13) {
 return new Unknown64(machInst);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70731?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42b280d4bd1b4ab9d8c633bdc523bd08c281d218
Gerrit-Change-Number: 70731
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-F64MM.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email

to review the following change.


Change subject: arch-arm: Declare support for Armv8.2-F64MM.
..

arch-arm: Declare support for Armv8.2-F64MM.

Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-F64MM.

This indicates that all pre-requisites for Armv8.2 SVE FP64
double-precision floating-point matrix multiplication instructions
have been met.

FMMLA, and LD1RO* instructions have been implemented, as well as the
128-bit element variants of TRN1, TRN2, UZP1, UZP2, ZIP1, and ZIP2.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
3 files changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 31ecbcb..fbd93b6 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -54,6 +54,7 @@
 "FEAT_RDM",
 # Armv8.2
 "FEAT_F32MM",
+"FEAT_F64MM",
 "FEAT_SVE",
 # Armv8.3
 "FEAT_FCMA",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 06d1dcc..5517632 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -79,6 +79,7 @@
 "FEAT_LVA",  # Optional in Armv8.2
 "FEAT_LPA",  # Optional in Armv8.2
 "FEAT_F32MM", # Optional in Armv8.2
+"FEAT_F64MM", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -165,6 +166,7 @@
 "FEAT_LPA",
 "FEAT_SVE",
 "FEAT_F32MM",
+"FEAT_F64MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -199,6 +201,7 @@
 "FEAT_LPA",
 "FEAT_SVE",
 "FEAT_F32MM",
+"FEAT_F64MM",
 ]


diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6cabfca..362f996 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5405,6 +5405,7 @@
 .reset([this](){
 AA64ZFR0 zfr0_el1 = 0;
 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :  
0;
+zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 :  
0;

 return zfr0_el1;
 }())
 .faultRead(EL0, faultIdst)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70729?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idac3a3ca590e6eb2beb217a40a8c10af1e917440
Gerrit-Change-Number: 70729
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-I8MM NEON extension.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

 40> specres;
     Bitfield<39, 36> sb;
 Bitfield<35, 32> frintts;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70737?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fb9318f67cc9d2737079283e1a095630c4d2ad9
Gerrit-Change-Number: 70737
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Declare support for Armv8.2-I8MM.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70733?usp=email

to review the following change.


Change subject: arch-arm: Declare support for Armv8.2-I8MM.
..

arch-arm: Declare support for Armv8.2-I8MM.

Sets the appropriate bit in the ID_AA64ZFR0_EL1 sysreg that declares
support for ARMv8.2-I8MM.

This indicates that all pre-requisites for Armv8.2 SVE Int8 matrix
multiplication instructions have been met.

SMMLA, SUDOT, UMMLA, USMMLA, and USDOT instructions are implemented.

For more information please refer to the "ARM Architecture Reference
Manual Supplement - The Scalable Vector Extension (SVE), for ARMv8-A"
(https://developer.arm.com/architectures/cpu-architecture/a-profile/
docs/arm-architecture-reference-manual-supplement-armv8-a)

Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
3 files changed, 5 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index fbd93b6..ffe63eb 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -56,6 +56,7 @@
 "FEAT_F32MM",
 "FEAT_F64MM",
 "FEAT_SVE",
+"FEAT_I8MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 5517632..9e66ee7 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -80,6 +80,7 @@
 "FEAT_LPA",  # Optional in Armv8.2
 "FEAT_F32MM", # Optional in Armv8.2
 "FEAT_F64MM", # Optional in Armv8.2
+"FEAT_I8MM", # Optional in Armv8.2
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -167,6 +168,7 @@
 "FEAT_SVE",
 "FEAT_F32MM",
 "FEAT_F64MM",
+"FEAT_I8MM",
 # Armv8.3
 "FEAT_FCMA",
 "FEAT_JSCVT",
@@ -202,6 +204,7 @@
 "FEAT_SVE",
 "FEAT_F32MM",
 "FEAT_F64MM",
+"FEAT_I8MM",
 ]


diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 362f996..6b299aa 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5406,6 +5406,7 @@
 AA64ZFR0 zfr0_el1 = 0;
 zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :  
0;
 zfr0_el1.f64mm = release->has(ArmExtension::FEAT_F64MM) ? 1 :  
0;

+zfr0_el1.i8mm = release->has(ArmExtension::FEAT_I8MM) ? 1 : 0;
 return zfr0_el1;
 }())
 .faultRead(EL0, faultIdst)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70733?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id97e1c5de8c23a25336a6b323034e9eca8e598e4
Gerrit-Change-Number: 70733
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Fix too long lines in existing Arm NEON instructons.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

;> 1) & 0x1;
-// Use division instead of a shift to ensure the sign  
extension works
-// right. The compiler will figure out if it can be a shift.  
Mask the

-// inputs so they get truncated correctly.
+// Use division instead of a shift to ensure the sign extension
+// works right. The compiler will figure out if it can be a  
shift.

+// Mask the inputs so they get truncated correctly.
 destElem = (((srcElem1 & ~(Element)1) / 2) -
 ((srcElem2 & ~(Element)1) / 2)) - borrowBit;
 '''
@@ -2802,7 +2802,8 @@
 FPSCR fpscr = (FPSCR) FpscrQc;
 destElem = srcElem1;
 if (srcElem1 < 0 ||
-((BigElement)destElem & mask(sizeof(Element) * 8)) !=  
srcElem1) {

+((BigElement)destElem & mask(sizeof(Element) * 8))
+ != srcElem1) {
 fpscr.qc = 1;
 destElem = mask(sizeof(Element) * 8);
 if (srcElem1 < 0)
@@ -2821,9 +2822,9 @@
 Element carryBit =
 (((unsigned)srcElem1 & 0x1) +
  ((unsigned)srcElem2 & 0x1) + 1) >> 1;
-// Use division instead of a shift to ensure the sign  
extension works
-// right. The compiler will figure out if it can be a shift.  
Mask the

-// inputs so they get truncated correctly.
+// Use division instead of a shift to ensure the sign extension
+// works right. The compiler will figure out if it can be a  
shift.

+// Mask the inputs so they get truncated correctly.
 destElem = (((srcElem1 & ~(Element)1) / 2) +
 ((srcElem2 & ~(Element)1) / 2)) + carryBit;
 '''
@@ -3013,7 +3014,8 @@
 if (bits(destElem, sizeof(Element) * 8 - 1) == 0) {
 if (bits(tmp, sizeof(Element) * 8 - 1) == 1 ||
 tmp < srcElem1 || tmp < destElem) {
-destElem = (((Element) 1) << (sizeof(Element) * 8 -  
1)) - 1;

+destElem = (((Element) 1) << (sizeof(Element) * 8 - 1))
+   - 1;
 fpscr.qc = 1;
 } else {
 destElem = tmp;
@@ -3021,9 +3023,11 @@
 } else {
 Element absDestElem = (~destElem) + 1;
 if (absDestElem < srcElem1) {
-// Still check for positive sat., no need to check for  
negative sat.

+// Still check for positive sat., no need to check for
+// negative sat.
 if (bits(tmp, sizeof(Element) * 8 - 1) == 1) {
-destElem = (((Element) 1) << (sizeof(Element) * 8  
- 1)) - 1;
+destElem = (((Element) 1) << (sizeof(Element) * 8  
- 1))

+   - 1;
 fpscr.qc = 1;
 } else {
 destElem = tmp;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70735?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I587fcb2d75c4ab9de47fa53b4ae96526a20afe3f
Gerrit-Change-Number: 70735
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

2022 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -72,6 +72,7 @@
 static const OpClass SimdMiscOp = enums::SimdMisc;
 static const OpClass SimdMultOp = enums::SimdMult;
 static const OpClass SimdMultAccOp = enums::SimdMultAcc;
+static const OpClass SimdMatMultAccOp = enums::SimdMatMultAcc;
 static const OpClass SimdShiftOp = enums::SimdShift;
 static const OpClass SimdShiftAccOp = enums::SimdShiftAcc;
 static const OpClass SimdDivOp = enums::SimdDiv;
@@ -87,6 +88,7 @@
 static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc;
 static const OpClass SimdFloatMultOp = enums::SimdFloatMult;
 static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc;
+static const OpClass SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc;
 static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt;
 static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp;
 static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Gerrit-Change-Number: 70734
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added 128-bit encodings of SVE TRN, UZP, and ZIP insts.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Op2_x[s - eltsInPairsCount];
 }
 }
-for (unsigned i = 0; i < eCount; i++) {
+// Fill output vector with pairs of elements
+for (unsigned i = 0; i < eltsInPairsCount; i++) {
 AA64FpDest_x[i] = auxDest[i];
 }
+// Fill any trailing non-full pairs with zeros
+for (unsigned i = eltsInPairsCount; i < eCount; i++) {
+AA64FpDest_x[i] = 0;
+}
 '''
-sveBinInst('uzp1', 'Uzp1', 'SimdAluOp', unsignedTypes, '',
-   customIterCode=uzpIterCode % 0)
-sveBinInst('uzp2', 'Uzp2', 'SimdAluOp', unsignedTypes, '',
-   customIterCode=uzpIterCode % 1)
+sveBinInst('uzp1', 'Uzp1', 'SimdAluOp', extendedUnsignedTypes, '',
+   customIterCode=uzpIterCode % dict(mnemonic='uzp1', part=0))
+sveBinInst('uzp2', 'Uzp2', 'SimdAluOp', extendedUnsignedTypes, '',
+   customIterCode=uzpIterCode % dict(mnemonic='uzp2', part=1))
 # WHILELE (32-bit)
 whileLECode = '''
 cond = srcElem1 <= srcElem2;
@@ -5000,22 +5051,35 @@
zipPredIterCode % 1)
 # ZIP1, ZIP2 (vectors)
 zipIterCode = '''
+// SVE F64MM support requires that there are at least two elements
+// in the vector.
+if (eCount < 2) {
+return std::make_shared(machInst, false,
+  "%(mnemonic)s");
+}
 int s;
-int part = %d;
+int part = %(part)d;
 ArmISA::VecRegContainer tmpVecC;
 auto auxDest = tmpVecC.as();
-for (unsigned i = 0; i < eCount / 2; i++) {
-s = i + (part * (eCount / 2));
+const unsigned eltPairsCount = eCount / 2;
+const unsigned eltsInPairsCount = eltPairsCount * 2;
+for (unsigned i = 0; i < eltPairsCount; i++) {
+s = i + (part * (eltsInPairsCount / 2));
 auxDest[2 * i] = AA64FpOp1_x[s];
 auxDest[2 * i + 1] = AA64FpOp2_x[s];
 }
-for (unsigned i = 0; i < eCount; i++) {
+// Fill output vector with pairs of elements
+for (unsigned i = 0; i < eltsInPairsCount; i++) {
 AA64FpDest_x[i] = auxDest[i];
 }
+// Fill any trailing non-full pairs with zeros
+for (unsigned i = eltsInPairsCount; i < eCount; i++) {
+AA64FpDest_x[i] = 0;
+}
 '''
-sveBinInst('zip1', 'Zip1', 'SimdAluOp', unsignedTypes, '',
-       customIterCode=zipIterCode % 0)
-sveBinInst('zip2', 'Zip2', 'SimdAluOp', unsignedTypes, '',
-   customIterCode=zipIterCode % 1)
+sveBinInst('zip1', 'Zip1', 'SimdAluOp', extendedUnsignedTypes, '',
+   customIterCode=zipIterCode % dict(mnemonic='zip1', part=0))
+sveBinInst('zip2', 'Zip2', 'SimdAluOp', extendedUnsignedTypes, '',
+   customIterCode=zipIterCode % dict(mnemonic='zip2', part=1))

 }};

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70728?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I496576340c48410fedb2cf6fc7d1a02e219b3bd4
Gerrit-Change-Number: 70728
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE Integer Matrix instructions.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

t('mls', 'Mls', 'SimdMultAccOp', signedTypes, mlsCode)
+
+mmlaCode = ('destElem += srcElemA * srcElemB')
+# SMMLA (vectors)
+sveMatMulInst('smmla', 'Smmla', 'SimdMultAccOp',
+  (('int32_t', 'int8_t', 'int8_t'),),
+  numDestRows=2, numDestCols=2, K=8,
+  elt_mul_op=mmlaCode)
+# USMMLA (vectors)
+sveMatMulInst('usmmla', 'Usmmla', 'SimdMultAccOp',
+  (('int32_t', 'uint8_t', 'int8_t'),),
+  numDestRows=2, numDestCols=2, K=8,
+  elt_mul_op=mmlaCode)
+# UMMLA (vectors)
+sveMatMulInst('ummla', 'Ummla', 'SimdMultAccOp',
+  (('uint32_t', 'uint8_t', 'uint8_t'),),
+  numDestRows=2, numDestCols=2, K=8,
+  elt_mul_op=mmlaCode)
+
 # MOVPRFX (predicated)
 movCode = 'destElem = srcElem1;'
 sveUnaryInst('movprfx', 'MovprfxPredM', 'SimdMiscOp', unsignedTypes,

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70730?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia50e28fae03634cbe04b42a9900bab65a604817f
Gerrit-Change-Number: 70730
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Added Armv8.2-I8MM SVE mixed-sign dot product instrs.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

;], isIndexed = False)
+# USDOT (indexed)
+sveDotInst('usdot', 'Usdoti', 'SimdAluOp', ['uint8_t, int8_t,  
int32_t'],

+   isIndexed = True)
+# USDOT (vectors)
+sveDotInst('usdot', 'Usdotv', 'SimdAluOp', ['uint8_t, int8_t,  
int32_t'],

+   isIndexed = False)
 # UMAX (immediate)
 sveWideImmInst('umax', 'UmaxImm', 'SimdCmpOp', unsignedTypes, maxCode)
 # UMAX (vectors)
diff --git a/src/arch/arm/isa/templates/sve.isa  
b/src/arch/arm/isa/templates/sve.isa

index 9043e23..7c41b40 100644
--- a/src/arch/arm/isa/templates/sve.isa
+++ b/src/arch/arm/isa/templates/sve.isa
@@ -1113,17 +1113,22 @@
 }};

 def template SveWideningTerImmOpDeclare {{
-template 
+template 
 class %(class_name)s : public %(base_class)s
 {
+  static_assert(sizeof(_SElementA) == sizeof(_SElementB),
+"Source elements must have the same size.");
+
   private:
 %(reg_idx_arr_decl)s;

   protected:
 typedef _DElement Element;
-typedef _SElement SElement;
+typedef _SElementA SElementA;
+typedef _SElementB SElementB;
 typedef _DElement DElement;
-typedef _SElement TPSElem;
+typedef _SElementA TPSrcAElem;
+typedef _SElementB TPSrcBElem;
 typedef _DElement TPDElem;

   public:
@@ -1142,7 +1147,7 @@
 }};

 def template SveWideningTerOpDeclare {{
-template 
+template 
 class %(class_name)s : public %(base_class)s
 {
   private:
@@ -1150,9 +1155,11 @@

   protected:
 typedef _DElement Element;
-typedef _SElement SElement;
+typedef _SElementA SElementA;
+typedef _SElementB SElementB;
 typedef _DElement DElement;
-typedef _SElement TPSElem;
+typedef _SElementA TPSrcAElem;
+typedef _SElementB TPSrcBElem;
 typedef _DElement TPDElem;

   public:
@@ -1269,6 +1276,26 @@
 }
 }};

+def template SveWideningTerOpExecute {{
+template 
+Fault %(class_name)s::execute
+   (ExecContext *xc,
+trace::InstRecord *traceData) const
+{
+Fault fault = NoFault;
+%(op_decl)s;
+%(op_rd)s;
+
+%(code)s;
+if (fault == NoFault)
+{
+%(op_wb)s;
+}
+
+return fault;
+}
+}};
+
 def template SveNonTemplatedOpExecute {{
 Fault
 %(class_name)s::execute(ExecContext *xc,

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70732?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I83841654cee74b940f967b3a37b99d87c01bd92c
Gerrit-Change-Number: 70732
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Support Arm SVE Load-Broadcast Octaword instructions.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

'''
+''' % dict(memAccessSize=memAccessSize)
 memAccCode = '''
-__uint128_t qword;
-RegElemType* qp = reinterpret_cast(&qword);
-for (int i = 0; i < 16/sizeof(RegElemType); ++i) {
+// Copy active elements of the data from memory into a temporary
+// quadword/octaword
+__uint128_t qwords[%(numQwordSegments)d];
+eCount = %(memAccessSize)d/sizeof(RegElemType);
+RegElemType* qp = reinterpret_cast(&qwords);
+for (int i = 0; i < eCount; ++i) {
 if (GpOp_x[i]) {
 qp[i] = memDataView[i];
 } else {
 qp[i] = 0;
 }
 }
-eCount = ArmStaticInst::getCurSveVecLen<__uint128_t>(
+// Repeat the temporary quadword/octaword segment into the
+// vector register. Zero fill the remainder for non-full
+// octawords.
+unsigned numQwords = ArmStaticInst::getCurSveVecLen<__uint128_t>(
 xc->tcBase());
-for (int i = 0; i < eCount; ++i) {
-AA64FpDest_uq[i] = qword;
+unsigned numFullQwords = numQwords -
+ (numQwords %% %(numQwordSegments)d);
+for (int i = 0; i < numQwords; ++i) {
+if (i < numFullQwords) {
+AA64FpDest_uq[i] = qwords[i %% %(numQwordSegments)d];
+} else {
+AA64FpDest_uq[i] = 0;
+}
 }
-'''
-iop = ArmInstObjParams('ld1rq',
-'SveLd1RqSI' if offsetIsImm else 'SveLd1RqSS',
-'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
+''' % dict(memAccessSize=memAccessSize,
+   numQwordSegments=numQwordSegments)
+iop = ArmInstObjParams(
+inst_config.mnemonic,
+inst_config.classname,
+inst_config.baseclass,
 {'tpl_header': tplHeader,
  'tpl_args': tplArgs,
  'rden_code': loadRdEnableCode,
@@ -1539,8 +1566,7 @@
 SveContigLoadCompleteAcc.subst(iop))
 for ttype in ('uint8_t', 'uint16_t', 'uint32_t', 'uint64_t'):
 substDict = {'tpl_args': '<%s, %s>' % (ttype, ttype),
-'class_name': 'SveLd1RqSI' if offsetIsImm
-  else 'SveLd1RqSS'}
+ 'class_name': inst_config.classname}
 exec_output += SveContigMemExecDeclare.subst(substDict)

 # LD1[S]{B,H,W,D} (scalar plus immediate)
@@ -1556,9 +1582,14 @@
 emitSveLoadAndRepl()

 # LD1RQ{B,H,W,D} (scalar plus immediate)
-emitSveLoadAndReplQuad(offsetIsImm = True)
+emitSveLoadAndReplMulti(offsetIsImm=True, numQwordSegments=1)
 # LD1RQ{B,H,W,D} (scalar plus scalar)
-emitSveLoadAndReplQuad(offsetIsImm = False)
+emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=1)
+
+    # LD1RO{B,H,W,D} (scalar plus immediate)
+emitSveLoadAndReplMulti(offsetIsImm=True, numQwordSegments=2)
+# LD1RO{B,H,W,D} (scalar plus scalar)
+emitSveLoadAndReplMulti(offsetIsImm=False, numQwordSegments=2)

 # LD{2,3,4}{B,H,W,D} (scalar plus immediate)
 # ST{2,3,4}{B,H,W,D} (scalar plus immediate)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70727?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I98ee4f56c8099bf40c9034baa488d318ae57d3aa
Gerrit-Change-Number: 70727
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add support for Armv8.2-DotProd NEON extension.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

);
+default:
+  return new Unknown64(machInst);
+  }
   default:
 return new Unknown64(machInst);
 }
diff --git a/src/arch/arm/isa/insts/neon64.isa  
b/src/arch/arm/isa/insts/neon64.isa

index 0da7f06..53c0f11 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1082,6 +1082,71 @@
complex=True)
 threeEqualRegInstX("fcmla", "FcmlaQX", "SimdFloatMultAccOp",
floatTypes, 4, fcmla_vec, True, complex=True)
+
+def intDotInst(name, Name, opClass,
+   destIsSigned, src1IsSigned, src2IsSigned,
+   rCount, byElem):
+destType = "int32_t" if destIsSigned else "uint32_t"
+src1Type = "int8_t" if src1IsSigned else "uint8_t"
+src2Type = "int8_t" if src2IsSigned else "uint8_t"
+dotCode = '''
+using Src1Element = %(src1Type)s;
+using Src2Element = %(src2Type)s;
+
+// Neon dot instructions always generate one output element
+// from 4 pairs of source elements.
+static_assert(sizeof(Element) == 4 * sizeof(Src1Element));
+static_assert(sizeof(Element) == 4 * sizeof(Src2Element));
+
+// Extended source element types to avoid overflow of intermediate
+// calculations.
+using ExtendedSrc1Element =
+typename vector_element_traits::
+extend_element::type;
+using ExtendedSrc2Element =
+typename vector_element_traits::
+extend_element::type;
+
+for (unsigned i = 0; i < eCount; ++i) {
+Element src1ElemsPacked = letoh(srcReg1.elements[i]);
+Element src2ElemsPacked =  
letoh(srcReg2.elements[%(src2Index)s]);

+
+Src1Element *src1Elems =
+reinterpret_cast(&src1ElemsPacked);
+Src2Element *src2Elems =
+reinterpret_cast(&src2ElemsPacked);
+
+// Dot instructions accumulate into the dest reg
+Element destElem = letoh(destReg.elements[i]);
+
+for (unsigned j = 0; j < 4; ++j) {
+ExtendedSrc1Element src1Elem =
+static_cast(src1Elems[j]);
+ExtendedSrc2Element src2Elem =
+static_cast(src2Elems[j]);
+destElem += src1Elem * src2Elem;
+}
+destReg.elements[i] = htole(destElem);
+}
+''' % dict(src1Type=src1Type, src2Type=src2Type,
+   src2Index="imm" if byElem else "i")
+threeEqualRegInstX(name, Name, opClass, (destType,), rCount,
+   dotCode, readDest=True, byElem=byElem,
+   complex=True)
+
+# SDOT (vector)
+intDotInst('sdot', 'SdotDX', 'SimdAluOp', True, True, True, 2, False)
+intDotInst('sdot', 'SdotQX', 'SimdAluOp', True, True, True, 4, False)
+# SDOT (element)
+intDotInst('sdot', 'SdotElemDX', 'SimdAluOp', True, True, True, 2,  
True)
+intDotInst('sdot', 'SdotElemQX', 'SimdAluOp', True, True, True, 4,  
True)

+# UDOT (vector)
+intDotInst('udot', 'UdotDX', 'SimdAluOp', False, False, False, 2,  
False)
+intDotInst('udot', 'UdotQX', 'SimdAluOp', False, False, False, 4,  
False)

+# UDOT (element)
+intDotInst('udot', 'UdotElemDX', 'SimdAluOp', False, False, False, 2,  
True)
+intDotInst('udot', 'UdotElemQX', 'SimdAluOp', False, False, False, 4,  
True)

+
 # CLS
 clsCode = '''
 unsigned count = 0;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6b299aa..3a39137 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3988,6 +3988,7 @@
   isar0_el1.sha1 = 0;
   isar0_el1.aes = 0;
   }
+  isar0_el1.dp = release->has(ArmExtension::FEAT_DOTPROD) ? 0x1 :  
0x0;
       isar0_el1.atomic = release->has(ArmExtension::FEAT_LSE) ? 0x2 :  
0x0;

   isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
   isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70736?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4caa3b97a74c65f32421487c55c3e36427194e61
Gerrit-Change-Number: 70736
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Add support for Arm SVE fmmla instruction.

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

 _op1, _op2)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
+
+Fault execute(ExecContext *, trace::InstRecord *) const override;
+};
+}};
+
 def template SveTerImmUnpredOpDeclare {{
 template 
 class %(class_name)s : public %(base_class)s
@@ -1284,3 +1311,32 @@
 Fault %(class_name)s<%(targs)s>::execute(
 ExecContext *, trace::InstRecord *) const;
 }};
+
+def template SveMatMulOpExecute {{
+template 
+Fault %(class_name)s::execute(
+ExecContext *xc,
+trace::InstRecord *traceData) const
+{
+Fault fault = NoFault;
+%(op_decl)s;
+%(op_rd)s;
+
+%(code)s;
+if (fault == NoFault)
+{
+%(op_wb)s;
+}
+
+return fault;
+}
+}};
+
+def template SveMatMulOpExecDeclare {{
+template
+Fault
+%(class_name)s<%(destEltType)s,%(srcEltAType)s,%(srcEltBType)s>
+::execute(ExecContext *, trace::InstRecord *) const;
+}};
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index a151177..6cabfca 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -5402,6 +5402,11 @@

 // SVE
 InitReg(MISCREG_ID_AA64ZFR0_EL1)
+.reset([this](){
+AA64ZFR0 zfr0_el1 = 0;
+zfr0_el1.f32mm = release->has(ArmExtension::FEAT_F32MM) ? 1 :  
0;

+return zfr0_el1;
+}())
 .faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid3))
 .allPrivileges().exceptUserMode().writes(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70726?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If3547378ffa48527fe540767399bcc37a5dab524
Gerrit-Change-Number: 70726
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email

to review the following change.


Change subject: arch-arm: Rename AdvSIMD instruction pool
..

arch-arm: Rename AdvSIMD instruction pool

The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool

This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension

Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/neon64.isa
2 files changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 9ad2de2..47d509e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2461,7 +2461,7 @@
 return new Unknown64(machInst);
 }
 } else if (bits(machInst, 15) == 1) {
-return decodeNeon3SameExtra(machInst);
+return decodeNeon3RegExtension(machInst);
 } else if (bits(machInst, 10) == 1) {
 if (bits(machInst, 23, 22))
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 72b7e28..c200da7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -39,9 +39,9 @@
 // AdvSIMD three same
 template 
 StaticInstPtr decodeNeon3Same(ExtMachInst machInst);
-// AdvSIMD three same Extra
+// AdvSIMD three register extension
 template 
-StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst);
+StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst);
 // AdvSIMD three different
 inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst);
 // AdvSIMD two-reg misc
@@ -507,7 +507,7 @@

 template 
 StaticInstPtr
-decodeNeon3SameExtra(ExtMachInst machInst)
+decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
 uint8_t size   = bits(machInst, 23, 22);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Gerrit-Change-Number: 70724
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

mOp64Constructor.subst(rmifIop)
+exec_output += BasicExecute.subst(rmifIop)
+
+setfCode = '''
+const int msb = %d;
+RegVal tmp = Op1;
+CondCodesNZ = (bits(tmp, msb) << 1) | (bits(tmp, msb, 0) ? 0 : 1);
+CondCodesV = bits(tmp, msb) ^ bits(tmp, msb + 1);
+'''
+setf8Iop = ArmInstObjParams("setf8", "Setf8", "RegOp64",
+flagmCheckCode + setfCode % 7)
+header_output += RegOp64Declare.subst(setf8Iop)
+decoder_output += RegOp64Constructor.subst(setf8Iop)
+exec_output += BasicExecute.subst(setf8Iop)
+
+setf16Iop = ArmInstObjParams("setf16", "Setf16", "RegOp64",
+ flagmCheckCode + setfCode % 15)
+header_output += RegOp64Declare.subst(setf16Iop)
+decoder_output += RegOp64Constructor.subst(setf16Iop)
+exec_output += BasicExecute.subst(setf16Iop)
 }};
diff --git a/src/arch/arm/isa/templates/misc64.isa  
b/src/arch/arm/isa/templates/misc64.isa

index af6b4c6..a2024f7 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -58,6 +58,56 @@
 }
 }};

+def template RegOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+  private:
+%(reg_idx_arr_decl)s;
+
+  public:
+// Constructor
+%(class_name)s(ExtMachInst machInst, RegIndex _op1);
+
+Fault execute(ExecContext *, trace::InstRecord *) const override;
+};
+}};
+
+def template RegOp64Constructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
+}};
+
+def template RegImmImmOp64Declare {{
+class %(class_name)s : public %(base_class)s
+{
+  private:
+%(reg_idx_arr_decl)s;
+
+  public:
+// Constructor
+%(class_name)s(ExtMachInst machInst,
+   RegIndex _op1,
+   uint64_t _imm1, uint64_t _imm2);
+Fault execute(ExecContext *, trace::InstRecord *) const override;
+};
+}};
+
+def template RegImmImmOp64Constructor {{
+%(class_name)s::%(class_name)s(ExtMachInst machInst,
+   RegIndex _op1,
+   uint64_t _imm1, uint64_t _imm2) :
+%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+   _op1, _imm1, _imm2)
+{
+%(set_reg_idx_arr)s;
+%(constructor)s;
+}
+}};
+
 def template RegRegImmImmOp64Declare {{
 class %(class_name)s : public %(base_class)s
 {
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index ec5670e..9e633c0 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3891,6 +3891,9 @@
   isar0_el1.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
   isar0_el1.tme = release->has(ArmExtension::TME) ? 0x1 : 0x0;
   isar0_el1.tlb = release->has(ArmExtension::FEAT_TLBIOS) ? 0x1 :  
0x0;

+  isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
+  0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
+  0x1 : 0x0;
   return isar0_el1;
   }())
   .faultRead(EL1, HCR_TRAP(tid3))

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Gerrit-Change-Number: 70719
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email

to review the following change.


Change subject: arch-arm: Improve debugging of CC regs accesses
..

arch-arm: Improve debugging of CC regs accesses

As of now we are simply printing the CC reg index which is
not particularly helpful. With this patch we actually print
the (NZ|C|V) reg name.

Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/cc.hh
1 file changed, 23 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index ba75527..474e48e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -61,10 +61,31 @@
 NumRegs
 };

+const char * const RegName[NumRegs] = {
+"nz",
+"c",
+"v",
+"ge",
+"fp",
+"zero"
+};
+
 } // namespace cc_reg

-inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
-cc_reg::NumRegs, debug::CCRegs);
+class CCRegClassOps : public RegClassOps
+{
+  public:
+std::string
+regName(const RegId &id) const override
+{
+return cc_reg::RegName[id.index()];
+}
+};
+
+static inline CCRegClassOps ccRegClassOps;
+
+inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName,
+cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps);

 namespace cc_reg
 {
@@ -77,15 +98,6 @@
 Fp = ccRegClass[_FpIdx],
 Zero = ccRegClass[_ZeroIdx];

-const char * const RegName[NumRegs] = {
-"nz",
-"c",
-"v",
-"ge",
-"fp",
-"zero"
-};
-
 } // namespace cc_reg

 enum ConditionCode

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Gerrit-Change-Number: 70718
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

}())
+.fault(EL1, faultSmenEL1)
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .allPrivileges().exceptUserMode();
 InitReg(MISCREG_TPIDR2_EL0)
 .allPrivileges();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Gerrit-Change-Number: 70722
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

, rn);
-  case 0x1:
-return new Rev1664(machInst, rdzr, rn);
-  case 0x2:
-if (bits(machInst, 31) == 0)
-return new Rev64(machInst, rdzr, rn);
-else
-return new Rev3264(machInst, rdzr, rn);
-  case 0x3:
-if (bits(machInst, 31) != 1)
-return new Unknown64(machInst);
-return new Rev64(machInst, rdzr, rn);
-  case 0x4:
-return new Clz64(machInst, rdzr, rn);
-  case 0x5:
-return new Cls64(machInst, rdzr, rn);
-  default:
-return new Unknown64(machInst);
-}
+return decodeDataProcOneS(machInst);
 }
   default:
 GEM5_UNREACHABLE;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Gerrit-Change-Number: 70717
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email

to review the following change.


Change subject: arch-arm: Define a AA64ZFR0 data type
..

arch-arm: Define a AA64ZFR0 data type

Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 13 insertions(+), 0 deletions(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 214d418..b7a1207 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -203,6 +203,19 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64ZFR0)
+Bitfield<59, 56> f64mm;
+Bitfield<55, 52> f32mm;
+Bitfield<47, 44> i8mm;
+Bitfield<43, 40> sm4;
+Bitfield<35, 32> sha3;
+Bitfield<27, 24> b16b16;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> bitPerm;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sveVer;
+EndBitUnion(AA64ZFR0)
+
 BitUnion64(AA64SMFR0)
 Bitfield<63> fa64;
 Bitfield<59, 56> smEver;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Gerrit-Change-Number: 70725
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

9 @@
 "tpidr2_el0",
 "mpamsm_el1",

+"rndr",
+"rndrrs",
+
 "num_phys_regs",

 // Dummy registers
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 71fdd60..214d418 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -346,6 +346,7 @@
 EndBitUnion(NSACR)

 BitUnion64(SCR)
+Bitfield<40> trndr;
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Gerrit-Change-Number: 70721
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

s(0);
 InitReg(MISCREG_ID_AA64MMFR0_EL1)
   .reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
   AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
@@ -3994,8 +4019,9 @@
   mmfr0_el1.parange = encodePhysAddrRange64(parange);
   return mmfr0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR1_EL1)
   .reset([p,release=release](){
   AA64MMFR1 mmfr1_el1 = p.id_aa64mmfr1_el1;
@@ -4005,17 +4031,20 @@
   mmfr1_el1.pan = release->has(ArmExtension::FEAT_PAN) ? 0x1 : 0x0;
   return mmfr1_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64MMFR2_EL1)
   .reset([p,release=release](){
   AA64MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
   mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
   mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 :  
0x0;
+  mmfr2_el1.ids = release->has(ArmExtension::FEAT_IDST) ? 0x1 :  
0x0;

   return mmfr2_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);

 InitReg(MISCREG_APDAKeyHi_EL1)
   .fault(EL1, faultPauthEL1)
@@ -4059,14 +4088,17 @@
   .allPrivileges().exceptUserMode();

 InitReg(MISCREG_CCSIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_CLIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_AIDR_EL1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid1))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_CSSELR_EL1)
   .allPrivileges().exceptUserMode()
   .fault(EL1, HCR_TRAP(tid2))
@@ -5370,6 +5402,7 @@

 // SVE
 InitReg(MISCREG_ID_AA64ZFR0_EL1)
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid3))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ZCR_EL3)
@@ -5409,8 +5442,9 @@
 smfr0_el1.fa64 = 0x1;
 return smfr0_el1;
 }())
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid3))
-.allPrivileges().exceptUserMode().writes(0);
+.allPrivileges().writes(0);
 InitReg(MISCREG_SVCR)
 .res0([](){
 SVCR svcr_mask = 0;
@@ -5431,8 +5465,9 @@
 smidr_el1.implementer = 0x41;
 return smidr_el1;
 }())
+.faultRead(EL0, faultIdst)
 .faultRead(EL1, HCR_TRAP(tid1))
-.allPrivileges().exceptUserMode().writes(0);
+.allPrivileges().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
 .res0(mask(63, 4))
 .fault(EL1, faultEsm)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Gerrit-Change-Number: 70723
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email

to review the following change.


Change subject: arch-arm: Extend SCR to be 64-bit wide
..

arch-arm: Extend SCR to be 64-bit wide

Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index c139f1a..71fdd60 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -345,7 +345,7 @@
 Bitfield<0>  cp0;
 EndBitUnion(NSACR)

-BitUnion32(SCR)
+BitUnion64(SCR)
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Gerrit-Change-Number: 70720
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix printing of VecElemClass registers

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email )



Change subject: arch-arm: Fix printing of VecElemClass registers
..

arch-arm: Fix printing of VecElemClass registers

At the moment it is not possible to trace the value of VecElemClass
registers. If a AArch32 SIMD binary is run with tracing on,
simulation will fail the following assertion [1].

std::string
valString(const void *val, size_t size) const override
{
assert(size == sizeof(ValueType));

The problem is that Arm VecElems are stored in RegVal (uint64_t),
but the VecElem data type (ValueType above) per se is a uint32_t.

So valString is getting called with size = 8 (coming from RegVal)
but ValueType has size = 4. We fix this problem by using RegVal as
a VecElemRegClassOps template parameter to make them match.
This is not changing anything from a functionality perspective.
The result will be that we will be able to print VecElems as 64bit
values.

This solution is the most simple one but a bit dirty. I believe
in the long term we should make the VecElemClass use the void* interface
rather than the RegVal one. In this way we will be able to correctly
print the VecElem size as 32bit value.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/cpu/reg_class.hh#L362

Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/regs/vec.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 00ab87f..19f37c9 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -93,7 +93,7 @@
 const int PREDREG_FFR = 16;
 const int PREDREG_UREG0 = 17;

-static inline VecElemRegClassOps
+static inline VecElemRegClassOps
 vecRegElemClassOps(NumVecElemPerVecReg);
 static inline TypedRegClassOps vecRegClassOps;
 static inline TypedRegClassOps  
vecPredRegClassOps;


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70697?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic3fc252d41449f828b77f938fefc0cd4274b1c57
Gerrit-Change-Number: 70697
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

S_Xt,
 MISCREG_TLBI_ASIDE1IS_Xt,
+MISCREG_TLBI_ASIDE1OS_Xt,
 MISCREG_TLBI_VAAE1IS_Xt,
+MISCREG_TLBI_VAAE1OS_Xt,
 MISCREG_TLBI_VALE1IS_Xt,
+MISCREG_TLBI_VALE1OS_Xt,
 MISCREG_TLBI_VAALE1IS_Xt,
+MISCREG_TLBI_VAALE1OS_Xt,
 MISCREG_TLBI_VMALLE1,
 MISCREG_TLBI_VAE1_Xt,
 MISCREG_TLBI_ASIDE1_Xt,
@@ -693,12 +699,19 @@
 MISCREG_TLBI_VALE1_Xt,
 MISCREG_TLBI_VAALE1_Xt,
 MISCREG_TLBI_IPAS2E1IS_Xt,
+MISCREG_TLBI_IPAS2E1OS_Xt,
 MISCREG_TLBI_IPAS2LE1IS_Xt,
+MISCREG_TLBI_IPAS2LE1OS_Xt,
 MISCREG_TLBI_ALLE2IS,
+MISCREG_TLBI_ALLE2OS,
 MISCREG_TLBI_VAE2IS_Xt,
+MISCREG_TLBI_VAE2OS_Xt,
 MISCREG_TLBI_ALLE1IS,
+MISCREG_TLBI_ALLE1OS,
 MISCREG_TLBI_VALE2IS_Xt,
+MISCREG_TLBI_VALE2OS_Xt,
 MISCREG_TLBI_VMALLS12E1IS,
+MISCREG_TLBI_VMALLS12E1OS,
 MISCREG_TLBI_IPAS2E1_Xt,
 MISCREG_TLBI_IPAS2LE1_Xt,
 MISCREG_TLBI_ALLE2,
@@ -707,8 +720,11 @@
 MISCREG_TLBI_VALE2_Xt,
 MISCREG_TLBI_VMALLS12E1,
 MISCREG_TLBI_ALLE3IS,
+MISCREG_TLBI_ALLE3OS,
 MISCREG_TLBI_VAE3IS_Xt,
+MISCREG_TLBI_VAE3OS_Xt,
 MISCREG_TLBI_VALE3IS_Xt,
+MISCREG_TLBI_VALE3OS_Xt,
 MISCREG_TLBI_ALLE3,
 MISCREG_TLBI_VAE3_Xt,
 MISCREG_TLBI_VALE3_Xt,
@@ -2344,11 +2360,17 @@
 "at_s1e3r_xt",
 "at_s1e3w_xt",
 "tlbi_vmalle1is",
+"tlbi_vmalle1os",
 "tlbi_vae1is_xt",
+"tlbi_vae1os_xt",
 "tlbi_aside1is_xt",
+"tlbi_aside1os_xt",
 "tlbi_vaae1is_xt",
+"tlbi_vaae1os_xt",
 "tlbi_vale1is_xt",
+"tlbi_vale1os_xt",
 "tlbi_vaale1is_xt",
+"tlbi_vaale1os_xt",
 "tlbi_vmalle1",
 "tlbi_vae1_xt",
 "tlbi_aside1_xt",
@@ -2356,12 +2378,19 @@
 "tlbi_vale1_xt",
 "tlbi_vaale1_xt",
 "tlbi_ipas2e1is_xt",
+"tlbi_ipas2e1os_xt",
 "tlbi_ipas2le1is_xt",
+"tlbi_ipas2le1os_xt",
 "tlbi_alle2is",
+"tlbi_alle2os",
 "tlbi_vae2is_xt",
+"tlbi_vae2os_xt",
 "tlbi_alle1is",
+"tlbi_alle1os",
 "tlbi_vale2is_xt",
+"tlbi_vale2os_xt",
 "tlbi_vmalls12e1is",
+"tlbi_vmalls12e1os",
 "tlbi_ipas2e1_xt",
 "tlbi_ipas2le1_xt",
 "tlbi_alle2",
@@ -2370,8 +2399,11 @@
 "tlbi_vale2_xt",
 "tlbi_vmalls12e1",
 "tlbi_alle3is",
+"tlbi_alle3os",
 "tlbi_vae3is_xt",
+    "tlbi_vae3os_xt",
 "tlbi_vale3is_xt",
+"tlbi_vale3os_xt",
 "tlbi_alle3",
 "tlbi_vae3_xt",
 "tlbi_vale3_xt",

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3
Gerrit-Change-Number: 70567
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Gerrit-Change-Number: 70557
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

 case MISCREG_SCR:
 getMMUPtr(tc)->invalidateMiscReg();
 break;
@@ -1327,21 +1280,6 @@
 idx = MISCREG_CPSR;
 }
 break;
-  case MISCREG_SVCR:
-{
-SVCR svcr = miscRegs[MISCREG_SVCR];
-SVCR newSvcr = newVal;
-
-// Don't allow other bits to be set
-svcr.sm = newSvcr.sm;
-svcr.za = newSvcr.za;
-newVal = svcr;
-}
-break;
-  case MISCREG_SMPRI_EL1:
-// Only the bottom 4 bits are settable
-newVal = newVal & 0xF;
-break;
   case MISCREG_AT_S1E1R_Xt:
 addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
 return;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6f918b2..9203810 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2662,6 +2662,7 @@
   .reset(midr)
   .hyp().monNonSecure();
 InitReg(MISCREG_VMPIDR)
+  .res1(mask(31, 31))
   .hyp().monNonSecure();
 InitReg(MISCREG_SCTLR)
   .banked()
@@ -2739,13 +2740,17 @@
   .hyp().monNonSecure();
 InitReg(MISCREG_HCR)
   .hyp().monNonSecure()
-  .res0(0x9000);
+  .res0(release->has(ArmExtension::VIRTUALIZATION) ?
+  0x9000 : mask(31, 0));
 InitReg(MISCREG_HCR2)
   .hyp().monNonSecure()
-  .res0(0xffa9ff8c);
+  .res0(release->has(ArmExtension::VIRTUALIZATION) ?
+  0xffa9ff8c : mask(31, 0));
 InitReg(MISCREG_HDCR)
   .hyp().monNonSecure();
 InitReg(MISCREG_HCPTR)
+  .res0(mask(29, 21) | mask(19, 16) | mask(14, 14))
+  .res1(mask(13, 12) | mask(9, 0))
   .hyp().monNonSecure();
 InitReg(MISCREG_HSTR)
   .hyp().monNonSecure();
@@ -2794,7 +2799,8 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_DFSR)
-  .banked();
+  .banked()
+  .res0(mask(31, 14) | mask(8, 8));
 InitReg(MISCREG_DFSR_NS)
   .bankedChild()
   .privSecure(!aarch32EL3)
@@ -2803,7 +2809,8 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_IFSR)
-  .banked();
+  .banked()
+  .res0(mask(31, 13) | mask(11, 11) | mask(8, 6));
 InitReg(MISCREG_IFSR_NS)
   .bankedChild()
   .privSecure(!aarch32EL3)
@@ -3118,6 +3125,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_AMAIR0)
+  .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
   .banked();
 InitReg(MISCREG_AMAIR0_NS)
   .bankedChild()
@@ -3127,6 +3135,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_AMAIR1)
+  .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
   .banked();
 InitReg(MISCREG_AMAIR1_NS)
   .bankedChild()
@@ -3976,6 +3985,8 @@
   .mapsTo(MISCREG_VPIDR);
 InitReg(MISCREG_VMPIDR_EL2)
   .hyp().mon()
+  .res0(mask(63, 40) | mask(29, 25))
+  .res1(mask(31, 31))
   .mapsTo(MISCREG_VMPIDR);
 InitReg(MISCREG_SCTLR_EL1)
   .allPrivileges().exceptUserMode()
@@ -5263,6 +5274,12 @@
 }())
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SVCR)
+.res0([](){
+SVCR svcr_mask = 0;
+svcr_mask.sm = 1;
+svcr_mask.za = 1;
+return ~svcr_mask;
+}())
 .allPrivileges();
 InitReg(MISCREG_SMIDR_EL1)
 .reset([](){
@@ -5274,6 +5291,7 @@
 }())
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
+.res0(mask(63, 4))
 .allPrivileges().exceptUserMode().reads(1);
 InitReg(MISCREG_SMPRIMAP_EL2)
 .hyp().mon();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894
Gerrit-Change-Number: 70563
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug  
arch

..

arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70561
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.cc
1 file changed, 1 insertion(+), 4 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6c5a9dd..6f918b2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,10 +2273,7 @@

 // AArch32 CP14 registers
 InitReg(MISCREG_DBGDIDR)
-  /* For now just implement the version number.
-   * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
-   */
-  .reset(0x5 << 16)
+  .reset(0x6 << 16) // Armv8 Debug architecture
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDSCRint)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Gerrit-Change-Number: 70561
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement RAZ/WI with raz specifier
..

arch-arm: Implement RAZ/WI with raz specifier

Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 5 insertions(+), 6 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 14349b1..7df8978 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -470,12 +470,6 @@
 return readMiscRegNoEffect(idx);
 }
 break;
-  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_AIDR:  // AUX ID set to 0
-  case MISCREG_TCMTR: // No TCM's
-return 0;

   case MISCREG_CLIDR:
 warn_once("The clidr register always reports 0 caches.\n");
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 960c2be..6c5a9dd 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2505,12 +2505,15 @@
   .unimplemented()
   .allPrivileges();
 InitReg(MISCREG_JIDR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_TEEHBR)
   .allPrivileges();
 InitReg(MISCREG_JOSCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_JMCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();

 // AArch32 CP15 registers
@@ -2548,6 +2551,7 @@
   .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TCMTR)
+  .raz() // No TCM's
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TLBTR)
   .reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@
 InitReg(MISCREG_CLIDR)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_AIDR)
+  .raz() // AUX ID set to 0
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CSSELR)
   .banked();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Gerrit-Change-Number: 70560
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Provide default mask for raz/rao helpers
..

arch-arm: Provide default mask for raz/rao helpers

Rather than forcing raz registers to write something like:

.raz(uint64_t(-1))

we provide a shorter version where if
no bitmask is specified we assume the entire register is
raz/rao. This won't be probably used by rao but I
am striving for symmetry and providing a default won't
probably hurt

Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70559
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.hh
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 3a32623..abbd1c6 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1249,13 +1249,13 @@
 return *this;
 }
 chain
-raz(uint64_t mask) const
+raz(uint64_t mask = (uint64_t)-1) const
 {
 entry._raz  = mask;
 return *this;
 }
 chain
-rao(uint64_t mask) const
+rao(uint64_t mask = (uint64_t)-1) const
 {
 entry._rao  = mask;
 return *this;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Gerrit-Change-Number: 70559
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Simplify FPSCR writes
..

arch-arm: Simplify FPSCR writes

The old logic was setting up a mask which was covering pretty much
the entire register, except for the FPSCR[14:13] and FPSCR[6:5]
register fields. Those RES0 fields were treated as WI.
We simplify this by explicitly marking them as RES0 at construction
time

Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 32 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 83df61f..9c8e282 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -815,38 +815,7 @@
 return;

   case MISCREG_FPSCR:
-{
-const uint32_t ones = (uint32_t)(-1);
-FPSCR fpscrMask = 0;
-fpscrMask.ioc = ones;
-fpscrMask.dzc = ones;
-fpscrMask.ofc = ones;
-fpscrMask.ufc = ones;
-fpscrMask.ixc = ones;
-fpscrMask.idc = ones;
-fpscrMask.ioe = ones;
-fpscrMask.dze = ones;
-fpscrMask.ofe = ones;
-fpscrMask.ufe = ones;
-fpscrMask.ixe = ones;
-fpscrMask.ide = ones;
-fpscrMask.len = ones;
-fpscrMask.fz16 = ones;
-fpscrMask.stride = ones;
-fpscrMask.rMode = ones;
-fpscrMask.fz = ones;
-fpscrMask.dn = ones;
-fpscrMask.ahp = ones;
-fpscrMask.qc = ones;
-fpscrMask.v = ones;
-fpscrMask.c = ones;
-fpscrMask.z = ones;
-fpscrMask.n = ones;
-newVal = (newVal & (uint32_t)fpscrMask) |
- (readMiscRegNoEffect(MISCREG_FPSCR) &
-  ~(uint32_t)fpscrMask);
-tc->getDecoderPtr()->as().setContext(newVal);
-}
+tc->getDecoderPtr()->as().setContext(newVal);
 break;
   case MISCREG_FPSR:
 {
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9203810..2d76143 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2199,6 +2199,7 @@
   .reset(p.fpsid)
   .allPrivileges();
 InitReg(MISCREG_FPSCR)
+  .res0(mask(14, 13) | mask(6, 5))
   .allPrivileges();
 InitReg(MISCREG_MVFR1)
   .reset([] () {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Gerrit-Change-Number: 70565
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Extend SCTLR to be 64-bit wide
..

arch-arm: Extend SCTLR to be 64-bit wide

In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide

Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70566
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index e6f7e40..c139f1a 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -371,7 +371,7 @@
 Bitfield<0> ns;
 EndBitUnion(SCR)

-BitUnion32(SCTLR)
+BitUnion64(SCTLR)
 Bitfield<31>   enia;// ARMv8.3 PAuth
 Bitfield<30>   enib;// ARMv8.3 PAuth
 Bitfield<30>   te;  // Thumb Exception Enable (AArch32 only)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Gerrit-Change-Number: 70566
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

EG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 7a06da1..960c2be 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,6 +2273,10 @@

 // AArch32 CP14 registers
 InitReg(MISCREG_DBGDIDR)
+  /* For now just implement the version number.
+   * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
+   */
+  .reset(0x5 << 16)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDSCRint)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
@@ -2514,6 +2518,34 @@
   .reset(midr)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CTR)
+  .reset([system=p.system](){
+  //all caches have the same line size in gem5
+  //4 byte words in ARM
+  unsigned line_size_words =
+  system->cacheLineSize() / 4;
+  unsigned log2_line_size_words = 0;
+
+  while (line_size_words >>= 1) {
+  ++log2_line_size_words;
+  }
+
+  CTR ctr = 0;
+  //log2 of minimun i-cache line size (words)
+  ctr.iCacheLineSize = log2_line_size_words;
+  //b11 - gem5 uses pipt
+  ctr.l1IndexPolicy = 0x3;
+  //log2 of minimum d-cache line size (words)
+  ctr.dCacheLineSize = log2_line_size_words;
+  //log2 of max reservation size (words)
+  ctr.erg = log2_line_size_words;
+  //log2 of max writeback size (words)
+  ctr.cwg = log2_line_size_words;
+  //b100 - gem5 format is ARMv7
+  ctr.format = 0x4;
+
+  return ctr;
+  }())
+  .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TCMTR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2528,8 +2560,20 @@
   .warnNotFail()
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0)
+  .reset(0x0031) // !ThumbEE | !Jazelle | Thumb | ARM
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR1)
+  .reset([release=release,system=system](){
+  // Timer | Virti | !M Profile | TrustZone | ARMv4
+  bool have_timer = (system && system->getGenericTimer() !=  
nullptr);

+  return 0x0001 |
+  (release->has(ArmExtension::SECURITY) ?
+  0x0010 : 0x0) |
+  (release->has(ArmExtension::VIRTUALIZATION) ?
+  0x1000 : 0x0) |
+  (have_timer ? 0x0001 : 0x0);
+  }())
+  .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_DFR0)
   .reset(p.pmu ? 0x0300 : 0)
@@ -3772,9 +3816,13 @@
   pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
   return pfr0_el1;
   }())
+  .unserialize(0)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64PFR1_EL1)
+  .reset(release->has(ArmExtension::FEAT_SME) ?
+  0x1 << 24 : 0)
+  .unserialize(0)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64DFR0_EL1)
@@ -3919,6 +3967,7 @@
   .reads(1)
   .mapsTo(MISCREG_CTR);
 InitReg(MISCREG_DCZID_EL0)
+  .reset(0x04) // DC ZVA clear 64-byte chunks
   .reads(1);
 InitReg(MISCREG_VPIDR_EL2)
   .hyp().mon()

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Gerrit-Change-Number: 70558
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

EL1, val);
 break;
-  case MISCREG_DBGBCR1_EL1:
-selfDebug->updateDBGBCR(1, val);
-break;
-  case MISCREG_DBGBCR2_EL1:
-selfDebug->updateDBGBCR(2, val);
-break;
-  case MISCREG_DBGBCR3_EL1:
-selfDebug->updateDBGBCR(3, val);
-break;
-  case MISCREG_DBGBCR4_EL1:
-selfDebug->updateDBGBCR(4, val);
-break;
-  case MISCREG_DBGBCR5_EL1:
-selfDebug->updateDBGBCR(5, val);
-break;
-  case MISCREG_DBGBCR6_EL1:
-selfDebug->updateDBGBCR(6, val);
-break;
-  case MISCREG_DBGBCR7_EL1:
-selfDebug->updateDBGBCR(7, val);
-break;
-  case MISCREG_DBGBCR8_EL1:
-selfDebug->updateDBGBCR(8, val);
-break;
-  case MISCREG_DBGBCR9_EL1:
-selfDebug->updateDBGBCR(9, val);
-break;
-  case MISCREG_DBGBCR10_EL1:
-selfDebug->updateDBGBCR(10, val);
-break;
-  case MISCREG_DBGBCR11_EL1:
-selfDebug->updateDBGBCR(11, val);
-break;
-  case MISCREG_DBGBCR12_EL1:
-selfDebug->updateDBGBCR(12, val);
-break;
-  case MISCREG_DBGBCR13_EL1:
-selfDebug->updateDBGBCR(13, val);
-break;
-  case MISCREG_DBGBCR14_EL1:
-selfDebug->updateDBGBCR(14, val);
-break;
-  case MISCREG_DBGBCR15_EL1:
-selfDebug->updateDBGBCR(15, val);
-break;
-  case MISCREG_DBGWCR0_EL1:
-selfDebug->updateDBGWCR(0, val);
-break;
-  case MISCREG_DBGWCR1_EL1:
-selfDebug->updateDBGWCR(1, val);
-break;
-  case MISCREG_DBGWCR2_EL1:
-selfDebug->updateDBGWCR(2, val);
-break;
-  case MISCREG_DBGWCR3_EL1:
-selfDebug->updateDBGWCR(3, val);
-break;
-  case MISCREG_DBGWCR4_EL1:
-selfDebug->updateDBGWCR(4, val);
-break;
-  case MISCREG_DBGWCR5_EL1:
-selfDebug->updateDBGWCR(5, val);
-break;
-  case MISCREG_DBGWCR6_EL1:
-selfDebug->updateDBGWCR(6, val);
-break;
-  case MISCREG_DBGWCR7_EL1:
-selfDebug->updateDBGWCR(7, val);
-break;
-  case MISCREG_DBGWCR8_EL1:
-selfDebug->updateDBGWCR(8, val);
-break;
-  case MISCREG_DBGWCR9_EL1:
-selfDebug->updateDBGWCR(9, val);
-break;
-  case MISCREG_DBGWCR10_EL1:
-selfDebug->updateDBGWCR(10, val);
-break;
-  case MISCREG_DBGWCR11_EL1:
-selfDebug->updateDBGWCR(11, val);
-break;
-  case MISCREG_DBGWCR12_EL1:
-selfDebug->updateDBGWCR(12, val);
-break;
-  case MISCREG_DBGWCR13_EL1:
-selfDebug->updateDBGWCR(13, val);
-break;
-  case MISCREG_DBGWCR14_EL1:
-selfDebug->updateDBGWCR(14, val);
-break;
-  case MISCREG_DBGWCR15_EL1:
-selfDebug->updateDBGWCR(15, val);
+  case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1:
+selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val);
 break;
   case MISCREG_IFSR:
 {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6
Gerrit-Change-Number: 70562
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Remove unnecessary case in ISA::readMiscReg
..

arch-arm: Remove unnecessary case in ISA::readMiscReg

Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70564
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 0 insertions(+), 2 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ab6e3f7..83df61f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -567,8 +567,6 @@
 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
 return l2ctlr;
 }
-  case MISCREG_DBGDSCRint:
-return readMiscRegNoEffect(MISCREG_DBGDSCRint);
   case MISCREG_ISR:
   case MISCREG_ISR_EL1:
 {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Gerrit-Change-Number: 70564
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield

2023-05-16 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email )


Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield
..

arch-arm: Fix position of AA64ISAR0.AES bitfield

The bitfield was wrongly [1] placed in the LSBs of the register

[1]: https://developer.arm.com/documentation/ddi0601/2022-03/\
AArch64-Registers/\
ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0

Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70637
Reviewed-by: Richard Cooper 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index e446ce5..e6f7e40 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -123,7 +123,7 @@
 Bitfield<19, 16> crc32;
 Bitfield<15, 12> sha2;
 Bitfield<11, 8> sha1;
-Bitfield<3, 0> aes;
+Bitfield<7, 4> aes;
 EndBitUnion(AA64ISAR0)

 BitUnion64(AA64ISAR1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Gerrit-Change-Number: 70637
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix position of AA64ISAR0.AES bitfield

2023-05-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email )



Change subject: arch-arm: Fix position of AA64ISAR0.AES bitfield
..

arch-arm: Fix position of AA64ISAR0.AES bitfield

The bitfield was wrongly [1] placed in the LSBs of the register

[1]: https://developer.arm.com/documentation/ddi0601/2022-03/\
AArch64-Registers/\
ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0

Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index e446ce5..e6f7e40 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -123,7 +123,7 @@
 Bitfield<19, 16> crc32;
 Bitfield<15, 12> sha2;
 Bitfield<11, 8> sha1;
-Bitfield<3, 0> aes;
+Bitfield<7, 4> aes;
 EndBitUnion(AA64ISAR0)

 BitUnion64(AA64ISAR1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70637?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Gerrit-Change-Number: 70637
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_TLBIOS

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev

 MISCREG_TLBI_VMALLE1,
 MISCREG_TLBI_VAE1_Xt,
 MISCREG_TLBI_ASIDE1_Xt,
@@ -693,12 +699,19 @@
 MISCREG_TLBI_VALE1_Xt,
 MISCREG_TLBI_VAALE1_Xt,
 MISCREG_TLBI_IPAS2E1IS_Xt,
+MISCREG_TLBI_IPAS2E1OS_Xt,
 MISCREG_TLBI_IPAS2LE1IS_Xt,
+MISCREG_TLBI_IPAS2LE1OS_Xt,
 MISCREG_TLBI_ALLE2IS,
+MISCREG_TLBI_ALLE2OS,
 MISCREG_TLBI_VAE2IS_Xt,
+MISCREG_TLBI_VAE2OS_Xt,
 MISCREG_TLBI_ALLE1IS,
+MISCREG_TLBI_ALLE1OS,
 MISCREG_TLBI_VALE2IS_Xt,
+MISCREG_TLBI_VALE2OS_Xt,
 MISCREG_TLBI_VMALLS12E1IS,
+MISCREG_TLBI_VMALLS12E1OS,
 MISCREG_TLBI_IPAS2E1_Xt,
 MISCREG_TLBI_IPAS2LE1_Xt,
 MISCREG_TLBI_ALLE2,
@@ -707,8 +720,11 @@
 MISCREG_TLBI_VALE2_Xt,
 MISCREG_TLBI_VMALLS12E1,
 MISCREG_TLBI_ALLE3IS,
+MISCREG_TLBI_ALLE3OS,
 MISCREG_TLBI_VAE3IS_Xt,
+MISCREG_TLBI_VAE3OS_Xt,
 MISCREG_TLBI_VALE3IS_Xt,
+MISCREG_TLBI_VALE3OS_Xt,
 MISCREG_TLBI_ALLE3,
 MISCREG_TLBI_VAE3_Xt,
 MISCREG_TLBI_VALE3_Xt,
@@ -2344,11 +2360,17 @@
 "at_s1e3r_xt",
 "at_s1e3w_xt",
 "tlbi_vmalle1is",
+"tlbi_vmalle1os",
 "tlbi_vae1is_xt",
+"tlbi_vae1os_xt",
 "tlbi_aside1is_xt",
+"tlbi_aside1os_xt",
 "tlbi_vaae1is_xt",
+"tlbi_vaae1os_xt",
 "tlbi_vale1is_xt",
+"tlbi_vale1os_xt",
 "tlbi_vaale1is_xt",
+"tlbi_vaale1os_xt",
 "tlbi_vmalle1",
 "tlbi_vae1_xt",
 "tlbi_aside1_xt",
@@ -2356,12 +2378,19 @@
 "tlbi_vale1_xt",
 "tlbi_vaale1_xt",
 "tlbi_ipas2e1is_xt",
+"tlbi_ipas2e1os_xt",
 "tlbi_ipas2le1is_xt",
+"tlbi_ipas2le1os_xt",
 "tlbi_alle2is",
+"tlbi_alle2os",
 "tlbi_vae2is_xt",
+"tlbi_vae2os_xt",
 "tlbi_alle1is",
+"tlbi_alle1os",
 "tlbi_vale2is_xt",
+"tlbi_vale2os_xt",
 "tlbi_vmalls12e1is",
+"tlbi_vmalls12e1os",
 "tlbi_ipas2e1_xt",
 "tlbi_ipas2le1_xt",
 "tlbi_alle2",
@@ -2370,8 +2399,11 @@
 "tlbi_vale2_xt",
 "tlbi_vmalls12e1",
 "tlbi_alle3is",
+"tlbi_alle3os",
 "tlbi_vae3is_xt",
+"tlbi_vae3os_xt",
 "tlbi_vale3is_xt",
+"tlbi_vale3os_xt",
 "tlbi_alle3",
 "tlbi_vae3_xt",
 "tlbi_vale3_xt",

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70567?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3
Gerrit-Change-Number: 70567
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement RES0/RES1 with miscreg specifiers

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev

  SVCR svcr = miscRegs[MISCREG_SVCR];
-SVCR newSvcr = newVal;
-
-// Don't allow other bits to be set
-svcr.sm = newSvcr.sm;
-svcr.za = newSvcr.za;
-newVal = svcr;
-}
-break;
-  case MISCREG_SMPRI_EL1:
-// Only the bottom 4 bits are settable
-newVal = newVal & 0xF;
-break;
   case MISCREG_AT_S1E1R_Xt:
 addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
 return;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6f918b2..9203810 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2662,6 +2662,7 @@
   .reset(midr)
   .hyp().monNonSecure();
 InitReg(MISCREG_VMPIDR)
+  .res1(mask(31, 31))
   .hyp().monNonSecure();
 InitReg(MISCREG_SCTLR)
   .banked()
@@ -2739,13 +2740,17 @@
   .hyp().monNonSecure();
 InitReg(MISCREG_HCR)
   .hyp().monNonSecure()
-  .res0(0x9000);
+  .res0(release->has(ArmExtension::VIRTUALIZATION) ?
+  0x9000 : mask(31, 0));
 InitReg(MISCREG_HCR2)
   .hyp().monNonSecure()
-  .res0(0xffa9ff8c);
+  .res0(release->has(ArmExtension::VIRTUALIZATION) ?
+  0xffa9ff8c : mask(31, 0));
 InitReg(MISCREG_HDCR)
   .hyp().monNonSecure();
 InitReg(MISCREG_HCPTR)
+  .res0(mask(29, 21) | mask(19, 16) | mask(14, 14))
+  .res1(mask(13, 12) | mask(9, 0))
   .hyp().monNonSecure();
 InitReg(MISCREG_HSTR)
   .hyp().monNonSecure();
@@ -2794,7 +2799,8 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_DFSR)
-  .banked();
+  .banked()
+  .res0(mask(31, 14) | mask(8, 8));
 InitReg(MISCREG_DFSR_NS)
   .bankedChild()
   .privSecure(!aarch32EL3)
@@ -2803,7 +2809,8 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_IFSR)
-  .banked();
+  .banked()
+  .res0(mask(31, 13) | mask(11, 11) | mask(8, 6));
 InitReg(MISCREG_IFSR_NS)
   .bankedChild()
   .privSecure(!aarch32EL3)
@@ -3118,6 +3125,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_AMAIR0)
+  .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
   .banked();
 InitReg(MISCREG_AMAIR0_NS)
   .bankedChild()
@@ -3127,6 +3135,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_AMAIR1)
+  .res0(release->has(ArmExtension::LPAE) ? 0 : mask(31, 0))
   .banked();
 InitReg(MISCREG_AMAIR1_NS)
   .bankedChild()
@@ -3976,6 +3985,8 @@
   .mapsTo(MISCREG_VPIDR);
 InitReg(MISCREG_VMPIDR_EL2)
   .hyp().mon()
+  .res0(mask(63, 40) | mask(29, 25))
+  .res1(mask(31, 31))
   .mapsTo(MISCREG_VMPIDR);
 InitReg(MISCREG_SCTLR_EL1)
   .allPrivileges().exceptUserMode()
@@ -5263,6 +5274,12 @@
 }())
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SVCR)
+.res0([](){
+SVCR svcr_mask = 0;
+svcr_mask.sm = 1;
+svcr_mask.za = 1;
+return ~svcr_mask;
+}())
 .allPrivileges();
 InitReg(MISCREG_SMIDR_EL1)
 .reset([](){
@@ -5274,6 +5291,7 @@
 }())
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
+.res0(mask(63, 4))
 .allPrivileges().exceptUserMode().reads(1);
 InitReg(MISCREG_SMPRIMAP_EL2)
 .hyp().mon();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70563?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894
Gerrit-Change-Number: 70563
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Provide default mask for raz/rao helpers

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email

to review the following change.


Change subject: arch-arm: Provide default mask for raz/rao helpers
..

arch-arm: Provide default mask for raz/rao helpers

Rather than forcing raz registers to write something like:

.raz(uint64_t(-1))

we provide a shorter version where if
no bitmask is specified we assume the entire register is
raz/rao. This won't be probably used by rao but I
am striving for symmetry and providing a default won't
probably hurt

Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.hh
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 3a32623..abbd1c6 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1249,13 +1249,13 @@
 return *this;
 }
 chain
-raz(uint64_t mask) const
+raz(uint64_t mask = (uint64_t)-1) const
 {
 entry._raz  = mask;
 return *this;
 }
 chain
-rao(uint64_t mask) const
+rao(uint64_t mask = (uint64_t)-1) const
 {
 entry._rao  = mask;
 return *this;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70559?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Gerrit-Change-Number: 70559
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email

to review the following change.


Change subject: arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug  
arch

..

arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch

Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.cc
1 file changed, 1 insertion(+), 4 deletions(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 6c5a9dd..6f918b2 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,10 +2273,7 @@

 // AArch32 CP14 registers
 InitReg(MISCREG_DBGDIDR)
-  /* For now just implement the version number.
-   * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
-   */
-  .reset(0x5 << 16)
+  .reset(0x6 << 16) // Armv8 Debug architecture
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDSCRint)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70561?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Gerrit-Change-Number: 70561
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add UNSERIALIZE flag to address cpt compatibility

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email

to review the following change.


Change subject: arch-arm: Add UNSERIALIZE flag to address cpt compatibility
..

arch-arm: Add UNSERIALIZE flag to address cpt compatibility

This patch is adding the MISCREG_UNSERIALIZE flag to expose
the user to the following checkpoint compatibility problem:

What happens when a checkpoint is restored with a different
architectural configuration?

The current behaviour is to silently restore the checkpoint
and to populate the ISA registers accordingly. However some of
these restored values will be used and some of them will
be actually discarded.

For example the value of the MISCREG_ID_AA64ISAR0_EL1 register
(initially configured at construction time [1]) will be overwritten by
the checkpointed value in ISA::unserialize (checkpointed params win over
current params). On the other hand we "discard" the checkpointed value
for registers handled in the ISA::readMiscReg method (not accessing the
storage) like MISCREG_ID_AA64PFR0_EL1 [2] (current params win over
checkpointed params).

In other words some registers will be unserialized while some others
will discard the checkpointed value in favour of the current
configuration setup. This categorization is currently implicit and it
ultimately depends on whether or not a register read access its storage
(see MISCREG_ID_AA64PFR0_EL1 above).

With this patch we formalize this distinction. We allow the developer to
be explict on which register should not be unserialized and should
instead use the new simulation parameters.

If there is a mismatch between the reset value of such register and
the checkpointed one, we warn the user and we undo the unserialization
for such register.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L437
[2]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L1019

Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.hh
2 files changed, 20 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ffd9cfc..f55235d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1879,6 +1879,18 @@
 {
 DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
 UNSERIALIZE_MAPPING(miscRegs, miscRegName, NUM_PHYS_MISCREGS);
+
+for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
+if (!lookUpMiscReg[idx].info[MISCREG_UNSERIALIZE] &&
+miscRegs[idx] != lookUpMiscReg[idx].reset()) {
+warn("Checkpoint value for register %s does not match "
+ "current configuration (checkpointed: %#x, current: %#x)",
+ miscRegName[idx], miscRegs[idx],
+ lookUpMiscReg[idx].reset());
+miscRegs[idx] = lookUpMiscReg[idx].reset();
+}
+}
+
 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
 updateRegMap(tmp_cpsr);
 }
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 265a697..3a32623 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1125,6 +1125,7 @@
 MISCREG_IMPLEMENTED,
 MISCREG_UNVERIFIABLE,   // Does the value change on every read  
(e.g. a

 // arch generic counter)
+MISCREG_UNSERIALIZE,// Should the checkpointed value be  
restored?

 MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
 // tells whether the instruction should  
raise a

 // warning or fail
@@ -1277,6 +1278,12 @@
 return *this;
 }
 chain
+unserialize(bool v = true) const
+{
+entry.info[MISCREG_UNSERIALIZE] = v;
+return *this;
+}
+chain
 warnNotFail(bool v = true) const
 {
 entry.info[MISCREG_WARN_NOT_FAIL] = v;
@@ -1595,7 +1602,7 @@
   : entry(e)
 {
 // force unimplemented registers to be thusly declared
-implemented(1);
+implemented(1).unserialize(1);
 }
 };


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70557?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Gerrit-Change-Number: 70557
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
g

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCTLR to be 64-bit wide

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email

to review the following change.


Change subject: arch-arm: Extend SCTLR to be 64-bit wide
..

arch-arm: Extend SCTLR to be 64-bit wide

In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide

Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index e446ce5..7e7ff67 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -371,7 +371,7 @@
 Bitfield<0> ns;
 EndBitUnion(SCR)

-BitUnion32(SCTLR)
+BitUnion64(SCTLR)
 Bitfield<31>   enia;// ARMv8.3 PAuth
 Bitfield<30>   enib;// ARMv8.3 PAuth
 Bitfield<30>   te;  // Thumb Exception Enable (AArch32 only)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70566?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Gerrit-Change-Number: 70566
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move RO values from ISA::read to the reset field

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev

tReg(MISCREG_DBGDIDR)
+  /* For now just implement the version number.
+   * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
+   */
+  .reset(0x5 << 16)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
 InitReg(MISCREG_DBGDSCRint)
   .allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
@@ -2514,6 +2518,34 @@
   .reset(midr)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CTR)
+  .reset([system=p.system](){
+  //all caches have the same line size in gem5
+  //4 byte words in ARM
+  unsigned line_size_words =
+  system->cacheLineSize() / 4;
+  unsigned log2_line_size_words = 0;
+
+  while (line_size_words >>= 1) {
+  ++log2_line_size_words;
+  }
+
+  CTR ctr = 0;
+  //log2 of minimun i-cache line size (words)
+  ctr.iCacheLineSize = log2_line_size_words;
+  //b11 - gem5 uses pipt
+  ctr.l1IndexPolicy = 0x3;
+  //log2 of minimum d-cache line size (words)
+  ctr.dCacheLineSize = log2_line_size_words;
+  //log2 of max reservation size (words)
+  ctr.erg = log2_line_size_words;
+  //log2 of max writeback size (words)
+  ctr.cwg = log2_line_size_words;
+  //b100 - gem5 format is ARMv7
+  ctr.format = 0x4;
+
+  return ctr;
+  }())
+  .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TCMTR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2528,8 +2560,20 @@
   .warnNotFail()
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR0)
+  .reset(0x0031) // !ThumbEE | !Jazelle | Thumb | ARM
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_PFR1)
+  .reset([release=release,system=system](){
+  // Timer | Virti | !M Profile | TrustZone | ARMv4
+  bool have_timer = (system && system->getGenericTimer() !=  
nullptr);

+  return 0x0001 |
+  (release->has(ArmExtension::SECURITY) ?
+  0x0010 : 0x0) |
+  (release->has(ArmExtension::VIRTUALIZATION) ?
+  0x1000 : 0x0) |
+  (have_timer ? 0x0001 : 0x0);
+  }())
+  .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_DFR0)
   .reset(p.pmu ? 0x0300 : 0)
@@ -3772,9 +3816,13 @@
   pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
   return pfr0_el1;
   }())
+  .unserialize(0)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64PFR1_EL1)
+  .reset(release->has(ArmExtension::FEAT_SME) ?
+  0x1 << 24 : 0)
+  .unserialize(0)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AA64DFR0_EL1)
@@ -3919,6 +3967,7 @@
   .reads(1)
   .mapsTo(MISCREG_CTR);
 InitReg(MISCREG_DCZID_EL0)
+  .reset(0x04) // DC ZVA clear 64-byte chunks
   .reads(1);
 InitReg(MISCREG_VPIDR_EL2)
   .hyp().mon()

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Gerrit-Change-Number: 70558
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Simplify FPSCR writes

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email

to review the following change.


Change subject: arch-arm: Simplify FPSCR writes
..

arch-arm: Simplify FPSCR writes

The old logic was setting up a mask which was covering pretty much
the entire register, except for the FPSCR[14:13] and FPSCR[6:5]
register fields. Those RES0 fields were treated as WI.
We simplify this by explicitly marking them as RES0 at construction
time

Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 32 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 83df61f..9c8e282 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -815,38 +815,7 @@
 return;

   case MISCREG_FPSCR:
-{
-const uint32_t ones = (uint32_t)(-1);
-FPSCR fpscrMask = 0;
-fpscrMask.ioc = ones;
-fpscrMask.dzc = ones;
-fpscrMask.ofc = ones;
-fpscrMask.ufc = ones;
-fpscrMask.ixc = ones;
-fpscrMask.idc = ones;
-fpscrMask.ioe = ones;
-fpscrMask.dze = ones;
-fpscrMask.ofe = ones;
-fpscrMask.ufe = ones;
-fpscrMask.ixe = ones;
-fpscrMask.ide = ones;
-fpscrMask.len = ones;
-fpscrMask.fz16 = ones;
-fpscrMask.stride = ones;
-fpscrMask.rMode = ones;
-fpscrMask.fz = ones;
-fpscrMask.dn = ones;
-fpscrMask.ahp = ones;
-fpscrMask.qc = ones;
-fpscrMask.v = ones;
-fpscrMask.c = ones;
-fpscrMask.z = ones;
-fpscrMask.n = ones;
-newVal = (newVal & (uint32_t)fpscrMask) |
- (readMiscRegNoEffect(MISCREG_FPSCR) &
-  ~(uint32_t)fpscrMask);
-tc->getDecoderPtr()->as().setContext(newVal);
-}
+tc->getDecoderPtr()->as().setContext(newVal);
 break;
   case MISCREG_FPSR:
 {
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9203810..2d76143 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2199,6 +2199,7 @@
   .reset(p.fpsid)
   .allPrivileges();
 InitReg(MISCREG_FPSCR)
+  .res0(mask(14, 13) | mask(6, 5))
   .allPrivileges();
 InitReg(MISCREG_MVFR1)
   .reset([] () {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70565?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Gerrit-Change-Number: 70565
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Remove unnecessary case in ISA::readMiscReg

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email

to review the following change.


Change subject: arch-arm: Remove unnecessary case in ISA::readMiscReg
..

arch-arm: Remove unnecessary case in ISA::readMiscReg

Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
1 file changed, 0 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ab6e3f7..83df61f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -567,8 +567,6 @@
 l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
 return l2ctlr;
 }
-  case MISCREG_DBGDSCRint:
-return readMiscRegNoEffect(MISCREG_DBGDSCRint);
   case MISCREG_ISR:
   case MISCREG_ISR_EL1:
 {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70564?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Gerrit-Change-Number: 70564
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Implement RAZ/WI with raz specifier

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email

to review the following change.


Change subject: arch-arm: Implement RAZ/WI with raz specifier
..

arch-arm: Implement RAZ/WI with raz specifier

Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 5 insertions(+), 6 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 14349b1..7df8978 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -470,12 +470,6 @@
 return readMiscRegNoEffect(idx);
 }
 break;
-  case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
-  case MISCREG_AIDR:  // AUX ID set to 0
-  case MISCREG_TCMTR: // No TCM's
-return 0;

   case MISCREG_CLIDR:
 warn_once("The clidr register always reports 0 caches.\n");
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 960c2be..6c5a9dd 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2505,12 +2505,15 @@
   .unimplemented()
   .allPrivileges();
 InitReg(MISCREG_JIDR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_TEEHBR)
   .allPrivileges();
 InitReg(MISCREG_JOSCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();
 InitReg(MISCREG_JMCR)
+  .raz() // Jazelle trivial implementation, RAZ/WI
   .allPrivileges();

 // AArch32 CP15 registers
@@ -2548,6 +2551,7 @@
   .unserialize(0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TCMTR)
+  .raz() // No TCM's
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TLBTR)
   .reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@
 InitReg(MISCREG_CLIDR)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_AIDR)
+  .raz() // AUX ID set to 0
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CSSELR)
   .banked();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Gerrit-Change-Number: 70560
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Group self hosted debug writes in ISA switch

2023-05-12 Thread Giacomo Travaglini (Gerrit) via gem5-dev

MISCREG_DBGBCR3_EL1:
-selfDebug->updateDBGBCR(3, val);
-break;
-  case MISCREG_DBGBCR4_EL1:
-selfDebug->updateDBGBCR(4, val);
-break;
-  case MISCREG_DBGBCR5_EL1:
-selfDebug->updateDBGBCR(5, val);
-break;
-  case MISCREG_DBGBCR6_EL1:
-selfDebug->updateDBGBCR(6, val);
-break;
-  case MISCREG_DBGBCR7_EL1:
-selfDebug->updateDBGBCR(7, val);
-break;
-  case MISCREG_DBGBCR8_EL1:
-selfDebug->updateDBGBCR(8, val);
-break;
-  case MISCREG_DBGBCR9_EL1:
-selfDebug->updateDBGBCR(9, val);
-break;
-  case MISCREG_DBGBCR10_EL1:
-selfDebug->updateDBGBCR(10, val);
-break;
-  case MISCREG_DBGBCR11_EL1:
-selfDebug->updateDBGBCR(11, val);
-break;
-  case MISCREG_DBGBCR12_EL1:
-selfDebug->updateDBGBCR(12, val);
-break;
-  case MISCREG_DBGBCR13_EL1:
-selfDebug->updateDBGBCR(13, val);
-break;
-  case MISCREG_DBGBCR14_EL1:
-selfDebug->updateDBGBCR(14, val);
-break;
-  case MISCREG_DBGBCR15_EL1:
-selfDebug->updateDBGBCR(15, val);
-break;
-  case MISCREG_DBGWCR0_EL1:
-selfDebug->updateDBGWCR(0, val);
-break;
-  case MISCREG_DBGWCR1_EL1:
-selfDebug->updateDBGWCR(1, val);
-break;
-  case MISCREG_DBGWCR2_EL1:
-selfDebug->updateDBGWCR(2, val);
-break;
-  case MISCREG_DBGWCR3_EL1:
-selfDebug->updateDBGWCR(3, val);
-break;
-  case MISCREG_DBGWCR4_EL1:
-selfDebug->updateDBGWCR(4, val);
-break;
-  case MISCREG_DBGWCR5_EL1:
-selfDebug->updateDBGWCR(5, val);
-break;
-  case MISCREG_DBGWCR6_EL1:
-selfDebug->updateDBGWCR(6, val);
-break;
-  case MISCREG_DBGWCR7_EL1:
-selfDebug->updateDBGWCR(7, val);
-break;
-  case MISCREG_DBGWCR8_EL1:
-selfDebug->updateDBGWCR(8, val);
-break;
-  case MISCREG_DBGWCR9_EL1:
-selfDebug->updateDBGWCR(9, val);
-break;
-  case MISCREG_DBGWCR10_EL1:
-selfDebug->updateDBGWCR(10, val);
-break;
-  case MISCREG_DBGWCR11_EL1:
-selfDebug->updateDBGWCR(11, val);
-break;
-  case MISCREG_DBGWCR12_EL1:
-selfDebug->updateDBGWCR(12, val);
-break;
-  case MISCREG_DBGWCR13_EL1:
-selfDebug->updateDBGWCR(13, val);
-break;
-  case MISCREG_DBGWCR14_EL1:
-selfDebug->updateDBGWCR(14, val);
-break;
-  case MISCREG_DBGWCR15_EL1:
-selfDebug->updateDBGWCR(15, val);
+  case MISCREG_DBGWCR0_EL1 ... MISCREG_DBGWCR15_EL1:
+selfDebug->updateDBGWCR(idx - MISCREG_DBGWCR0_EL1, val);
 break;
   case MISCREG_IFSR:
 {

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70562?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6
Gerrit-Change-Number: 70562
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

nitReg(MISCREG_RVBAR_EL3)
+  .reset(FullSystem && system->highestEL() == EL3 ?
+  system->resetAddr() : 0)
   .mon().writes(0);
 InitReg(MISCREG_RMR_EL3)
   .mon();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70470?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Gerrit-Change-Number: 70470
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

most
+// representative value.
+SMCR smcr_el1 = 0;
+smcr_el1.fa64 = 1;
+smcr_el1.len = smeVL - 1;
+return smcr_el1;
+}())
 .allPrivileges().exceptUserMode();
 InitReg(MISCREG_TPIDR2_EL0)
 .allPrivileges();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Gerrit-Change-Number: 70469
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

4MMFR2 mmfr2_el1 = p.id_aa64mmfr2_el1;
+mmfr2_el1.uao = release->has(ArmExtension::FEAT_UAO) ? 0x1 : 0x0;
+mmfr2_el1.varange = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_AA64MMFR2_EL1] = mmfr2_el1;
 }

 void
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index f5e2502..7cff4ca 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2497,6 +2497,7 @@
 InitReg(MISCREG_ID_PFR1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_DFR0)
+  .reset(p.pmu ? 0x0300 : 0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AFR0)
   .allPrivileges().exceptUserMode().writes(0);
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 9af5337..e446ce5 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -118,6 +118,7 @@
 Bitfield<39, 36> sm3;
 Bitfield<35, 32> sha3;
 Bitfield<31, 28> rdm;
+Bitfield<27, 24> tme;
 Bitfield<23, 20> atomic;
 Bitfield<19, 16> crc32;
 Bitfield<15, 12> sha2;
@@ -202,6 +203,17 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64SMFR0)
+Bitfield<63> fa64;
+Bitfield<59, 56> smEver;
+Bitfield<55, 52> i16i64;
+Bitfield<48> f64f64;
+Bitfield<39, 36> i8i32;
+Bitfield<35> f16f32;
+Bitfield<34> b16f32;
+Bitfield<32> f32f32;
+EndBitUnion(AA64SMFR0)
+
 BitUnion32(HDCR)
 Bitfield<27>   tdcc;
 Bitfield<11>   tdra;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13
Gerrit-Change-Number: 70468
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: VMPIDR_EL2 can be used in secure mode as well
..

arch-arm: VMPIDR_EL2 can be used in secure mode as well

This was some old code still assuming EL2 is not implemented in secure
mode. This is wrong since the introduction of FEAT_SEL2 in gem5

Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70471
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6764569..05d1cab 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -139,8 +139,6 @@
 {
 const ExceptionLevel current_el = currEL(tc);

-const bool is_secure = isSecureBelowEL3(tc);
-
 switch (current_el) {
   case EL0:
 // Note: in MsrMrs instruction we read the register value before
@@ -150,7 +148,7 @@
 warn_once("Trying to read MPIDR at EL0\n");
 [[fallthrough]];
   case EL1:
-if (ArmSystem::haveEL(tc, EL2) && !is_secure)
+if (EL2Enabled(tc))
 return tc->readMiscReg(MISCREG_VMPIDR_EL2);
 else
 return getMPIDR(arm_sys, tc);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Gerrit-Change-Number: 70471
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

  .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_MMFR4)
+  .reset(p.id_mmfr4)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR0)
+  .reset(p.id_isar0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR1)
+  .reset(p.id_isar1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR2)
+  .reset(p.id_isar2)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR3)
+  .reset(p.id_isar3)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR4)
+  .reset(p.id_isar4)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR5)
+  .reset([p,release=release] () {
+ISAR5 isar5 = p.id_isar5;
+if (release->has(ArmExtension::CRYPTO)) {
+isar5.crc32 = 1;
+isar5.sha2 = 1;
+isar5.sha1 = 1;
+isar5.aes = 2;
+} else {
+isar5.crc32 = 0;
+isar5.sha2 = 0;
+isar5.sha1 = 0;
+isar5.aes = 0;
+}
+isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
+return isar5;
+  }())
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR6)
+  .reset([p,release=release] () {
+ISAR6 isar6 = p.id_isar6;
+isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
+return isar6;
+  }())
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CCSIDR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2527,6 +2572,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_VPIDR)
+  .reset(midr)
   .hyp().monNonSecure();
 InitReg(MISCREG_VMPIDR)
   .hyp().monNonSecure();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6
Gerrit-Change-Number: 70467
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email )


Change subject: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version
..

arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version

Signed-off-by: Giacomo Travaglini 
Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70460
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/regs/misc.cc
1 file changed, 4 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index e984164..4221a15 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3579,10 +3579,12 @@
   .mapsTo(MISCREG_ID_ISAR6);
 InitReg(MISCREG_MVFR0_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MVFR0);
 InitReg(MISCREG_MVFR1_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MVFR1);
 InitReg(MISCREG_MVFR2_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0
Gerrit-Change-Number: 70460
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email )


Change subject: arch-arm: Make MISCREGs reset value configurable
..

arch-arm: Make MISCREGs reset value configurable

Signed-off-by: Giacomo Travaglini 
Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70458
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.hh
1 file changed, 7 insertions(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index bf25ea3..69d1461 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2022 Arm Limited
+ * Copyright (c) 2010-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1231,6 +1231,12 @@
 return *this;
 }
 chain
+reset(uint64_t res_val) const
+{
+entry._reset = res_val;
+return *this;
+}
+chain
 res0(uint64_t mask) const
 {
 entry._res0 = mask;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f
Gerrit-Change-Number: 70458
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email )


Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions
..

arch-arm: Rewrite ISA::initID32 using BitUnions

Signed-off-by: Giacomo Travaglini 
Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70466
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc_types.hh
2 files changed, 39 insertions(+), 19 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a66a938..4033d0f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -280,8 +280,6 @@
 miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
 miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
 miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
-miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;

 miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
@@ -289,24 +287,25 @@
 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
 miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;

-/** MISCREG_ID_ISAR5 */
-// Crypto
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 19, 4,
-release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
-// RDM
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 27, 24,
-release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
-// FCMA
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 31, 28,
-release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+ISAR5 isar5 = p.id_isar5;
+if (release->has(ArmExtension::CRYPTO)) {
+isar5.crc32 = 1;
+isar5.sha2 = 1;
+isar5.sha1 = 1;
+isar5.aes = 2;
+} else {
+isar5.crc32 = 0;
+isar5.sha2 = 0;
+isar5.sha1 = 0;
+isar5.aes = 0;
+}
+isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_ISAR5] = isar5;

-/** ID_ISAR6 */
-miscRegs[MISCREG_ID_ISAR6] = insertBits(
-miscRegs[MISCREG_ID_ISAR6], 3, 0,
-release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
+ISAR6 isar6 = p.id_isar6;
+isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_ISAR6] = isar6;
 }

 void
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 0fe5a00..9af5337 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -75,6 +75,27 @@
 Bitfield<0> sp; // AArch64
 EndBitUnion(CPSR)

+BitUnion32(ISAR5)
+Bitfield<31, 28> vcma;
+Bitfield<27, 24> rdm;
+Bitfield<19, 16> crc32;
+Bitfield<15, 12> sha2;
+Bitfield<11, 8> sha1;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sevl;
+EndBitUnion(ISAR5)
+
+BitUnion32(ISAR6)
+Bitfield<31, 28> clrbhb;
+Bitfield<27, 24> i8mm;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> specres;
+Bitfield<15, 12> sb;
+Bitfield<11, 8> fhm;
+Bitfield<7, 4> dp;
+Bitfield<3, 0> jscvt;
+EndBitUnion(ISAR6)
+
 BitUnion64(AA64DFR0)
 Bitfield<43, 40> tracefilt;
 Bitfield<39, 36> doublelock;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Gerrit-Change-Number: 70466
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email )


Change subject: arch-arm: Map CTR_EL0 to AArch32 version
..

arch-arm: Map CTR_EL0 to AArch32 version

Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70463
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 706716e..a31b6de 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3681,7 +3681,8 @@
 InitReg(MISCREG_CTR_EL0)
   .faultRead(EL0, faultCtrEL0)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .reads(1);
+  .reads(1)
+  .mapsTo(MISCREG_CTR);
 InitReg(MISCREG_DCZID_EL0)
   .reads(1);
 InitReg(MISCREG_VPIDR_EL2)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Gerrit-Change-Number: 70463
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email )


Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset  
value

..

arch-arm: Replace 0ing of miscRegs with assignment of reset value

The reset variable in the MiscRegLUTEntry class defines the per-register
reset value. Rather than simply zeroing the misc registers we should
assign them their reset value when clearing them.

As of now the reset variable is unused so using it is functionally
equivalent of calling memset. This will however change once we start
using the reset field

Signed-off-by: Giacomo Travaglini 
Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70457
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa.cc
1 file changed, 3 insertions(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index aec8243..5a0dec5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -141,7 +141,9 @@
 }

 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
-memset(miscRegs, 0, sizeof(miscRegs));
+for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
+miscRegs[idx] = lookUpMiscReg[idx].reset();
+}

 initID32(p);


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Gerrit-Change-Number: 70457
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email )


Change subject: arch-arm: Fix read redirection for MIDR register
..

arch-arm: Fix read redirection for MIDR register

This patch is fixing read redirection for the MIDR register
in the following ways:

1) Is allowing a virtualization of the register (via VPIDR)
even in secure mode (available with FEAT_SEL2)
2) Is extending this logic to the AArch64 version (MIDR_EL1)

It is also rewriting the base logic using Armv8 terminology
(checking the EL rather than the mode as an example).

Signed-off-by: Giacomo Travaglini 
Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70464
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 65d8b97..da23e0b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -864,12 +864,11 @@
   case MISCREG_ID_AFR0: // not implemented, so alias MIDR
   case MISCREG_REVIDR:  // not implemented, so alias MIDR
   case MISCREG_MIDR:
-cpsr = readMiscRegNoEffect(MISCREG_CPSR);
-scr  = readMiscRegNoEffect(MISCREG_SCR_EL3);
-if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
-return readMiscRegNoEffect(idx);
-} else {
+  case MISCREG_MIDR_EL1:
+if (currEL() == EL1 && EL2Enabled(tc)) {
 return readMiscRegNoEffect(MISCREG_VPIDR);
+} else {
+return readMiscRegNoEffect(idx);
 }
 break;
   case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Gerrit-Change-Number: 70464
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email )


Change subject: arch-arm: Map MIDR_EL1 to AArch32 version
..

arch-arm: Map MIDR_EL1 to AArch32 version

Signed-off-by: Giacomo Travaglini 
Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70461
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b0a856e..65d8b97 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -334,7 +334,6 @@
 midr = 0x410fc0f0;

 miscRegs[MISCREG_MIDR] = midr;
-miscRegs[MISCREG_MIDR_EL1] = midr;
 miscRegs[MISCREG_VPIDR] = midr;

 miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 4221a15..000124c 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3507,7 +3507,8 @@

 // AArch64 registers (Op0=1,3);
 InitReg(MISCREG_MIDR_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_REVIDR_EL1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Gerrit-Change-Number: 70461
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

ceptUserMode();
@@ -2447,6 +2471,7 @@
 InitReg(MISCREG_TCMTR)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_TLBTR)
+  .reset(1) // Separate Instruction and Data TLBs
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_MPIDR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2870,6 +2895,19 @@
   .banked();
 InitReg(MISCREG_PRRR_NS)
   .bankedChild()
+  .reset(
+(1 << 19) | // 19
+(0 << 18) | // 18
+(0 << 17) | // 17
+(1 << 16) | // 16
+(2 << 14) | // 15:14
+(0 << 12) | // 13:12
+(2 << 10) | // 11:10
+(2 << 8)  | // 9:8
+(2 << 6)  | // 7:6
+(2 << 4)  | // 5:4
+(1 << 2)  | // 3:2
+0)
   .privSecure(!aarch32EL3)
   .nonSecure().exceptUserMode();
 InitReg(MISCREG_PRRR_S)
@@ -2888,6 +2926,22 @@
   .banked();
 InitReg(MISCREG_NMRR_NS)
   .bankedChild()
+  .reset(
+(1 << 30) | // 31:30
+(0 << 26) | // 27:26
+(0 << 24) | // 25:24
+(3 << 22) | // 23:22
+(2 << 20) | // 21:20
+(0 << 18) | // 19:18
+(0 << 16) | // 17:16
+(1 << 14) | // 15:14
+(0 << 12) | // 13:12
+(2 << 10) | // 11:10
+(0 << 8)  | // 9:8
+(3 << 6)  | // 7:6
+(2 << 4)  | // 5:4
+(0 << 2)  | // 3:2
+0)
   .privSecure(!aarch32EL3)
   .nonSecure().exceptUserMode();
 InitReg(MISCREG_NMRR_S)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec4878217c38707be4ce7d4746ff95a208b4
Gerrit-Change-Number: 70465
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email )


Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version
..

arch-arm: Map MPIDR_EL1 to AArch32 version

As of now the mapping is not actually needed:
the MPIDR and MPIDR_EL1 registes are both read using the same helper
(readMPIDR). In the future we could store the getMPIDR result in the
AArch32 version without the need to re-calculate the fix affinity
numbers

Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70462
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 000124c..706716e 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3510,7 +3510,8 @@
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MPIDR);
 InitReg(MISCREG_REVIDR_EL1)
   .faultRead(EL1, HCR_TRAP(tid1))
   .allPrivileges().exceptUserMode().writes(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Gerrit-Change-Number: 70462
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour

2023-05-11 Thread Giacomo Travaglini (Gerrit) via gem5-dev

52,7 +1751,6 @@
 "nmrr_mair1_ns",
 "nmrr_mair1_s",
 "pmxevtyper_pmccfiltr",
-"sctlr_rst",
 "sev_mailbox",
 "tlbi_needsync",


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Gerrit-Change-Number: 70459
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove clear32/64 methods

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

/public/gem5/+/70470?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Gerrit-Change-Number: 70470
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID64 using BitUnions

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

AO) ? 0x1 : 0x0;
+mmfr2_el1.lva = release->has(ArmExtension::FEAT_LVA) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_AA64MMFR2_EL1] = mmfr2_el1;
 }

 void
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index f5e2502..7cff4ca 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2497,6 +2497,7 @@
 InitReg(MISCREG_ID_PFR1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_DFR0)
+  .reset(p.pmu ? 0x0300 : 0)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_AFR0)
   .allPrivileges().exceptUserMode().writes(0);
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 9af5337..e446ce5 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -118,6 +118,7 @@
 Bitfield<39, 36> sm3;
 Bitfield<35, 32> sha3;
 Bitfield<31, 28> rdm;
+Bitfield<27, 24> tme;
 Bitfield<23, 20> atomic;
 Bitfield<19, 16> crc32;
 Bitfield<15, 12> sha2;
@@ -202,6 +203,17 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64SMFR0)
+Bitfield<63> fa64;
+Bitfield<59, 56> smEver;
+Bitfield<55, 52> i16i64;
+Bitfield<48> f64f64;
+Bitfield<39, 36> i8i32;
+Bitfield<35> f16f32;
+Bitfield<34> b16f32;
+Bitfield<32> f32f32;
+EndBitUnion(AA64SMFR0)
+
 BitUnion32(HDCR)
 Bitfield<27>   tdcc;
 Bitfield<11>   tdra;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70468?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13
Gerrit-Change-Number: 70468
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: VMPIDR_EL2 can be used in secure mode as well

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email

to review the following change.


Change subject: arch-arm: VMPIDR_EL2 can be used in secure mode as well
..

arch-arm: VMPIDR_EL2 can be used in secure mode as well

This was some old code still assuming EL2 is not implemented in secure
mode. This is wrong since the introduction of FEAT_SEL2 in gem5

Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/utility.cc
1 file changed, 1 insertion(+), 3 deletions(-)



diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 6764569..05d1cab 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -139,8 +139,6 @@
 {
 const ExceptionLevel current_el = currEL(tc);

-const bool is_secure = isSecureBelowEL3(tc);
-
 switch (current_el) {
   case EL0:
 // Note: in MsrMrs instruction we read the register value before
@@ -150,7 +148,7 @@
 warn_once("Trying to read MPIDR at EL0\n");
 [[fallthrough]];
   case EL1:
-if (ArmSystem::haveEL(tc, EL2) && !is_secure)
+if (EL2Enabled(tc))
 return tc->readMiscReg(MISCREG_VMPIDR_EL2);
 else
 return getMPIDR(arm_sys, tc);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70471?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Gerrit-Change-Number: 70471
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID64

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

4 = 1;
+smcr_el1.len = smeVL - 1;
+return smcr_el1;
+}())
 .allPrivileges().exceptUserMode();
 InitReg(MISCREG_TPIDR2_EL0)
 .allPrivileges();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70469?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Gerrit-Change-Number: 70469
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Remove ISA::initID32

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR1)
+  .reset(p.id_isar1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR2)
+  .reset(p.id_isar2)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR3)
+  .reset(p.id_isar3)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR4)
+  .reset(p.id_isar4)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR5)
+  .reset([p,release=release] () {
+ISAR5 isar5 = p.id_isar5;
+if (release->has(ArmExtension::CRYPTO)) {
+isar5.crc32 = 1;
+isar5.sha2 = 1;
+isar5.sha1 = 1;
+isar5.aes = 2;
+} else {
+isar5.crc32 = 0;
+isar5.sha2 = 0;
+isar5.sha1 = 0;
+isar5.aes = 0;
+}
+isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
+return isar5;
+  }())
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_ID_ISAR6)
+  .reset([p,release=release] () {
+ISAR6 isar6 = p.id_isar6;
+isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
+return isar6;
+  }())
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_CCSIDR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2527,6 +2572,7 @@
   .bankedChild()
   .secure().exceptUserMode();
 InitReg(MISCREG_VPIDR)
+  .reset(midr)
   .hyp().monNonSecure();
 InitReg(MISCREG_VMPIDR)
   .hyp().monNonSecure();

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70467?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6
Gerrit-Change-Number: 70467
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MIDR_EL1 to AArch32 version

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email

to review the following change.


Change subject: arch-arm: Map MIDR_EL1 to AArch32 version
..

arch-arm: Map MIDR_EL1 to AArch32 version

Signed-off-by: Giacomo Travaglini 
Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b0a856e..65d8b97 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -334,7 +334,6 @@
 midr = 0x410fc0f0;

 miscRegs[MISCREG_MIDR] = midr;
-miscRegs[MISCREG_MIDR_EL1] = midr;
 miscRegs[MISCREG_VPIDR] = midr;

 miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 4221a15..000124c 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3507,7 +3507,8 @@

 // AArch64 registers (Op0=1,3);
 InitReg(MISCREG_MIDR_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_REVIDR_EL1)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70461?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Gerrit-Change-Number: 70461
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix read redirection for MIDR register

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email

to review the following change.


Change subject: arch-arm: Fix read redirection for MIDR register
..

arch-arm: Fix read redirection for MIDR register

This patch is fixing read redirection for the MIDR register
in the following ways:

1) Is allowing a virtualization of the register (via VPIDR)
even in secure mode (available with FEAT_SEL2)
2) Is extending this logic to the AArch64 version (MIDR_EL1)

It is also rewriting the base logic using Armv8 terminology
(checking the EL rather than the mode as an example).

Signed-off-by: Giacomo Travaglini 
Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 5 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 65d8b97..da23e0b 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -864,12 +864,11 @@
   case MISCREG_ID_AFR0: // not implemented, so alias MIDR
   case MISCREG_REVIDR:  // not implemented, so alias MIDR
   case MISCREG_MIDR:
-cpsr = readMiscRegNoEffect(MISCREG_CPSR);
-scr  = readMiscRegNoEffect(MISCREG_SCR_EL3);
-if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
-return readMiscRegNoEffect(idx);
-} else {
+  case MISCREG_MIDR_EL1:
+if (currEL() == EL1 && EL2Enabled(tc)) {
 return readMiscRegNoEffect(MISCREG_VPIDR);
+} else {
+return readMiscRegNoEffect(idx);
 }
 break;
   case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70464?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Gerrit-Change-Number: 70464
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Move MISCREG init logic from ISA to reset field

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

es().exceptUserMode().writes(0);
 InitReg(MISCREG_MPIDR)
   .allPrivileges().exceptUserMode().writes(0);
@@ -2870,6 +2895,19 @@
   .banked();
 InitReg(MISCREG_PRRR_NS)
   .bankedChild()
+  .reset(
+(1 << 19) | // 19
+(0 << 18) | // 18
+(0 << 17) | // 17
+(1 << 16) | // 16
+(2 << 14) | // 15:14
+(0 << 12) | // 13:12
+(2 << 10) | // 11:10
+(2 << 8)  | // 9:8
+(2 << 6)  | // 7:6
+(2 << 4)  | // 5:4
+(1 << 2)  | // 3:2
+0)
   .privSecure(!aarch32EL3)
   .nonSecure().exceptUserMode();
 InitReg(MISCREG_PRRR_S)
@@ -2888,6 +2926,22 @@
   .banked();
 InitReg(MISCREG_NMRR_NS)
   .bankedChild()
+  .reset(
+(1 << 30) | // 31:30
+(0 << 26) | // 27:26
+(0 << 24) | // 25:24
+(3 << 22) | // 23:22
+(2 << 20) | // 21:20
+(0 << 18) | // 19:18
+(0 << 16) | // 17:16
+(1 << 14) | // 15:14
+(0 << 12) | // 13:12
+(2 << 10) | // 11:10
+(0 << 8)  | // 9:8
+(3 << 6)  | // 7:6
+(2 << 4)  | // 5:4
+(0 << 2)  | // 3:2
+0)
   .privSecure(!aarch32EL3)
   .nonSecure().exceptUserMode();
 InitReg(MISCREG_NMRR_S)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70465?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec4878217c38707be4ce7d4746ff95a208b4
Gerrit-Change-Number: 70465
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MPIDR_EL1 to AArch32 version

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email

to review the following change.


Change subject: arch-arm: Map MPIDR_EL1 to AArch32 version
..

arch-arm: Map MPIDR_EL1 to AArch32 version

As of now the mapping is not actually needed:
the MPIDR and MPIDR_EL1 registes are both read using the same helper
(readMPIDR). In the future we could store the getMPIDR result in the
AArch32 version without the need to re-calculate the fix affinity
numbers

Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 000124c..706716e 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3510,7 +3510,8 @@
   .allPrivileges().exceptUserMode().writes(0)
   .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MPIDR);
 InitReg(MISCREG_REVIDR_EL1)
   .faultRead(EL1, HCR_TRAP(tid1))
   .allPrivileges().exceptUserMode().writes(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70462?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Gerrit-Change-Number: 70462
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email

to review the following change.


Change subject: arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version
..

arch-arm: Map MVFR0_EL1/MVFR1_EL1 to AArch32 version

Signed-off-by: Giacomo Travaglini 
Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.cc
1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index e984164..4221a15 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3579,10 +3579,12 @@
   .mapsTo(MISCREG_ID_ISAR6);
 InitReg(MISCREG_MVFR0_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MVFR0);
 InitReg(MISCREG_MVFR1_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().exceptUserMode().writes(0)
+  .mapsTo(MISCREG_MVFR1);
 InitReg(MISCREG_MVFR2_EL1)
   .faultRead(EL1, HCR_TRAP(tid3))
   .allPrivileges().exceptUserMode().writes(0);

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70460?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I28753de7b437be58e5ac891ac2e549bbab6b53b0
Gerrit-Change-Number: 70460
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Map CTR_EL0 to AArch32 version

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email

to review the following change.


Change subject: arch-arm: Map CTR_EL0 to AArch32 version
..

arch-arm: Map CTR_EL0 to AArch32 version

Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.cc
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 706716e..a31b6de 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3681,7 +3681,8 @@
 InitReg(MISCREG_CTR_EL0)
   .faultRead(EL0, faultCtrEL0)
   .faultRead(EL1, HCR_TRAP(tid2))
-  .reads(1);
+  .reads(1)
+  .mapsTo(MISCREG_CTR);
 InitReg(MISCREG_DCZID_EL0)
   .reads(1);
 InitReg(MISCREG_VPIDR_EL2)

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70463?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Gerrit-Change-Number: 70463
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Generalize SCTLR_RST behaviour

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev

ew, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70459?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Gerrit-Change-Number: 70459
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Rewrite ISA::initID32 using BitUnions

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email

to review the following change.


Change subject: arch-arm: Rewrite ISA::initID32 using BitUnions
..

arch-arm: Rewrite ISA::initID32 using BitUnions

Signed-off-by: Giacomo Travaglini 
Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc_types.hh
2 files changed, 39 insertions(+), 19 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a66a938..4033d0f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -280,8 +280,6 @@
 miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
 miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
 miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
-miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
-miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;

 miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
 miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
@@ -289,24 +287,25 @@
 miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
 miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;

-/** MISCREG_ID_ISAR5 */
-// Crypto
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 19, 4,
-release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
-// RDM
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 27, 24,
-release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
-// FCMA
-miscRegs[MISCREG_ID_ISAR5] = insertBits(
-miscRegs[MISCREG_ID_ISAR5], 31, 28,
-release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+ISAR5 isar5 = p.id_isar5;
+if (release->has(ArmExtension::CRYPTO)) {
+isar5.crc32 = 1;
+isar5.sha2 = 1;
+isar5.sha1 = 1;
+isar5.aes = 2;
+} else {
+isar5.crc32 = 0;
+isar5.sha2 = 0;
+isar5.sha1 = 0;
+isar5.aes = 0;
+}
+isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_ISAR5] = isar5;

-/** ID_ISAR6 */
-miscRegs[MISCREG_ID_ISAR6] = insertBits(
-miscRegs[MISCREG_ID_ISAR6], 3, 0,
-release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
+ISAR6 isar6 = p.id_isar6;
+isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
+miscRegs[MISCREG_ID_ISAR6] = isar6;
 }

 void
diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 0fe5a00..9af5337 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -75,6 +75,27 @@
 Bitfield<0> sp; // AArch64
 EndBitUnion(CPSR)

+BitUnion32(ISAR5)
+Bitfield<31, 28> vcma;
+Bitfield<27, 24> rdm;
+Bitfield<19, 16> crc32;
+Bitfield<15, 12> sha2;
+Bitfield<11, 8> sha1;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sevl;
+EndBitUnion(ISAR5)
+
+BitUnion32(ISAR6)
+Bitfield<31, 28> clrbhb;
+Bitfield<27, 24> i8mm;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> specres;
+Bitfield<15, 12> sb;
+Bitfield<11, 8> fhm;
+Bitfield<7, 4> dp;
+Bitfield<3, 0> jscvt;
+EndBitUnion(ISAR6)
+
 BitUnion64(AA64DFR0)
 Bitfield<43, 40> tracefilt;
 Bitfield<39, 36> doublelock;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70466?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Gerrit-Change-Number: 70466
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Make MISCREGs reset value configurable

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email

to review the following change.


Change subject: arch-arm: Make MISCREGs reset value configurable
..

arch-arm: Make MISCREGs reset value configurable

Signed-off-by: Giacomo Travaglini 
Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f
Reviewed-by: Richard Cooper 
---
M src/arch/arm/regs/misc.hh
1 file changed, 7 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index bf25ea3..69d1461 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2022 Arm Limited
+ * Copyright (c) 2010-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1231,6 +1231,12 @@
 return *this;
 }
 chain
+reset(uint64_t res_val) const
+{
+entry._reset = res_val;
+return *this;
+}
+chain
 res0(uint64_t mask) const
 {
 entry._res0 = mask;

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70458?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I536065a2de5faeb8ab64391f8ca2aa83fb2cc82f
Gerrit-Change-Number: 70458
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Replace 0ing of miscRegs with assignment of reset value

2023-05-10 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email

to review the following change.


Change subject: arch-arm: Replace 0ing of miscRegs with assignment of reset  
value

..

arch-arm: Replace 0ing of miscRegs with assignment of reset value

The reset variable in the MiscRegLUTEntry class defines the per-register
reset value. Rather than simply zeroing the misc registers we should
assign them their reset value when clearing them.

As of now the reset variable is unused so using it is functionally
equivalent of calling memset. This will however change once we start
using the reset field

Signed-off-by: Giacomo Travaglini 
Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Reviewed-by: Richard Cooper 
---
M src/arch/arm/isa.cc
1 file changed, 3 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index aec8243..5a0dec5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -141,7 +141,9 @@
 }

 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
-memset(miscRegs, 0, sizeof(miscRegs));
+for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
+miscRegs[idx] = lookUpMiscReg[idx].reset();
+}

 initID32(p);


--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70457?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79
Gerrit-Change-Number: 70457
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Attention: Richard Cooper 
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org

1 2 3 4 5 6 7 8 9 10 >

1 - 100 of 2118 matches

Mail list logo