* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing passed.
* build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
passed.
*
More or less, yes I did. I made some modifications though. I can
definitely try to incorporate this into Timing too though.
Tim
On Mon, 09 Nov 2009 18:26:25 -, nathan binkert n...@binkert.org
wrote:
Did you pull the code in translation.hh out of cpu/simple/timing.hh?
If so, does it
Hi everyone,
I'd like to be able to simulate benchmarks using SMARTS. Does anyone have
any experience doing this with M5? From what I can see, there needs to be
the following changes made to get this working correctly. Please can you
let me know if any of this is already available!
1) Allowing
changeset 16817406af29 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=16817406af29
description:
X86: Fix bugs in movd implementation.
Unfortunately my implementation of the movd instruction had two bugs.
In one case, when moving a 32-bit value into an
On Mon, 9 Nov 2009, nathan binkert wrote:
Can you swap your ULL at the end with the ULL macro? We use that
everywhere right now. it's in src/base/types.hh
Though, I do wonder if it still necessary.
well, I don't know if it's necessary or not. But I've updated the patch
like below. Does
Looks good to me.
Nate
On Tue, Nov 10, 2009 at 9:21 AM, Vince Weaver vi...@csl.cornell.edu wrote:
On Mon, 9 Nov 2009, nathan binkert wrote:
Can you swap your ULL at the end with the ULL macro? We use that
everywhere right now. it's in src/base/types.hh
Though, I do wonder if it still
So I started looking into what might be needed for proper fnstsw support.
Below is a patch. I'm sure I've got a lot of things wrong.
The status word is a 16-bit register that holds exception bits, result
status flags, and the x87 stack top value. Currently m5 tracks the top
value
It looks like there are some extra spaces before the ULLs.
Gabe
Quoting nathan binkert n...@binkert.org:
Looks good to me.
Nate
On Tue, Nov 10, 2009 at 9:21 AM, Vince Weaver vi...@csl.cornell.edu wrote:
On Mon, 9 Nov 2009, nathan binkert wrote:
Can you swap your ULL at the end with
changeset 4ac7bc30c482 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4ac7bc30c482
description:
ARM: Fix the integer register indexes.
The PC indexes in the various register sets was defined in the section
for
unaliased registers which was throwing off
changeset 6437ad24a8a0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=6437ad24a8a0
description:
ARM: Implement fault classes.
Implement some fault classes using the curriously recurring template
pattern,
similar to SPARCs.
diffstat:
9 files changed,
changeset 530e457c88c7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=530e457c88c7
description:
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/arch/x86/isa/microops/ldstop.isa |4 ++--
diffs (21
changeset b3ab661715ac in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=b3ab661715ac
description:
X86: Explain what really didn't work with unmapped addresses in SE mode.
diffstat:
1 file changed, 13 insertions(+), 3 deletions(-)
src/arch/x86/tlb.cc | 16
changeset 44010fc924d4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=44010fc924d4
description:
X86: Don't panic on faults on prefetches in SE mode.
diffstat:
1 file changed, 15 insertions(+), 11 deletions(-)
src/arch/x86/tlb.cc | 26 +++---
changeset 48d10ba361c9 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=48d10ba361c9
description:
Mem: Eliminate the NO_FAULT request flag.
diffstat:
8 files changed, 26 insertions(+), 10 deletions(-)
src/arch/alpha/faults.cc |2 +-
changeset f58db256bcf2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f58db256bcf2
description:
Merge with the head.
diffstat:
13 files changed, 204 insertions(+), 990 deletions(-)
src/arch/arm/SConscript |2
changeset 73d89772f409 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=73d89772f409
description:
ARM: Fix some bugs in the ISA desc and fill out some instructions.
diffstat:
5 files changed, 98 insertions(+), 41 deletions(-)
src/arch/arm/isa/bitfields.isa|1
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