[gem5-users] Multiple Problems with HMC Simulation in gem5

Hi All, While simulating HMC in gem5(right out of the box), I encountered following errors: 1) Executing se.py with HMC as memory option: build/X86/gem5.opt configs/example/se.py --mem-type HMC_2500_1x32 -c hello yields following error: if opt.arch == "distributed" or opt.arch == "mixed":

[gem5-users] Exiting Simulation in multi-core design

Hi All, In multi-core simulation, --max-insts means exit simulation if "any" thread reach instruction count. Which file in gem5 should I modify it so that "sum of total instructions" executed by "all" threads reach this count. Thanks Muzamil ___

[gem5-users] Host Memory Size vs Simulator Memory Size

Hi All, I have a question regarding relationship (if any) that exists between host memory size and memory range assigned using option --mem-size=MEM_SIZE. If memory size of my host machine is 4GB(RAM), can I assign --mem-size=8GB in gem5 simulator se mode? If yes, what is the origin of these type

[gem5-users] Host Memory Size vs Simulator Memory Size

Hi All, I have a question regarding relationship (if any) that exists between host memory size and memory range assigned using option --mem-size=MEM_SIZE. If memory size of my host machine is 4GB(RAM), can I assign --mem-size=8GB in gem5 simulator se mode? If yes, what is the origin of these type

[gem5-users] "Portable" gem5.opt binary

Hi, Is there a way to create an optimized gem5 binary (gem5.opt) that is compiled statically and is portable from one system to another (from ubuntu to redhat linux) without recompiling using "scons"? I want to run simulations remotely and my remote system doesn't have "scons" installed and

[gem5-users] "Tried to read/write unmapped address"

Hi All, I am running se.py with spec2006 benchmarks with memory model of HMC. After switching CPUs from fast forward to detailed, this error pops up and simulation aborts. panic: Tried to write unmapped address 0x7a9ed740. Memory Usage: 8714168 KBytes Program aborted at tick 3243857330565

[gem5-users] --mem-size and --mem-channel options

Hi All, I have a doubt if --mem-size option in se.py is the total size of physical memory available or is the size of memory available per channel. For Example: if --mem-size = 4GB and --mem-channel = 2, then memory ranges per channel is 2GB? or the total available memory is 8GB,

[gem5-users] "Tried to read/write unmapped address"

Hi All, This issue has been discussed for a while now, but I don't understand the actual reason why it happens... For some memory configs, this error pops up, aborting the simulation while for others (changing cache/memory sizes), simulation works just fine. I got following error while running

Re: [gem5-users] gem5-users Digest, Voz.ll 1z632, Issue TylenolVoz.lll

Afawwzqsdl.slm On Jul 23, 2017 11:00 AM, wrote: Send gem5-users mailing list submissions to gem5-users@gem5.org To subscribe or unsubscribe via the World Wide Web, visit http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users or, via email, send a

[gem5-users] DRAM Device Size

Hi All, I have a little confusion in understanding the way "device_size" is described. Below is a piece of code from DRAMCtrl.py. """ # A single DDR3-1600 x64 channel (one command and address bus), with # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in # an 8x8 configuration.

[gem5-users] DRAM Controller (gem5 vs DRAMSim2)

Hi All, I have a doubt on my mind for a while if DRAM Controller model in gem5 is more detailed and accurate or the DRAM Controller model of DRAMSim2? Do we have support like sub-array level parallelism (SALP) and refreshing certain selected number of rows (instead of a whole bank) available in

[gem5-users] DRAMSim2 Integration with gem5

Hi All, I have integrated DRAMSim2 with gem5 and want to try different config files. I changed the device and system config file options in the gem5/src/mem/DRAMSim2.py file but it is taking already specified config files, not different files from folder gem5/ext/dramsim2/DRAMSim2/ini? Do I have

[gem5-users] BBV file not generated(or found)

Hi All, I am trying to generate BBV file for SimPoint creation using the following command: build/X86/gem5.opt configs/example/spec06_config.py --benchmark bzip2 --benchmark_stdout=m5out/bzip2.out --benchmark_stderr=m5out/bzip2.err -I 1 --simpoint-profile --simpoint-interval 1

[gem5-users] Error running spec2006 Benchmarks on multiple cores

Hi All, Does anyone has modified script of se.py that is able to run spec2006 benchmarks on multi-core cpu (different benchmarks for different cores)? I am able to run a single benchmark on one core but when i use it to run different benchmarks on different cores, it gives me errors. Please

Re: [gem5-users] [Re: [Raziye--gem5-users] My Gem5 failed to run Spec2006腾讯Q群：612987168 (yi)]

Hi Yi, The script you shared only runs single spec2006 benchmark on single cpu core. How it can be extended to run different benchmarks on different cpu-cores? Thanks Muzamil Message: 4 Date: Sun, 19 Mar 2017 08:34:58 +0330 From: raziye deylamsalehi To: gem5

[gem5-users] Simulation doesn't switch to Detailed CPU after fast forwarding

Hi all, I am running basic se.py config file: $ gem5/build/X86/gem5.opt configs/example/se.py with following options: $GEM5_DIR/build/X86/gem5.opt\ --outdir=$OUTPUT_DIR\ $GEM5_DIR/configs/example/spec06_config.py\ --benchmark=$BENCHMARK\

Re: [gem5-users] Simulation error with se.py

Hi Sam, I was getting the same error. Actually hmctest.py creates a structure "system.ser_ranges" and address ranges are not assigned to each serial link from se.py (which imports from MemConfig.py). You may have to edit MemConfig.py in (configs/common) to assign mem_ranges explicitly to all

[gem5-users] Problem running hmctest.py

Hi All, I am trying to run hmctest.py but it doesn't work right out of the box: Command Line => $ build/X86/gem5.opt configs/example/hmctest.py and gives the following error: AttributeError: '_m5.param_SubSystem.SubSystemParams' object has no attribute 'enable_buff_div' I tried to hide this

[gem5-users] HMC Simulation Error(HMC_2500_1x32)

Hi All, There are few problems in HMC simulation that have not been fixed so far: 1. hmctest.py doesn't work right out of the box and gives error: Command line: /gem5$ build/X86/gem5.opt configs/example/hmctest.py Simulation Error: Traceback (most recent call last): File "", line 1, in

[gem5-users] Long persisting simulation error in HMC model (HMC_2500_1x32)

Hi All, There are few problems in HMC simulation that have not been fixed so far: 1. hmctest.py doesn't work right out of the box and gives error: Command line: /gem5$ build/X86/gem5.opt configs/example/hmctest.py Simulation Error: Traceback (most recent call last): File "", line 1, in

[gem5-users] Switching CPU modes(Simple to Detailed)

Hi All I posted this question before and looking for an answer/suggestion. I am trying to switch to DerivO3CPU() from AtomicSimpleCPU(). I was following instruction on webpage *http://www.gem5.org/Checkpoints < http://www.gem5.org/Checkpoints>* in *sampling* section and getting errors like: 1.

[gem5-users] Switching between CPU modes (simple vs detailed)

Hi All, I am also trying to switch to DerivO3CPU() from AtomicSimpleCPU(). I was following instruction on webpage *http://www.gem5.org/Checkpoints * in *sampling* section and getting errors like: 1. AttributeError: Class DerivO3CPU has no parameter switchedOut

[gem5-users] Fast Forwarding and Checkpointing in multi-core CPU

Hi All, I have couple of questions regarding fast-forwarding and checkpointing in multi-core CPU. 1. If I want to fast-forward my benchmark for certain number of instructions, do I have to simulate my CPU in atomic mode (AtomicSimpleCPU()) for the number of instructions being fast forwarded? 2.

[gem5-users] Problem running some SPEC2006 Benchmarks

Hi All, I am testing SPEC 2006 benchmarks in gem5. Most of them are working just fine but few of them giving errors like: Cannot open input file x even I specified file path in Mybench.py file and also made sure that file exists in particular folder. Some benchmarks that give problem

[gem5-users] hmctest.py not running out of the box

Hi All, I am trying to run hmctest.py out of the box using following command: build/X86/gem5.opt configs/example/hmctest.py but getting error: AttributeError: '_m5.param_SubSystem.SubSystemParams' object has no attribute 'enable_buff_div' This error was not there when i tried to run it a

[gem5-users] Demand vs Prefetch Requests

Hi All, I just want to make sure, data placed in prefetch queue will essentially reduce overall available cache space for data brought by demand requests? Also, if cache has LRU replacement policy, that would also apply to prefetched data as well? Please correct me if I am wrong!!! Thanks

[gem5-users] "Bringing multiple Cache-Lines from Main Memory"

Hi All, When we have a miss in LLC and found that address in row-buffer (row currently open) in main memory, how can we bring multiple cache-lines residing in that row buffer (along with requested one) in to caches? Is there currently any support available in gem5? Thanks Muzamil

[gem5-users] "Page Management Policies Definitions"

Hello All, I just want to know where are the definitions of page management policies in gem5? i.e. "open, close, open_adaptive and close_adaptive" (in dram_ctrl.hh and dram_ctrl.cc)? Thanks Muzamil ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] Maximum Simulated Instructions

Hi All, I am running four different benchmarks on a quad-core CPU. I have two questions: 1. What is the difference between: max_insts_all_threads and max_insts_any_thread? *** /* code from BaseCPU.py */ max_insts_all_threads = Param.Counter(0, "terminate when all threads have

[gem5-users] Creating multiple instances of SimObject

Hi all, I was just wondering if I'd have to create multiple instances of any SimObject in a single system, how would I do that? Just assign an ID to each instance same as we assign "cpu_id" to different cores in a multi-core system? Muzamil ___

[gem5-users] Capturing address traces

Hi, I was just wondering what is the best way to capture address traces generated by CPU for a particular application running in SE mode? Any help!!! Muzamil ___ gem5-users mailing list gem5-users@gem5.org

[gem5-users] Bug in implementing "Creating SimObjects in the memory system"

Hi Jason, While trying to implement "Creating SimObjects in the memory system" and after using the command: build/X86/gem5.opt src/learning_gem5/simple_memobj/simple_memobj.py I got the following error: info: Entering event queue @ 0. Starting simulation... gem5.opt:

[gem5-users] Bug in implementing "Creating SimObjects in the memory system"

Hi Jason, While trying to implement "Creating SimObjects in the memory system" from the tutorial, I encountered an error stating: I used command: info: Entering event queue @ 0. Starting simulation... gem5.opt: build/X86/mem/port.cc:182: bool MasterPort::sendTimingReq(PacketPtr): Assertion

Re: [gem5-users] Memory Side Prefetcher (Jason Lowe-Power) (Andreas Hansson)

Hi Andreas, I was thinking exactly the same way first that I should use cache as a little "buffer" closer to memory as "memory" side prefetcher but wanted a second opinion which you gave me. Thanks for that. I want to use a little buffer in the logic base of HMC (individual vault controller), so

Re: [gem5-users] Memory Side Prefetcher (Jason Lowe-Power)

Hi Jason, Thanks for your reply. Just to make sure, adding a new SimObject means to create memory side prefetcher from the scratch, (as you explained in your book, creating python files to declare object and its parameters, header files and source file to explain functionality in detail)? Is

[gem5-users] Memory Side Prefetcher

Hi All, I am trying to implement prefetching but only feature available currently is CPU side prefetching where prefetchers are implemented in caches. How can I implement prefetchers in memory controller? Should I include and instantiate existing prefetchers available, in memory controller

[gem5-users] Device size vs. Address Range Assigned

Hi All, While simulating gem5, we usually get a warning saying" warn: DRAM device capacity (8 Mbytes) does not match the address range assigned (256 Mbytes) What does it actually mean? How can we assign more address range than available memory space we have available? Please help me get clear

[gem5-users] SPEC CPU2006 script for gem5

Hi Yi, Please share the script you are running SPEC CPU2006 benchmarks with for X86 architecture. Thanks Muzamil Message: 12 Date: Thu, 16 Mar 2017 19:19:38 +0800 (CST) From: yi To: "gem5 users mailing list" Subject: Re: [gem5-users] My Gem5 failed to

[gem5-users] Error Simulating Simple Config. file with DerivO3CPU

Hi All, I tried to simulate simple.py with DerivO3 CPU and got the following error: command line: build/X86/gem5.opt configs/tutorial/simple.py Beginning simulation! info: Entering event queue @ 0. Starting simulation... gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer

[gem5-users] Simulation Error with "close_adaptive" paging policy

Hi All, I am simulating HMC model aith multi-core CPU any trying different "paging" policies. open, close and open_adaptive works just fine but there is a problem with close-adaptive and getting following error: gem5.opt: build/X86/mem/dram_ctrl.cc:1875: void

[gem5-users] Fast Forwarding in Simulation

Hi All, I am trying to run a simple configuration script consisting of SimpleCPU, caches and main memory. I have added SPEC CPU2006 benchmark as a workload and it runs just fine. I want to add options like "--fast-forward" and "maxinsts" to reduce total simulation time and fast-forward to

[gem5-users] Adding Fast Forwarding option on command line

Hi All, I am writing my own configuration script and want to include instruction fast forwarding option. Is there any reference available to consult about including "--fast-forward" in command line options? or can it be given as an option [e.g. m5.simulate(fast-forward)]? Please help!!! Thanks

[gem5-users] Running Benchmarks on multi-core processor

Hi All, I am trying to run Spec CPU2006 Benchmarks on multi-core processor. Is it possible to assign same benchmark among different cpu cores to share the workload or it can only be run on single core at a time? Also, is it possible to assign different (or same) benchmark to different cores and

[gem5-users] gem5 segmentation fault with SPEC CPU2006 benchmarks

Hi all, I was trying to run SPEC CPU2006 benchmarks with a simple configuration following the instructions given at: http://www.gem5.org/SPEC_CPU2006_benchmarks and modifying the given two codes accordingly. When I ran simulation with any benchmark: build/X86/gem5.opt configs/tutorial/cmp.py

Re: [gem5-users] Error in Simulating hmctest.py with CPU

m5.org> Subject: Re: [gem5-users] Error in Simulating hmctest.py with CPU Message-ID: <CAFEhpUf2b0M5pt+gsOTNuKi1+OZ=fuqsp9t-ytc-zedcakb...@mail.gmail.com> Content-Type: text/plain; charset="utf-8" Hi Muzamil, On Thu, Feb 16, 2017 at 5:29 PM Muzamil Rafique <muzamil.ravian...@gma

[gem5-users] "LiveProcess" is not defined!!!

Hi All, I just updated my gem5 repo and now I am getting error which was not the case before. By running simple.py, I am getting following error: command line: build/X86/gem5.opt configs/tutorial/simple.py Traceback (most recent call last):

Re: [gem5-users] FS Simulation using HMC_2500_x32 and Caches

Serhat From: gem5-users [gem5-users-boun...@gem5.org<mailto:gem5-users-bounces@ gem5.org>] on behalf of Muzamil Rafique [muzamil.ravian...@gmail.com] Sent: 13 February 2017 20:28 To: gem5-users@gem5.org<mailto:gem5-users@gem5.org> Subject: [gem5-u

[gem5-users] Error in Simulating hmctest.py with CPU

Hi All, I was trying to run a simple system consisting of a CPU, L1 and L2 caches and HMC as main memory. (Similar to hmctest.py and just replacing traffic generators by cpu and adding L1 and L2 caches). While running "same" architecture, where all available memory is accessible by all four

[gem5-users] Error in simulating hmctest.py with CPU and caches (L1 and L2)

Hi All, There seems to be a bug in HMC model (I guess). I ran hmctest.py out of the box and it was working just fine. I tried to connect CPU (timingSimpleCPU()) instead of traffic generators (tgen), without any caches, while cache ports (icache and dcache ports) directly to membus, and simulated.

[gem5-users] FS Simulation using HMC_2500_x32 and Caches

Hi All, I was trying to run Full System Simulation using following command: build/X86/gem5.opt configs/example/fs.py --mem-type=HMC_2500_x32 --caches --l2cache but getting the following error: REAL SIMULATION info: Entering event queue @ 0. Starting simulation... warn: Don't know

Re: [gem5-users] Parsing options in hmctest.py

Hi Jason, Thanks for your reply. I followed your instruction and to amaze me, most of the options available didn't work. I checked .config file and assigning different options in CL won't change corresponding options in .config file. Also I was not able to find the python file where these

[gem5-users] Parsing options in hmctest.py

Hi All, I was trying to add "page policy" as an option in hmctest.py file for simulation purpose. I added following code: parser.add_option("--page_policy", type = "int", default = 2, help = "0:open; 1:open_adaptive; 2: close; 3:close_adaptive") How would I verify if it worked

[gem5-users] Error using runspec in SPEC2006 Benchmarks

Hi All, I am trying to use runspec in an effort to compile and run SPEC2006 benchmarks and getting following erroe: */cpu2006$ runspec --config=example-simple.cfg --action=build --tune=base bzip2 -I* runspec v4662 - Copyright 1999-2006 Standard Performance Evaluation Corporation Using

Re: [gem5-users] gem5-users Digest, Vol 126, Issue 14

each the person managing the list at > gem5-users-ow...@gem5.org > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of gem5-users digest..." > > > Today's Topics: > >1. HMC Simulation (Muzamil Rafique) >

[gem5-users] HMC Simulation

Hi, Thanks Andreas Hansson and Abdul Mutaal for your response. But still I have couple of issues. *1.* I have downloaded latest version of gem 5 and tried to simulate hmctest.py in folder configs/example/hmctest.py using command: build/ARM/gem5.opt configs/example/hmctest.py and get the

[gem5-users] HMC Simulation

Hi All, I have 2 questions. Q1. gem5-stable is no longer available. Where to download stable version of gem5? Q2. I am trying to run HMC simulation with following command (on latest version of gem5) and getting the following error. build/ARM/gem5.opt configs/example/fs.py -I 1000

Re: [gem5-users] HMC Simulation (Abdul Mutaal)

Hi Abdul, Thanks for response. I am following your instruction to follow: http://reviews.gem5.org/r/3374/ But it is written there: *To run, it requires the main HMC config patch * *http://reviews.gem5.org/r/3373/ * But getting error for all the files:

[gem5-users] HMC Simulation

Hi, I am trying to simulate HMC (hybrid memory cube) (files (*HMC.py, MemConfig.py, fs,py*) downloaded from http://reviews.gem5.org/r/2986/diff/10/#2) using command: ./build/ARM/gem5.opt configs/example/fs.py \ --mem-type=HMC_2500_x32 --mem-channels=16 \ --caches --l2cache \