Hi,
You should establish a link between your cache and the ISA. It shouldn't be
hard to hack things around.
A cleaner solution would involve using probe points. You could use a probe
listener per ISA object. For every alocation update on the l2 cache, the
listeners will be awakened and the
On 26/02/2024 05:33, Ananth.PaiJ--- via gem5-users wrote:
Hello *,
Hi
While building gem5 with EXTRAS= mechanism I’m encountering an error.
Error :
[SO Param] m5.objects.BranchPredictor, BranchTargetBuffer ->
ARM/python/_m5/param_BranchTargetBuffer.cc
terminate called after throwing an
Hi Pooja,
It looks like an old version of gem5 (considering configs/example/se.py has
been moved to configs/deprecated/example/se.py). As you are trying to run an
Arm simulation, can I suggest you to use
configs/example/arm/starter_se.py instead?
Kind Regards
Giacomo
From: Pooja
Hi Nazmus,
You should have a look at
https://github.com/gem5/gem5/blob/stable/src/arch/arm/insts/sve_macromem.hh
To simply answer your question, the micro-op cracking happens in the
instruction definition and that's why you can't find anything
in the cpu/pipeline code. If you want to
Hi Nazmus
On 15/01/2024 14:32, Nazmus Sakib wrote:
Hello. Thanks for your response.
I am running O3 cpu (ARMO3CPU), not minor.
It's the same:
https://github.com/gem5/gem5/blob/stable/src/cpu/o3/lsq.cc#L816
Also, I get it that LSQ unit can do this.
But a cache must have separate logic for
Hi Nazmus,
On 15/01/2024 02:41, Nazmus Sakib wrote:
Thank you. I will try to switch to starter_se.py.
I still had some questions regarding SVE.
1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction,
which is replaced by whilelow when I compile without setting the
Which stats are you interested on in particular?
Also when you say for each simulated instruction, do you mean for each
simulated instructionn TYPE? For example:
ADD -> stats for this particular instruction type
MUL -> stats for this particular instruction type
Kind Regards
Giacomo
On
You are right, I created a PR to fix this:
https://github.com/gem5/gem5/pull/764
Kind Regards
Giacomo
From: Nazmus Sakib
Date: Thursday, 11 January 2024 at 19:34
To: Giacomo Travaglini , The gem5 Users mailing
list
Cc: Jason Lowe-Power
Subject: Re: ARM SVE ISA
Not compiling with
Hi Nazmus,
I can see from what you posted you are compiling the testcase with 512b vector
width. I believe you should amend the gem5 VL accordingly… Basically writing up
in the gem5 config:
cpu.isa[0].sve_vl_se = 4
According to [1].
This should fix your problem. Another solution I believe
Hi saras,
You are using a fully-fledged ubuntu distribution. May I suggest you a more
lightweight solution?
Please have a look at the ubuntu18.04 option in
https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries
Kind Regards
Giacomo
From: saras nanda via gem5-users
Date:
Hi saras,
Could you post an extract of the kernel panic from m5out/system.terminal?
Kind Regards
Giacomo
From: saras nanda via gem5-users
Date: Sunday, 26 November 2023 at 22:13
To: The gem5 Users mailing list
Cc: saras nanda
Subject: [gem5-users] Query regarding Running Custom FS image for
Hi,
Did you call m5.instantiate before calling m5.simulate? (I don’t see it from
the code snippet you posted)
Kind Regards
Giacomo
From: Tran, Huy Dinh via gem5-users
Date: Thursday, 2 November 2023 at 20:33
To: gem5-users@gem5.org
Cc: Tran, Huy Dinh
Subject: [gem5-users] m5.switchCpus for
Hi all,
You can in principle try to setup an SMT simulation for the O3CPU by tweaking
the smt parameters of the CPU [1]
In practice this has not been tested in a long time and it is very likely it is
broken.
Kind Regards
Giacomo
[1]:
Hi Ashan,
In a FS simulation you would usually access a device with a driver. In general,
it depends on the programming interface of your device.
Kind Regards
Giacomo
From: Ashan Peiris via gem5-users
Date: Monday, 9 October 2023 at 18:41
To: gem5-users@gem5.org
Cc: Ashan Peiris
Subject:
Hi Setu,
It might depend on the ISA you are using.
You can generate an instruction trace by running gem5 with --debug-flags=Exec
option and this is valid for all ISAs. If you are simulating an Arm CPU, an
instruction trace in the Tarmac format can also be generated.
Kind Regards
Giacomo
Hi Ananth,
This is a real issue I noticed myself as well (thought I didn’t have time to
address nor to report it).
I will create an issue on GitHub hoping to find some time in the near future.
In the meantime, if this is stopping you, may I recommend you to checkout an
earlier version of gem5?
Hi Atul,
Just to clarify your setup:
Are you compiling your benchmark for Linux and running Linux + benchmark on
gem5? Or are you running it baremetal on the simulated platform? There’s
nothing inherently wrong on observing SVCs and MSR/MRS if your application
contains some syscalls… If you
Hi,
m5.options.outdir is probably what you are looking for.
Kind Regards
Giacomo
From: Caio Vieira via gem5-users
Date: Wednesday, 23 August 2023 at 10:24
To: The gem5 Users mailing list
Cc: Caio Vieira
Subject: [gem5-users] Get gem5 output directory from python config
Hi,
I would like to
Hi Chathura,
I don’t know the other ISAs, but Arm supports an IOMMU (SMMU in Arm
terminology):
https://github.com/gem5/gem5/blob/stable/src/dev/arm/RealView.py#L1475
Kind Regards
Giacomo
From: Chathura Rajapaksha via gem5-users
Date: Thursday, 17 August 2023 at 14:28
To: gem5-users@gem5.org
Hello, it would help if you could run it with gdb, place a breakpoint in
BaseKVMCPU::setOneReg and tell us which register gem5 is trying to set
Kind Regards
Giacomo
From: 何雨彬 via gem5-users
Date: Tuesday, 15 August 2023 at 07:00
To: gem5
Cc: 何雨彬
Subject: [gem5-users] boot arm with kvm
Hi Ziyang,
We don’t have a DSU model in gem5. If you are not interested in modelling the
DSU per se and you are only interested on recreating a DSU-like system (a
DynamIQ cluster), you can proceed as you suggested.
I also encourage you to have a look at the fs_bigLITTLE.py example script [1];
Hi
On 25/05/2023 18:50, AbdelQader AlKilany via gem5-users wrote:
Hello gem5 users,
I was wondering if anyone has recently run an ARM fs simulation using a KVM CPU
type, and if so whether there are any instructions on how to do so.
(I've read that SE KVM is only supported with X86, but FS KVM
Hi,
the ALPHA ISA has been removed from gem5.
If you still want to use ALPHA, you’ll have to checkout an older version of the
simulator, otherwise you’ll have to pick a different ISA.
Kind Regards
Giacomo
From: Sravani Sravanam 20PHD7041 via gem5-users
Date: Thursday, 25 May 2023 at 08:55
= process
cpu.createThreads()
system.workload = SEWorkload.init_compatible(binary)
The gem5/assembly/test executes successfully on my local environment, and I'm
using M1 arm64 cpu
Thanks,
Ziyao
On Sun, May 21, 2023 at 10:39 PM Giacomo Travaglini via gem5-users
mailto:gem5-users@gem5.org&g
Hi,
If the command line is just
$ build/ARM_MESI/gem5.opt configs/FS_ruby.py,
Are you sure you are passing the object file to the Workload object?
(_is_compatible_with is called with a None object)
Also the script is called FS ruby but you seem to have instantiated a SE
workload
Just for the sake of completeness (I know Arun asked about X86).
There is a multi-level TLB for Arm; it is possible for other ISAs to implement
the same, it requires a developer to move the translateAtomic/Timing methods
from the TLB to the MMU
Kind Regards
Giacomo
From: Jason Lowe-Power via
Are you using the fs_bitLITTLE.py script?
Big/Little CPUs should be grouped under the bigCluster/littleCluster SimObjects.
This should be visible in both config.ini and in the stats file (e.g.)
[…]
system.bigCluster.clk_domain.clock500 #
Clock period in
Hi Iana,
In theory it shouldn't be a problem to run a dynamically linked binary on a Arm
host... Could you run the application with GDB and check why the mmap is
failing?
Kind Regards
Giacomo
From: Iana Chertkova via gem5-users
Sent: 28 April 2023 03:24
To:
Hi,
I am not surprised. The disk image contains an init script with m5 operations
(probably m5 readfile).
m5 is a gem5 specific pseudo-instruction and does not get recognised by QEMU.
You should either amend the init file within the disk or point to a different
init executable from QEMU
Hi Zhang,
That parameter configures the *maximum* (hardware constrained) vector length.
It is possible to choose a different (smaller) vector length for a process by
configuring the following registers
ZCR_EL1 [1]
ZCR_EL2 [2]
ZCR_EL3 [3]
So I believe the problem is that while you are
Hi,
FEAT_PAuth should be enabled by default, unless you are using a really old
version of gem5.
May I suggest you to debug the instruction (or ArmISA::auth) with gdb to
understand what is going on?
autib should generate an exception if FEAT_PAuth is disabled (and shouldn't be
treated as
Hi Shuo,
That’s correct; we don’t fully support SVE2 for now…
We *might* have a partial implementation as we support SME (in develop branch;
it will be merged in next release)
Kind Regards
Giacomo
From: Ayaz Akram via gem5-users
Reply to: The gem5 Users mailing list
Date: Tuesday, 11 April
This has been fixed by:
https://gem5-review.googlesource.com/c/public/gem5/+/66851/3
And it will be available in next release
Kind Regards
Giacomo
From: Artak Arakelyan via gem5-users
Reply to: The gem5 Users mailing list
Date: Monday, 3 April 2023 at 15:49
To: "gem5-users@gem5.org"
Cc:
Hi,
On 15/03/2023 23:34, Kar, Anurag Arunkumar via gem5-users wrote:
Hi,
I’m trying to use Arm Pointer Authentication (Arm v8.3 PAC extension) with a
cross compiled binary which has the PAC instructions with return address
signing (I checked, the instructions are there).
I tried inserting
Hi Anurag
On 15/03/2023 12:57, Kar, Anurag Arunkumar via gem5-users wrote:
Hi,
I tried following previous archived threads which said the solution to this
problem was to provide the path to PYTHON_CONFIG and not using a conda
environment.
I am not using a conda environment and am providing
Hi Jonathan,
On 08/03/2023 17:47, Jonathan Kang wrote:
Thanks Giacomo,
A few questions:
1. Who is Jason? So that I can contact him
Jason Lowe-Power, here CCed
1. Regarding ELFie, I found these:
*
https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
Hi Jonathan
On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
Hi all,
I’m attempting to get SPEC 2k17 to run on our performance model that uses an
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I
was wondering if anyone has had experience capturing
Hi Haseung
On 06/03/2023 11:47, 봉하승 wrote:
Hi Giacomo,
Got it, thanks for your reply.
Can you tell me what architecture or processor the default ARM configuration
used in gem5'O3CPU is based on?
The O3CPU is ISA agnostic, so it is not Arm specific. The architecture under
use is defined by
Hi Haseung,
In Arm FP registers share the same storage with SIMD (Vector) registers, so we
usually refer to them as SIMD registers.
This is why in gem5 we don’t use the floating point register type and we use
the vector type only
Kind Regards
Giacomo
From: 봉하승 via gem5-users
Reply to: The
Hi ikram,
On 01/02/2023 10:19, IKRAM via gem5-users wrote:
Hi
Below are commands and log info of the error mentioned in the subject line.
Info of workload is:
file demo.elf
demo.elf: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV), statically
linked, with debug_info, not stripped
Hi, there is no command-line option, but you just need to edit the system
frequency in BaseSimpleSystem [1]
Kind Regards
Giacomo
[1]:
https://github.com/gem5/gem5/blob/stable/configs/example/arm/devices.py#L274
From: Νικόλαος Ταμπουρατζής via gem5-users
Date: Friday, 23 December 2022 at
Hi,
I would say it depends on the config script you are using.
For example se.py is a correctly assigning different clock domains between the
system and the CPUs:
system.clk_domain = SrcClockDomain(
clock=args.sys_clock, voltage_domain=system.voltage_domain
)
[…]
system.cpu_clk_domain =
Hi,
If you are just planning on introducing a single register, you could consider
extending the number of IntRegs, or to add this extra register as a MiscReg
(but be careful in the latter case, as MiscRegs are not renamed).
If you really want to define a new register class, we have recently
Hello, yes, it is supported.
You could use the following blog post [1] as a starting point. There was also a
talk at the ISCA2022 workshop about booting OP-TEE in gem5; you could probably
look for it on youtube IIRC
Kind Regards
Giacomo
[1]:
This is weird; it never took me more than 20 seconds to generate a single
checkpoint in gem5.
I suspect most of the time is spent on draining the system.
Would you be able to debug which draining method is stalling the checkpointing
process?
Kind Regards
Giacomo
From: Hanhwi Jang via
Hello, it was a bug which got fixed by the following patches, which are merged
in develop and will be part of next release
https://gem5-review.googlesource.com/c/public/gem5/+/64072/4
https://gem5-review.googlesource.com/c/public/gem5/+/64073/4
Let me know if it works
Kind Regards
Giacomo
Hi Jonathan, thanks for your email.
I haven't heard of anything like that, but it would be really nice to have an
ETM trace player available in gem5.
Have you had a look at the TraceCPU documentation available in the gem5
website? [1]
The TraceCPU is really supposed to be used for
Hi,
Are you running FS or SE simulations? In FS it is configurable through the
guest kernel, in SE mode we use 4K by default (see src/arch/arm/page_size.hh)
You might try to change the hardcoded value in the page_size.hh file though
this has never been tested and it might not work without some
That’s great!
FYI, overriding the getAddrRanges is not strictly needed if the BasicPioDevice
is correctly initialised. That basically means initialising pioAddr and pioSize
member variables:
https://github.com/gem5/gem5/blob/stable/src/dev/io_device.cc#L81
I am telling you this as while you
Yes apologies, I now realize your range was already covered in the existing
_off_chip_ranges list
I’d recommend you to debug with gdb what is returned by the
CusDevice::getAddrRanges method. It gets called by the xbar and it effectively
registers the device pio range in the interconnect map.
Hi Joshua.
You probably need to add the physical address range of your device to the
_off_chip_ranges list [1]. This will be assigned to the membus->iobus bridge so
that when the membus receives the cpu packet, it knows it must forward it to
the io bridge
Let me know if this works
Kind
Hi Pedro,
The GIC is indeed the likely culprit as 8 PEs is the architectural limit of
GICv2 (which is the interrupt controller used by VExpress_GEM5_V1, the default
fs_bigLITTLE.py platform).
If using KVM I honestly don’t see an easy way around it: we have on upstream a
device driver
Hi George,
Thanks for reporting this, I noticed the same issue. When we transitioned from
the old m5 subsystem (assembly based) to the new C based one we forgot to
provide an implementation for workbegin and workend I suppose. Putting Gabe on
CC
Kind Regards
Giacomo
From: George
Hi Tom
1. I am not surprised, the gem5 disassembly has some flaws especially when
it comes to aliases. The instruction is implemented correctly, it is just
wrongly traced. We should fix these tiny bugs but as of now I just suggest you
to not blindly rely on what is produced by the
Hi,
It is possible you are not able to bring up secondary CPUs when booting Linux.
I would suggest you to have a look at the dmesg dump to check if there’s a
problem.
Just in case, please update bootloaders by either recompiling them from source
or by downloading them at
I suggest you have a look at how memory mapped m5ops are implemented:
https://github.com/gem5/gem5/blob/develop/src/arch/arm/mmu.cc#L185
If the memory reference lies within a specific address range (m5opRange) the
memory access is replaced by the local accessor callback (recorded in the
Hi Pedro,
As you correctly stated, you could make an instruction work in KVM mode by
implementing them as pseudo instruction and using the memory mapped
implementation (m5 –addr).
If you run your instruction in KVM mode, the host won’t recognize the
instruction and your guest VM will get an
Hi Gelin,
Are you compiling gem5 in debug mode?
You can do that by using “debug” instead of “opt”:
$scons build/ARM/gem5.debug -j`nproc`
Kind Regards
Giacomo
From: Gelin Fu via gem5-users
Date: Monday, 22 November 2021 at 12:26
To: gem5-users@gem5.org
Cc: Gelin Fu <20153...@cqu.edu.cn>
Hi Gelin, thanks for reporting this.
Would you mind running it with gdb and let us know which is the event failing
the assertion?
(gem5.opt: build/ARM/sim/eventq.hh:766: void
gem5::EventQueue::schedule(gem5::Event*, gem5::Tick, bool): Assertion `when >=
getCurTick()' failed)
Kind regards
Hi Nathanael, this is a know problem in develop that will be fixed in next
release.
It comes from the fact that we are using 4 table walkers (for S1I-TLB, S1D-TLB,
S2I-TLB and S2D-TLB).
I am currently working on:
a) Implementing a VA indexed walk cache replacing current PWCs (.gem5
> -Original Message-
> From: Ali Ghandour via gem5-users
> Sent: 12 October 2021 08:50
> To: gem5-users@gem5.org
> Cc: Ali Ghandour
> Subject: [gem5-users] Re: Porting a configuration file from gem5 v20 to gem5
> v21
>
> Hi Giacomo,
>
> Indeed, I was able to use
Hi Ali,
> -Original Message-
> From: Ali Ghandour via gem5-users
> Sent: 05 October 2021 15:44
> To: gem5-users@gem5.org
> Cc: Ali Ghandour
> Subject: [gem5-users] Re: Porting a configuration file from gem5 v20 to gem5
> v21
>
> In FS mode, full errror stack below:
>
> Traceback (most
Hi Carlos,
> -Original Message-
> From: Carlos Andres Lara Niño via gem5-users
> Sent: 05 October 2021 17:06
> To: gem5-users@gem5.org
> Cc: Carlos Andres Lara Niño
> Subject: [gem5-users] --machine-type=VExpress_EMM causing ports
> collision
>
> Hello,
> I'm trying to learn gem5 and
Thanks Mahita for spotting a real bug. I have posted a fix [1]; hopefully it
will be backported to gem5 v21.1
Kind regards
Giacomo
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51407
> -Original Message-
> From: Mahita Nagabhiru
> Sent: 01 October 2021 20:07
> To: Giacomo
Hi Mahita,
Could you debug it with gdb and let us know which stat gets initialized twice?
Kind Regards
Giacomo
> -Original Message-
> From: Mahita Nagabhiru
> Sent: 29 September 2021 12:00
> To: Giacomo Travaglini
> Cc: gem5 users mailing list
> Subject: Re: [gem5-users] Support for
Hi Mahita,
Yes Armv8.1-LSE is implemented and therefore you should be able to use CAS
ISA definition of CAS:
https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.isa#L226
System level switch for LSE:
https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L75
As
reason for implementing it in full system simulation only?
>
> Can we implement it in SE mode?
>
> Best regards.
>
> On Thursday, September 23, 2021, 11:04:42 AM GMT+3, Giacomo Travaglini
> via gem5-users wrote:
>
>
> Hi
>
> It has been fixed for full-system simu
Hi
It has been fixed for full-system simulation (the patch you are referring to is
providing visibility of the PMU to the linux kernel),
But the syscall in SE mode is still un-implemented.
Kind Regards
Giacomo
> -Original Message-
> From: walt_90--- via gem5-users
> Sent: 22
Hi Andreas,
Could you provide us more information about the platform you are using?
More specifically
1) Are you using any configs/example/arm based script?
2) Which bus is connected to the device DMA port?
You need a cache between the device and the coherent bus. This is why we
usually
Hi Gelin,
I understand the confusion.
Even if there are no SIMD operations, you are issuing FP operations and those
are using vector elements as
single and double precision scalar registers are elements of the SIMD vector
registers
Kind Regards
Giacomo
> -Original Message-
> From:
This is great Pedro! Thanks for the pointers, other KVM users might find it
useful.
Regarding the Linux Kernel question, there is no preferred version from our
side.
You can even build a vanilla arm64 kernel and it should just work. IIRC we
provided support until 5.8 in gem5 v21.0
Kind
Thanks Deric,
I wonder if it is linked to this problem:
https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-1074
What happens if you cross-compile for aarch64?
Kind Regards
Giacomo
> -Original Message-
> From: Deric Cheung via gem5-users
> Sent: 16 August 2021
Hi Pedro,
The MSR (immediate) is the software interface for modifying the PSTATE of the
PE.
In this case the instruction is trying to change the PSTATE.UAO field, which is
not implemented in gem5
This is why you are not able to restore the checkpoint in atomic. Implementing
UAO should fix it.
Hi Burak,
This is a python configuration problem. You need to make sure the table walker
port is connected.
Please double check the ArmMMU.walkerPorts() method is called in the FS script
Kind Regards
Giacomo
> -Original Message-
> From: Burak Öçalan via gem5-users
> Sent: 22 August
Hi Deric,
This is a known issue.
You can work around the problem in two different ways:
1) Cross-compile your program for aarch64
2) Hardcode the ISA.highestELIs64 to false as you are effectively
cross-compiling for AArch32
Kind Regards
Giacomo
> -Original Message-
> From: Deric
That is correct, you should just recompile the DTB; no need to recompile gem5
Kind Regards
Giacomo
> -Original Message-
> From: Md Rubel Ahmed via gem5-users
> Sent: 31 July 2021 10:05
> To: gem5-users@gem5.org
> Cc: Md Rubel Ahmed
> Subject: [gem5-users] VExpress_GEM5_V1, Ethernet,
Hi,
> -Original Message-
> From: Burak Öçalan via gem5-users
> Sent: 27 July 2021 17:05
> To: gem5-users@gem5.org
> Cc: Burak Öçalan
> Subject: [gem5-users] Adding ArmTLB to prefetchers
>
> Hi.
>
> I'm working on Indirect Memory Prefetcher. This prefetcher requires a TLB to
> work
Hi Preet
> -Original Message-
> From: Preet Derasari via gem5-users
> Sent: 24 July 2021 17:05
> To: gem5-users@gem5.org
> Cc: Preet Derasari
> Subject: [gem5-users] How to set data breakpoints/watchpoints in FS/SE
> modes
>
> Hi!
>
> I am trying to figure out ways in which I can use
Hi Majid,
Out of curiosity, are you sure the configuration is the same? Could you try to
rebuild the bootloader in system/arm/bootloader/arm64 and make sure the config
script is pointing to it?
(Either with M5_PATH or by using the --bootloader option)
Please let me know if this works
Kind
Hi Nikos,
The author submitted a partial implementation to gerrit (Simply modelling a
PCIe Link) some time ago:
https://gem5-review.googlesource.com/c/public/gem5/+/13024
A Root Complex and PCI Express Switch implementation was supposed to be
uploaded but this never happened as far as I know.
Hi Nikolaos, this is great!
>
> I would like to connect one gem5 to another through ssh (because I
> would like to use MPI).
>
> I have installed the openssh-client packet through qemu but I get the
> above connection refused. After that, I installed the openssh-server
> through qemu, but it is
Hi,
> -Original Message-
> From: Md Rubel Ahmed via gem5-users
> Sent: 05 July 2021 22:24
> To: gem5 users mailing list
> Cc: Md Rubel Ahmed
> Subject: [gem5-users] How to find the address range of an ARM IO device
>
> Greetings,
>
> I was trying to get the address range of each device
Hi Javed,
You are correct in your assumptions. I believe the confusion arises from the
overuse of the "System" keyword. As a summary,
The System class (defined in src/sim/system.hh) is the child of the Root node
and encompasses most of the simulated models (cpu, memory subsystem, devices,
Hi Javed
> -Original Message-
> From: Javed Osmany via gem5-users
> Sent: 09 June 2021 15:01
> To: gem5 users mailing list
> Cc: Javed Osmany
> Subject: [gem5-users] Arm bitLITTLE config
>
> Hello
>
>
>
> The system I would like to model consists of three clusters [Big, Middle,
>
Hi Jason,
At a certain point I should really come up with an ISA documentation to upload
on gem5.org
Anyway, those are magic operands defined in the operands file [1].
(More specifically [2] and [3]).
When the ISA parser detect those magic words, it translates them into an
appropriate action
Thanks Pedro,
It seems like you are getting an undefined instruction. What is probably
happening is your host CPU having a feature which is not implemented in gem5,
so when you switch to the guest(gem5) the sandboxing check is skipped and an
exception is thrown. As you are happy with your
Hi Pedro,
What happens if you try to simulate the GIC?
Have a look at what we do in fs_bigLITTLE with the --kvm-userspace-gic option.
You should be able to replicate that in fs.py (though I would recommend you to
switch to the fs_bigLITTLE script if possible )
Kind Regards
Giacomo
P.S. I
Hi Javed,
> -Original Message-
> From: Javed Osmany via gem5-users
> Sent: 18 May 2021 14:16
> To: gem5-users@gem5.org
> Cc: Javed Osmany
> Subject: [gem5-users] Using the CHI protocol for GEM5
>
> Hello
>
>
>
> Previously, when experimenting with MESI or MOESI coherence protocol,
> the
Hi Pedro, glad it worked
> -Original Message-
> From: Pedro Henrique Exenberger Becker
> Sent: 14 May 2021 10:48
> To: Giacomo Travaglini
> Cc: gem5 users mailing list
> Subject: Re: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Hi Giacomo,
>
>
>
> --little-cpus option
Hi Jason,
> -Original Message-
> From: jzell001--- via gem5-users
> Sent: 14 May 2021 00:44
> To: gem5-users@gem5.org
> Cc: jzell...@ucr.edu
> Subject: [gem5-users] Tracing Instructions in gem5 (re: Adding a New
> Instruction)
>
> Hi Everyone,
>
> I am fairly new to gem5, so I apologize
Hi Pedro
> The main problem I still have is fs_bigLITTLE.py with --big-cpus 8 (I want to
> have an 8-core setup) causes panic:
> info: Using bootloader at address 0x10
> info: Using kernel entry physical address at 0x8008
> info: Loading DTB file: m5out/system.dtb at address 0x8800
>
Hi
> -Original Message-
> From: Đức Anh via gem5-users
> Sent: 11 May 2021 13:34
> To: gem5 users mailing list
> Cc: Đức Anh
> Subject: [gem5-users] Qemu equivalent command/simulation to Gem5
>
> Dear all,
>
> I have a Linux kernel v5.10.27 build for arm64 architecture that is runnable
Hi Adrian,
I don't know to be honest why this is happening in fs.py only.
In general, have you tried to recompile the gem5 bootloader or alternatively to
download the latest precompiled version? [1]
Kind Regards
Giacomo
[1]:
Hi Adrian,
> -Original Message-
> From: adrian via gem5-users
> Sent: 07 May 2021 09:36
> To: gem5-users@gem5.org
> Cc: adrian.barre...@gmail.com
> Subject: [gem5-users] Ruby in Arm?
>
> Hi guys,
>
> I've always used the classic memory model when running timing simulations
> using Arm,
Yes, that is correct
Kind Regards
Giacomo
> -Original Message-
> From: Taiyu Zhou via gem5-users
> Sent: 28 April 2021 13:12
> To: gem5-users@gem5.org
> Cc: Taiyu Zhou
> Subject: [gem5-users] Re: How to use HTM in gem5-20?
>
> Thank you so much for your reply.
> So, is it gem5-20
Hi,
Arm has provided an HTM implementation.
I suggest you to have a look at the following blog post by Timothy Hayes (he
wrote the implementation)
http://www.gem5.org/project/2020/10/27/tme.html
Kind Regards
Giacomo
> -Original Message-
> From: Taiyu Zhou via gem5-users
> Sent: 28
FYI the debug flag option is
--debug-flags=SyscallAll
Kind Regards
Giacomo
> -Original Message-
> From: Gabe Black via gem5-users
> Sent: 21 April 2021 01:20
> To: gem5 users mailing list
> Cc: Gabe Black
> Subject: [gem5-users] Re: ARM and opening a file
>
> If this works on x86,
I believe it just takes a lot of time (I have been noticing the same).
Could you try to wait for completion?
Kind Regards
Giacomo
> -Original Message-
> From: VAIDYA ROHINI VILAS via gem5-users
> Sent: 20 April 2021 06:32
> To: gem5 users mailing list
> Cc: VAIDYA ROHINI VILAS
>
Hi Wenqi
> -Original Message-
> From: wq...@utexas.edu
> Sent: 09 April 2021 23:07
> To: Giacomo Travaglini ; gem5 users mailing
> list
> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>
> Hi Giacomo,
>
> Thanks for letting me know what the problem is, I am
Hi Wenqi,
I have found the problem; in order to fix it you should recompile the
bootloaders from system/arm/bootloader/arm64 and replace all of them with the
ones in M5_PATH/binaries
That solves the problem on my side.
I am gonna update the guest binaries tarball in gem5.org (I was going to do
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