[gem5-users] Destructor invocation
Hello everyone, I am trying to profile some information while running an application on gem5 using classic cache model. I have added a data structure in the BaseCache class file (src/mem/cache/base.cc <http://base.cc/>). I would like to print the contents of the data structure at the end of the simulation. I don’t see any prints from the BaseCache class destructor at the end of the simulation. How are the BaseCache class objects being destroyed? I tried printing the contents of the data structure within the OutputStream class destructor, I could see the prints, however the data structure was freed by then. When does gem5 free user defined data structures defined within base.cc <http://base.cc/>? Thanks in advance. With regards Shyam Murthy Computer Science UW Madison ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Addition of gem5 x86 instructions
Thanks a lot for the clarification Gabe. Thanks, Shyam On Sun, Mar 31, 2019 at 6:29 AM Gabe Black wrote: > Hi Shyam. There are float to integer and integer to float conversion > microops in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which > is short for convert. You can definitely implement new instructions and > submit the code for review. There are instructions in the CONTRIBUTING.md > file in the root of the gem5 source tree. > > Gabe > > On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy > wrote: > >> Apologize for the wrong title in my previous email. Correcting. >> >> Thanks, >> Shyam >> >> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy >> wrote: >> >>> Hi Gabe, >>> >>> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some >>> unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to >>> name a few. I see that within the *src/arch/x86/isa/insts/x87/* >>> *arithmetic* folder, there are placeholder files to write >>> implementations for some of the macro operations, like square root and >>> rounding. Can I write my implementations and have my code reviewed, so that >>> it can be checked in? >>> In addition, for float to integer operation, I did not find any >>> corresponding micro-op in the folder *src/arch/x86/isa/microops, *is >>> there already a corresponding micro-op (that I missed), or should I write >>> my own? >>> >>> Thanks, >>> Shyam >>> >> ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Addition of gem5 x86 instructions
Hi Gabe,
I wrote this implementation for the frndint macroop:
*def macroop FRNDINT {cvtf_d2i st(0), st(0)};*
However, when I run the application using this instruction on gem5, I seem
to get this error:* gem5.opt: build/X86/cpu/simple_thread.hh:251: RegVal
SimpleThread::readIntReg(int): Assertion `flatIndex < TheISA::NumIntRegs'
failed.*
I just wanted to know what I was missing in my implementation for FRNDINT
macroop?
Thanks,
Shyam
On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy
wrote:
> Thanks a lot for the clarification Gabe.
>
> Thanks,
> Shyam
>
> On Sun, Mar 31, 2019 at 6:29 AM Gabe Black wrote:
>
>> Hi Shyam. There are float to integer and integer to float conversion
>> microops in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which
>> is short for convert. You can definitely implement new instructions and
>> submit the code for review. There are instructions in the CONTRIBUTING.md
>> file in the root of the gem5 source tree.
>>
>> Gabe
>>
>> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy
>> wrote:
>>
>>> Apologize for the wrong title in my previous email. Correcting.
>>>
>>> Thanks,
>>> Shyam
>>>
>>> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy
>>> wrote:
>>>
>>>> Hi Gabe,
>>>>
>>>> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
>>>> unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to
>>>> name a few. I see that within the *src/arch/x86/isa/insts/x87/*
>>>> *arithmetic* folder, there are placeholder files to write
>>>> implementations for some of the macro operations, like square root and
>>>> rounding. Can I write my implementations and have my code reviewed, so that
>>>> it can be checked in?
>>>> In addition, for float to integer operation, I did not find any
>>>> corresponding micro-op in the folder *src/arch/x86/isa/microops, *is
>>>> there already a corresponding micro-op (that I missed), or should I write
>>>> my own?
>>>>
>>>> Thanks,
>>>> Shyam
>>>>
>>>
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[gem5-users] Addition of gem5 x86 instructions
Apologize for the wrong title in my previous email. Correcting. Thanks, Shyam On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy wrote: > Hi Gabe, > > As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some > unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to name > a few. I see that within the *src/arch/x86/isa/insts/x87/**arithmetic* > folder, there are placeholder files to write implementations for some of > the macro operations, like square root and rounding. Can I write my > implementations and have my code reviewed, so that it can be checked in? > In addition, for float to integer operation, I did not find any > corresponding micro-op in the folder *src/arch/x86/isa/microops, *is > there already a corresponding micro-op (that I missed), or should I write > my own? > > Thanks, > Shyam > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] gabebl...@google.com
Hi Gabe, As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to name a few. I see that within the *src/arch/x86/isa/insts/x87/**arithmetic* folder, there are placeholder files to write implementations for some of the macro operations, like square root and rounding. Can I write my implementations and have my code reviewed, so that it can be checked in? In addition, for float to integer operation, I did not find any corresponding micro-op in the folder *src/arch/x86/isa/microops, *is there already a corresponding micro-op (that I missed), or should I write my own? Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPEC 2017 runs on gem5
Hi Jason, Any thoughts on this? Thanks, Shyam > On Mar 8, 2019, at 4:26 PM, Shyam Murthy wrote: > > Hi All, > > When I am running a lot of the SPEC '17 applications on gem5, I am getting a > warning message that says warn: instruction 'movntdq_Mo_Vo' unimplemented. > The source code for the binary does not seem to indicate the usage of the > movntdq instruction. > I assume it is the glibc that is using this instruction, because of > indication from the cpuid that there is support for SSE2. I tried disabling > both the bits for SSE2 and SSE in the edx register, which ought to cause > glibc to not use the binary that contains the same instruction, but I > continue to see the same error. Is there something I am missing? Or is there > an easier workaround? > > Thanks, > Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] SPEC 2017 runs on gem5
Hi All, When I am running a lot of the SPEC '17 applications on gem5, I am getting a warning message that says *warn: instruction 'movntdq_Mo_Vo' unimplemented*. The source code for the binary does not seem to indicate the usage of the movntdq instruction. I assume it is the glibc that is using this instruction, because of indication from the cpuid that there is support for SSE2. I tried disabling both the bits for SSE2 and SSE in the edx register, which ought to cause glibc to not use the binary that contains the same instruction, but I continue to see the same error. Is there something I am missing? Or is there an easier workaround? Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPEC 2017 runs on gem5
Hi, I am using se.py within config/example. Thanks, Shyam > On Mar 11, 2019, at 11:42 PM, SM Farabi Mahmud wrote: > > Can you share the configuration file that you're using? > > On Fri, Mar 8, 2019, 4:26 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote: > Hi All, > > When I am running a lot of the SPEC '17 applications on gem5, I am getting a > warning message that says warn: instruction 'movntdq_Mo_Vo' unimplemented. > The source code for the binary does not seem to indicate the usage of the > movntdq instruction. > I assume it is the glibc that is using this instruction, because of > indication from the cpuid that there is support for SSE2. I tried disabling > both the bits for SSE2 and SSE in the edx register, which ought to cause > glibc to not use the binary that contains the same instruction, but I > continue to see the same error. Is there something I am missing? Or is there > an easier workaround? > > Thanks, > Shyam > ___ > gem5-users mailing list > gem5-users@gem5.org <mailto:gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Addition of gem5 x86 instructions
Hi Gabe,
Any thoughts on the below?
Thanks,
Shyam
> On Apr 13, 2019, at 10:21 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> One additional question, regarding another instruction I was trying to
> implement (FCMOVNBE).
> I thought of emulating a sequence similar what we have for CMOVNBE.
> def macroop CMOVNBE_R_R
>
> {
>
> mov reg, reg, reg, flags=(CCvZF,)
>
> mov reg, reg, regm, flags=(nCCvZF,)
>
> };
>
>
>
> def macroop CMOVNBE_R_M
>
> {
>
> ld t1, seg, sib, disp
>
> mov reg, reg, reg, flags=(CCvZF,)
>
> mov reg, reg, t1, flags=(nCCvZF,)
>
> };
>
>
>
> def macroop CMOVNBE_R_P
>
> {
>
> rdip t7
>
> ld t1, seg, riprel, disp
>
> mov reg, reg, reg, flags=(CCvZF,)
>
> mov reg, reg, t1, flags=(nCCvZF,)
>
> };
>
> However, I think this implementation is made easier because of the usage of
> the mov microop which seems to be a condRegOp. However movfp being a
> FPUnaryOp, I assume I can’t translate a similar sequence using movfp for
> FCMOVNBE. Is there an alternate microop I can make use of, or should I
> implement a microop or is there an alternate workaround?
>
>
> Thanks,
> Shyam
>> On Apr 13, 2019, at 6:57 PM, Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote:
>>
>> Hi Gabe,
>>
>> Thanks for the help with the FRNDINT instruction.
>> I was trying to implement another instruction, namely FISTP. This was my
>> initial implementation
>> def macroop FISTP {
>> cvtf_d2i t1, st(0)
>> movfp st(0), t1
>> pop87
>> };
>> But I think the instruction writes to a destination, I was unsure how to
>> specify the same. (which I will have to specify in place of highlighted
>> st(0) here)
>> Is this approach correct for this instruction, because I thought it was
>> similar to FRNDINT otherwise, with the addition of extra POP instruction to
>> pop st(0)?
>>
>> Thanks,
>> Shyam
>>
>>
>> On Sun, Apr 7, 2019 at 2:23 AM Gabe Black > <mailto:gabebl...@google.com>> wrote:
>> Hy Shyam. That microop takes a floating point register as it's source and an
>> integer register as its destination. You're passing in two floating point
>> indexes which won't work. To avoid implementing a new microop (too many
>> microops is probably not realistic), you could use the mov2fp microop to
>> move the newly converted value in an integer microcode only register (like
>> t1, for instance) back into an FP register like st(0).
>>
>> Gabe
>>
>> On Fri, Apr 5, 2019 at 6:53 PM Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote:
>> Hi Gabe,
>>
>> I wrote this implementation for the frndint macroop:
>> def macroop FRNDINT {
>> cvtf_d2i st(0), st(0)
>> };
>>
>> However, when I run the application using this instruction on gem5, I seem
>> to get this error: gem5.opt: build/X86/cpu/simple_thread.hh:251: RegVal
>> SimpleThread::readIntReg(int): Assertion `flatIndex < TheISA::NumIntRegs'
>> failed.
>> I just wanted to know what I was missing in my implementation for FRNDINT
>> macroop?
>>
>> Thanks,
>> Shyam
>>
>>
>> On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote:
>> Thanks a lot for the clarification Gabe.
>>
>> Thanks,
>> Shyam
>>
>> On Sun, Mar 31, 2019 at 6:29 AM Gabe Black > <mailto:gabebl...@google.com>> wrote:
>> Hi Shyam. There are float to integer and integer to float conversion
>> microops in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which
>> is short for convert. You can definitely implement new instructions and
>> submit the code for review. There are instructions in the CONTRIBUTING.md
>> file in the root of the gem5 source tree.
>>
>> Gabe
>>
>> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote:
>> Apologize for the wrong title in my previous email. Correcting.
>>
>> Thanks,
>> Shyam
>>
>> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy > &
[gem5-users] Query regarding CPU Switching
Hi Jason,
I am trying to hit the start of the ROI for an application and then switch
to the Detailed CPU. For this, I wrote my version of the run function in
Simulation.py. I am able to successfully intercept the start of workbegin,
however I am unable to successfully CPUs.
*def run1(options, root, testsys, cpu_call):cptdir = getcwd()
maxtick = m5.MaxTickroot.apply_config(options.param)checkpoint_dir
= Nonem5.instantiate(checkpoint_dir)# the number of cpusnp =
options.num_cpusswitch_cpus = Noneswitch_cpus_1 = None
switch_cpus = [TimingSimpleCPU(switched_out=True,
cpu_id=(i)) for i in xrange(np)]switch_cpus_1 =
[DerivO3CPU(switched_out=True, cpu_id=(i))for i in
xrange(np)]for i in xrange(np):switch_cpus[i].system =
testsysswitch_cpus_1[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus_1[i].workload = testsys.cpu[i].workload
switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain
switch_cpus[i].isa = testsys.cpu[i].isaswitch_cpus_1[i].isa =
testsys.cpu[i].isawhile True:exit_event = m5.simulate()
exit_cause = exit_event.getCause()testsys.switch_cpus =
switch_cpus_1# testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus_1[i]) for i in
xrange(np)] # switch_cpu_list_1 = [(testsys.cpu[i], switch_cpus_1[i])
for i in xrange(np)]if exit_cause == "workbegin":
print("Switched CPUS @ tick on hitting ROI %s" % (m5.curTick()))
m5.switchCpus(testsys, switch_cpu_list)elif exit_cause ==
"workend":print("Reached ROI end")break
print(exit_event.getCause())*
The above is my function. It correctly captures the workbegin, however it
throws an error related to the new CPU it tried to switch to:
* File "", line 1, in File
"/afs/cs.wisc.edu/u/s/h/shyamm/gem5_2/src/python/m5/main.py
", line 438,
in mainexec(filecode, scope) File "configs/example/se.py", line 274,
in Simulation.run1(options, root, system, FutureClass) File
"/afs/cs.wisc.edu/u/s/h/shyamm/gem5_2/configs/common/Simulation.py
",
line 467, in run1m5.switchCpus(testsys, switch_cpu_list) File
"/afs/cs.wisc.edu/u/s/h/shyamm/gem5_2/src/python/m5/simulate.py
", line
275, in switchCpusif not new_cpu.switchedOut(): File
"/afs/cs.wisc.edu/u/s/h/shyamm/gem5_2/src/python/m5/SimObject.py
", line
1204, in __getattr__raise AttributeError(err_string)AttributeError:
object 'DerivO3CPU' has no attribute 'switchedOut' (C++ object is not yet
constructed, so wrapped C++ methods are unavailable.)*
The python bind does happen in the BaseCPU.py file for switchedOut
function, I was unable to follow why this exception is still being thrown.
Anything I am missing Jason?
Thanks,
Shyam
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Re: [gem5-users] Addition of gem5 x86 instructions
Hi Gabe,
One additional question, regarding another instruction I was trying to
implement (FCMOVNBE).
I thought of emulating a sequence similar what we have for CMOVNBE.
def macroop CMOVNBE_R_R
{
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
However, I think this implementation is made easier because of the usage of the
mov microop which seems to be a condRegOp. However movfp being a FPUnaryOp, I
assume I can’t translate a similar sequence using movfp for FCMOVNBE. Is there
an alternate microop I can make use of, or should I implement a microop or is
there an alternate workaround?
Thanks,
Shyam
> On Apr 13, 2019, at 6:57 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> Thanks for the help with the FRNDINT instruction.
> I was trying to implement another instruction, namely FISTP. This was my
> initial implementation
> def macroop FISTP {
> cvtf_d2i t1, st(0)
> movfp st(0), t1
> pop87
> };
> But I think the instruction writes to a destination, I was unsure how to
> specify the same. (which I will have to specify in place of highlighted st(0)
> here)
> Is this approach correct for this instruction, because I thought it was
> similar to FRNDINT otherwise, with the addition of extra POP instruction to
> pop st(0)?
>
> Thanks,
> Shyam
>
>
> On Sun, Apr 7, 2019 at 2:23 AM Gabe Black <mailto:gabebl...@google.com>> wrote:
> Hy Shyam. That microop takes a floating point register as it's source and an
> integer register as its destination. You're passing in two floating point
> indexes which won't work. To avoid implementing a new microop (too many
> microops is probably not realistic), you could use the mov2fp microop to move
> the newly converted value in an integer microcode only register (like t1, for
> instance) back into an FP register like st(0).
>
> Gabe
>
> On Fri, Apr 5, 2019 at 6:53 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> Hi Gabe,
>
> I wrote this implementation for the frndint macroop:
> def macroop FRNDINT {
> cvtf_d2i st(0), st(0)
> };
>
> However, when I run the application using this instruction on gem5, I seem to
> get this error: gem5.opt: build/X86/cpu/simple_thread.hh:251: RegVal
> SimpleThread::readIntReg(int): Assertion `flatIndex < TheISA::NumIntRegs'
> failed.
> I just wanted to know what I was missing in my implementation for FRNDINT
> macroop?
>
> Thanks,
> Shyam
>
>
> On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> Thanks a lot for the clarification Gabe.
>
> Thanks,
> Shyam
>
> On Sun, Mar 31, 2019 at 6:29 AM Gabe Black <mailto:gabebl...@google.com>> wrote:
> Hi Shyam. There are float to integer and integer to float conversion microops
> in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which is short
> for convert. You can definitely implement new instructions and submit the
> code for review. There are instructions in the CONTRIBUTING.md file in the
> root of the gem5 source tree.
>
> Gabe
>
> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> Apologize for the wrong title in my previous email. Correcting.
>
> Thanks,
> Shyam
>
> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> Hi Gabe,
>
> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
> unimplemented instructions namely frndint, fsqrt and fistp to name a few. I
> see that within the src/arch/x86/isa/insts/x87/arithmetic folder, there are
> placeholder files to write implementations for some of the macro operations,
> like square root and rounding. Can I write my implementations and have my
> code reviewed, so that it can be checked in?
> In addition, for float to integer operation, I did not find any corresponding
> micro-op in the folder src/arch/x86/isa/microops, is there already a
> corresponding micro-op (that I missed), or should I write my own?
>
> Thanks,
> Shyam
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Re: [gem5-users] Addition of gem5 x86 instructions
Hi Gabe,
Thanks for the help with the FRNDINT instruction.
I was trying to implement another instruction, namely *FISTP. *This was my
initial implementation
def macroop FISTP {
cvtf_d2i t1, st(0)
movfp *st(0)*, t1
pop87
};
But I think the instruction writes to a destination, I was unsure how to
specify the same. (which I will have to specify in place of highlighted
st(0) here)
Is this approach correct for this instruction, because I thought it was
similar to FRNDINT otherwise, with the addition of extra POP instruction to
pop st(0)?
Thanks,
Shyam
On Sun, Apr 7, 2019 at 2:23 AM Gabe Black wrote:
> Hy Shyam. That microop takes a floating point register as it's source and
> an integer register as its destination. You're passing in two floating
> point indexes which won't work. To avoid implementing a new microop (too
> many microops is probably not realistic), you could use the mov2fp microop
> to move the newly converted value in an integer microcode only register
> (like t1, for instance) back into an FP register like st(0).
>
> Gabe
>
> On Fri, Apr 5, 2019 at 6:53 PM Shyam Murthy
> wrote:
>
>> Hi Gabe,
>>
>> I wrote this implementation for the frndint macroop:
>>
>>
>> *def macroop FRNDINT {cvtf_d2i st(0), st(0)};*
>>
>> However, when I run the application using this instruction on gem5, I
>> seem to get this error:* gem5.opt: build/X86/cpu/simple_thread.hh:251:
>> RegVal SimpleThread::readIntReg(int): Assertion `flatIndex <
>> TheISA::NumIntRegs' failed.*
>> I just wanted to know what I was missing in my implementation for FRNDINT
>> macroop?
>>
>> Thanks,
>> Shyam
>>
>>
>> On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy
>> wrote:
>>
>>> Thanks a lot for the clarification Gabe.
>>>
>>> Thanks,
>>> Shyam
>>>
>>> On Sun, Mar 31, 2019 at 6:29 AM Gabe Black wrote:
>>>
>>>> Hi Shyam. There are float to integer and integer to float conversion
>>>> microops in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which
>>>> is short for convert. You can definitely implement new instructions and
>>>> submit the code for review. There are instructions in the CONTRIBUTING.md
>>>> file in the root of the gem5 source tree.
>>>>
>>>> Gabe
>>>>
>>>> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy
>>>> wrote:
>>>>
>>>>> Apologize for the wrong title in my previous email. Correcting.
>>>>>
>>>>> Thanks,
>>>>> Shyam
>>>>>
>>>>> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy
>>>>> wrote:
>>>>>
>>>>>> Hi Gabe,
>>>>>>
>>>>>> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
>>>>>> unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to
>>>>>> name a few. I see that within the *src/arch/x86/isa/insts/x87/*
>>>>>> *arithmetic* folder, there are placeholder files to write
>>>>>> implementations for some of the macro operations, like square root and
>>>>>> rounding. Can I write my implementations and have my code reviewed, so
>>>>>> that
>>>>>> it can be checked in?
>>>>>> In addition, for float to integer operation, I did not find any
>>>>>> corresponding micro-op in the folder *src/arch/x86/isa/microops, *is
>>>>>> there already a corresponding micro-op (that I missed), or should I write
>>>>>> my own?
>>>>>>
>>>>>> Thanks,
>>>>>> Shyam
>>>>>>
>>>>>
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Re: [gem5-users] Execute function for instructions in O3 CPU model
Thanks for the information Ciro. Thanks, Shyam On Sun, May 19, 2019 at 3:07 PM Ciro Santilli wrote: > On Sun, May 19, 2019 at 8:04 PM Shyam Murthy > wrote: > > > > Hi Gabe, > > > > Within the file src/cpu/o3/iew_impl.hh, there is a call made to execute > function within the dynamic inst class (inst->execute()). I was trying to > lookup the function definition for this, but I could only find the function > prototype within src/cpu/o3/dyn_inst.hh (Fault execute()). Where can I look > for the function definition? > > > > gem5 uses code generation heavily for cpu decode and execute. grep -r > inside the build folder and you will find all definitions there on > generated code. Then git grep identifiers, or pieces of identifiers on > source tree to try and figure out which .isa file they come from. > > > Thanks, > > Shyam > > ___ > > gem5-users mailing list > > gem5-users@gem5.org > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Execute function for instructions in O3 CPU model
Hi Gabe, Within the file src/cpu/o3/iew_impl.hh, there is a call made to execute function within the dynamic inst class (inst->execute()). I was trying to lookup the function definition for this, but I could only find the function prototype within src/cpu/o3/dyn_inst.hh (Fault execute()). Where can I look for the function definition? Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPECCPU 2006 application crashes on x86 gem5
Thanks a lot for the inputs, Gururaj and Gabe. Thanks, Shyam On Mon, Jul 1, 2019 at 1:21 AM Saileshwar, Gururaj wrote: > Hi Shyam, > > I also faced this issue with “movntdq_Mo_Vo” in the recent past when I > was trying to compile and run SPEC2006 with Gem5. > > I managed to debug it to some extent – the source of these unimplemented > instructions is likely one of the linked libraries (mostly glibc) that the > binary uses. > > While I didn’t manage to find a fix, I got a work-around: I compiled my > binaries with static linking (-static flag to linker) on a older system > that apparently did not use this instruction. Subsequently, those binaries > also worked with Gem5 on my newer system where I was originally facing this > issue. Sorry, I am unable to give you precise versions of the SW I used – I > no longer have access. > > Hope this helps! > Gururaj > > From: gem5-users on behalf of Gabe Black < > gabebl...@google.com> > Reply-To: gem5 users mailing list > Date: Sunday, June 30, 2019 at 10:42 PM > To: Shyam Murthy > Cc: gem5 users mailing list > Subject: Re: [gem5-users] SPECCPU 2006 application crashes on x86 gem5 > > Hi Shyam. Part of the issue is an unfortunate aspect of how gcc works > where there are some components that are built when gcc itself is > built/installed which use certain settings, and if you link against them > later (which gcc will do implicitly/automatically in at least a couple > cases) those settings won't change and you can get, for instance, > instructions that you'd turned off. There can be even bigger issues if you > change flags that break ABI compatibility since those libraries won't work > at all instead of just disregarding your settings. > > There are apparently also header files which get pulled in which use > features you can technically disable, but disabling them breaks those > headers. > > I think the linked thread is probably where someone was using instructions > which were too new to be supported, but in your case I think (without > having the time to check for sure) that that instruction isn't supported > because it's the non-temporal version, and there isn't (or at least wasn't) > a good way to implement that behavior. I vaguely remember adding a flag > which disabled caching which you might find if you look at the repository > history or archived emails, so it may be possible to implement that > instruction properly now. > > Gabe > > On Sun, Jun 30, 2019 at 4:38 PM Shyam Murthy > wrote: > >> Hi, >> >> Additionally, I also tried using the -mno-sse2 flag, with which it >> compiles, but the error persists. However, when I tried to compile using >> the -mno-sse flag, then compilation fails saying: >> >> */usr/include/x86_64-linux-gnu/bits/stdlib-float.h: In function 'atof': >> /usr/include/x86_64-linux-gnu/bits/stdlib-float.h:26:1: error: SSE register >> return with SSE disabled* >> >> Thanks, >> Shyam >> >> On Sun, Jun 30, 2019 at 3:24 PM Shyam Murthy >> wrote: >> >>> Hi, >>> >>> This is slightly different, there is no panic message here. However, >>> this instruction is unimplemented, but is required by the application for >>> its execution, causing it to abort. As in your link, Gabe mentions that we >>> need to tell the compiler not to use this instruction. I was unsure how to >>> achieve the same, I tried passing the -msse flag to gcc during compilation, >>> but the movntdq instruction still seems to be getting generated. >>> >>> Thanks, >>> Shyam >>> >>> On Sun, Jun 30, 2019 at 1:06 PM Kleovoulos Kalaitzidis < >>> kleovoulos.kalaitzi...@inria.fr> wrote: >>> >>>> Hello, >>>> it is normal to get these warnings for unimplemented instructions. >>>> However, in my experience, these warnings are not the case for aborting. >>>> Normally some panic message follows, but maybe not related to this "warn". >>>> For instance, there is the case of avx instructions that are not >>>> implemented and will abort the execution : >>>> https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode >>>> >>>> Regards, >>>> >>>> -- >>>> Kleovoulos Kalaitzidis >>>> Doctorant - Équipe PACAP >>>> >>>> Centre de recherche INRIA Rennes - Bretagne Atlantique >>>> Bâtiment 12E, Bureau E321, Campus de Beaulieu, >>>> 35042 Rennes Cedex, France >>>> >>>> -- >>>> >>>> *From: *"Shyam M
Re: [gem5-users] x86 instruction decoding
Hi Gabe, I was reading through this today (https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf#page=129). Within gem5 however, for instructions MOVZX_B_R_M and MOVZX_W_R_M, the translated microops are such that they entail partial register stalls, because they are translated into load byte and load word, which in turn cause a partial register stall. However, the usage of MOVZX/MOVSX instruction were specifically optimizations developers and compilers use to eliminate these partial register stalls. So, is the current modeling not overly conservative? My main concern also came from an application, where the compiler generates load bytes zero extending them to 32 bits (as per the optimization), but gem5 still generates stalls because of the load byte microop. I think this might have to be slightly remodeled I guess, but only place being conservative and needing a stall might be when zero extension happens into 16 bits. Let me know if you feel my thinking is correct. Thanks, Shyam > On Aug 1, 2019, at 3:38 PM, Gabe Black wrote: > > There is no way to disable that. The number and identity of the instructions > sources/destinations would need to change based on the operand size, and > that's not implemented. You could possibly add extra information to the > microops to help determine when that sort of thing is happening. All the > microops that do partial register updates have that behavior (so most of > them), not just lea. > > Gabe > > On Wed, Jul 31, 2019 at 8:06 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote: > Thanks Gabe, suppose I’m trying to carry out a data flow analysis on the > program, then quite often I rely on the source registers tagged by gem5. In > this process, would I not be tracking false dependencies? Is there a way I > can disable this? > > Additionally, have you modelled the same only for LEA op, or for other > operations too? You were making a call to merge method within the static inst > class, I assumed this was because x86 has a lot of instructions like ADD AX, > imm, where the source register is clobbered with the output as well. However, > I guess primarily you have made calls to the merge method within the static > inst class to also model partial register updates. > > Thanks, > Shyam > >> On Jul 31, 2019, at 9:03 PM, Gabe Black > <mailto:gabebl...@google.com>> wrote: >> >> Hi Shyam. I think the reason is that x86 instructions (and the microops as >> I've implemented them) can do partial register updates, ie writing to only >> the lowest byte of a register. In that case, you need the old value to fill >> in part of the new value of the register. When writing to 32 bits or more of >> the register (although x86 is full of exceptions), you'd generally not need >> the old value since you're either writing all 64 bits or zero extending to >> 64 bits in the 32 bit case. That optimization is not implemented, and may or >> may not be realistic. >> >> Gabe >> >> On Tue, Jul 30, 2019 at 2:40 PM Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote: >> The main reason I am asking is because I am trying to do some dependency >> analysis in the programs, and false dependencies show up in the process >> because architecture registers that are destination registers also get >> populated as source registers (when there is no true dependency). Am I >> understanding something incorrectly? >> >> Thanks, >> Shyam >> >> On Tue, Jul 30, 2019 at 2:25 PM Shyam Murthy > <mailto:shyammurth...@gmail.com>> wrote: >> Hi Gabe, >> >> Why is that for some of the operations like ld and lea, the decoding logic >> within build/X86/arch/generated/decoder-ns.cc.inc, the destination register >> is also decoded as a src register? >> >> Thanks, >> Shyam >> ___ >> gem5-users mailing list >> gem5-users@gem5.org <mailto:gem5-users@gem5.org> >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> > ___ > gem5-users mailing list > gem5-users@gem5.org <mailto:gem5-users@gem5.org> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Load schedule in O3 CPU
Hi All, I had a couple of questions about how loads are scheduled in O3 CPU on gem5. Does the instruction schedule happen for a load expecting a cache hit? Is there a replay in case of a miss? I see that code defers memory instructions on a TLB miss. Is there similar code that handles loads that miss in the cache? Thanks for the help in advance. Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] Load schedule in O3 CPU
Hi Gururaj, Yes, that was my question. I was reading through this old post on the mail archive (https://www.mail-archive.com/gem5-users@gem5.org/msg08525.html <https://www.mail-archive.com/gem5-users@gem5.org/msg08525.html>). I was trying to see if I could find the modeling for cache miss replay in the O3 code base, but I was unable to. Thanks, Shyam On Fri, Aug 16, 2019 at 8:04 PM Saileshwar, Gururaj mailto:gurura...@gatech.edu>> wrote: Hi Shyam, If I understand your question correctly, you are wondering whether it supports speculative scheduling? Based on my limited understanding of the DerivO3CPU scheduler, I think the scheduling policy only schedules a instruction once it knows all its dependencies are ready. I don’t think it speculatively schedules subsequent instructions dependent on a load, predicting that the load hits in the cache. More experienced folks may correct me if I am wrong. Cheers, Gururaj From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Shyam Murthy mailto:shyammurth...@gmail.com>> Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>> Date: Friday, August 16, 2019 at 4:50 PM To: gem5 users mailing list mailto:gem5-users@gem5.org>> Subject: [gem5-users] Load schedule in O3 CPU Hi All, I had a couple of questions about how loads are scheduled in O3 CPU on gem5. Does the instruction schedule happen for a load expecting a cache hit? Is there a replay in case of a miss? I see that code defers memory instructions on a TLB miss. Is there similar code that handles loads that miss in the cache? Thanks for the help in advance. Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org <mailto:gem5-users@gem5.org> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users <http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Classic cache write buffer entries
Hi All, I had one question regarding write buffers in Classic cache. When we have a write back operation, the assumption is that we will find an entry to place the block that is to be written back. There seems to be an assert within src/mem/cache/write_queue.cc file (*assert(!freeList.empty())*). I assume, if we make any microarchitectural change that induces more writebacks, then I guess the simulator will not stall, but the assert would fire instead? Is my understanding correct? If I am making such a microarchitectural change, then I assume my options are to either increase writebuffer entries from the default, or force a stall at that point (which I am not too sure how to do). Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] x86 instruction decoding
Hi Gabe, Why is that for some of the operations like ld and lea, the decoding logic within *build/X86/arch/generated/decoder-ns.cc.inc, *the destination register is also decoded as a src register? Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] x86 instruction decoding
The main reason I am asking is because I am trying to do some dependency analysis in the programs, and false dependencies show up in the process because architecture registers that are destination registers also get populated as source registers (when there is no true dependency). Am I understanding something incorrectly? Thanks, Shyam On Tue, Jul 30, 2019 at 2:25 PM Shyam Murthy wrote: > Hi Gabe, > > Why is that for some of the operations like ld and lea, the decoding logic > within *build/X86/arch/generated/decoder-ns.cc.inc, *the destination > register is also decoded as a src register? > > Thanks, > Shyam > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] x86 instruction decoding
Thanks Gabe, suppose I’m trying to carry out a data flow analysis on the program, then quite often I rely on the source registers tagged by gem5. In this process, would I not be tracking false dependencies? Is there a way I can disable this? Additionally, have you modelled the same only for LEA op, or for other operations too? You were making a call to merge method within the static inst class, I assumed this was because x86 has a lot of instructions like ADD AX, imm, where the source register is clobbered with the output as well. However, I guess primarily you have made calls to the merge method within the static inst class to also model partial register updates. Thanks, Shyam > On Jul 31, 2019, at 9:03 PM, Gabe Black wrote: > > Hi Shyam. I think the reason is that x86 instructions (and the microops as > I've implemented them) can do partial register updates, ie writing to only > the lowest byte of a register. In that case, you need the old value to fill > in part of the new value of the register. When writing to 32 bits or more of > the register (although x86 is full of exceptions), you'd generally not need > the old value since you're either writing all 64 bits or zero extending to 64 > bits in the 32 bit case. That optimization is not implemented, and may or may > not be realistic. > > Gabe > > On Tue, Jul 30, 2019 at 2:40 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote: > The main reason I am asking is because I am trying to do some dependency > analysis in the programs, and false dependencies show up in the process > because architecture registers that are destination registers also get > populated as source registers (when there is no true dependency). Am I > understanding something incorrectly? > > Thanks, > Shyam > > On Tue, Jul 30, 2019 at 2:25 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote: > Hi Gabe, > > Why is that for some of the operations like ld and lea, the decoding logic > within build/X86/arch/generated/decoder-ns.cc.inc, the destination register > is also decoded as a src register? > > Thanks, > Shyam > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPECCPU 2006 application crashes on x86 gem5
Hi, This is slightly different, there is no panic message here. However, this instruction is unimplemented, but is required by the application for its execution, causing it to abort. As in your link, Gabe mentions that we need to tell the compiler not to use this instruction. I was unsure how to achieve the same, I tried passing the -msse flag to gcc during compilation, but the movntdq instruction still seems to be getting generated. Thanks, Shyam On Sun, Jun 30, 2019 at 1:06 PM Kleovoulos Kalaitzidis < kleovoulos.kalaitzi...@inria.fr> wrote: > Hello, > it is normal to get these warnings for unimplemented instructions. > However, in my experience, these warnings are not the case for aborting. > Normally some panic message follows, but maybe not related to this "warn". > For instance, there is the case of avx instructions that are not > implemented and will abort the execution : > https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode > > Regards, > > -- > Kleovoulos Kalaitzidis > Doctorant - Équipe PACAP > > Centre de recherche INRIA Rennes - Bretagne Atlantique > Bâtiment 12E, Bureau E321, Campus de Beaulieu, > 35042 Rennes Cedex, France > > -- > > *From: *"Shyam Murthy" > *To: *"gem5 users mailing list" > *Sent: *Sunday, June 30, 2019 7:02:37 PM > *Subject: *[gem5-users] SPECCPU 2006 application crashes on x86 gem5 > > Hi All, > I am trying to run some of the FP applications from SPECCPU 2006. However, > for some of these applications (like povray, tonto), I get an error that > says: > > warn: instruction 'movntdq_Mo_Vo' unimplemented. > > I am compiling these applications on my machine, and then running them on > x86 gem5. My machine uses gcc version 7.4.0. I tried using gcc version 5.5 > (already installed on my machine), but the problem persists. > > > Any suggestions as to what I can do to fix this? > > > Thanks, > > Shyam > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] SPECCPU 2006 application crashes on x86 gem5
Hi All, I am trying to run some of the FP applications from SPECCPU 2006. However, for some of these applications (like povray, tonto), I get an error that says: warn: instruction 'movntdq_Mo_Vo' unimplemented. I am compiling these applications on my machine, and then running them on x86 gem5. My machine uses gcc version 7.4.0. I tried using gcc version 5.5 (already installed on my machine), but the problem persists. Any suggestions as to what I can do to fix this? Thanks, Shyam ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Re: [gem5-users] SPECCPU 2006 application crashes on x86 gem5
Hi, Additionally, I also tried using the -mno-sse2 flag, with which it compiles, but the error persists. However, when I tried to compile using the -mno-sse flag, then compilation fails saying: */usr/include/x86_64-linux-gnu/bits/stdlib-float.h: In function 'atof':/usr/include/x86_64-linux-gnu/bits/stdlib-float.h:26:1: error: SSE register return with SSE disabled* Thanks, Shyam On Sun, Jun 30, 2019 at 3:24 PM Shyam Murthy wrote: > Hi, > > This is slightly different, there is no panic message here. However, this > instruction is unimplemented, but is required by the application for its > execution, causing it to abort. As in your link, Gabe mentions that we need > to tell the compiler not to use this instruction. I was unsure how to > achieve the same, I tried passing the -msse flag to gcc during compilation, > but the movntdq instruction still seems to be getting generated. > > Thanks, > Shyam > > On Sun, Jun 30, 2019 at 1:06 PM Kleovoulos Kalaitzidis < > kleovoulos.kalaitzi...@inria.fr> wrote: > >> Hello, >> it is normal to get these warnings for unimplemented instructions. >> However, in my experience, these warnings are not the case for aborting. >> Normally some panic message follows, but maybe not related to this "warn". >> For instance, there is the case of avx instructions that are not >> implemented and will abort the execution : >> https://gem5-users.gem5.narkive.com/jO22f7kV/spec2017-on-gem5-se-mode >> >> Regards, >> >> -- >> Kleovoulos Kalaitzidis >> Doctorant - Équipe PACAP >> >> Centre de recherche INRIA Rennes - Bretagne Atlantique >> Bâtiment 12E, Bureau E321, Campus de Beaulieu, >> 35042 Rennes Cedex, France >> >> -- >> >> *From: *"Shyam Murthy" >> *To: *"gem5 users mailing list" >> *Sent: *Sunday, June 30, 2019 7:02:37 PM >> *Subject: *[gem5-users] SPECCPU 2006 application crashes on x86 gem5 >> >> Hi All, >> I am trying to run some of the FP applications from SPECCPU 2006. >> However, for some of these applications (like povray, tonto), I get an >> error that says: >> >> warn: instruction 'movntdq_Mo_Vo' unimplemented. >> >> I am compiling these applications on my machine, and then running them on >> x86 gem5. My machine uses gcc version 7.4.0. I tried using gcc version 5.5 >> (already installed on my machine), but the problem persists. >> >> >> Any suggestions as to what I can do to fix this? >> >> >> Thanks, >> >> Shyam >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> ___ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Re: BTB hits reported as 0 and direct/indirect branch instruction classification missing
Hi Jason, Thanks, I am working off the stable branch. This seems to be the last commit, based on git log. commit fa70478413e4650d0058cbfe81fd5ce362101994 (*HEAD -> **kvm_branch*, *tag: v20.0.0.3*, *upstream/master*, *master*) Author: Bobby R. Bruce Date: Fri Jul 3 15:39:52 2020 -0700 misc: Updated release notes and version number Updated the release notes and version number for the v20.0.0.3 hot-fix. Change-Id: I3fe8eda1e6859f76a91fbcee595426bd25bfe432 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30956 Reviewed-by: Bobby R. Bruce Reviewed-by: Jason Lowe-Power Maintainer: Bobby R. Bruce Tested-by: kokoro Thanks, Shyam On Thu, Sep 10, 2020 at 10:00 AM Jason Lowe-Power wrote: > Is this on the stable branch (master, gem5-20.0) or develop? > > I believe there are some related issues: > https://gem5.atlassian.net/browse/GEM5-338 > https://gem5.atlassian.net/browse/GEM5-732 > https://gem5.atlassian.net/browse/GEM5-720 > > Some of those have been resolved and will be part of the 20.1 release > (coming in a couple of weeks). > > Cheers, > Jason > > On Wed, Sep 9, 2020 at 8:55 AM Shyam Murthy via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi, >> >> I was running a few applications on gem5 using the O3CPU model and X86 >> ISA. I observed that gem5 reports BTB hits/lookups to be 0. All predicted >> taken branches (direct jumps, conditional jumps predicted taken as well as >> indirect jumps) consult with the indirect predictor and use up space in the >> target cache (I'd expect the target cache is used only by indirect >> branches). >> I think the issue is that branches don't get classified into >> directControl and indirectControl, causing the BTB to never get looked up. >> Is this understanding of mine correct, or am I missing something? >> >> Thanks, >> Shyam >> ___ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] BTB hits reported as 0 and direct/indirect branch instruction classification missing
Hi, I was running a few applications on gem5 using the O3CPU model and X86 ISA. I observed that gem5 reports BTB hits/lookups to be 0. All predicted taken branches (direct jumps, conditional jumps predicted taken as well as indirect jumps) consult with the indirect predictor and use up space in the target cache (I'd expect the target cache is used only by indirect branches). I think the issue is that branches don't get classified into directControl and indirectControl, causing the BTB to never get looked up. Is this understanding of mine correct, or am I missing something? Thanks, Shyam ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Indirect target predictor
Hi All, Is there any other target predictor for indirect jumps on gem5 apart from simple indirect predictor? Thanks, Shyam ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
