Hi Tom. The data could have been written there as the result of a system
call which would not have executed as instructions in gem5, or it could
have been part of the initial binary. The address looks like a stack
address, so there's a good chance it came from a system call.
I'm just guessing,
I just built the gem5 library following the instructions in the README and
it built fine. What namespace errors did you see? That sounds to me like
some part of your code base isn't up to date, since gem5 reworked its
namespaces a little while ago. I do see that the errors in your
I don't think we ever transitioned from an assembly based mechanism to a C
based one, since we have always (as far as I know) used both, assembly to
actually invoke the call into gem5, and C to provide a friendly
interface/wrapper around the assembly. That said, yes, it looks like work
begin and
Those operands are set up in arch/arm/isa/operands.isa, and get their value
using very different indices. XBase uses the "base" field of the
instruction object, while XURa uses "ura". The "u" in "ura" most likely
comes from the fact that that register is "register a" as intended for use
in
*Very* superficially looking at this (just at what's in the emails here),
you might want to make sure the BaseCPU destructor is virtual, or at least
the destructor of a base class is. If it isn't currently, the destructor of
SimObject should probably be virtual. I don't know for sure whether that
Hi Yao, please include the actual error message when asking about these
sorts of things, since without it it's much harder to tell what happened.
That said, this sounds like a problem with {} brackets somewhere in an
included file, where things ended up inside scopes and/or namespaces they
Hi Yao, please copy text into emails and don't use screenshots. What SCons
is doing is that it's trying to compile a small program which includes
sys/mman.h, links against either no additional library or the "rt" library,
and includes a call to shm_open().
As far as why opt is smaller than fast, that could be because the compiler
is optimizing more aggressively for performance at the cost of binary size
with those settings? Just a guess.
Gabe
On Fri, Jan 7, 2022 at 10:45 AM Thomas, Samuel via gem5-users <
gem5-users@gem5.org> wrote:
> Hi Jason,
>
In SE mode, there are going to be at least small (and perhaps large)
differences between how a program runs in gem5 vs a real system. Some of
those will be from system calls which are not implemented exactly right in
gem5, or are slightly different because they're actually happening on your
host
I think this may not be quite right, or I'm misunderstanding what Jason is
saying. The Tick number returned in atomic mode is supposed to approximate
how long the access took, and it's up to the caller to do something with
that. Often the caller does throw away the number, but that's what it's
The issue in Jira is a known issue where the cxx config mechanism works in
a fundamentally not quite correct way, and while it usually works out, it
doesn't for the systemc stuff. You can use the cxx config mechanism or the
(built in) systemc, but not both.
Given that these instructions build
Hi Xiaokang.
1. All of those CPU models will be able to execute the same set of
instructions since they use the same instruction implementations. The HPI
CPU is really just the O3CPU with some of the configuration set a certain
way, I think.
2. I don't know for sure, but there are some constants
Hi Hiromichi, there isn't really any documentation for how that system
works. You can find much of the code for it in the src/base/loader
directory, and in the Process subclasses for the different architectures in
src/arch/.
Gabe
On Wed, Dec 8, 2021 at 11:47 PM hiromichi.haneda--- via gem5-users
Hi James, there are not. I put a little time into making it easier to build
your own images with known good configurations and tools, but there's a lot
to do there still.
Gabe
On Wed, Dec 8, 2021 at 10:49 PM jamesbondtia--- via gem5-users <
gem5-users@gem5.org> wrote:
> Hi,
>
> I noticed that
Hi Jason. Some instructions need to be broken down into microops because
they might not be realistic to do all at once, or because they need to
perform multiple memory accesses. Other instructions don't, so they're
implemented as regular instructions which are not broken down into microops.
Gabe
+Bobby Bruce
On Fri, Dec 3, 2021 at 6:45 PM Gabe Black wrote:
> I think you want this change:
>
> https://gem5-review.googlesource.com/c/public/gem5/+/49183
>
> On Fri, Dec 3, 2021 at 4:26 PM Nirmit Jallawar wrote:
>
>> Hi Gabe,
>>
>>
>>
>> Here is the backtrace using gdb:
>>
>>
>>
>>
I think you want this change:
https://gem5-review.googlesource.com/c/public/gem5/+/49183
On Fri, Dec 3, 2021 at 4:26 PM Nirmit Jallawar wrote:
> Hi Gabe,
>
>
>
> Here is the backtrace using gdb:
>
>
>
> 7335000: system.cpu: T0 : 0x7801bbdd @_end+140737354234813. 4 :
> CALL_NEAR_I : wrip
Hey Nirmit, thanks for the backtrace, but could you please run this under
gdb and get the backtrace that way? It will figure out what the function
names are, etc, where gem5's built in backtrace just has offsets.
Gabe
On Thu, Dec 2, 2021 at 3:37 PM Nirmit Jallawar wrote:
> Hi Matt, Gabe,
>
>
>
Hi Jason. The instruction definitions in gem5 can be quite complex, and
it's unlikely you'll find a lot of information about specific details like
this through Google. Probably a good place to start is to try to understand
how the ISA description files work in general, since that will give you
I realize this is probably a hard question to answer with Exec being
broken, but do you know what instruction is causing the problem? HINT_NOP?
Probably the first thing that someone should do (if they haven't already)
is to run this under gdb and see what the backtrace looks like, since that
would
his problem? I spent lot of time on this with out making any
> progress.
>
> Thanks,
> Sachin
>
>
> On Mon, Nov 15, 2021 at 5:51 PM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> I'm not 100% sure this is right, but I think what you do is assi
I'm not 100% sure this is right, but I think what you do is assign the same
process object to each core you want a thread to run on.
Gabe
On Mon, Nov 15, 2021 at 10:25 AM Sachin Vijay Kumar via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
>
> I have some basic question about assigning a
The first error is because that is a big endian binary, and gem5 only
supports the little endian version of MIPS. The second error is not because
of the cross compiler, it's because something is wrong with the
configuration (or gem5 itself) and an error is detected while running.
Specifically, the
Please take a look at util/m5/README.md for information about when the
different modes will work.
On Mon, Nov 1, 2021 at 8:14 AM Liyichao via gem5-users
wrote:
> Thanks for your reply.
>
> But when I work on the Gem5 v20.0.0.3，
> m5 —addr exit doesn‘t take effect on O3，
> and it just takes
gem5 does not write UART output to the console, it writes it to a file in
the m5out directory, and makes it available if you connect to the console
output socket using m5term (or any other telnet client). If you use
aggressive debug flags like ExecAll, that will slow down execution
dramatically
ild gem5.opt of ARM on X86 server, the print “Info: KVM for null
> not supported on arm host.” will also be presented
>
>
>
> *发件人:* Gabe Black via gem5-users [mailto:gem5-users@gem5.org]
> *发送时间:* 2021年10月29日 11:43
> *收件人:* gem5 users mailing list
> *抄送:* Gabe Black
> *主
Hi, I just grepped through all of gem5's source, and, even ignoring
capitalization, the string "KVM for" does not appear outside of a couple
comments. I have no idea where that string is coming from, but it doesn't
seem to be from gem5 itself.
Gabe
On Thu, Oct 28, 2021 at 8:04 PM Liyichao via
Oh, I see, I didn't realize you were trying to call it from python, or even
that that was exposed to python. It would probably be possible to expose
that parameter as well, although that would require a change to gem5. I
think that change would be worth doing, but may be a bit of a tangent from
You can also take a look at the "clobber" argument which will tell the
mapping function to overwrite existing mappings. You can see in the panic
that that's what it's checking, ie it found an overlap and it wasn't told
to go ahead and clobber those, so it has to give up.
Gabe
On Tue, Oct 26,
I agree with Hoa that you're using virtual addresses, and those are
unrelated to the physical addresses you're trying to access. The second
method is probably moving an immediate constant into the register, and not
loading from a memory address. mmap-ing the physical pages you're
interested in
Hi Gogineni. By adding extra entries to x86's system call table, all you
did was tell gem5 those system calls existed so that it could print a more
informative message about them not being implemented. Your second change,
when you added getrandomFunc to the getrandom entry, would work, except you
It sounds to me like you've somehow installed the gem5 git hooks for
everything on your machine through either the user global or a machine
global git config. What you want to do is install the hooks (scripts or
links in .git/hooks) in the gem5 repository itself. SCons will prompt you
to do this
It's normal for valgrind to slow things down a lot. One thing you can do to
at least improve the quality of the errors you get is to use the
suppressions file in util/valgrind-suppressions. The python interpreter
does a lot of things which upset valgrind, and this tells valgrind mostly
to ignore
The standard library you're linking against is newer, and is using a system
call that gem5 doesn't implement. You'll either need to use an older
standard library, or implement that system call. If you're trying to run
gem5's tests, then I know at least one of the x86 ones uses dynamic linking
and
Hi, sorry for taking a while to get back to you. The cxx-config code is not
quite correct, although it basically works in most cases. It fails to build
with the systemc integration, but you don't want to use gem5's built in
systemc kernel anyway, if you're going to run it inside another external
-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7f3f7d2bfef6]
>> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x8006b)[0x7f3f7d2c306b]
>> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7f3f7d2b7d6d]
>>
>> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_Eva
ibpython3.8.so.1.0(+0x74d6d)[0x7f3f7d2b7d6d]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x12fd)[0x7f3f7d2b946d]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7f3f7d40de3b]
>
> /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_Py
Please give this a try:
https://gem5-review.googlesource.com/c/public/gem5/+/49183
On Tue, Aug 10, 2021 at 9:37 PM Deric Cheung via gem5-users <
gem5-users@gem5.org> wrote:
> Host OS: Ubuntu 12.04 LTS
> Host CPU: Intel i7-2600 3.40 GHz
>
> I'm trying to debug an x86 application on an O3CPU
Great, I'm glad that fixed it for you. Could you please upload your fix so
other people can benefit from it too?
https://www.gem5.org/contributing
Gabe
On Mon, Jul 26, 2021 at 11:39 AM Mohit Gambhir via gem5-users <
gem5-users@gem5.org> wrote:
> Thanks for that workaround. Introducing
Yes, I haven't looked at the code itself, but that explanation seems very
plausible. The way the ISA parser works is basically if something is on the
left hand side of an =, then it's assumed to be a destination, and
otherwise it's a source. It bases its decision *purely* on text, with no
That sounds plausible. In general, when you write to a register in x86, you
may be doing a partial write where the old data in the register needs to be
preserved. For instance, if %rax has 0x0123456789abcdef in it, and you want
to write 0x1 to %al, then you need both the old value and the value
Yeah, this looks like your system ran out of memory:
g++: fatal error: Killed signal terminated program lto1
That's probably the kernel going around killing processes using lots of
memory since it's running out.
Gabe
On Mon, May 24, 2021 at 7:27 PM Eliot Moss wrote:
> On 5/24/2021 10:12 PM,
The last lines in your original email are:
[SOPARMHH] VirtIO9PBase -> X86/params/VirtIO9PBase.hh
[SOPARMHH] VirtIO9PDiod -> X86/params/VirtIO9PDiod.hh
[SOPARMHH] VirtIO9PProxy -> X86/params/VirtIO9PProxy.hh
[SOPARMHH] VirtIO9PSocket -> X86/params/VirtIO9PSocket.hh
[ CXX]
Well, whatever the reason, there are no error messages in your original
email :-)
Gabe
On Mon, May 24, 2021 at 7:01 PM Eliot Moss wrote:
> On 5/24/2021 9:47 PM, Gabe Black wrote:
> > Hi Eliot, unfortunately this output doesn't seem to include stderr, and
> so doesn't have any of the
> >
Yeah, I wouldn't have expected that either, but if that's what you're
seeing it's hard to argue otherwise. I don't think that's an inherent
behavior of LTO, but it might be an unintended side effect somehow, maybe
pulled in indirectly? It's probably worth a Jira ticket.
Gabe
On Mon, May 24, 2021
Hi Eliot. The decoder, particularly the x86 decoder, is one of the most
complex areas of gem5, and unfortunately there isn't any comprehensive
documentation explaining how it works. I did put together this document a
while ago (
I don't think LTO strips debug symbols... But yes, LTO does significantly
increase link time if your machine doesn't have lots of cores to
parallelize the link. It slows it down in general, but with gcc you can
parallelize the link with LTO where you can't without LTO for some reason,
and that
Hi. VPtr<> is supposed to be equivalent to void *. Even with a c void *
though, you can't (in standard c) use it as an array of bytes. If you need
it to be an array of bytes, you need to use VPtr. There are some
facilities to cast VPtrs of different types, but I don't remember how
extensive that
This question has been asked (and answered) on this list already. Please
don't ask the same question multiple times.
Gabe
On Wed, Apr 21, 2021 at 9:14 PM VAIDYA ROHINI VILAS via gem5-users <
gem5-users@gem5.org> wrote:
> Hello,
> I am trying to build gem5 for X86 architecture but it does not
>
It looks like you might be running out of memory, which building too many
things at once could contribute to. The final link is going to use a lot of
memory no matter what, most likely.
Gabe
On Wed, Apr 21, 2021 at 3:34 AM Hoa Nguyen wrote:
> Hi,
>
> Can you be more specific about the command
Yeah, I don't think gdb in SE mode handles page faults well, but there was
actually a change proposed very recently which should help improve that.
You can probably cherry-pick that change locally if you want to try it out.
https://gem5-review.googlesource.com/c/public/gem5/+/44685
Gabe
On Tue,
Hello, Liyichao. While gdb debugging in gem5 is a great tool, it's a bit
limited as far as the sort of debugging you're talking about. It can see
the CPU state when you're in user space programs, but it doesn't understand
that different user space programs are different things, or know how to
look
If this works on x86, the chances are good that the system call
implementations are fine since they're likely the same between the two, but
there could be some glue (flag translation, which system calls that are
hooked up) which is different. You should try enabling the system call
DPRINTF flags
1. Yes. You can also use the ethernet bridge to bridge the network within
gem5 out to the host network so you can access the "real" network/internet.
2. Yes, caches are separate components, so you can add in caches as you
want, and configure their properties.
Gabe
On Fri, Apr 16, 2021 at 10:05
That's essentially right, although gem5 does have some plumbing to run
multiple event queues within the same simulation which can coordinate with
each other within a small window (quantum) of time. gem5 has support for
fibers/threads/coroutines, but these are not typically used to model
events.
Hi Pavel.
1. Yes, this is possible, I've done that as part of my work. The (a?) hard
part is getting the software set up correctly, but gem5 as it is should be
able to run it. Be warned that android is a big, complex system and can
take a long time to boot and run on gem5, which can be
Hi Gabriel. One big reason not to use shared libraries is performance,
although that doesn't mean the idea is without merit. In the long term, I
would like to give gem5 a kconfig like configuration mechanism, where you
could specify things to be built into gem5 itself, things to be excluded,
and
Maybe a python 2 vs 3 issue? I haven't used this script myself.
Gabe
On Mon, Apr 12, 2021 at 2:02 AM weiwei Zhao via gem5-users <
gem5-users@gem5.org> wrote:
> cmd：./util/o3-pipeview.py -c 1000 -o DP1d_corr/pipeview.out --color
> DP1d_corr/trace.out
>
> Processing trace... Traceback (most
The opt build now uses link time optimization (LTO) and does not use
partial linking. On slower machines and/or machines with fewer cores (and
maybe less memory?) this seems to really slow things down, where on
machines with more cores, LTO linking happens to be parallel where normal
linking
Hi, it looks like your script (/tmp/my_script) is exiting. I think the init
process isn't supposed to exit.
Gabe
On Sun, Apr 11, 2021 at 4:13 AM kong han via gem5-users
wrote:
> Hi all,
>
> Now I using the Latest linux kernel and disk images to run fs mode with
> KVM CPU (
>
Hi. The automatically generated create() method will only exist if your
SimObject can be constructed with a constant reference to the parameter
type. Or in other words, if it has a constructor of the form
TraceManager(const TraceManagerParams ). You can disable that by
just adding a dummy
Hi Nikos, how old is your gem5 checkout? The change below fixed some
aspects of how PCI devices are managed, including one which could cause
failures like you're seeing.
commit 9be18aa66ddb8db4da043279819d45bc72b7b086
Author: Gabe Black
Date: Fri Oct 2 03:00:04 2020 -0700
On Wed, Mar 31, 2021
Hi Jeageun, you should take a look at util/m5/README.md for an explanation
of how the m5 utility works and how it should be used in different
environments. It looks like it's trying to use the instruction based
mechanism to call into gem5, and that won't work in KVM. In KVM, you have
to use the
Hi Xijing. I don't think anyone has gotten x86 and caches and
locking/atomic instructions to fully work, so it's just a known bug in gem5
at the moment. If you want to simulate that sort of system, I would suggest
using ARM if possible. We'd love to fix this at some point, but there are a
lot of
Please take the version that works for you and create a review:
http://www.gem5.org/contributing
It's much easier to look at changes in the code review interface, and we
can add reviewers who are most familiar with this code.
Gabe
On Tue, Mar 16, 2021 at 2:59 AM Liyichao wrote:
> Adding
Hi Sam, there are a few ways you can do that.
1. You could set up a PC based event if you know what PC your behavior will
always be triggered from (see examples like skipping udelay for some
versions of the linux kernel).
2. You could create a new gem5 op by picking an unused number and a wrapper
Basically you want to make sure you've moved to the right event queue by
the time any code you call tries to schedule an event. The VirtIO devices
themselves don't seem to, but the code they're calling (interacting with
other devices, sending transactions to the memory system) could be. If it
Yes exactly, did that help?
Gabe
On Mon, Mar 15, 2021 at 10:29 PM Liyichao wrote:
> Hi Gabe:
>
> You mean that the code to be modified just like this?
>
>
>
> void
>
> PciVirtIO::kick()
>
> {
>
> DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
>
>
I think what you want to do is in the kick() functions in MmioVirtIO and
PciVirtIO, you want to declare a ScopedMigration at the start of the
function, and pass its constructor the result of the eventQueue() method.
The SimObject class inherits from EventManager and knows what event queue
it's
This code seems to be calling system calls like mprotect which are not
implemented, and which are probably doing something important as far as how
the program works. Implementing these accurately would be complicated, and
so you best bet is probably to use full system mode.
Gabe
On Fri, Mar 12,
I haven't looked at the code yet, but this is probably because the v9
implementation is getting asynchronous input which might be received by one
thread, which then tries to schedule an event on an event queue associated
with another queue. Most of the time this is not an issue since gem5 is
Hi Deepak. On a real system, you would probably use ACPI to tell the
chipset to power down the machine, but on gem5 you can probably just run
the "exit" pseudo instruction which will tell gem5 to exit back to the
python config file.
Gabe
On Wed, Mar 10, 2021 at 2:07 AM Deepak Mohan via
You have a circular dependency in your include files system.hh gets past
the compiler guard, then includes base.hh which includes cache.hh which
tries to include system.hh. Since system.hh has already started to be
included it gets skipped, but since it was only started none of the things
it
The ARM in --cmd should be lower case.
On Mon, Feb 22, 2021 at 1:17 AM VAIDYA ROHINI VILAS via gem5-users <
gem5-users@gem5.org> wrote:
> I am trying to run gem5 in se mode by command *" build/ARM/gem5.opt
> configs/example/se.py --cmd=tests/test-progs/hello/bin/ARM/linux/hello"*
> error coming
Hi Lukas. It's not really clear from your description what the problem is,
but I would expect the "size()" method to be very simple, and so the "root"
pointer is probably null or corrupt. You should probably look into where
that value is coming from and what might have happened to it.
Gabe
On
Hi Lukas. Would you mind filing a bug in Jira describing what's wrong with
the --dual option? The provided configs have gotten really big and complex
over the years, and it can be hard to work with them to, for instance, add
a new device like you're trying to. You might consider making your own
Hi Kevin. It looks like that change has already been checked in on the
develop branch in October. Judging by the dates on the releases, I'd guess
that would be included on version 20.1 (September), although I haven't
verified that specifically. It should definitely be in the develop branch,
and
Hi Veronia. scons build/x86/out/m5 asks scons to build the m5 utility, not
the m5 library which is called build/x86/out/libm5.a. You may have some
other library on your system called m5 which -lm5 is picking up which
doesn't have that symbol.
Gabe
On Thu, Feb 4, 2021 at 3:52 AM Veronia Bahaa via
across a similar discussion in the archives [2], which did seem
> similar,
> > but didn’t address the problem described below. Is the bug you’re
> referring to
> > the one addressed by CL `35516` [3]?
> >
> >
> >
> > Thanks for taking a look at this!
>
Are you using up to date develop? There was a bug like this a while ago,
but it's been fixed on develop for a while as well.
Gabe
On Thu, Jan 21, 2021 at 6:35 PM Bohren, Jonathan via gem5-users <
gem5-users@gem5.org> wrote:
> We've been using the `VExpress_GEM5_V1` platform but it was failing
This is from newer versions of scons changing how initialization works, and
where and when gem5's scons files update the python search path. It's fixed
on the develop branch, if you want to try that.
Gabe
On Tue, Jan 19, 2021 at 2:39 AM 刘宗惠 via gem5-users
wrote:
> Hello,
>
> I am new to gem5
SE mode does not work at the standard library level, it works at the system
call level. As long as your custom standard library uses the normal linux
system calls and the normal linux system call ABI, you shouldn't have to do
anything special. There could be a very minor technical exception on x86
I just did a quick check, and it looks like the RISCV ISA definition
includes support for the instruction based pseudo ops. If you add support
to the m5 utility, then it might just work.
Gabe
On Wed, Dec 2, 2020 at 9:04 PM Volkan Mutlu via gem5-users <
gem5-users@gem5.org> wrote:
> Hello
Don't use -o,loop with mount. That creates another loopback device and then
tries to use that, and apparently reuses /dev/loop4. If you look in /dev,
there will also be a /dev/loop4p1 (for instance) for each partition. Mount
that device instead.
Gabe
On Wed, Dec 2, 2020 at 12:07 AM Boya Chen via
That's probably a disk image and not a file system image. You need to tell
losetup to scan for the partition table with I think the -p option.
Gabe
On Tue, Dec 1, 2020 at 10:02 AM Choe, Jiwon via gem5-users <
gem5-users@gem5.org> wrote:
> I'm running into the same issue as well.
>
> -Jiwon
>
>
You need to include base/trace.hh which defines DPRINTF itself.
Gabe
On Sat, Nov 21, 2020 at 8:33 PM yujiecui--- via gem5-users <
gem5-users@gem5.org> wrote:
> I want to know the cache information when the replacement algorithm is
> executed. So I made the following changes in the latest
gem5 does not use mercurial any more and hasn't for a while, and so using
hg commands probably won't work. You should be able to apply the patches
using the normal "patch" command, or even with git using the "git am"
command, but if your patches are really old (likely if they're geared
towards
In what way was it not possible? Did you get an error message?
Gabe
On Wed, Nov 18, 2020 at 1:51 PM Cristobal Ramirez Lazo via gem5-users <
gem5-users@gem5.org> wrote:
> Dear all,
> I would like to use the m5ops functions such as "m5_reset_stats" in my own
> c++ program.
> I have done it for
I am currently using? Will that won't create compatibility issues?
>>>
>>> On Sat, Nov 14, 2020 at 1:38 PM Gabe Black via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> Probably not. There were some other fixes which made things partiall
wrote:
> Can I use m5 util from the current stable branch with the old gem5 repo I
> am currently using? Will that won't create compatibility issues?
>
> On Sat, Nov 14, 2020 at 1:38 PM Gabe Black via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Probably not. Th
Probably not. There were some other fixes which made things partially work
with PIE code, but the version of the utility you're using may be too old
to include those, or you might be trying to use it in a way that the
partial support didn't cover (different ISA for instance). You'll probably
save
That version of gem5 is a few years old and doesn't have the updates to the
m5 utility that made it use scons. In that version, you need to use make.
Gabe
On Fri, Nov 13, 2020 at 7:43 PM krishnan gosakan via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
> I am trying to compile m5 utils. I
Sinclair via gem5-users <
>>> gem5-users@gem5.org> wrote:
>>>
>>>> Hi Gabe,
>>>>
>>>> I don't have the broken build in front of me, and it's possible it is
>>>> because I'm running on an Ubuntu 16 machine, but I had to add
the
>> error message I got when debugging this. If c++14 works though, great.
>>
>> Thanks for the updated info -- I built the tutorial out of the old one,
>> so next time I'll make sure to update it accordingly.
>>
>> Thanks,
>> Matt
>>
>> On Mon, Nov
BTW, I do think I need to explicitly set the c++ version in the scons file,
like in Matt's original email above. I'd probably set it to c++14 though,
to be consistent with gem5 proper. I think that will likely fix a build
issue Bobby had with an older (7.x I think) version of gcc, where the
If you want the frequency of the CPUs to change independently from each
other, I think you need to set up a ClockDomain object for each, instead of
letting them implicitly inherit the one from the System object.
On Mon, Nov 9, 2020 at 2:26 AM Đức Anh via gem5-users
wrote:
> Hello all,
>
> I am
The --script option works by setting up a file for the m5 utility to read
in from the actual on disk init script found in the disk image. If the m5
utility isn't called, or is called incorrectly, or the script it extracts
isn't then run, the --script option won't work.
It's been a while, but I
Hi folks. If you're using the magic address based version of the gem5 ops,
then you should call, for instance, m5_exit_addr and not just m5_exit. The
"normal" functions are now always the magic instructions which essentially
only gem5 CPU models know how to execute. All call mechanisms are built
The way create methods and constructors were set up was standardized and
largely automated recently. If you're backporting a change across when that
happened, you're going to have to adjust those so they work with the old,
less consistent versions, but it should be very straightforward (turning
That sounds like the problem I fixed with this CL:
https://gem5-review.googlesource.com/c/public/gem5/+/35516
Gabe
On Thu, Nov 5, 2020 at 4:42 AM Liyichao via gem5-users
wrote:
> Hi Gabe:
>
> I have looked at the email below, I also has the same question.
> As you mentioned, I just
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