[gem5-users] Re: Transfer cache information to misc register in arm

[Giacomo Travaglini via gem5-users]

Hi,

You should establish a link between your cache and the ISA. It shouldn't be 
hard to hack things around.
A cleaner solution would involve using probe points. You could use a probe 
listener per ISA object. For every alocation update on the l2 cache, the 
listeners will be awakened and the sysreg value updated accordingly.

Hope this helps

Giacomo

From: tyhtyh--- via gem5-users 
Sent: 06 March 2024 12:57
To: gem5-users@gem5.org 
Cc: tyh...@mail.ustc.edu.cn 
Subject: [gem5-users] Transfer cache information to misc register in arm

I am a beginner who has just started to learn Gem5. Recently, I attempted to 
use the msr instruction to read out the currently allocated entries in L2cache 
(variable "int allocated" in gem5 stable \ src \ mem \ cache \ queue.hh). I 
have added a new system register for this purpose (by modifying gem5 stable \ 
src \ arch \ arm \ regs \ misc.hh and misc.cc), and the mrs instruction can 
correctly read the value of this register. But what confuses me is how to pass 
this variable to the MiscRegLUTEntry, or in other words, there is an array 
called RegVal miscRegs [NUM-MISCREGS] in "gem 5 stable \ src \ arch \ arm \ 
isa. hh" (which I think is used to store different misc register values). What 
should I do to pass the allocated variable in src \ mem \ cache \ queue.hh to 
miscRegs [NUM-MISCREGS] in src \ arch \ arm \ isa. hh?Thank you very much for 
your help！
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[gem5-users] Re: Assistance required: SimObject params throwing error

[Giacomo Travaglini via gem5-users]

On 26/02/2024 05:33, Ananth.PaiJ--- via gem5-users wrote:
Hello *,


Hi


While building gem5 with EXTRAS= mechanism I’m encountering an error.
Error :
[SO Param] m5.objects.BranchPredictor, BranchTargetBuffer -> 
ARM/python/_m5/param_BranchTargetBuffer.cc
terminate called after throwing an instance of 'pybind11::error_already_set'
 what():  AttributeError: m5.objects.SystemC_Example.py already found in 
importer


My quick guess is that you might have two SystemC_Example.py files in your 
EXTRAS directory which might conflict with each other.

I believe one is in 
https://github.com/gem5/gem5/blob/stable/util/systemc/systemc_within_gem5/systemc_gem5_tlm/SystemC_Example.py;
 I would make sure there is no other one that gets discovered by SCons.

Kind Regards


Giacomo


At:
 (57): add_module
 (93): install

And this stays the same for all params build irrespective of which simobject 
its building. But I have not called that anywhere else.
I’m currently using gem5v23.1. gcc 11.2. python 3.10.12.

Warm regards,
Ananth Pai J

Infineon Technologies IN
DES PTS TI EA SME
Phone: +91 7349045724
ananth.p...@infineon.com




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[gem5-users] Re: Issues faced while running STREAM benchmark in SE mode.

[Giacomo Travaglini via gem5-users]

Hi Pooja,

It looks like an old version of gem5 (considering configs/example/se.py has 
been moved to configs/deprecated/example/se.py). As you are trying to run an 
Arm simulation, can I suggest you to use
configs/example/arm/starter_se.py instead?

Kind Regards

Giacomo

From: Pooja Allampallewar via gem5-users 
Date: Wednesday, 21 February 2024 at 14:20
To: gem5-users@gem5.org 
Cc: RICHA K , Pooja Allampallewar 
Subject: [gem5-users] Issues faced while running STREAM benchmark in SE mode.
Hi,

I am trying to execute Stream benchmark in SE mode, however there are several 
errors encountered in the code files. Is there a change in the command or way 
to execute the benchmarks? Here are the detailed steps I followed:
- Compiled Stream benchmark for ARM to get the stream-arm-c binary.
- Then executing the command :

./build/ARM/gem5.fast --outdir=m5out-stream configs/example/se.py 
--cpu-type=DerivO3CPU --caches -c ../benchmarks/Stream/stream-arm-c

The command gives the error in CacheConfig file (attached with the mail).

However if i am not specifying CPU, then the command gives an error message in 
se.py:
run() supports 5 inputs, only 4 provided

Any guidance along these lines is really appreciated.

Regards

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[gem5-users] Re: ARM SVE ISA

[Giacomo Travaglini via gem5-users]

Hi Nazmus,


You should have a look at 
https://github.com/gem5/gem5/blob/stable/src/arch/arm/insts/sve_macromem.hh


To simply answer your question, the micro-op cracking happens in the 
instruction definition and that's why you can't find anything

in the cpu/pipeline code. If you want to change things, you should amend the 
instruction definition accordingly.


Kind Regards


Giacomo



On 25/01/2024 16:08, Nazmus Sakib wrote:
Hello. I had a followup question.
As I understand from a list of enums, gem5 has different implementations for 
SVE load/store, like for unit and non unit stride, indexed (gather/scatter).
In case of a gather. I can see from ExecAll and other debug files, one load is 
separated into micro ops. Each microOp is responsible for one address and one 
word.
I know part of the memory traffic is controlled/determined by the ISA, like 
InitiateAcc() or CompleteAccess().
But which files should I look into, if I wanted to find:
1. Exactly where in the cpu pipeline this process is taking place ? I mean the 
process of one load instruction breaking down into several microOp ? and also, 
how they are fed into the registers ? This is a ISA specific problem and in 
LSQunit they just commit it, so I am assuming  the decoder has a part here.  I 
am just curious as how (or at least where) this interface between the ISA and 
the pipeline works, and also, if I wanted to change the ISA implementation of 
this (suppose I decide not to break this into microOps) where should I look for 
?
2. In the stat files, I do not see any statistics that point to this. So 
basically, even though it is a single load, all the statistics like cache hit 
miss etc are compiled for each individual microOps, as if they were scalar 
instructions, not vector ?


From: Giacomo Travaglini 

Sent: 15 January 2024 07:55
To: Nazmus Sakib ; The gem5 Users mailing list 

Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA

WARNING This email originated external to the NMSU email system. Do not click 
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Hi Nazmus


On 15/01/2024 14:32, Nazmus Sakib wrote:
Hello. Thanks for your response.
I am running O3 cpu (ARMO3CPU), not minor.


It's the same:

https://github.com/gem5/gem5/blob/stable/src/cpu/o3/lsq.cc#L816


Also, I get it that LSQ unit can do this.
But a cache must have separate logic for scalar and vector read/writes, as 
scheduling events to support a timing model for vector load/store must be 
different ?


A gem5 cache only reasons in terms of cacheline (64bytes) and same goes for a 
coherent interconnect, regardless of vector vs scalar.



Also, the interconnection (bus or crossbar or whatever) must be large enough to 
support vector read/writes ?


As I mentioned earlier, memory requests bigger than a cacheline will be split 
into fragments at the LSQ. To give you a more concrete example: say that you 
have a 1024bits vector (128bytes). A single vector load will be split into 2 
64bytes memory requests. The D-cache will see two requests to two consecutive 
cachelines. It will produce two GetS if it is a miss, or it will return them if 
present.

The LSQ will wait for both requests to return with data and will coalesce them 
before returning data to the writeback vector register.


I hope this helps


Giacomo




From: Giacomo Travaglini 

Sent: 15 January 2024 03:30
To: Nazmus Sakib ; The gem5 Users mailing list 

Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA

WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

Hi Nazmus,


On 15/01/2024 02:41, Nazmus Sakib wrote:
Thank you. I will try to switch to starter_se.py.
I still had some questions regarding SVE.
1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction, 
which is replaced by whilelow when I compile without setting the vector bit 
value. Now on gem5, it seems whilelow and the corresponding incw instructions 
works fine, because when I keep sve_vl=1 in gem5, incw increments by 0x4 ( 128 
bits) and when I set sve_vl=4 the incw increments by 0x16 (512 bits). But what 
I am curious about, is whether there is anything wrong with the implementation 
of PTRUE instruction in gem5.


Without inspecting the disassembled program, I simply guess using 
msve-vector-bit=512 forces the code to not be VL agnostic and hardcodes it to 
512. So there's nothing surprising in failing the run with a non matching 
hardware.

I believe the proof there is nothing inherently wrong in ptrue in gem5 comes 
from the fact that, keeping the 512b binary untouched (with ptrue), and only 
setting VL=4, you have a 

[gem5-users] Re: ARM SVE ISA

[Giacomo Travaglini via gem5-users]

Hi Nazmus


On 15/01/2024 14:32, Nazmus Sakib wrote:
Hello. Thanks for your response.
I am running O3 cpu (ARMO3CPU), not minor.


It's the same:

https://github.com/gem5/gem5/blob/stable/src/cpu/o3/lsq.cc#L816


Also, I get it that LSQ unit can do this.
But a cache must have separate logic for scalar and vector read/writes, as 
scheduling events to support a timing model for vector load/store must be 
different ?


A gem5 cache only reasons in terms of cacheline (64bytes) and same goes for a 
coherent interconnect, regardless of vector vs scalar.



Also, the interconnection (bus or crossbar or whatever) must be large enough to 
support vector read/writes ?


As I mentioned earlier, memory requests bigger than a cacheline will be split 
into fragments at the LSQ. To give you a more concrete example: say that you 
have a 1024bits vector (128bytes). A single vector load will be split into 2 
64bytes memory requests. The D-cache will see two requests to two consecutive 
cachelines. It will produce two GetS if it is a miss, or it will return them if 
present.

The LSQ will wait for both requests to return with data and will coalesce them 
before returning data to the writeback vector register.


I hope this helps


Giacomo




From: Giacomo Travaglini 

Sent: 15 January 2024 03:30
To: Nazmus Sakib ; The gem5 Users mailing list 

Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA

WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

Hi Nazmus,


On 15/01/2024 02:41, Nazmus Sakib wrote:
Thank you. I will try to switch to starter_se.py.
I still had some questions regarding SVE.
1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction, 
which is replaced by whilelow when I compile without setting the vector bit 
value. Now on gem5, it seems whilelow and the corresponding incw instructions 
works fine, because when I keep sve_vl=1 in gem5, incw increments by 0x4 ( 128 
bits) and when I set sve_vl=4 the incw increments by 0x16 (512 bits). But what 
I am curious about, is whether there is anything wrong with the implementation 
of PTRUE instruction in gem5.


Without inspecting the disassembled program, I simply guess using 
msve-vector-bit=512 forces the code to not be VL agnostic and hardcodes it to 
512. So there's nothing surprising in failing the run with a non matching 
hardware.

I believe the proof there is nothing inherently wrong in ptrue in gem5 comes 
from the fact that, keeping the 512b binary untouched (with ptrue), and only 
setting VL=4, you have a successful run.


2. As shown in my first email, my data arrays are 64 bytes in size. An sve load 
instruction with sve_vl=4 will allow all 64 bytes to be loaded by one ld1w 
instruction (theoretically at least in an actual cpu ). I can see from the 
outputs generated by debug flag LSQUnit and CacheALL, that indeed all 64 bytes 
are accessed by one instruction. For example:
system.cpu.dcache: access for WriteReq [81010:8104f]
The address range here are for 64 byte (16 integer of 4 byte in my test code).
But, without support in the bus/interconnection connected with cpu to deal with 
64 bytes (or whatever is the vector length)  and additional code in gem5 to 
support multi-word read/write , shouldnt only one word (I am guessing that is 4 
byte in gem5 for arm) can be read from cache to cpu ? In that case, how are all 
64 bytes is requested and read from cache to cpu in gem5 with one instruction? 
Is there some underlying mechanism, like micro-ops or some architectural 
feature that is taking place transparently ? Or maybe a simple loop that is not 
part of the debug flag output? I tried to look in src/mem/cache/base.cc and 
cache.cc but could not get an answer.


Simply put, the O3/Minor LSQ will allow every request which does not span 
between a cacheline boundary. If a memory request spans two cachelines, the 
request will be split in two (or more) fragments [1].


Hope this helps


Giacomo


[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/minor/lsq.cc#L1632




From: Giacomo Travaglini 

Sent: 12 January 2024 03:56
To: Nazmus Sakib ; The gem5 Users mailing list 

Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA


You don't often get email from 
giacomo.travagl...@arm.com. Learn why this is 
important

WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

You are right, I created a PR to fix this:



https://github.com/gem5/gem5/pull/764



Kind Regards



Giacomo

[gem5-users] Re: ARM SVE ISA

[Giacomo Travaglini via gem5-users]

Hi Nazmus,


On 15/01/2024 02:41, Nazmus Sakib wrote:
Thank you. I will try to switch to starter_se.py.
I still had some questions regarding SVE.
1. When I compile with msve-vector-bit set to 512, I can see PTRUE instruction, 
which is replaced by whilelow when I compile without setting the vector bit 
value. Now on gem5, it seems whilelow and the corresponding incw instructions 
works fine, because when I keep sve_vl=1 in gem5, incw increments by 0x4 ( 128 
bits) and when I set sve_vl=4 the incw increments by 0x16 (512 bits). But what 
I am curious about, is whether there is anything wrong with the implementation 
of PTRUE instruction in gem5.


Without inspecting the disassembled program, I simply guess using 
msve-vector-bit=512 forces the code to not be VL agnostic and hardcodes it to 
512. So there's nothing surprising in failing the run with a non matching 
hardware.

I believe the proof there is nothing inherently wrong in ptrue in gem5 comes 
from the fact that, keeping the 512b binary untouched (with ptrue), and only 
setting VL=4, you have a successful run.


2. As shown in my first email, my data arrays are 64 bytes in size. An sve load 
instruction with sve_vl=4 will allow all 64 bytes to be loaded by one ld1w 
instruction (theoretically at least in an actual cpu ). I can see from the 
outputs generated by debug flag LSQUnit and CacheALL, that indeed all 64 bytes 
are accessed by one instruction. For example:
system.cpu.dcache: access for WriteReq [81010:8104f]
The address range here are for 64 byte (16 integer of 4 byte in my test code).
But, without support in the bus/interconnection connected with cpu to deal with 
64 bytes (or whatever is the vector length)  and additional code in gem5 to 
support multi-word read/write , shouldnt only one word (I am guessing that is 4 
byte in gem5 for arm) can be read from cache to cpu ? In that case, how are all 
64 bytes is requested and read from cache to cpu in gem5 with one instruction? 
Is there some underlying mechanism, like micro-ops or some architectural 
feature that is taking place transparently ? Or maybe a simple loop that is not 
part of the debug flag output? I tried to look in src/mem/cache/base.cc and 
cache.cc but could not get an answer.


Simply put, the O3/Minor LSQ will allow every request which does not span 
between a cacheline boundary. If a memory request spans two cachelines, the 
request will be split in two (or more) fragments [1].


Hope this helps


Giacomo


[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/minor/lsq.cc#L1632




From: Giacomo Travaglini 

Sent: 12 January 2024 03:56
To: Nazmus Sakib ; The gem5 Users mailing list 

Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA


You don't often get email from 
giacomo.travagl...@arm.com. Learn why this is 
important

WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

You are right, I created a PR to fix this:



https://github.com/gem5/gem5/pull/764



Kind Regards



Giacomo



From: Nazmus Sakib 
Date: Thursday, 11 January 2024 at 19:34
To: Giacomo Travaglini , The 
gem5 Users mailing list 
Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA

Not compiling with -msve-vector-bits did the trick. It runs perfectly, whether 
I set the cpu[0].isa[0].sve_vl_se to 4 or keep it to 1.
Thank you for the suggestions !!
One last thing, the starter_se.py does not seem to have support for 
--cpu-type=ArmO3CPU (or am I missing something) ?



From: Giacomo Travaglini 

Sent: 11 January 2024 12:16
To: The gem5 Users mailing list 

Cc: Jason Lowe-Power ; Nazmus Sakib 

Subject: Re: ARM SVE ISA




You don't often get email from 
giacomo.travagl...@arm.com. Learn why this is 
important


WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

Hi Nazmus,



I can see from what you posted you are compiling the testcase with 512b vector 
width. I believe you should amend the gem5 VL accordingly… Basically writing up 
in the gem5 config:



cpu.isa[0].sve_vl_se = 4



According to [1].

This should fix your problem. Another solution I believe would be to compile 
without specifying the VL. Then it should be VL agnostic code I presume.



Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is 
per se 

[gem5-users] Re: About gem5 stats granularity

[Giacomo Travaglini via gem5-users]

Which stats are you interested on in particular?


Also when you say for each simulated instruction, do you mean for each
simulated instructionn TYPE? For example:


ADD -> stats for this particular instruction type

MUL -> stats for this particular instruction type


Kind Regards


Giacomo


On 12/01/2024 12:57, elio.vinciguerra--- via gem5-users wrote:


Hi everybody, I should have the statistics provided by gem5 in
stats.txt with an instruction level granularity. I noticed that by
default gem5 provides them global, from the beginning of execution to
the end. Is it possible to change this behavior and somehow get the
stats for each simulated instruction?


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[gem5-users] Re: ARM SVE ISA

[Giacomo Travaglini via gem5-users]

You are right, I created a PR to fix this:

https://github.com/gem5/gem5/pull/764

Kind Regards

Giacomo

From: Nazmus Sakib 
Date: Thursday, 11 January 2024 at 19:34
To: Giacomo Travaglini , The gem5 Users mailing 
list 
Cc: Jason Lowe-Power 
Subject: Re: ARM SVE ISA
Not compiling with -msve-vector-bits did the trick. It runs perfectly, whether 
I set the cpu[0].isa[0].sve_vl_se to 4 or keep it to 1.
Thank you for the suggestions !!
One last thing, the starter_se.py does not seem to have support for 
--cpu-type=ArmO3CPU (or am I missing something) ?

From: Giacomo Travaglini 
Sent: 11 January 2024 12:16
To: The gem5 Users mailing list 
Cc: Jason Lowe-Power ; Nazmus Sakib 
Subject: Re: ARM SVE ISA

You don't often get email from giacomo.travagl...@arm.com. Learn why this is 
important
WARNING This email originated external to the NMSU email system. Do not click 
on links or open attachments unless you are sure the content is safe.

Hi Nazmus,



I can see from what you posted you are compiling the testcase with 512b vector 
width. I believe you should amend the gem5 VL accordingly… Basically writing up 
in the gem5 config:



cpu.isa[0].sve_vl_se = 4



According to [1].

This should fix your problem. Another solution I believe would be to compile 
without specifying the VL. Then it should be VL agnostic code I presume.



Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is 
per se deprecated



Kind Regards



Giacomo



[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179



From: Nazmus Sakib via gem5-users 
Date: Thursday, 11 January 2024 at 17:54
To: gem5-users@gem5.org 
Cc: Jason Lowe-Power , Nazmus Sakib 
Subject: [gem5-users] ARM SVE ISA

Hello.
I am trying to run a simple program with SVE instructions on gem5. However, the 
output with debug flag ExecALL suggests there is a issue with the decoder.
Here is the test code:

#define STREAM_ARRAY_SIZE 16
void main()

{

for (int j=0; j___
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[gem5-users] Re: ARM SVE ISA

[Giacomo Travaglini via gem5-users]

Hi Nazmus,

I can see from what you posted you are compiling the testcase with 512b vector 
width. I believe you should amend the gem5 VL accordingly… Basically writing up 
in the gem5 config:

cpu.isa[0].sve_vl_se = 4

According to [1].
This should fix your problem. Another solution I believe would be to compile 
without specifying the VL. Then it should be VL agnostic code I presume.

Anyway, I also recommend you use configs/example/arm/starter_se.py as se.py is 
per se deprecated

Kind Regards

Giacomo

[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmISA.py#L179

From: Nazmus Sakib via gem5-users 
Date: Thursday, 11 January 2024 at 17:54
To: gem5-users@gem5.org 
Cc: Jason Lowe-Power , Nazmus Sakib 
Subject: [gem5-users] ARM SVE ISA
Hello.
I am trying to run a simple program with SVE instructions on gem5. However, the 
output with debug flag ExecALL suggests there is a issue with the decoder.
Here is the test code:
#define STREAM_ARRAY_SIZE 16
void main()
{
for (int j=0; j___
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[gem5-users] Re: Full System Simulation on ARM system takes too long

[Giacomo Travaglini via gem5-users]

Hi saras,

You are using a fully-fledged ubuntu distribution. May I suggest you a more 
lightweight solution?

Please have a look at the ubuntu18.04 option in 
https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries

Kind Regards

Giacomo

From: saras nanda via gem5-users 
Date: Friday, 15 December 2023 at 23:48
To: The gem5 Users mailing list 
Cc: Kaustav Goswami , muke...@protonmail.com 
, saras nanda 
Subject: [gem5-users] Re: Full System Simulation on ARM system takes too long
Even after hours of booting even 2-3 days consecutively my image wouldn't reach 
the login prompt to make the checkpointing it would reach
[  OK  ] Started Create Volatile Files and Directories.
 Starting Update UTMP about System Boot/Shutdown...
 Starting Network Time Synchronization...
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Synchronized.

and then stay at this point forever and I cant even get the login prompt to do 
checkpointing etc etc

please let me know what can I do about this issue .

regards
saras

On Wed, Dec 6, 2023 at 4:35 PM Kaustav Goswami via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Saras,

You’re booting up the disk image with timing cores and the disk’s init command 
is to load /sbin/init. It is expected that it’ll take 10ish hours to boot 
Ubuntu in this case. /sbin/init starts the default services for Ubuntu via 
systemd (
[0.314602] systemd[1]: System time before build time, advancing clock.). 
This takes a lot of time.


If you want to load the disk image faster then boot the disk image using kvm or 
atomic cpu and then on the first m5 exit switch to timing cores. Alternatively 
you can pass init=/bin/bash or something to the kernel which will skip systemd 
(although it’ll mean that you’ll only load the kernel, and none of the Ubuntu 
services).


Thanks,
Kaustav.


On Wed, Dec 6, 2023 at 1:09 PM saras nanda via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hello Everyone,

I am doing a Full System simulation on ARM , I edited my image on qemu and 
installed all necessary files

After that, I started the Gem5 FS using the following command,

./build/ARM/gem5.opt configs/example/arm/fs_power.py 
--kernel=/home/saras/gem5-resources/src/arm-ubuntu/gem5/full_system_images/binaries/vmlinux.arm64
 
--disk=/home/saras/gem5-resources/src/arm-ubuntu/gem5/full_system_images/disks/arm64-ubuntu-server.img
 --caches
The image gets booted up but takes a very long time to complete the process and 
I haven't reached the login part yet, but the whole thing takes about 7-8 hours 
to run halfway through.

The m5term output is as follows.

 m5 terminal: Terminal 0 
[0.00] Booting Linux on physical CPU 0x00 [0x410fd070]
[0.00] Linux version 4.18.0+ (arm-employee@arm-computer) (gcc version 
7.4.0 (Ubuntu/Linaro 7.4.0-1ubuntu1~18.04.1)) #1 SMP PREEMPT Wed Nov 6 14:10:00 
GMT 2019
[0.00] Machine model: V2P-CA15
[0.00] earlycon: pl11 at MMIO 0x1c09 (options '')
[0.00] bootconsole [pl11] enabled
[0.00] Memory limited to 2048MB
[0.00] cma: Reserved 16 MiB at 0xff00
[0.00] On node 0 totalpages: 524288
[0.00]   DMA32 zone: 8192 pages used for memmap
[0.00]   DMA32 zone: 0 pages reserved
[0.00]   DMA32 zone: 524288 pages, LIFO batch:31
[0.00] random: get_random_bytes called from start_kernel+0xa8/0x3e8 
with crng_init=0
[0.00] percpu: Embedded 23 pages/cpu @(ptrval) s53976 r8192 
d32040 u94208
[0.00] pcpu-alloc: s53976 r8192 d32040 u94208 alloc=23*4096
[0.00] pcpu-alloc: [0] 0 [0] 1
[0.00] Detected PIPT I-cache on CPU0
[0.00] CPU features: enabling workaround for ARM erratum 832075
[0.00] CPU features: enabling workaround for ARM erratum 834220
[0.00] CPU features: enabling workaround for EL2 vector hardening
[0.00] CPU features: detected: Kernel page table isolation (KPTI)
[0.00] Built 1 zonelists, mobility grouping on.  Total pages: 516096
[0.00] Kernel command line: earlyprintk earlycon=pl011,0x1c09 
console=ttyAMA0 lpj=19988480 norandmaps loglevel=8 mem=2GB root=/dev/vda1 rw 
init=/sbin/init vmalloc=768MB
[0.00] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[0.00] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[0.00] Memory: 2034232K/2097152K available (6910K kernel code, 452K 
rwdata, 2312K rodata, 448K init, 217K bss, 46536K reserved, 16384K cma-reserved)
[0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[0.00] Preemptible hierarchical RCU implementation.
[0.00] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2.
[0.00] Tasks RCU enabled.
[0.00] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[0.00] NR_IRQS: 64, 

[gem5-users] Re: Query regarding Running Custom FS image for ARM FS simulation

[Giacomo Travaglini via gem5-users]

Hi saras,

Could you post an extract of the kernel panic from m5out/system.terminal?

Kind Regards

Giacomo

From: saras nanda via gem5-users 
Date: Sunday, 26 November 2023 at 22:13
To: The gem5 Users mailing list 
Cc: saras nanda 
Subject: [gem5-users] Query regarding Running Custom FS image for ARM FS 
simulation
Hello Everyone ,

I am trying to run some benchmarks on ARM FS simulation , I have modified my 
disk image using qemu and runs successfully on qemu emulator (running qemu as 
VM ) but when I pass the same disk image to the ARM FS I get the kernel panic 
error
These are the commands I used in qemu to modify my image :

sudo qemu-system-aarch64 -m 1024 -cpu cortex-a57 -M virt -nographic -pflash 
flash0.img -pflash flash1.img -drive 
if=none,file=ubuntu-18.04-server-cloudimg-arm64.img,id=hd0 -drive 
file=user-data.img,format=raw,id=cloud -device virtio-blk-device,drive=hd0 -net 
user,hostfwd=tcp::8080-:22 -net nic -vnc :3

I have

Passed the same image to ARM FS in gem5  using the following command :

/build/ARM/gem5.opt configs/example/arm/fs_power.py 
--kernel=/home/saras/gem5-resources/src/arm-ubuntu/gem5/full_system_images/binaries/vmlinux.arm64
 
--disk=/home/saras/gem5-resources/src/arm-ubuntu/gem5/full_system_images/disks/ubuntu-18.04-server-cloudimg-arm64.img
 --caches

I have also resized the image size using qemuing command

I want to avoid the kernel panic error and mount my image successfully on gem5 
ARM FS mode .
Kindly let me know what needs to be rectified.

Thankyou

Regards
Saras


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[gem5-users] Re: m5.switchCpus for ARM starter_fs.py config

[Giacomo Travaglini via gem5-users]

Hi,

Did you call m5.instantiate before calling m5.simulate? (I don’t see it from 
the code snippet you posted)
Kind Regards

Giacomo

From: Tran, Huy Dinh via gem5-users 
Date: Thursday, 2 November 2023 at 20:33
To: gem5-users@gem5.org 
Cc: Tran, Huy Dinh 
Subject: [gem5-users] m5.switchCpus for ARM starter_fs.py config
Hi gem5 team,

I'm currently using QPoints which helps 
create checkpoints for QEMU and these checkpoints can be later used for 
simulation in gem5. QPoints uses the starter_fs.py script from 
configs/example/arm/starter_fs.py which doesn't use stdlib and very old way of 
setting up the system for gem5. QPoints also uses a gem5 version that was 2 
years ago. There has been a great amount of modifications to gem5 to make it 
compatible with QEMU checkpoints.

My task is to implement switching CPUs for this starter_fs.py script which I'm 
facing a lot of issues. I tried using the SimpleSwitchableProcessor() but I 
don't know how to connect that processor to the system. I also tried to use 
m5.switchCpus() and faced an error shown here:

build/ARM/sim/simulate.cc:107: info: Entering event queue @ 9943912964000.  
Starting simulation...
switching cpus
Traceback (most recent call last):
  File "", line 1, in 
  File "build/ARM/python/m5/main.py", line 455, in main
  File "/qpoints/gem5/configs/example/arm/my_fs.py", line 309, in 
main()
  File "/qpoints/gem5/configs/example/arm/my_fs.py", line 297, in main
m5.switchCpus(root.system, switch_cpu_list)
  File "build/ARM/python/m5/simulate.py", line 280, in switchCpus
  File "build/ARM/python/m5/SimObject.py", line 1416, in __getattr__
AttributeError: object 'TimingSimpleCPU' has no attribute 'switchedOut'
  (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)




Here is my code for implementing m5.switchCpus:



switch_cpus = O3CPU(switched_out=True)
switch_cpus_1 = TimingSimpleCPU(switched_out=False)
switch_cpus.system = root.system
switch_cpus_1.system = root.system
switch_cpus.clk_domain = root.system.clk_domain
switch_cpus_1.clk_domain = root.system.clk_domain
switch_cpus.voltage_domain = root.system.voltage_domain
switch_cpus_1.voltage_domain = root.system.voltage_domain

while True:
exit_event = m5.simulate(1)
exit_cause = exit_event.getCause()
   switch_cpu_list = [(switch_cpus, switch_cpus_1) ]
   m5.switchCpus(root.system, switch_cpu_list)
exit_event = m5.simulate(1)
exit_cause = exit_event.getCause()
break
print(exit_event.getCause())





This old version of gem5 doesn't have stdlib for ArmBoard so implementing it in 
the simple modern way is not possible. Plus, the author of QPoints made a great 
effort to modify gem5 and the script to work with QEMU checkpoints so I feel 
like I have to use the modified starter_fs.py script that was provided.

Any guidance would be greatly appreciated!

Thanks,
Huy

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[gem5-users] Re: Is SMT Supported in ARM Full System Simulation

[Giacomo Travaglini via gem5-users]

Hi all,

You can in principle try to setup an SMT simulation for the O3CPU by tweaking 
the smt parameters of the CPU [1]
In practice this has not been tested in a long time and it is very likely it is 
broken.

Kind Regards

Giacomo

[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/o3/BaseO3CPU.py#L177

From: Eliot Moss via gem5-users 
Date: Tuesday, 10 October 2023 at 13:29
To: The gem5 Users mailing list 
Cc: Abdelrahman S. Hussein , Eliot Moss 

Subject: [gem5-users] Re: Is SMT Supported in ARM Full System Simulation
On 10/10/2023 4:04 AM, Abdelrahman S. Hussein via gem5-users wrote:
> Hello,
>
> I am considering using ARM ISA for simulation on gem5. I understand that SMT 
> is NOT supported for Full System Simulation
> for x86. I just would like to know if gem5 supports SMT for Full System 
> simulation in ARM ISA.

Not as far as I know.  This has to do with the underlying
generic models used in gem5.  They are customized to each
instruction set by fiddling parameters, adding functional
units, etc., and of course the instruction formats and
actions can be adjusted.  But the nature of the models
(in-order, out-of-order) are the same.

If I am wrong I'm sure someone will correct me!

Best wishes - Eliot Moss
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[gem5-users] Re: Accessing host devices from gem5 simulator in FS mode.

[Giacomo Travaglini via gem5-users]

Hi Ashan,

In a FS simulation you would usually access a device with a driver. In general, 
it depends on the programming interface of your device.

Kind Regards

Giacomo


From: Ashan Peiris via gem5-users 
Date: Monday, 9 October 2023 at 18:41
To: gem5-users@gem5.org 
Cc: Ashan Peiris 
Subject: [gem5-users] Re: Accessing host devices from gem5 simulator in FS mode.
Hi All,

Can anyone please give me a pointer to this?

On Sun, Oct 8, 2023 at 10:55 AM Ashan Peiris 
mailto:ashan...@gmail.com>> wrote:
Hi,

Is there a way to access host devices (Eg : PCIE), from gem5 simulator in FS 
mode?

In SE mode, we have access since it doesn't have its own OS and uses host OS to 
run the simulation.

I need to get access to host devices similarly in FS mode as well. Appreciate 
your help.

--
Thanks,
Ashan


--
Thanks,
Ashan
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[gem5-users] Re: How to use Gem5 to collect instruction traces

[Giacomo Travaglini via gem5-users]

Hi Setu,

It might depend on the ISA you are using.
You can generate an instruction trace by running gem5 with --debug-flags=Exec 
option and this is valid for all ISAs. If you are simulating an Arm CPU, an 
instruction trace in the Tarmac format can also be generated.

Kind Regards

Giacomo

From: Setu Gupta via gem5-users 
Date: Tuesday, 26 September 2023 at 19:55
To: gem5-users@gem5.org 
Cc: Setu Gupta 
Subject: [gem5-users] How to use Gem5 to collect instruction traces
Hi

I want to use Gem5 to generate instruction traces which I then want to use in 
other simulators. How can I generate traces using Gem5, and what format are the 
traces in?

Thanks and Regards
Setu
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[gem5-users] Re: Assistance Required: Gem5 Example Error on WSL Ubuntu 22.04

[Giacomo Travaglini via gem5-users]

Hi Ananth,

This is a real issue I noticed myself as well (thought I didn’t have time to 
address nor to report it).
I will create an issue on GitHub hoping to find some time in the near future.

In the meantime, if this is stopping you, may I recommend you to checkout an 
earlier version of gem5? From my initial investigation it seemed to me this bug 
has been introduced 1 or 2 releases ago.

Kind Regards

Giacomo

From: Ananth.PaiJ--- via gem5-users 
Date: Wednesday, 13 September 2023 at 05:25
To: gem5-users@gem5.org 
Cc: snehith.she...@infineon.com , 
ananth.p...@infineon.com 
Subject: [gem5-users] Assistance Required: Gem5 Example Error on WSL Ubuntu 
22.04
Hello,

I hope this email finds you well. I am writing to seek assistance with a 
challenge I am facing while building Gem5 in the "util/tlm" directory on my WSL 
(Windows Subsystem for Linux) Ubuntu 22.04 environment.

Following the instructions provided in the Gem5 README file, I successfully 
executed the initial build commands:

scons build/ARM/gem5.opt
scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 
build/ARM/libgem5_opt.so
Both commands worked perfectly, resulting in the successful building of Gem5 
and the creation of a library.

However, when I attempted to build the SConstruct in the "util/tlm" directory 
by running scons, I encountered an error message:
scons: Reading SConscript files ...
AttributeError: 'Values' object has no attribute 'duplicate_sources':
  File "/home/paija/gem5/util/tlm/SConstruct", line 69:
deps += SConscript('src/SConscript', variant_dir='build/tlm', 
exports='env', duplicate=GetOption('duplicate_sources'))
  File "/home/paija/.local/lib/python3.10/site-packages/SCons/Script/Main.py", 
line 490:
return getattr(OptionsParser.values, name)
  File 
"/home/paija/.local/lib/python3.10/site-packages/SCons/Script/SConsOptions.py", 
line 118:
return getattr(self.__dict__['__defaults__'], attr)

I have thoroughly reviewed the code and dependencies in the "util/tlm" 
directory, but I have not been successful in identifying the root cause of this 
issue. I have also followed the Gem5 README instructions to the best of my 
ability.

As a WSL Ubuntu 22.04 user, I understand that there might be certain nuances 
and configurations specific to this environment. Since Gem5 is a complex tool, 
I thought it would be best to seek guidance from experts like yourself who may 
have experience in addressing similar challenges.

I would greatly appreciate it if you could provide me with some insights, 
suggestions, or steps to troubleshoot and resolve this build issue. If there 
are specific logs or details you require, please let me know, and I will be 
happy to provide them.

Your assistance would be invaluable in helping me overcome this obstacle and 
continue my work with Gem5. Thank you in advance for your time and support.

I look forward to hearing from you soon.

Best regards,
Ananth Pai J (IFIN DES PTS TI EA SME)
ananth.p...@infineon.com

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[gem5-users] Re: Help needed regarding EL2 MSR MRS instruction call (Arm-v8a aarch64) in gem5

[Giacomo Travaglini via gem5-users]

Hi Atul,

Just to clarify your setup:

Are you compiling your benchmark for Linux and running Linux + benchmark on 
gem5? Or are you running it baremetal on the simulated platform? There’s 
nothing inherently wrong on observing SVCs and MSR/MRS if your application 
contains some syscalls… If you really want to know why the CPU is going to EL2, 
you need to check your syscall trace and see if there’s anything weird.


  1.  Gem5 + Linux + benchmark -> Run your application with strace
  2.  Gem5 + benchmark -> If you run gem5 with the Exec tracer 
(“—debug-flags=Exec”) symbols will be printed in the instruction trace, so you 
will be able to gather from the function names the reason why there are many 
syscalls.

It might be this is not the reason why there is a divergence in performance 
with real hardware… However, I am curious to know why you are going to EL2 
rather than EL1 with SVC… I would check if FEAT_VHE is enabled in your 
simulation. If yes, try to disable it and let me know if you observe a 
difference (in performance). Otherwise, disable virtualization as a whole…

Kind Regards

Giacomo


From: Atul Rahman via gem5-users 
Date: Thursday, 31 August 2023 at 17:44
To: gem5-users@gem5.org 
Cc: Atul Rahman 
Subject: [gem5-users] Help needed regarding EL2 MSR MRS instruction call 
(Arm-v8a aarch64) in gem5
Hello,
I am running a benchmark binary compiled with clang with  armv8a+fp+simd+crypto 
options.
All the workloads of this compiled benchmark have similar performance in gem5 
compared to actual mobile device except this one workload (quite simple 
workload, running Convolutional Neural Network by using C++ code from scratch 
without using any external library).
I generated tarmac tracing for first few thousand instructions starting from 
the ROI.
I see that, there are SVC instructions and MSR, MRS instructions at EL2 level. 
I am failing to understand, why there is no HVC instructions in tarmac tracing 
log but I am seeing so many MSR and MRS instructions executed at EL2! I do 
think, this is causing the particular workload to perform poorly. I don’t see 
any such EL2 instructions for other workloads of the same benchmark,
I am using gem5’s fs_bigLIttle.py script (O3 ARM CPU tuned) for FS simulation.

Any insight on this topic would be very helpful. Thanks.
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[gem5-users] Re: Get gem5 output directory from python config

[Giacomo Travaglini via gem5-users]

Hi,

m5.options.outdir is probably what you are looking for.

Kind Regards

Giacomo

From: Caio Vieira via gem5-users 
Date: Wednesday, 23 August 2023 at 10:24
To: The gem5 Users mailing list 
Cc: Caio Vieira 
Subject: [gem5-users] Get gem5 output directory from python config
Hi,

I would like to know how to get the gem5 output directory (flags
--outdir=DIR, -d=DIR in gem5's binary) from the python config script. If
this feature is not implemented, then it would be nice to make it
available by creating a function in src/gem5/runtime.py and allow the
user to probe this like get_runtime_isa().

Reason: My goal is to create a better communication between host and
guest by using m5's writefile. However, I've noticed that paths given to
writefile starts from gem5's output directory. I know that I can work
around this issue by creating an argument in my python script and give
it the same value I pass to gem5 --outdir.

Cheers,
Caio Vieira
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[gem5-users] Re: IOMMU Support in GEM5 Full System Simulation

[Giacomo Travaglini via gem5-users]

Hi Chathura,

I don’t know the other ISAs, but Arm supports an IOMMU (SMMU in Arm 
terminology):

https://github.com/gem5/gem5/blob/stable/src/dev/arm/RealView.py#L1475

Kind Regards

Giacomo

From: Chathura Rajapaksha via gem5-users 
Date: Thursday, 17 August 2023 at 14:28
To: gem5-users@gem5.org 
Cc: Chathura Rajapaksha 
Subject: [gem5-users] IOMMU Support in GEM5 Full System Simulation
Hi All,

I am looking into simulating a system with an IOMMU.
I could not find any details about IOMMU in the official documentation.
Is there support for IOMMU in full system simulation (for x86, Arm or RISC-V)?
If not, are there any known open-source projects that provide this
functionality to GEM5?

Thank you in advance.
Best regards,
Chathura
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[gem5-users] Re: boot arm with kvm

[Giacomo Travaglini via gem5-users]

Hello, it would help if you could run it with gdb, place a breakpoint in 
BaseKVMCPU::setOneReg and tell us which register gem5 is trying to set



Kind Regards



Giacomo

From: 何雨彬 via gem5-users 
Date: Tuesday, 15 August 2023 at 07:00
To: gem5 
Cc: 何雨彬 
Subject: [gem5-users] boot arm with kvm

hello！

i am using gem5's KVM to accelerate my simulation, but in version 22.0, I 
encountered the following issue:

 REAL SIMULATION 
build/ARM/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config.
build/ARM/dev/arm/energy_ctrl.cc:252: warn: Existing EnergyCtrl, but no enabled 
DVFSHandler found.
build/ARM/sim/simulate.cc:192: info: Entering event queue @ 0.  Starting 
simulation...
build/ARM/cpu/kvm/base.cc:863: panic: KVM: Failed to set register 
(0x603000100042) value (errno: 22)


I found a similar error in the email list before, but after checking the 
patches, I realized that the patches were all there but the issue still wasn't 
resolved.

After that, I switched the gem5 version to 20.1.0.5, but after running it, the 
gem5's output remained stuck, and there was no output in m5term.

Here is my command line:




sudo ./build/ARM/gem5.opt ./configs/example/fs.py 
--disk=/home/lyq/gem5/benchmark/itecgo/itecgo/expand-aarch64-ubuntu-trusty-headless.img
  --kernel=/home/lyq/gem5/benchmark/itecgo/itecgo/vmlinux.euler --mem-size=12GB 
--bootloader=/home/lyq/gem5/benchmark/itecgo/boot.arm64  
--script=/home/lyq/gem5/benchmark/RCS/403.gcc.rcS --caches 
--cpu-type=ArmV8KvmCPU

Is there anything I should check? I can provide more information if needed.



Thank you for any help!

mike

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[gem5-users] Re: Config ARM DSU in Gem5 simulator

[Giacomo Travaglini via gem5-users]

Hi Ziyang,

We don’t have a DSU model in gem5. If you are not interested in modelling the 
DSU per se and you are only interested on recreating a DSU-like system (a 
DynamIQ cluster), you can proceed as you suggested.

I also encourage you to have a look at the fs_bigLITTLE.py example script [1]; 
it can serve as a good starting point.

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/stable/configs/example/arm/fs_bigLITTLE.py

From: Peng, Ziyang via gem5-users 
Date: Tuesday, 1 August 2023 at 04:11
To: gem5-users@gem5.org 
Cc: Peng, Ziyang 
Subject: [gem5-users] Config ARM DSU in Gem5 simulator
Hi all,
I am a Gem5 user currently studying with the ARM architecture. In ARM, there is 
a DSU(DyanamIQ Shared 
Unit)
 comprises the L3 memory system, control logic, and external interfaces to 
support DynamIQ cluster.
I would like to ask is there a way to configure DSU model in the Gem5 simulator 
or exist  a more detailed ARM based configuration in Gem5?
>From my understanding, I can config a L3Cache with a coherent XBar to simulate 
>the DSU part?


Thanks + regards,
Ziyang

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[gem5-users] Re: KVM with ARM host

[Giacomo Travaglini via gem5-users]

Hi

On 25/05/2023 18:50, AbdelQader AlKilany via gem5-users wrote:
Hello gem5 users,

I was wondering if anyone has recently run an ARM fs simulation using a KVM CPU 
type, and if so whether there are any instructions on how to do so.

(I've read that SE KVM is only supported with X86, but FS KVM is supported for 
ARM as well?)


Yes it is


I am using an ARM host and just to check KVM is working with my CPU I ran QEMU 
with KVM.

I have tried running scripts such as fs.py and fs_bigLITTLE.py with KVM CPU, as 
well at stdlib scripts mimicking x86-ubuntu-run-with-kvm.py.

I keep getting errors such as:

build/ALL/cpu/kvm/device.cc:96: panic: Failed to set attribute (group: 3, attr: 
0, errno: 22)
or
build/ARM/cpu/kvm/vm.cc:544: panic: KVM: Failed to create device (errno: 19)


I have already seen this error and this usually comes from an incompatibility 
between the guest/host interrupt controller (GIC).

If you are running fs_bigLITTLE.py without the --machine-type argument you are 
probably using VExpress_GEM5_V1 which uses a GICv2 controller.


It could be your host machine uses GICv3. You have 2 solutions:


a) You use VExpress_GEM5_Foundation (which has a GICv3 controller)

b) You use VExpress_GEM5_V1 (default) with the --kvm-userspace-gic option


Let me know if it works


Giacomo


[1]: 
https://github.com/gem5/gem5/blob/stable/configs/example/arm/fs_bigLITTLE.py#L303

or
build/ALL/arch/arm/kvm/base_cpu.cc:223: panic: KVM: Failed to initialize vCPU; 
errno 22 (Invalid argument)


If anyone has successfully run KVM with ARM or has also had this problem please 
let me know.

Thank you for any help 
Abdal



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[gem5-users] Re: reg installation of gem5

[Giacomo Travaglini via gem5-users]

Hi,

the ALPHA ISA has been removed from gem5.
If you still want to use ALPHA, you’ll have to checkout an older version of the 
simulator, otherwise you’ll have to pick a different ISA.

Kind Regards

Giacomo

From: Sravani Sravanam 20PHD7041 via gem5-users 
Date: Thursday, 25 May 2023 at 08:55
To: gem5 users mailing list 
Cc: Sravani Sravanam 20PHD7041 
Subject: [gem5-users] reg installation of gem5
after giving this command in the terminal sudo scons build/ALPHA/gem5.opt -j 2 
it is showing Cannot find variables file(s)
   /home/sravani/Downloads/gem5/build/ALPHA/gem5.build/variables or
   /home/sravani/Downloads/gem5/build/variables/ALPHA or default file(s)
   /home/sravani/Downloads/gem5/build_opts/ALPHA
why? i want to use gem5 in building network on chip. please help someone
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[gem5-users] Re: AttributeError when using my own binary

[Giacomo Travaglini via gem5-users]

Thanks Ziyao,

Gem5 does not support macOS syscall emulation (nor it supports Mac-O loading).. 
You can still run a gem5 simulation on macOS but you should compile the binary 
for a linux target (I don’t know If it possible to cross-compile on the M1 to 
aarch64-linux, but you can definitely (cross)compile it on a different Linux 
machine)

Hope it helps

Giacomo

From: Ziyao Yan via gem5-users 
Date: Sunday, 21 May 2023 at 15:52
To: The gem5 Users mailing list 
Cc: Ziyao Yan 
Subject: [gem5-users] Re: AttributeError when using my own binary
Hi Giacomo,

Oh I'm sorry for that confusion. The FS_ruby.py is my modified script which I 
forgot to change the name, it's actually a SE workload and works fine with the 
Gem5 provided hello binary (gem5/tests/test-progs/hello/bin/arm/linux/hello). 
Here is the code snippet of that script

binary = os.path.join('gem5/assembly/test')

# Create a process for a simple "multi-threaded" application
process = Process()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = [binary]
# Set the cpu to use the process as its workload and create thread contexts
for cpu in system.cpu:
cpu.workload = process
cpu.createThreads()

system.workload = SEWorkload.init_compatible(binary)


The gem5/assembly/test executes successfully on my local environment, and I'm 
using M1 arm64 cpu

Thanks,
Ziyao

On Sun, May 21, 2023 at 10:39 PM Giacomo Travaglini via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,

If the command line is just

$ build/ARM_MESI/gem5.opt configs/FS_ruby.py,

Are you sure you are passing the object file to the Workload object? 
(_is_compatible_with is called with a None object)
Also the script is called FS ruby but you seem to have instantiated a SE 
workload (ArmSeWorkload).

There’s something wrong in the custom script…

Kind Regards

Giacomo

From: Ziyao Yan via gem5-users mailto:gem5-users@gem5.org>>
Date: Sunday, 21 May 2023 at 09:30
To: gem5-users@gem5.org<mailto:gem5-users@gem5.org> 
mailto:gem5-users@gem5.org>>
Cc: Ziyao Yan mailto:ziyao...@umich.edu>>
Subject: [gem5-users] AttributeError when using my own binary
Hi all,

I'm currently working on ISA-level tasks and have generated my own binary using 
an assembler and linker. The binary executes successfully on my local 
environment (M1 ARM). However, when I attempt to run it on gem5, it fails to be 
recognized.

I used the following commands to assemble and link a simple "Hello World" 
assembly code (test.s):

$ as -arch arm64 -o test.o test.s
$ ld test.o -o test -l System -syslibroot `xcrun -sdk macosx --show-sdk-path` 
-e _start -arch arm64
$ ./test
Hello World!

While this works well on my local environment, I encounter an error when 
executing it in gem5 using the command:

$ build/ARM_MESI/gem5.opt configs/FS_ruby.py
The error message I receive is as follows:

AttributeError: 'NoneType' object has no attribute 'get_arch'
At:
  build/ARM_MESI/arch/arm/ArmSeWorkload.py(43): _is_compatible_with
  build/ARM_MESI/sim/Workload.py(91): 
  build/ARM_MESI/sim/Workload.py(91): find_compatible
  build/ARM_MESI/sim/Workload.py(100): init_compatible
  configs/FS_ruby.py(109): 
  build/ARM_MESI/python/m5/main.py(434): main

I would greatly appreciate it if anyone who has encountered a similar issue 
could provide some insights or guidance.

Thank you,
Ziyao

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[gem5-users] Re: AttributeError when using my own binary

[Giacomo Travaglini via gem5-users]

Hi,

If the command line is just

$ build/ARM_MESI/gem5.opt configs/FS_ruby.py,

Are you sure you are passing the object file to the Workload object? 
(_is_compatible_with is called with a None object)
Also the script is called FS ruby but you seem to have instantiated a SE 
workload (ArmSeWorkload).

There’s something wrong in the custom script…

Kind Regards

Giacomo

From: Ziyao Yan via gem5-users 
Date: Sunday, 21 May 2023 at 09:30
To: gem5-users@gem5.org 
Cc: Ziyao Yan 
Subject: [gem5-users] AttributeError when using my own binary
Hi all,

I'm currently working on ISA-level tasks and have generated my own binary using 
an assembler and linker. The binary executes successfully on my local 
environment (M1 ARM). However, when I attempt to run it on gem5, it fails to be 
recognized.

I used the following commands to assemble and link a simple "Hello World" 
assembly code (test.s):

$ as -arch arm64 -o test.o test.s
$ ld test.o -o test -l System -syslibroot `xcrun -sdk macosx --show-sdk-path` 
-e _start -arch arm64
$ ./test
Hello World!

While this works well on my local environment, I encounter an error when 
executing it in gem5 using the command:

$ build/ARM_MESI/gem5.opt configs/FS_ruby.py
The error message I receive is as follows:

AttributeError: 'NoneType' object has no attribute 'get_arch'
At:
  build/ARM_MESI/arch/arm/ArmSeWorkload.py(43): _is_compatible_with
  build/ARM_MESI/sim/Workload.py(91): 
  build/ARM_MESI/sim/Workload.py(91): find_compatible
  build/ARM_MESI/sim/Workload.py(100): init_compatible
  configs/FS_ruby.py(109): 
  build/ARM_MESI/python/m5/main.py(434): main

I would greatly appreciate it if anyone who has encountered a similar issue 
could provide some insights or guidance.

Thank you,
Ziyao

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[gem5-users] Re: Multi-level TLB is implemented in performance

[Giacomo Travaglini via gem5-users]

Just for the sake of completeness (I know Arun asked about X86).
There is a multi-level TLB for Arm; it is possible for other ISAs to implement 
the same, it requires a developer to move the translateAtomic/Timing methods 
from the TLB to the MMU

Kind Regards

Giacomo

From: Jason Lowe-Power via gem5-users 
Date: Thursday, 18 May 2023 at 16:38
To: The gem5 Users mailing list 
Cc: Laney Laney <522808...@qq.com>, Arun Kavumkal , 
Jason Lowe-Power 
Subject: [gem5-users] Re: Multi-level TLB is implemented in performance
There is not a multi-level TLB model in mainline gem5.

Cheers,
Jason

On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,
Can anyone please tell me whether a multi-level TLB implementation is currently 
available for x86?

Thanks
Arun

On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Yes, this is possible, and I believe it's already implemented for Arm.

The best place to start is src/arch//tlb.cc

Cheers,
Jason

On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,all. I would like to know if it is possible to implement multi-level TLB on 
gem5 performance by modeling the latency of TLB. If so, which files or 
functions should I start with?
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[gem5-users] Re: Identify ARM Big/Little CPU

[Giacomo Travaglini via gem5-users]

Are you using the fs_bitLITTLE.py script?
Big/Little CPUs should be grouped under the bigCluster/littleCluster SimObjects.

This should be visible in both config.ini and in the stats file (e.g.)

[…]
system.bigCluster.clk_domain.clock500   # 
Clock period in ticks (Tick)
system.bigCluster.cpus0.numCycles  627273   # 
Number of cpu cycles simulated (Cycle)
system.bigCluster.cpus0.numWorkItemsStarted0   
# Number of work items this cpu started (Count)
system.bigCluster.cpus0.numWorkItemsCompleted0  
 # Number of work items this cpu completed (Count)

So you should be able to match stats with the correct cpu type…

Is this what you meant?

Kind Regards

Giacomo

From: inderjitsingh.davu--- via gem5-users 
Date: Monday, 1 May 2023 at 04:41
To: gem5-users@gem5.org 
Cc: inderjitsingh.d...@gmail.com 
Subject: [gem5-users] Identify ARM Big/Little CPU

I am running ARM big.Little simulations. (eg. Big=2, Little=2)

I am unaware to identify which CPU0-CPU3 is Big and which is Little.

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[gem5-users] Re: SE mode with dynamic linking

[Giacomo Travaglini via gem5-users]

Hi Iana,

In theory it shouldn't be a problem to run a dynamically linked binary on a Arm 
host... Could you run the application with GDB and check why the mmap is 
failing?

Kind Regards

Giacomo

From: Iana Chertkova via gem5-users 
Sent: 28 April 2023 03:24
To: gem5-users@gem5.org 
Cc: Iana Chertkova 
Subject: [gem5-users] SE mode with dynamic linking

Hello,
Is it possible to run dynamically linked binary in SE mode on ARM system and 
for ARM? I'm trying to do it using --redirects /lib64=/usr/lib64 for dynamic 
libs , but it isn't working. I got an error build/ARM/sim/vma.cc:142: panic: 
Failed to map file into host address space: Invalid argument. I saw message 
that it works only for x86, but it is old information. Could you recommend 
something for me please?

Best regards
Iana

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[gem5-users] Re: qemu boot ubuntu image from gem5_guest_binaries fail

[Giacomo Travaglini via gem5-users]

Hi,


I am not surprised. The disk image contains an init script with m5 operations 
(probably m5 readfile).

m5 is a gem5 specific pseudo-instruction and does not get recognised by QEMU.


You should either amend the init file within the disk or point to a different 
init executable from QEMU command line (for example /bin/bash)


Kind Regards


Giacomo


On 26/04/2023 08:59, 李强 via gem5-users wrote:
Hi:

I am currently trying to boot ubuntu-18.04-arm64-docker.img using QEMU. The 
image file was extracted from aarch-system-20220707.tar.bz2, which I downloaded 
from https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries. 
I compiled my own kernel using the following commands:


```
git clone https://gem5.googlesource.com/arm/linux
make ARCH=arm64 CROSS_COMPILER=aarch64-linux-gnu- gem5_defconfig
make ARCH=arm64 CROSS_COMPILER=aarch64-linux-gnu- -j32
```

However, I encountered an error when I tried to boot using the QEMU command:

```
qemu-system-aarch64 \
-m 4096 \
-cpu cortex-a57 \
-nographic \
-machine virt \
-kernel /home/dev/gem5-all/power/prep/my-disks/linux/arch/arm64/boot/Image \
-append 'root=/dev/vda1 rw rootwait mem=4096M console=ttyAMA0,38400n8' \
-device virtio-blk-device,drive=image \
-drive 
if=none,id=image,file=/home/dev/gem5-all/power/prep/disks/ubuntu-18.04-arm64-docker.img

```

The error message I received was "

--[ end Kernel panic - not syncing: Attempted to kill init! 
exitcode=0x8400".


full log message is in attachment.

Could you please provide me with assistance on how to resolve this issue?

Thank you for your time and support.

Best regards,

Leon





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[gem5-users] Re: gem5 SVE vectoe length

[Giacomo Travaglini via gem5-users]

Hi Zhang,


That parameter configures the *maximum* (hardware constrained) vector length.

It is possible to choose a different (smaller) vector length for a process by 
configuring the following registers


ZCR_EL1 [1]

ZCR_EL2 [2]

ZCR_EL3 [3]


So I believe the problem is that while you are properly setting up the gem5 
parameter, those registers have been configured for a smaller vector length.


What happens if you change the vector length from the guest?

In Linux you can either change /proc/sys/abi/sve_default_vector_length 
(requires root permission) or use the prctl syscall [4] (from your program) 
with the PR_SVE_SET_VL flag.

Let me know if this works...


Kind Regards


Giacomo


[1]: 
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL1--SVE-Control-Register--EL1-?lang=en

[2]: 
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL2--SVE-Control-Register--EL2-?lang=en

[3]: 
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL3--SVE-Control-Register--EL3-?lang=en

[4]: https://man7.org/linux/man-pages/man2/prctl.2.html


On 20/04/2023 09:22, 等价无穷小 via gem5-users wrote:
Dear gem5 Community,

I hope this email finds you well. I am currently working on a project that 
involves using ARM SVE in gem5 FS mode, and I have encountered a problem that I 
would appreciate your help with.

While using the ARM SVE in gem5 FS mode, I added the command line parameter "--param 
'system.sve_vl = 16'" to specify the vector length. However, when I tried to 
retrieve the system vector length using the SVE intrinsic svcntb(), the result I obtained 
was a vector length of 256 bits. This is different from the expected result based on the 
parameter I set.

I am unsure if I have missed any important steps or if there is an issue with 
my configuration. I would be grateful if you could provide guidance on this 
matter or point me to any relevant resources or examples that could help me 
resolve the issue.

Thank you in advance for your assistance, and I look forward to your response.

Best regards,
Zhang Meng








[https://thirdqq.qlogo.cn/g?b=oidb=5VZd2RcseTmsoyuvL8f5OQ=0]
等价无穷小
zhang...@foxmail.com



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[gem5-users] Re: Checking if Arm PA works

[Giacomo Travaglini via gem5-users]

Hi,


FEAT_PAuth should be enabled by default, unless you are using a really old 
version of gem5.

May I suggest you to debug the instruction (or ArmISA::auth) with gdb to 
understand what is going on?


autib should generate an exception if FEAT_PAuth is disabled (and shouldn't be 
treated as NOP)


Kind Regards


Giacomo


On 06/04/2023 19:55, Kar, Anurag Arunkumar wrote:
Posting a follow up to this:

Do I need to enable PAuth in some way? Right now I see that the pointers don’t 
really have anything in their upper bits and almost feels like the AUT 
instructions are being treated as NOPs. I’m running with the IEW debug flag on 
with some added debug statements of my own.

Here, I manually inserted the 0xf in the top byte of the register 182 but it 
causes the execution to have a page table fault and abort.

[cid:part1.qJb1yqx7.35RiUdqu@arm.com]

Regards,
Anurag

From: Giacomo Travaglini 

Date: Thursday, March 16, 2023 at 5:15 AM
To: The gem5 Users mailing list 

Cc: Kar, Anurag Arunkumar 
Subject: Re: [gem5-users] Checking if Arm PA works

Hi,
On 15/03/2023 23:34, Kar, Anurag Arunkumar via gem5-users wrote:
Hi,

I’m trying to use Arm Pointer Authentication (Arm v8.3 PAC extension) with a 
cross compiled binary which has the PAC instructions with return address 
signing (I checked, the instructions are there).

I tried inserting some std::cout print statements in the ArmISA::auth function 
in pauth_helpers.cc. I’m just trying to see if it gets triggered and I didn’t 
see my print on the terminal. Is there a way for me to be sure PAuth is working 
as it should be before I start making modifications?



Are you running in SE or FS mode?

First of all I would check if my binary is executing correctly (does it work as 
intended?). Then you could run with



build/ARM/gem5.opt --debug-flags=Exec [...]



This will print the instruction trace to stdout; you can pipe it to a file and 
see if there's any PAC instruction being executed.



Kind Regards



Giacomo



Apologies if the question is basic.

Regards,
Anurag Kar



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[gem5-users] Re: Does Gem5 support arm64 SVE2?

[Giacomo Travaglini via gem5-users]

Hi Shuo,

That’s correct; we don’t fully support SVE2 for now…
We *might* have a partial implementation as we support SME (in develop branch; 
it will be merged in next release)

Kind Regards

Giacomo

From: Ayaz Akram via gem5-users 
Reply to: The gem5 Users mailing list 
Date: Tuesday, 11 April 2023 at 05:57
To: The gem5 Users mailing list 
Cc: Shuo , Ayaz Akram 
Subject: [gem5-users] Re: Does Gem5 support arm64 SVE2?

Hi Shuo,

If I am not mistaken, I think gem5 only supports SVE instructions.

-Ayaz

On Sun, Apr 9, 2023 at 7:44 PM Shuo via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
hello,

Does Gem5 support arm64 SVE2(Scalable Vector Extension2)?

Yours
Shuo
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[gem5-users] Re: gem5::cxxConfigInit is missing while trying to build utils/tlm examples

[Giacomo Travaglini via gem5-users]

This has been fixed by:

https://gem5-review.googlesource.com/c/public/gem5/+/66851/3

And it will be available in next release

Kind Regards

Giacomo

From: Artak Arakelyan via gem5-users 
Reply to: The gem5 Users mailing list 
Date: Monday, 3 April 2023 at 15:49
To: "gem5-users@gem5.org" 
Cc: Artak Arakelyan 
Subject: [gem5-users] gem5::cxxConfigInit is missing while trying to build 
utils/tlm examples

I'm trying to build the utils/tlm examples following the README

the compiler reports
build/tlm/sim_control.cc:75:11: error: 'cxxConfigInit' is not a member of 'gem5'
 gem5::cxxConfigInit();
   ^

grep does not find any  cxxConfigInit declaration in gem5 cloned repo

The --with-cxx-config has been set while compiling the libgem5_opt.so according 
to README


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[gem5-users] Re: Checking if Arm PA works

[Giacomo Travaglini via gem5-users]

Hi,

On 15/03/2023 23:34, Kar, Anurag Arunkumar via gem5-users wrote:
Hi,

I’m trying to use Arm Pointer Authentication (Arm v8.3 PAC extension) with a 
cross compiled binary which has the PAC instructions with return address 
signing (I checked, the instructions are there).

I tried inserting some std::cout print statements in the ArmISA::auth function 
in pauth_helpers.cc. I’m just trying to see if it gets triggered and I didn’t 
see my print on the terminal. Is there a way for me to be sure PAuth is working 
as it should be before I start making modifications?


Are you running in SE or FS mode?

First of all I would check if my binary is executing correctly (does it work as 
intended?). Then you could run with


build/ARM/gem5.opt --debug-flags=Exec [...]


This will print the instruction trace to stdout; you can pipe it to a file and 
see if there's any PAC instruction being executed.


Kind Regards


Giacomo


Apologies if the question is basic.

Regards,
Anurag Kar



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[gem5-users] Re: Error: Can't find a working Python installation redux

[Giacomo Travaglini via gem5-users]

Hi Anurag

On 15/03/2023 12:57, Kar, Anurag Arunkumar via gem5-users wrote:
Hi,

I tried following previous archived threads which said the solution to this 
problem was to provide the path to  PYTHON_CONFIG and not using a conda 
environment.

I am not using a conda environment and am providing the path in the scons 
command:

scons ./build/ARM_MESI_Three_Level/gem5.opt PYTHON_CONFIG=/usr/bin/python-config
scons: Reading SConscript files ...
Mkdir("/data/anurag/gem5-public/build/ARM_MESI_Three_Level/gem5.build")
Checking for linker -Wl,--as-needed support... (cached) yes
Checking for compiler -Wno-free-nonheap-object support... (cached) yes
Checking for compiler -gz support... (cached) yes
Checking for linker -gz support... (cached) yes
Info: Using Python config: python3-config
Checking for C header file Python.h... (cached) yes
Checking Python version... no
Error: Can't find a working Python installation


It seems like SCons is able to find the Python.h header file but it is not able 
to gather the python version of the interpreter for whatever reason (check 
CheckPythonLib). When I have these sporadic errors I usually remove the build 
folder and start a clean build. If the error is still present, you might want 
to debug CheckPythonLib with pdb.


If you don't want to do any debugging, you should consider using docker [1]


[1]: https://www.gem5.org/documentation/general_docs/building


Hope it helps


Giacomo


I have been able to build gem5 on this very machine before, I’m not sure what 
changed between then and now. Can someone help me debug this?

Regards,
Anurag



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[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

[Giacomo Travaglini via gem5-users]

Hi Jonathan,


On 08/03/2023 17:47, Jonathan Kang wrote:
Thanks Giacomo,

A few questions:


 1.  Who is Jason? So that I can contact him 


Jason Lowe-Power, here CCed



 1.  Regarding ELFie, I found these:
*   
https://github.com/UT-LCA/Scalability-Phase-Simpoint-of-SPEC-CPU2017/releases
*   https://github.com/intel/pinball2elf

#2 would seem to be able to generate ELFies from the x86 pinballs that were 
captured. However, I’m unfamiliar with how ELFies work. Do they still capture 
state and thus need to inject processor state prior to simulation? In which 
case the problem still exists that the ARM Cycle Model is incompatible….


The ELFie methodology generates guest bootcode which injects the architectural 
state before the beginning of the SimPoint


Kind Regards


Giacomo


Thanks,

Jonathan.

From: Giacomo Travaglini 

Date: Wednesday, March 8, 2023 at 6:26 AM
To: The gem5 Users mailing list 

Cc: Jonathan Kang 
Subject: Re: [gem5-users] Capturing SimPoint and running on ARM CycleModel
Hi Jonathan On 08/03/2023 01: 43, Jonathan Kang via gem5-users wrote: Hi all, 
I’m attempting to get SPEC 2k17 to run on our performance model that uses an 
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I 
was wondering
ZjQcmQRYFpfptBannerStart
This Message Is From an External Sender

ZjQcmQRYFpfptBannerEnd

Hi Jonathan
On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
Hi all,

I’m attempting to get SPEC 2k17 to run on our performance model that uses an 
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I 
was wondering if anyone has had experience capturing SimPoints using Gem5 and 
then running the resulting reduced binary on a Cycle Model. I know you can do 
it easily on Gem5 simple CPU in SE mode but I need it to work with our more 
accurate model.



You can easily generate SimPoints with gem5 as you correctly said. The problem 
is the checkpoint incompatibility between gem5 and Cycle Model. (restoring the 
gem5 checkpoint from the CA simulator).

It would be nice if we could generate an ELFie [1] from a gem5 checkpoint. As I 
have recently seen some commits mentioning ELFies you could ask Jason and his 
group if there's something going on...



Kind Regards



Giacomo



[1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340



Thanks in advance!

Jonathan Kang.



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[gem5-users] Re: Capturing SimPoint and running on ARM CycleModel

[Giacomo Travaglini via gem5-users]

Hi Jonathan

On 08/03/2023 01:43, Jonathan Kang via gem5-users wrote:
Hi all,

I’m attempting to get SPEC 2k17 to run on our performance model that uses an 
ARM Cycle Model (A55). Obviously it’d take forever to run the whole binary so I 
was wondering if anyone has had experience capturing SimPoints using Gem5 and 
then running the resulting reduced binary on a Cycle Model. I know you can do 
it easily on Gem5 simple CPU in SE mode but I need it to work with our more 
accurate model.


You can easily generate SimPoints with gem5 as you correctly said. The problem 
is the checkpoint incompatibility between gem5 and Cycle Model. (restoring the 
gem5 checkpoint from the CA simulator).

It would be nice if we could generate an ELFie [1] from a gem5 checkpoint. As I 
have recently seen some commits mentioning ELFies you could ask Jason and his 
group if there's something going on...


Kind Regards


Giacomo


[1]: https://dl.acm.org/doi/abs/10.1109/CGO51591.2021.9370340


Thanks in advance!

Jonathan Kang.



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[gem5-users] Re: There is not 'IsFloating' in arm/operands.isa

[Giacomo Travaglini via gem5-users]

Hi Haseung

On 06/03/2023 11:47, 봉하승 wrote:

Hi Giacomo,

Got it, thanks for your reply.

Can you tell me what architecture or processor the default ARM configuration 
used in gem5'O3CPU is based on?


The O3CPU is ISA agnostic, so it is not Arm specific. The architecture under 
use is defined by the ArmRelease object (not from the CPU type) and it is 
configurable from python. We run with the following extensions turned on by 
default in FS mode.


https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L129


You can tweak the release object and provide your own version, but unless there 
is a real motivation I would recommend you to stick with one of the architected 
versions (Armv8.1, Armv8.2, etc)


Kind Regards


Giacomo



Regards

Hasueng

2023년 3월 6일 (월) 오후 7:01, Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>>님이 작성:
Hi Haseung,

In Arm FP registers share the same storage with SIMD (Vector) registers, so we 
usually refer to them as SIMD registers.
This is why in gem5 we don’t use the floating point register type and we use 
the vector type only

Kind Regards

Giacomo

From: 봉하승 via gem5-users mailto:gem5-users@gem5.org>>
Reply to: The gem5 Users mailing list 
mailto:gem5-users@gem5.org>>
Date: Saturday, 4 March 2023 at 14:25
To: "gem5-users@gem5.org" 
mailto:gem5-users@gem5.org>>
Cc: "hasu...@ajou.ac.kr" 
mailto:hasu...@ajou.ac.kr>>
Subject: [gem5-users] There is not 'IsFloating' in arm/operands.isa


Hi,

I'm trying to use gem5 to simulate SPEC2017's LBM.

LBM is an FP workload, and the simulation shows that 
"system.switch_cpus.commit.floating" is zero in stats.txt.

As a result of a little search, it was confirmed that instructions such as fadd 
and fsub were classified as 'isVector'.

I wonder why fadd is not 'isFloating' but 'isVector'. And when classified like 
this, is there any possibility of simulation error in inst_queue or fu_pool?
If you know, please reply.

Thanks,

Haseung

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[gem5-users] Re: There is not 'IsFloating' in arm/operands.isa

[Giacomo Travaglini via gem5-users]

Hi Haseung,

In Arm FP registers share the same storage with SIMD (Vector) registers, so we 
usually refer to them as SIMD registers.
This is why in gem5 we don’t use the floating point register type and we use 
the vector type only

Kind Regards

Giacomo

From: 봉하승 via gem5-users 
Reply to: The gem5 Users mailing list 
Date: Saturday, 4 March 2023 at 14:25
To: "gem5-users@gem5.org" 
Cc: "hasu...@ajou.ac.kr" 
Subject: [gem5-users] There is not 'IsFloating' in arm/operands.isa


Hi,

I'm trying to use gem5 to simulate SPEC2017's LBM.

LBM is an FP workload, and the simulation shows that 
"system.switch_cpus.commit.floating" is zero in stats.txt.

As a result of a little search, it was confirmed that instructions such as fadd 
and fsub were classified as 'isVector'.

I wonder why fadd is not 'isFloating' but 'isVector'. And when classified like 
this, is there any possibility of simulation error in inst_queue or fu_pool?
If you know, please reply.

Thanks,

Haseung

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[gem5-users] Re: Attempted to execute unimplemented instruction 'msr' (inst 0xd51e4100)

[Giacomo Travaglini via gem5-users]

Hi ikram,

On 01/02/2023 10:19, IKRAM via gem5-users wrote:
Hi

Below are commands and log info of the error mentioned in the subject line.

Info of workload is:

file demo.elf

demo.elf: ELF 64-bit LSB executable, ARM aarch64, version 1 (SYSV), statically 
linked, with debug_info, not stripped


build/ARM/gem5.opt configs/learning_gem5/part1/two_level.py

command line: build/ARM/gem5.opt configs/learning_gem5/part1/two_level.py
build/ARM/base/loader/elf_object.cc:355: warn: Ignoring empty loadable segment 8
build/ARM/base/loader/elf_object.cc:355: warn: Ignoring empty loadable segment 9
Global frequency set at 1 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and 
pdf.
build/ARM/mem/dram_interface.cc:690: warn: DRAM device capacity (8192 Mbytes) 
does not match the address range assigned (512 Mbytes)
build/ARM/base/loader/elf_object.cc:355: warn: Ignoring empty loadable segment 8
build/ARM/base/loader/elf_object.cc:355: warn: Ignoring empty loadable segment 9
build/ARM/arch/arm/linux/se_workload.cc:73: warn: Unknown operating system; 
assuming Linux.
0: system.remote_gdb: listening for remote gdb on port 7000
Beginning simulation!
build/ARM/sim/simulate.cc:192: info: Entering event queue @ 0.  Starting 
simulation...
build/ARM/arch/arm/faults.cc:822: panic: Attempted to execute unimplemented 
instruction 'msr' (inst 0xd51e4100)


As you can see here you are hitting a panic as you encountered a MSR 
instruction. This is a privileged instruction and usually you cannot execute it 
in SE mode (which runs in userspace). This is why simulation is throwing an 
undefined instruction exception.

You need to figure out why your binary is producing a privileged instruction. 
My bet is that you cross-compiled the application with a baremetal toolchain. 
You need to use a GNU/Linux one to produce a linux application.


See https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads


Kind Regards


Giacomo

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[gem5-users] Re: How to use different clock frequency in cpu and system

[Giacomo Travaglini via gem5-users]

Hi, there is no command-line option, but you just need to edit the system 
frequency in BaseSimpleSystem [1]

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/stable/configs/example/arm/devices.py#L274

From: Νικόλαος Ταμπουρατζής via gem5-users 
Date: Friday, 23 December 2022 at 13:19
To: gem5-users 
Cc: Νικόλαος Ταμπουρατζής 
Subject: [gem5-users] How to use different clock frequency in cpu and system

Dear gem5 community,

I am using configs/example/arm/starter_fs.py configuration in order to
simulate ARM FS. However, I would like to use different clock
frequencies in the CPU and different in the system clock. Is there
this option in the latest gem5 release?

Thank you!

Best regards,
Nikos
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[gem5-users] Re: Switch CPU clock speed

[Giacomo Travaglini via gem5-users]

Hi,

I would say it depends on the config script you are using.
For example se.py is a correctly assigning different clock domains between the 
system and the CPUs:


system.clk_domain = SrcClockDomain(
clock=args.sys_clock, voltage_domain=system.voltage_domain
)

[…]

system.cpu_clk_domain = SrcClockDomain(
clock=args.cpu_clock, voltage_domain=system.cpu_voltage_domain
)

[…]

for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain


and finally, in Simulation.run:

515 for i in range(np):
516 if options.fast_forward:
517 testsys.cpu[i].max_insts_any_thread = 
int(options.fast_forward)
518 switch_cpus[i].system = testsys
519 switch_cpus[i].workload = testsys.cpu[i].workload
520 switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain


But these are just example scripts wrapping the m5.switchCpu API. Could it be 
that you are using a different script which is not performing the last 
assignment to the switch cpus?

Kind Regards

Giacomo



From: FILIPPO LANDI via gem5-users 
Date: Tuesday, 6 December 2022 at 16:20
To: gem5-users@gem5.org 
Cc: FILIPPO LANDI 
Subject: [gem5-users] Switch CPU clock speed
Hi, I'm using gem5 in gem5-aladdin software.
Using the fast forward option the switch cpu uses the system clock instead of 
the cpu clock.

I just want to know if it was a bug in an old gem5 version or it is a 
limitation of the simulator etc.
Maybe someone have tested it in a new build so can tell me if the clock is what 
they expect to be.

Thank you!
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[gem5-users] Re: Add custom Register In ARM

[Giacomo Travaglini via gem5-users]

Hi,

If you are just planning on introducing a single register, you could consider 
extending the number of IntRegs, or to add this extra register as a MiscReg 
(but be careful in the latter case, as MiscRegs are not renamed).

If you really want to define a new register class, we have recently pushed some 
patches which are implementing FEAT_SME in gem5 by adding matrix registers.
I suggest you have a look at the following patches:

https://gem5-review.googlesource.com/c/public/gem5/+/64333/1
https://gem5-review.googlesource.com/c/public/gem5/+/64334/1

You could use them as an example/to get an idea on what should be done

Kind Regards

Giacomo

From: 等价无穷小 via gem5-users 
Date: Tuesday, 29 November 2022 at 11:15
To: gem5-users 
Cc: 等价无穷小 
Subject: [gem5-users] Add custom Register In ARM
Hi all,
Recently, I wanted to add a new custom register in gem5, and the load/store 
instruction can take the custom register as src/dest register to move data from 
memory. Is there some suggestions about this?

And I have some confusion about the register implementation in gem5. In 
src/cpu/reg_class.hh/cc file, defining the RegClass and RegId class, if I add a 
new custom register, should I add a new Regclass, like CustomClass, and give it 
new RegId? And in the src/arch/arm, there are five files about the register: 
ccregs.hh、intregs.hh、miscregs.hh/cc 、registers.hh .In these files, everyone of 
these file almost enumorate the RegIndex, I understand it just a signature of a 
register, how can i map the register to the signature?

Thanks,
ZhangMeng
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[gem5-users] Re: Simulation of ARM TrustZone

[Giacomo Travaglini via gem5-users]

Hello, yes, it is supported.

You could use the following blog post [1] as a starting point. There was also a 
talk at the ISCA2022 workshop about booting OP-TEE in gem5; you could probably 
look for it on youtube IIRC

Kind Regards

Giacomo

[1]: 
https://community.arm.com/arm-research/b/articles/posts/running-trusted-firmware-a-on-gem5

From: Pavitra bhade via gem5-users 
Date: Tuesday, 29 November 2022 at 07:33
To: gem5-users@gem5.org , 
gem5-users-confirm+e2f5a27c00581d0f4a3594969c833c80e0f57...@gem5.org 
, 
gem5-users-j...@gem5.org 
Cc: Pavitra bhade 
Subject: [gem5-users] Simulation of ARM TrustZone
Dear All,

I am interested in simulating the ARM TrustZone on Gem5. Is that supported?

--
Pavitra Prakash Bhade
Ph.D. Student
Indian Institute of Technology Goa


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[gem5-users] Re: Slow checkpoint creation

[Giacomo Travaglini via gem5-users]

This is weird; it never took me more than 20 seconds to generate a single 
checkpoint in gem5.
I suspect most of the time is spent on draining the system.

Would you be able to debug which draining method is stalling the checkpointing 
process?

Kind Regards

Giacomo


From: Hanhwi Jang via gem5-users 
Date: Sunday, 13 November 2022 at 18:27
To: gem5-users@gem5.org 
Cc: Hanhwi Jang 
Subject: [gem5-users] Slow checkpoint creation
Hi everyone,

I recently returned to gem5 and tried to create SimPoints for SPEC and other 
workloads on ARM architecture.

gem5 works great as usual, but I am curious why it takes 10~30 mins to write 
just a single checkpoint. The simulated system has 16 GB DRAM. Typically taking 
a snapshot of a similar system spends just a couple of minutes if we use 
VMware, QEMU, or other hypervisors.

Is there anyone who dug into this issue?

Thanks,
Hanhwi
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[gem5-users] Re: panic: KVM: Failed to set register (0x6030000000100042) value

[Giacomo Travaglini via gem5-users]

Hello, it was a bug which got fixed by the following patches, which are merged 
in develop and will be part of next release

https://gem5-review.googlesource.com/c/public/gem5/+/64072/4
https://gem5-review.googlesource.com/c/public/gem5/+/64073/4

Let me know if it works

Kind Regards

Giacomo

From: Xiongfei Liao (廖雄飛) via gem5-users 
Date: Thursday, 3 November 2022 at 11:19
To: gem5-users@gem5.org 
Cc: Xiongfei Liao (廖雄飛) 
Subject: [gem5-users] panic: KVM: Failed to set register (0x603000100042) 
value
Hi,

We try to run a full-system simulation using ARMV8KvmCPU. The simulation cannot 
get started due to the below failure of setting register PSTATE.

-
… …
  0: system.kvm_vm: Mapping 8 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0xaebcb000 -> 0x0 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0xbb027000 -> 0x400 [size: 
0x4]
  0: system.kvm_vm: Mapping region: 0x0xacbcb000 -> 0x600 [size: 
0x200]
  0: system.kvm_vm: Mapping region: 0x0xa8bcb000 -> 0x800 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0xa4bcb000 -> 0xc00 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0xa2bcb000 -> 0x1800 [size: 
0x200]
  0: system.kvm_vm: Mapping region: 0x0xbc1b4000 -> 0x2e00 [size: 
0x8000]
  0: system.kvm_vm: Mapping region: 0x0x22bcb000 -> 0x8000 [size: 
0x8000]
build/ARM/cpu/kvm/base.cc:150: info: KVM: Coalesced MMIO disabled by config.
  0: system.littleCluster.cpus:   MPIDR(EL1) := 0x8000
build/ARM/dev/arm/energy_ctrl.cc:252: warn: Existing EnergyCtrl, but no enabled 
DVFSHandler found.
build/ARM/sim/simulate.cc:194: info: Entering event queue @ 0.  Starting 
simulation...
  0: system.littleCluster.cpus: Attaching cycle counter...
  0: system.littleCluster.cpus: In updateKvmState():
  0: system.littleCluster.cpus:   PSTATE := 0x3cd
build/ARM/cpu/kvm/base.cc:863: panic: KVM: Failed to set register 
(0x603000100042) value (errno: 22)
Memory Usage: 2693544 KBytes
Program aborted at tick 0
… …
---

This register 0x603000100042 is legal and 64-bit based on the document at 
the link: https://www.kernel.org/doc/Documentation/virtual/kvm/api.txt

What could be the reason for this? ARM CPU or software or anything else?

Any tips/suggestions are appreciated.

Thanks in advance.

All the best,
Xiongfei Liao

===

The environment settings are as below.
Host:
ARM server: Ampere eMag 2019
OS & Kernel: Ubuntu 20.04.5 LTS (GNU/Linux 5.4.0-131-generic aarch64)

Simulator:
gem5: cloned on Oct 27, 2022
bootloader: gem5 binaries 20220707/binaries/boot.arm64
kernel: gem5 binaries 20220707/binaries/vmlinux.arm64
disk: gem5 binaries ubuntu-18.04-arm64-docker.img


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[gem5-users] Re: TraceCPU and ARM ETM

[Giacomo Travaglini via gem5-users]

Hi Jonathan, thanks for your email.


I haven't heard of anything like that, but it would be really nice to have an 
ETM trace player available in gem5.

Have you had a look at the TraceCPU documentation available in the gem5 
website? [1]

The TraceCPU is really supposed to be used for memory-system design 
explorations, abstracting away the core microarchitecture. Is this what you

are looking for? Are you just interested on injecting instruction/data packets, 
or do you want your trace player to parse and act on a richer set of 
information?



If that is the case, doing an off-line translation from ETM format to elastic 
trace format might not be what you are looking for. What you could do is to

*re-use* part of the TraceCPU code (basically the back-end packet generation) 
and write your own front-end (ETM parser) and middle logic.



Let me know what you think about it.



Kind regards,



Giacomo


From: Jonathan Kang via gem5-users 
Sent: 13 April 2022 22:17
To: gem5-users@gem5.org 
Cc: Jonathan Kang 
Subject: [gem5-users] TraceCPU and ARM ETM


Hi all,



I’m new to Gem5 (just Googled it) and am interested in TraceCPU. A bit of 
background on what I’m trying to achieve:



  1.  I have a device (Snapdragon) that I am capturing ARM ETM traces on.
  2.  I’m looking for a way to use a trace-driven CPU model to replay these ARM 
traces in my performance model.
  3.  Unfortunately, the models from ARM do not support trace-driven; they’re 
execution-driven only.



I’ve read that TraceCPU does consume a trace but that it only supports traces 
that are generated by O3CPU (with certain timing annotations).



I was wondering: has anyone tried converting ETM (possibly with timestamps?) 
into a format that TraceCPU can consume?



Second question: is there documentation that describes the TraceCPU trace 
format? Perhaps I can write such a tool that’s (decently) accurate.



Thanks in advance for any advice!



Jonathan.

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[gem5-users] Re: Huge pages with ARM

[Giacomo Travaglini via gem5-users]

Hi,

Are you running FS or SE simulations? In FS it is configurable through the 
guest kernel, in SE mode we use 4K by default (see src/arch/arm/page_size.hh)
You might try to change the hardcoded value in the page_size.hh file though 
this has never been tested and it might not work without some adjustments

Giacomo

From: João Vieira via gem5-users 
Date: Tuesday, 22 March 2022 at 15:13
To: gem5-users@gem5.org 
Cc: Nuno Roma , Pedro Tomás , 
g...@deec.uc.pt , João Vieira 

Subject: [gem5-users] Huge pages with ARM
Hi,

I am trying to use Huge pages (as big as 1GB) in gem5, but there seems
to be little to none documentation about the subject.

Does anyone know how to change the page size?

I am using the ARM ISA, in case it matters.

Thanks in advance!

Kind regards

--

Joao Vieira
ECE PhD Student at Tecnico Lisboa | INESC-ID, Portugal
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[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

[Giacomo Travaglini via gem5-users]

That’s great!

FYI, overriding the getAddrRanges is not strictly needed if the BasicPioDevice 
is correctly initialised. That basically means initialising pioAddr and pioSize 
member variables:

https://github.com/gem5/gem5/blob/stable/src/dev/io_device.cc#L81

I am telling you this as while you fixed the mapping issue, an incorrect value 
for pioAddr and pioSize could potentially lead to other kinds of bugs in your 
device implementation 

Kind Regards

Giacomo

From: Klein Joshua Alexander Harrison 
Date: Monday, 21 March 2022 at 16:13
To: Giacomo Travaglini , gem5 users mailing list 

Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.

Hi Giacomo,



Thanks again for the suggestion.  I was able to solve the issue -- it turns out 
I forgot to implement getAddrRanges!



For the record (and in case someone in the future runs into the same issue), I 
had to add the following in cus_device.hh under the class definition:



AddrRangeList getAddrRanges() const override;





and then the following implementation in cus_device.cc:



AddrRangeList

CusDevice::getAddrRanges() const

{

AddrRangeList ranges;

ranges.push_back(RangeSize(0x1002, 0x1000));

return ranges;

}





Thank you again for your help!



Best regards,

Joshua Klein


From: Giacomo Travaglini 
Sent: Monday, March 21, 2022 4:27:06 PM
To: Klein Joshua Alexander Harrison; gem5 users mailing list
Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.

Yes apologies, I now realize your range was already covered in the existing 
_off_chip_ranges list
I’d recommend you to debug with gdb what is returned by the 
CusDevice::getAddrRanges method. It gets called by the xbar and it effectively 
registers the device pio range in the interconnect map.

Kind Regards

Giacomo


From: Klein Joshua Alexander Harrison 
Date: Monday, 21 March 2022 at 15:11
To: Giacomo Travaglini , gem5 users mailing list 

Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.
Hi Giacomo,

Thank you for the suggestion.  I added the address range to the 
_off_chip_devices list as suggested, and confirmed the address range is present 
in the config.ini:

[system.bridge]
type=Bridge
…
ranges=201326592:268566527 268566528:268570624 268570625:536870912  
788529152:2147483647
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[0]

Unfortunately however, I still run into the exact same issue.

Best regards,
Joshua Klein


From: Giacomo Travaglini 
Sent: Monday, March 21, 2022 3:24:02 PM
To: gem5 users mailing list
Cc: Klein Joshua Alexander Harrison
Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.

Hi Joshua.

You probably need to add the physical address range of your device to the 
_off_chip_ranges list [1]. This will be assigned to the membus->iobus bridge so 
that when the membus receives the cpu packet, it knows it must forward it to 
the io bridge

Let me know if this works

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/141cc37c2d4b93959d4c249b8f7e6a8b2ef75338/src/dev/arm/RealView.py#L1081

From: Klein Joshua Alexander Harrison via gem5-users 
Date: Monday, 21 March 2022 at 14:12
To: gem5-users@gem5.org 
Cc: Klein Joshua Alexander Harrison 
Subject: [gem5-users] “fatal: Unable to find destination for [0x1002 : 
0x1002] on system.iobus”, when adding new BasicPioDevice device.
Hi all,

I am trying to run an ARM full system simulation with a BasicPioDevice added 
onto the RealView Platform.  I am interested in interfacing it via ioremap.  
The device is set up like so in src/dev/arm/RealView.py (with the necessary C++ 
header/implementation files):

class CusDevice(BasicPioDevice):
type = ‘CusDevice’
cxx_header = "dev/arm/cus_device.hh”
pio_addr = Param.Addr(0x1002, "Address for custom device.”)


I then added it to the list of off-chip devices in RealView.py so it would be 
attached to the iobus, which is confirmed in the config.ini file:

[system.realview.cus_device]
type=CusDevice
…
pio_addr=268566528
pio_latency=10
power_model=
system=system
pio=system.iobus.master[9]


Then to access this device, I am using a kernel module that calls ioremap on 
the device’s address.  Ideally I want to read/write from /dev/cus_device to 
access it, but this is where I run into the fatal error:

root@aarch64-gem5:~/# echo h | /dev/cus_device
fatal: Unable to find destination for [0x1002 : 0x1002] on system.iobus


I have already confirmed that 0x1002 is within an IO memory region (more 
specifically, 0x1000-0x13ff are reserved for gem5-specific peripherals 
but only 0x1000-0x1001 are 

[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

[Giacomo Travaglini via gem5-users]

Yes apologies, I now realize your range was already covered in the existing 
_off_chip_ranges list
I’d recommend you to debug with gdb what is returned by the 
CusDevice::getAddrRanges method. It gets called by the xbar and it effectively 
registers the device pio range in the interconnect map.

Kind Regards

Giacomo


From: Klein Joshua Alexander Harrison 
Date: Monday, 21 March 2022 at 15:11
To: Giacomo Travaglini , gem5 users mailing list 

Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.
Hi Giacomo,

Thank you for the suggestion.  I added the address range to the 
_off_chip_devices list as suggested, and confirmed the address range is present 
in the config.ini:

[system.bridge]
type=Bridge
…
ranges=201326592:268566527 268566528:268570624 268570625:536870912  
788529152:2147483647
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[0]

Unfortunately however, I still run into the exact same issue.

Best regards,
Joshua Klein


From: Giacomo Travaglini 
Sent: Monday, March 21, 2022 3:24:02 PM
To: gem5 users mailing list
Cc: Klein Joshua Alexander Harrison
Subject: Re: “fatal: Unable to find destination for [0x1002 : 0x1002] 
on system.iobus”, when adding new BasicPioDevice device.

Hi Joshua.

You probably need to add the physical address range of your device to the 
_off_chip_ranges list [1]. This will be assigned to the membus->iobus bridge so 
that when the membus receives the cpu packet, it knows it must forward it to 
the io bridge

Let me know if this works

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/141cc37c2d4b93959d4c249b8f7e6a8b2ef75338/src/dev/arm/RealView.py#L1081

From: Klein Joshua Alexander Harrison via gem5-users 
Date: Monday, 21 March 2022 at 14:12
To: gem5-users@gem5.org 
Cc: Klein Joshua Alexander Harrison 
Subject: [gem5-users] “fatal: Unable to find destination for [0x1002 : 
0x1002] on system.iobus”, when adding new BasicPioDevice device.
Hi all,

I am trying to run an ARM full system simulation with a BasicPioDevice added 
onto the RealView Platform.  I am interested in interfacing it via ioremap.  
The device is set up like so in src/dev/arm/RealView.py (with the necessary C++ 
header/implementation files):

class CusDevice(BasicPioDevice):
type = ‘CusDevice’
cxx_header = "dev/arm/cus_device.hh”
pio_addr = Param.Addr(0x1002, "Address for custom device.”)


I then added it to the list of off-chip devices in RealView.py so it would be 
attached to the iobus, which is confirmed in the config.ini file:

[system.realview.cus_device]
type=CusDevice
…
pio_addr=268566528
pio_latency=10
power_model=
system=system
pio=system.iobus.master[9]


Then to access this device, I am using a kernel module that calls ioremap on 
the device’s address.  Ideally I want to read/write from /dev/cus_device to 
access it, but this is where I run into the fatal error:

root@aarch64-gem5:~/# echo h | /dev/cus_device
fatal: Unable to find destination for [0x1002 : 0x1002] on system.iobus


I have already confirmed that 0x1002 is within an IO memory region (more 
specifically, 0x1000-0x13ff are reserved for gem5-specific peripherals 
but only 0x1000-0x1001 are actually used before adding the custom 
device).  In case it is relevant, I am using the Linux 5.4.0 kernel with an 
Ubuntu 18.04 LTS image.

Accessing the custom device at address 0x1002 on the iobus is the precise 
goal, so given that writing to /dev/cus_device tries to write data to the 
correct address on the iobus, and I know cus_device.pio is attached to the 
iobus.master with the correct address, I am not sure why gem5 is unable to find 
the destination.  Any ideas on how to approach this issue would be greatly 
appreciated.

Best regards,
Joshua Klein

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[gem5-users] Re: “fatal: Unable to find destination for [0x10020000 : 0x10020000] on system.iobus”, when adding new BasicPioDevice device.

[Giacomo Travaglini via gem5-users]

Hi Joshua.

You probably need to add the physical address range of your device to the 
_off_chip_ranges list [1]. This will be assigned to the membus->iobus bridge so 
that when the membus receives the cpu packet, it knows it must forward it to 
the io bridge

Let me know if this works

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/141cc37c2d4b93959d4c249b8f7e6a8b2ef75338/src/dev/arm/RealView.py#L1081

From: Klein Joshua Alexander Harrison via gem5-users 
Date: Monday, 21 March 2022 at 14:12
To: gem5-users@gem5.org 
Cc: Klein Joshua Alexander Harrison 
Subject: [gem5-users] “fatal: Unable to find destination for [0x1002 : 
0x1002] on system.iobus”, when adding new BasicPioDevice device.
Hi all,

I am trying to run an ARM full system simulation with a BasicPioDevice added 
onto the RealView Platform.  I am interested in interfacing it via ioremap.  
The device is set up like so in src/dev/arm/RealView.py (with the necessary C++ 
header/implementation files):

class CusDevice(BasicPioDevice):
type = ‘CusDevice’
cxx_header = "dev/arm/cus_device.hh”
pio_addr = Param.Addr(0x1002, "Address for custom device.”)


I then added it to the list of off-chip devices in RealView.py so it would be 
attached to the iobus, which is confirmed in the config.ini file:

[system.realview.cus_device]
type=CusDevice
…
pio_addr=268566528
pio_latency=10
power_model=
system=system
pio=system.iobus.master[9]


Then to access this device, I am using a kernel module that calls ioremap on 
the device’s address.  Ideally I want to read/write from /dev/cus_device to 
access it, but this is where I run into the fatal error:

root@aarch64-gem5:~/# echo h | /dev/cus_device
fatal: Unable to find destination for [0x1002 : 0x1002] on system.iobus


I have already confirmed that 0x1002 is within an IO memory region (more 
specifically, 0x1000-0x13ff are reserved for gem5-specific peripherals 
but only 0x1000-0x1001 are actually used before adding the custom 
device).  In case it is relevant, I am using the Linux 5.4.0 kernel with an 
Ubuntu 18.04 LTS image.

Accessing the custom device at address 0x1002 on the iobus is the precise 
goal, so given that writing to /dev/cus_device tries to write data to the 
correct address on the iobus, and I know cus_device.pio is attached to the 
iobus.master with the correct address, I am not sure why gem5 is unable to find 
the destination.  Any ideas on how to approach this issue would be greatly 
appreciated.

Best regards,
Joshua Klein

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please notify the sender immediately and do not disclose the contents to any 
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[gem5-users] Re: Boot gets stuck sometimes ARM FS + KVM + 8 CPUs

[Giacomo Travaglini via gem5-users]

Hi Pedro,

The GIC is indeed the likely culprit as 8 PEs is the architectural limit of 
GICv2 (which is the interrupt controller used by VExpress_GEM5_V1, the default 
fs_bigLITTLE.py platform).

If using KVM I honestly don’t see an easy way around it: we have on upstream a 
device driver modification which allows to instantiate more than 8 CPUs with 
GICv2 [1]. It works if used in fully simulated CPU models; I suspect this won’t 
work with KVM though.

We have recently provided support for KVM simulations with GICv3 [2]. This has 
been merged on develop and it will be part of the next gem5 release. This will 
allow FS simulations with more than 8 KVM CPUs. So either you base your work on 
develop, or you try to backport those patches to 21.1.0.2

Kind Regards

Giacomo

[1]: 
https://gem5.googlesource.com/arm/linux/+/a2e8bda41866718ade4856d31f6c87e7234a3add
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/55615

From: Pedro Becker via gem5-users 
Date: Wednesday, 16 March 2022 at 15:35
To: gem5-users@gem5.org 
Cc: Pedro Becker 
Subject: [gem5-users] Boot gets stuck sometimes ARM FS + KVM + 8 CPUs
Hi all

I'm trying to boot arm FS with KVM in an ARM machine (an Nvidia Jetson) with 
multiple cores.
I had it working last year, on gem5 version 21.1.0.0. Later I had to update 
gem5 to version 21.1.0.2 because of some
errors in the stats generation of version 21.1.0.0.

So I had a lot of problems in the way, which were discussed here 
(https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/VCI74JOSRCQK3N64QRRGV3HLNVEYH4OC/#VCI74JOSRCQK3N64QRRGV3HLNVEYH4OC).
 But it was working.

Now I'm back on using that setup, but I'm getting a weird behavior using the 
fs_bigLITTLE.py script:

Basically, the boot is inconsistent with 8 CPUs. Sometimes it boots, sometimes 
it gets stuck at
[0.194001] smp: Bringing up secondary CPUs ...

I'm varying the numbers of  and  (such that 
+ <= 8) in the command below:

./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --kernel 
/scratch/pedro/aarch-my-system/binaries/vmlinux.arm64 --disk 
/scratch/pedro/ubuntu-18.04-arm64-8gb.img --cpu-type kvm --kvm-userspace-gic 
--mem-size 8GB --big-cpus  --little-cpus  --bootscript 
configs/boot/hello.rcS

Using 8 big CPUs generally cause it to get stuck, actually. Using 7 or fewer 
CPUs never made caused it to get stuck. Big little configurations seem to boot 
fine (e.g. 6 big + 2 little).
I wonder if it is because of using a simulated GIC to provide support to 8 CPUs.

Is that a known behavior?
Any workaround?

Thank you.
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[gem5-users] Re: M5 Fs utility workbegin

[Giacomo Travaglini via gem5-users]

Hi George,

Thanks for reporting this, I noticed the same issue. When we transitioned from 
the old m5 subsystem (assembly based) to the new C based one we forgot to 
provide an implementation for workbegin and workend I suppose. Putting Gabe on 
CC

Kind Regards

Giacomo

From: George Michelogiannakis via gem5-users 
Date: Wednesday, 9 March 2022 at 06:54
To: gem5-users@gem5.org 
Cc: George Michelogiannakis 
Subject: [gem5-users] M5 Fs utility workbegin
Hello Gem5 community,

I'm trying to use the M5 utility meant for full system mode to signal work 
begin and end. I see in the documentation that the utility supports these 
parameters:


  *   workbegin: Cause an exit evet of type, “workbegin”, that could be used to 
mark the begining of an ROI.
  *   workend: Cause an exit event of type, “workend”, that could be used to 
mark the termination of an ROI.
But when I run the utility in X86 after compiling it for X86 those two options 
aren't available as commands. There is a "fail" option with a parameter that 
isn't mentioned in the documentation. Is that the way to simulate workbegin and 
workend?

Thanks in advance,
  George M




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[gem5-users] Re: Doubt on the ARM exec trace results when compared with disassembly of the executable

[Giacomo Travaglini via gem5-users]

Hi Tom


  1.  I am not surprised, the gem5 disassembly has some flaws especially when 
it comes to aliases. The instruction is implemented correctly, it is just 
wrongly traced. We should fix these tiny bugs but as of now I just suggest you 
to not blindly rely on what is produced by the disassembler.
  2.  SVC itself does not update x0. The kernel routine handling the syscall 
will eventually produce a return value and it will store it in x0, so that it 
can be consumed by the SVC caller. This is part of the ABI, not of the ISA 
itself.

Kind Regards

Giacomo

From: tom jose via gem5-users 
Date: Monday, 14 February 2022 at 19:35
To: gem5-users@gem5.org 
Cc: tom jose 
Subject: [gem5-users] Doubt on the ARM exec trace results when compared with 
disassembly of the executable
Hi,
I tried running a simple hello world on ARM and went through the "exec" debug 
trace. I also used the disassembly of the executable to compare the sequence 
and register values. While doing so,i came across two doubts:
1. On the instruction "adds" being used instead of "cmn" but "xzr" not 
mentioned in the trace
2. Does svc instruction update x0 register? If so, how is the value stored in 
x0 determined? Can i know it from the disassembly of the executable or will i 
need to know about the code executed in the kernel as a result of svc syscall?

Details described below:

5896098: system.cpu_cluster.cpus: T0 : 0x421324 @_dl_discover_osversion+4:  
 add   x0, sp, #120   : IntAlu :  D=0x007efb58
...

6007986: system.cpu_cluster.cpus: T0 : 0x439b40 @__uname:   movz   x8, 
#160, #0  : IntAlu :  D=0x00a0
6007986: system.cpu_cluster.cpus: T0 : 0x439b44 @__uname+4:   svc   #0x0
   : IntAlu :
6064596: system.cpu_cluster.cpus: T0 : 0x439b48 @__uname+8:   adds   x0, 
#4095 : IntAlu :  D=0x
6064929: system.cpu_cluster.cpus: T0 : 0x439b4c @__uname+12:   b.cs   
<__uname+20>  : IntAlu :
6064929: system.cpu_cluster.cpus: T0 : 0x439b50 @__uname+16:   ret  
: IntAlu :
6065928: system.cpu_cluster.cpus: T0 : 0x421334 @_dl_discover_osversion+20: 
  add   x3, sp, #250   : IntAlu :  D=0x007efbda
6065928: system.cpu_cluster.cpus: T0 : 0x421338 @_dl_discover_osversion+24: 
  cbnz   w0, <_dl_discover_osversion+184> : IntAlu :
6066261: system.cpu_cluster.cpus: T0 : 0x42133c @_dl_discover_osversion+28: 
  movz   w6, #0, #0: IntAlu :  D=0x
6066594: system.cpu_cluster.cpus: T0 : 0x421340 @_dl_discover_osversion+32: 
  movz   w0, #0, #0: IntAlu :  D=0x

On doing the disassembly on the executable, we could see the following :
00439b40 <__uname>:
  439b40: d2801408 mov x8, #0xa0   // #160
  439b44: d401 svc #0x0
  439b48: b13ffc1f cmn x0, #0xfff
  439b4c: 5442 b.cs 439b54 <__uname+0x14>  // b.hs, b.nlast
  439b50: d65f03c0 ret

Doubt : in GEM5, " cmn x0, #0xfff "  is treated as adds instead of cmn. But 
from the ARM isa document, cmn is identical to "adds xzr, Xn, #imm". So is the 
GEM5 internally following this format with xzr? or does GEM5 update x0 here as 
the trace doesnt show xzr?

Disassembly on the executable:
00421320 <_dl_discover_osversion>:
  421320: d10803ff sub sp, sp, #0x200
  421324: 9101e3e0 add x0, sp, #0x78
  421328: a9007bfd stp x29, x30, [sp]
  42132c: 910003fd mov x29, sp
  421330: 94006204 bl 439b40 <__uname>
  421334: 9103ebe3 add x3, sp, #0xfa
  421338: 35000500 cbnz w0, 4213d8 <_dl_discover_osversion+0xb8>
  42133c: 5286 mov w6, #0x0   // #0
  421340: 5280 mov w0, #0x0   // #0

since the cbnz didnt take a branch, it means lower 32 bits of x0 (or w0 
register) is having a value 0.

So i tried looking through the ARM document on svc implementation: 
https://developer.arm.com/documentation/ddi0487/latest In page number 1957, 
description and operation for svc is described. There was no mention on x0 
being updated with the syscall return value. But i could see in few other 
websites:

https://cit.dixie.edu/cs/2810/arm64-assembly.html

https://azeria-labs.com/writing-arm-shellcode/

that [x0] or [register 0] is updated with the return value.



So could you please provide more insight on how the stored value on x0 is 
calculated? Any suggestions would be helpful.

Thanks in advance.
Regards,
Tom
[https://lh3.googleusercontent.com/a-/AOh14GgmWR1QY3N4mt8kWXuSPikx5kEFQpmcEgC_iA2Hkw=s40]



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[gem5-users] Re: Only one cpu was working in a multicore FS simulation in gem5 v21.1.0.2

[Giacomo Travaglini via gem5-users]

Hi,

It is possible you are not able to bring up secondary CPUs when booting Linux.
I would suggest you to have a look at the dmesg dump to check if there’s a 
problem.

Just in case, please update bootloaders by either recompiling them from source 
or by downloading them at

https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries

Kind Regards

Giacomo

From: Zhang Li via gem5-users 
Date: Friday, 17 December 2021 at 12:51
To: gem5-users@gem5.org 
Cc: Zhang Li 
Subject: [gem5-users] Only one cpu was working in a multicore FS simulation in 
gem5 v21.1.0.2
Dear,
Recently, I found a strange differences in statistics when I run exactly the 
same command in gem5 v20.1.0.0 and v21.1.0.2 respectively. In v20.1.0.0, all of 
the 8 cpus have committed instruction. However, in v21.1.0.2, all cpus except 
cpu0 have a statistics of 0 instruction committed, it seems that only cpu0 was 
working. Could I get some clues about this? Best regard!
[cid:image001.png@01D7F34B.134B55C0]
Here  is my command.
./build/ARM/gem5.opt -d fs_results/arm/8cores/test_multicores_Minor  
configs/example/fs.py \
--cpu-type=MinorCPU  --sys-clock=2.2GHz --cpu-clock=2.2GHz --num-cpus=8 \
--caches --l2cache --num-l2caches=2 \
--mem-type=HBM2_2000_4H_1x128 --mem-ranks=1 --mem-channels=8 --mem-size=4GB \
--l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l1d_assoc=2 --l1i_assoc=2 
--l2_assoc=16 --cacheline_size=64 \
--disk-image=$M5_PATH/full_system_images/disks/gem5_ubuntu16.img 
--kernel=$M5_PATH/full_system_images/binaries/vmlinux  \
-r 1 --restore-with-cpu=MinorCPU 
--param='system.realview.gic.gem5_extensions=True'

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[gem5-users] Re: Decisions when adding new instructions: accuracy and kvm support

[Giacomo Travaglini via gem5-users]

I suggest you have a look at how memory mapped m5ops are implemented:

https://github.com/gem5/gem5/blob/develop/src/arch/arm/mmu.cc#L185

If the memory reference lies within a specific address range (m5opRange) the 
memory access is replaced by the local accessor callback (recorded in the 
Request object with the setLocalAccessor method)

This callback is supported by every cpu model; it accepts the TC as a parameter 
and returns the number of Cycles needed to execute the pseudo op. This means 
the following


  1.  If you just care about setting up the overall execution time of your 
custom instruction, you can implement it by returning a different number of 
Cycles
  2.  If you want to model the instruction differently, you can reuse this 
mechanism to provide CPU type visibility to your guest application. You could 
ass a pseudo op which is getting the CPU ptr from the TC ptr, dynamic casting 
it to KVMCpu to check if we are in KVM mode and return 1 in KVM mode, 0 
otherwise

Another option could be to implement your instruction in the Arm HINT space and 
hope your host doesn’t complain when the instruction is executed in KVM mode 
and it treats it as a NOP instead

Kind regards

Giacomo


From: Pedro Becker via gem5-users 
Date: Friday, 26 November 2021 at 14:43
To: gem5-users@gem5.org 
Cc: Pedro Becker 
Subject: [gem5-users] Re: Decisions when adding new instructions: accuracy and 
kvm support
Hi Giacomo,

First of all, thanks for your time answering the question.
Your assumption about KVM is correct. I just use it to fast-forward, and I do 
not need to execute the instruction I want to implement in KVM mode.

Long story short: the same code for the ROI is executed during the 
fast-forwarding phase.

Do you know if it's possible to capture the CPU type that gem5 code is running, 
from the application?
This way I could manage to generate checkpoints with KVM using a functionally 
equivalent code that does not use my new instruction, and when I restore with a 
gem5 CPU, the new instruction is used.

Alternatively, perhaps, I can capture the "unimplemented instruction" from the 
application, and in that case, call a functionally equivalent code? I'm not 
sure if the CPU will let me continue the execution when the unimplemented 
instruction is found (with KVM), though. There should be some way to capture 
this kind of exception I guess...

If that is not a possible solution, then I'd have to run as many simulations as 
checkpoints I want (if I'm not mistaken one can go from KVM to gem5 CPU, but 
not go back to KVM), adapting the code to run up until the desired checkpoint 
time and changing some control variable so that my new instruction starts to be 
used. Although this is doable, it would be a little bit inconvenient as I take 
tens of checkpoints.

Any thoughts about these alternatives? I'll probably have to explore/try them 
anyway, but any hints on where to start are helpful.
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[gem5-users] Re: Decisions when adding new instructions: accuracy and kvm support

[Giacomo Travaglini via gem5-users]

Hi Pedro,

As you correctly stated, you could make an instruction work in KVM mode by 
implementing them as pseudo instruction and using the memory mapped 
implementation (m5 –addr).

If you run your instruction in KVM mode, the host won’t recognize the 
instruction and your guest VM will get an Undefined Instruction exception.

As from what I am understanding you are using KVM to simply fast-forward 
simulation, is there a specific need to run your instruction in KVM mode? Can’t 
you just fast-forward simulation until the ROI and then switch over a fully 
emulated cpu model (like O3) so that you can simulate the custom instruction in 
all its timing details?

Kind Regards

Giacomo

From: Pedro Becker via gem5-users 
Date: Friday, 26 November 2021 at 12:20
To: gem5-users@gem5.org 
Cc: Pedro Becker 
Subject: [gem5-users] Re: Decisions when adding new instructions: accuracy and 
kvm support
Just to partially answer my own question 2.

I just realized that M5 ops are pseudo instructions and they work with KVM 
("_addr" version), so I guess I could manage to do the same with my own 
instructions, if I was to implement them as pseudo-instructions.
I still don't know if there is a way to make them work with KVM if they are 
implemented as custom ISA extensions.
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[gem5-users] Re: Problem with checkpoint and restoration in gem5 se mode

[Giacomo Travaglini via gem5-users]

Hi Gelin,

Are you compiling gem5 in debug mode?
You can do that by using “debug” instead of “opt”:

$scons build/ARM/gem5.debug -j`nproc`

Kind Regards

Giacomo

From: Gelin Fu via gem5-users 
Date: Monday, 22 November 2021 at 12:26
To: gem5-users@gem5.org 
Cc: Gelin Fu <20153...@cqu.edu.cn>
Subject: [gem5-users] Re: Problem with checkpoint and restoration in gem5 se 
mode
Hi, Giacomo.Thanks for your reply.
I am not familiar with gdb in se mode. So I try to use debug functions such as 
curTick() and eventqDump(). But gdb tells me that there is no symbol about 
eventqDump() and curTick. So I only use backtrace when the program aborted.
I am using the command as below:
gdb --args $GEM5_BIN --outdir=$OUTPUT_PATH $GEM5_PATH/configs/example/se.py \
--num-cpu 1 --cpu-clock 2.5GHz --cpu-type O3_ARM_v7a_3 \
--restore-with-cpu O3_ARM_v7a_3 -r 1 --checkpoint-dir \
"$CHECK_PATH" --caches --mem-type DDR3_2133_8x8 --mem-size 1GB \
-c "$TARGET_PATH" --options "$DATA_PATH"
the gdb output are as below:
(gdb) r
Program received signal SIGABRT, Aborted.
__GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
51  ../sysdeps/unix/sysv/linux/raise.c: No such file or directory.
(gdb) bt
Program received signal SIGABRT, Aborted.
__GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
51  ../sysdeps/unix/sysv/linux/raise.c: No such file or directory.
(gdb) bt
#0  __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:51
#1  0x75ca7921 in __GI_abort () at abort.c:79
#2  0x75c9748a in __assert_fail_base (
fmt=0x75e1e750 "%s%s%s:%u: %s%sAssertion `%s' failed.\n%n",
assertion=assertion@entry=0x5868991a "when >= getCurTick()",
file=file@entry=0x58689902 "build/ARM/sim/eventq.hh",
line=line@entry=766,
function=function@entry=0x58689b20 
 "void gem5::EventQueue::schedule(gem5::Event*, 
gem5::Tick, bool)") at assert.c:92
#3  0x75c97502 in __GI___assert_fail (
assertion=0x5868991a "when >= getCurTick()",
file=0x58689902 "build/ARM/sim/eventq.hh", line=766,
function=0x58689b20  "void 
gem5::EventQueue::schedule(gem5::Event*, gem5::Tick, bool)") at assert.c:101
#4  0x55cc1dfe in gem5::EventQueue::schedule (this=0x5ad72ea0,
event=0x5ace0800, when=1010, global=false)
at build/ARM/sim/eventq.hh:766
#5  0x55dd3a94 in gem5::EventManager::schedule (this=0x5ace0708,
event=..., when=1010) at build/ARM/sim/eventq.hh:1021
#6  0x561fc1a9 in gem5::BaseCache::startup (this=0x5ace0700)
at build/ARM/mem/cache/base.cc:169

(gdb) p curTick
No symbol "curTick" in current context.
(gdb) p curTick()
No symbol "curTick" in current context.

Kind regards
Gelin
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[gem5-users] Re: Problem with checkpoint and restoration in gem5 se mode

[Giacomo Travaglini via gem5-users]

Hi Gelin, thanks for reporting this.
Would you mind running it with gdb and let us know which is the event failing 
the assertion?

(gem5.opt: build/ARM/sim/eventq.hh:766: void 
gem5::EventQueue::schedule(gem5::Event*, gem5::Tick, bool): Assertion `when >= 
getCurTick()' failed)

Kind regards

Giacomo


From: Gelin Fu via gem5-users 
Date: Wednesday, 17 November 2021 at 02:37
To: gem5-users@gem5.org 
Cc: Gelin Fu <20153...@cqu.edu.cn>
Subject: [gem5-users] Problem with checkpoint and restoration in gem5 se mode
Hello all,
  I want to use checkpoints to accelerate my simulation. The problem is that 
when I restore from the checkpoint, the gem5 simulation aborted.
  The mode I am using is se mode. I am using m5 pseudo instruction 
m5_checkpoint(0,0) in my application program to create checkpoints.
  I change the CPU model when restoring checkpoints and find out when the 
system doesn't have cache, the restoration is successful.

The error outputs are as below:
0: system.remote_gdb: listening for remote gdb on port 7005
build/ARM/sim/process.cc:389: warn: Checkpoints for pipes, device drivers and 
sockets do not work.
Switch at curTick count:1
gem5.opt: build/ARM/sim/eventq.hh:766: void 
gem5::EventQueue::schedule(gem5::Event*, gem5::Tick, bool): Assertion `when >= 
getCurTick()' failed.
Program aborted at tick 16277372800

   The command line to create checkpoint is:
$GEM5_BIN --outdir=$OUTPUT_PATH $GEM5_PATH/configs/example/se.py \
--num-cpu 1 --cpu-clock 2.5GHz --cpu-type AtomicSimpleCPU \
--mem-type DDR3_2133_8x8 --mem-size 1GB \
-c "$TARGET_PATH" --options "$DATA_PATH" --output  "$OUTPUT_PATH/output.txt"

The command line to restore checkpoint is:
$GEM5_BIN --outdir=$OUTPUT_PATH $GEM5_PATH/configs/example/se.py \
--num-cpu 1 --cpu-clock 2.5GHz --cpu-type O3_ARM_v7a_3 \
--caches --l2cache --l1i_size 64kB --l1d_size 32kB --l2_size 256kB --l1i_assoc 
8 --l1d_assoc 8 --l2_assoc 16 --cacheline_size 128 \
--l2-hwp-type StridePrefetcher --mem-type DDR3_2133_8x8 --mem-size 1GB \
-r 1 --checkpoint-dir "$CHECK_PATH" \
-c "$TARGET_PATH" --options "$DATA_PATH" --output $OUTPUT_PATH/output.txt" \

The version of gem5 I am using is 21.1.0.2.

Best Regards, Gelin
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[gem5-users] Re: Fatal when using ARM config file with walk cache

[Giacomo Travaglini via gem5-users]

Hi Nathanael, this is a know problem in develop that will be fixed in next 
release.

It comes from the fact that we are using 4 table walkers (for S1I-TLB, S1D-TLB, 
S2I-TLB and S2D-TLB).
I am currently working on:

a) Implementing a VA indexed walk cache replacing current PWCs (.gem5 
_walker_cache)
b) Merging table walkers into a single ported object

Kind Regards

Giacomo

> -Original Message-
> From: Nathanael Premillieu via gem5-users 
> Sent: 19 October 2021 12:44
> To: gem5 users mailing list 
> Cc: Nathanael Premillieu 
> Subject: [gem5-users] Fatal when using ARM config file with walk cache
>
> Hello,
>
>
>
> When using configuration files that define a walk cache
> (configs/common/cores/arm/O3_ARM_v7a.py and
> configs/common/cores/arm/HPI.py for example), I get the following error:
>
>
>
> fatal: Port .cpu.itb_walker_cache.cpu_side is already
> connected to .cpu.mmu.itb_walker.port, cannot connect
> .cpu.mmu.stage2_itb_walker.port
>
>
>
> The command line I use:
>
>
>
> $ ./build/ARM/gem5.opt configs/example/se.py --cpu-type O3_ARM_v7a_3
> -c tests/test-progs/hello/bin/arm/linux/hello --caches --l2cache
>
>
>
> It seems this problem is due to the connectWalkerPorts function defined in
> src/arch/arm/ArmMMU.py, in particular the following two lines (l.100-l.101):
>
>
>
> self.stage2_itb_walker.port = iport
>
> self.stage2_dtb_walker.port = dport
>
>
>
> Commenting them out seems to solve the problem, but I'm pretty sure this
> is not the correct way of solving it, but I'm not familiar enough with this 
> code
> to find a better one.
>
>
>
> Anyone has a better solution?
>
>
>
> Thanks,
>
> Nathanael Premillieu

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[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

[Giacomo Travaglini via gem5-users]

> -Original Message-
> From: Ali Ghandour via gem5-users 
> Sent: 12 October 2021 08:50
> To: gem5-users@gem5.org
> Cc: Ali Ghandour 
> Subject: [gem5-users] Re: Porting a configuration file from gem5 v20 to gem5
> v21
>
> Hi Giacomo,
>
> Indeed, I was able to use ArmMMU.connectWalkerPorts method and run
> the config file in fs mode.

Great!

> However, I a, still struggling with the segmentation fault in se mode.
>
> Does it make any sense to have a config file working in fs mode but failing in
> se? (notice that it is running in both fs and se mode in v20.0.0.)
>

It does as I believe the two issues (in SE and FS) are not related to each 
other. You are probably hitting another bug in SE mode.
If you are getting a segmentation fault you are probably trying to dereference 
an invalid pointer (nullptr?). With GDB, could you navigate the stack frames
until you find the invalid pointer? (just print the pointer you are trying to 
dereference)

> Ali
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Kind Regards

Giacomo
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[gem5-users] Re: Porting a configuration file from gem5 v20 to gem5 v21

[Giacomo Travaglini via gem5-users]

Hi Ali,

> -Original Message-
> From: Ali Ghandour via gem5-users 
> Sent: 05 October 2021 15:44
> To: gem5-users@gem5.org
> Cc: Ali Ghandour 
> Subject: [gem5-users] Re: Porting a configuration file from gem5 v20 to gem5
> v21
>
> In FS mode, full errror stack below:
>
> Traceback (most recent call last):
>   File "", line 1, in 
>   File "build/ARM/python/m5/main.py", line 455, in main
>   File "./RPIv4.py", line 535, in 
> main()
>   File "./RPIv4.py", line 512, in main
> root.system = systemCreate(args)
>   File "./RPIv4.py", line 297, in systemCreate
> system = RPISystemCreate(ArmSystem, args, mode)
>   File "./RPIv4.py", line 182, in RPISystemCreate
> return RPISystem(args, mode)
>   File "./RPIv4.py", line 127, in __init__
> self.configMem(args)
>   File "./RPIv4.py", line 158, in configMem
> self.cpu_cluster.connectDirect(self.membus)
>   File "/home/ali/Desktop/spirals/reproduce-spectre-
> gem5/gem5/./ARMv8A_Cortex_A72.py", line 325, in connectDirect
> cpu.dtb.walker.port = bus.slave
>   File "build/ARM/python/m5/SimObject.py", line 1416, in __getattr__

>From v21.0 the BaseCPU is interfacing to the MMU rather than the TLBs [1]:
So you should amend your configuration file accordingly. I suggest you to have 
a look at the
ArmMMU.connectWalkerPorts anyway [2]

> AttributeError: object 'ARM_A72_TLB_L1D' has no attribute 'walker'
>   (C++ object is not yet constructed, so wrapped C++ methods are
> unavailable.) ___
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Kind Regards

Giacomo


[1]: https://github.com/gem5/gem5/blob/v21.0.0.0/src/cpu/BaseCPU.py#L154
[2]: https://github.com/gem5/gem5/blob/v21.0.0.0/src/arch/arm/ArmMMU.py#L52
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[gem5-users] Re: --machine-type=VExpress_EMM causing ports collision

[Giacomo Travaglini via gem5-users]

Hi  Carlos,

> -Original Message-
> From: Carlos Andres Lara Niño via gem5-users 
> Sent: 05 October 2021 17:06
> To: gem5-users@gem5.org
> Cc: Carlos Andres Lara Niño 
> Subject: [gem5-users] --machine-type=VExpress_EMM causing ports
> collision
>
> Hello,
> I'm trying to learn gem5 and have been following the guide to the point
> where I can specify different characteristics of the system using the fs.py 
> file.

Out of curiosity, which guide are you currently following ?

>
> However, when I try the configuration
>
> build/ARM/gem5.opt \
> configs/example/fs.py \
> --cpu-type=TimingSimpleCPU \
> --num-cpus=2 \
> --caches \
> --l2cache \
> --machine-type=VExpress_EMM \
> --bootloader="$IMG_ROOT/binaries/boot_emm.arm64" \ --
> kernel="$IMG_ROOT/binaries/vmlinux.arm64" \ --disk-
> image="$IMG_ROOT/img/ubuntu-18.04-arm64-docker.img" \
> --cpu-clock=\['1 GHz','700 MHz','500 MHz'\]
>
> It produces the following error:
> build/ARM/mem/xbar.cc:431: fatal: system.iobus has two ports responding
> within range [0:0x4]:
> system.realview.cf_ctrl.pio
> system.realview.cf_ctrl.pio
>
> I've tinkered with the options a bit and reached the conclusion that setting 
> "-
> -machine-type=VExpress_EMM" invariably causes this issue.
>
> I haven't modified my gem5 distribution and the $IMG_ROOT path is as
> specified in the tutorial. What could be the problem?
>
> Best,
>

I really recommend you to use a more modern platform, like VExpress_GEM5_V1 or 
VExpress_GEM5_Foundation as VExpress_EMM is under deprecation

Kind Regards

Giacomo
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[gem5-users] Re: Support for CAS (compare and swap) instruction in ARM arch

[Giacomo Travaglini via gem5-users]

Thanks Mahita for spotting a real bug. I have posted a fix [1]; hopefully it 
will be backported to gem5 v21.1

Kind regards

Giacomo

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/51407

> -Original Message-
> From: Mahita Nagabhiru 
> Sent: 01 October 2021 20:07
> To: Giacomo Travaglini 
> Cc: gem5 users mailing list 
> Subject: Re: [gem5-users] Support for CAS (compare and swap) instruction in
> ARM arch
>
> Hi Giacomo,
>
> Looks like the regStats() function in HTMSequencer was interfering with
> ClockedObject::regStats() in AbstractController.cc; not fully sure what both
> regStats do but I commented regStats() out from HTMSequencer and the
> HTM part seems to be working now. I need to look into extending CAS to
> work with ruby next- so I will reach out again when I get stuck.
>
> On Thu, Sep 30, 2021 at 5:07 PM Giacomo Travaglini
> mailto:giacomo.travagl...@arm.com> >
> wrote:
>
>
>   Hi Mahita,
>
>   Could you debug it with gdb and let us know which stat gets
> initialized twice?
>
>   Kind Regards
>
>   Giacomo
>
>   > -Original Message-
>   > From: Mahita Nagabhiru   >
>   > Sent: 29 September 2021 12:00
>   > To: Giacomo Travaglini   >
>   > Cc: gem5 users mailing list mailto:gem5-
> us...@gem5.org> >
>   > Subject: Re: [gem5-users] Support for CAS (compare and swap)
> instruction in
>   > ARM arch
>   >
>   > Thanks a lot Giacomo.
>   > By default (without ruby), I am able to run my microbenchmark
> now; but I
>   > am trying to use the ruby side for memory modelling- I need to
> model CAS
>   > using that and also be able to use ARM HTM feature but when I run
> using "--
>   > ruby", I get the following panic message:
>   > "build/ARM_MESI_Three_Level_HTM/base/statistics.hh:953: fatal:
> fatal
>   > condition check() occurred: Stat has already been initialized"
>   > I have attached a log-file is that helps.
>   > I tried inspecting the usual files like
>   > src/mem/ruby/structures/CacheMemory.* , Sequencer,
> HtmSequencer etc
>   > but I cannot find the cause.
>   > I was able to use the HTM feature on the 20.1 stable version of
> gem5; so I am
>   > trying to do a diff between the latest files and the working version
> and I saw
>   > most changes were to accommodate the statistics base class
> correctly.
>   > I am not very well versed with gem5, so I'm really struggling to
> figure out the
>   > cause. Any suggestions?
>   >
>   > On Tue, Sep 28, 2021 at 3:50 PM Giacomo Travaglini
>   >  
>   > >
>   > wrote:
>   >
>   >
>   >   Hi Mahita,
>   >
>   >   Yes Armv8.1-LSE is implemented and therefore you should be
> able to
>   > use CAS
>   >
>   >   ISA definition of CAS:
>   >
> https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.i
>   > sa#L226
>   >   System level switch for LSE:
>   >
> https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L
>   > 75
>   >
>   >   As you can see we support it by default so you should be able to
> use
>   > it with no modification needed
>   >
>   >   Kind Regards
>   >
>   >   Giacomo
>   >
>   >   > -Original Message-
>   >   > From: Mahita Nagabhiru via gem5-users  us...@gem5.org 
>   >  > >
>   >   > Sent: 28 September 2021 15:42
>   >   > To: gem5-users@gem5.org 
>  >
>   >   > Cc: Mahita Nagabhiru  
>   >  > >
>   >   > Subject: [gem5-users] Support for CAS (compare and swap)
>   > instruction in
>   >   > ARM arch
>   >   >
>   >   > Hi,
>   >   >
>   >   > I am trying to experiment with lock-free data structures and
> one of
>   > the key
>   >   > instructions in my microbenchmarks is CAS (compare and swap)
>   > instruction. I
>   >   > need this in ARM architecture; I saw that gem5 page says LSE
>   > extensions are
>   >   > supported but I cannot find anything relevant in the "src/"
> directory
>   > on a
>   >   > quick grep except for a line in a config life:
>   > src/arch/arm/ArmSystem.py. Am I
>   >   > missing something here? Is there a guideline as to how to add
>   > support for an
>   >   > instruction for aarch64 in case it is not present?
>   >   > Any help would be highly appreciated!
>   >   >
>   >   >
>   >   > --
>   > 

[gem5-users] Re: Support for CAS (compare and swap) instruction in ARM arch

[Giacomo Travaglini via gem5-users]

Hi Mahita,

Could you debug it with gdb and let us know which stat gets initialized twice?

Kind Regards

Giacomo

> -Original Message-
> From: Mahita Nagabhiru 
> Sent: 29 September 2021 12:00
> To: Giacomo Travaglini 
> Cc: gem5 users mailing list 
> Subject: Re: [gem5-users] Support for CAS (compare and swap) instruction in
> ARM arch
>
> Thanks a lot Giacomo.
> By default (without ruby), I am able to run my microbenchmark now; but I
> am trying to use the ruby side for memory modelling- I need to model CAS
> using that and also be able to use ARM HTM feature but when I run using "--
> ruby", I get the following panic message:
> "build/ARM_MESI_Three_Level_HTM/base/statistics.hh:953: fatal: fatal
> condition check() occurred: Stat has already been initialized"
> I have attached a log-file is that helps.
> I tried inspecting the usual files like
> src/mem/ruby/structures/CacheMemory.* , Sequencer, HtmSequencer etc
> but I cannot find the cause.
> I was able to use the HTM feature on the 20.1 stable version of gem5; so I am
> trying to do a diff between the latest files and the working version and I saw
> most changes were to accommodate the statistics base class correctly.
> I am not very well versed with gem5, so I'm really struggling to figure out 
> the
> cause. Any suggestions?
>
> On Tue, Sep 28, 2021 at 3:50 PM Giacomo Travaglini
> mailto:giacomo.travagl...@arm.com> >
> wrote:
>
>
>   Hi Mahita,
>
>   Yes Armv8.1-LSE is implemented and therefore you should be able to
> use CAS
>
>   ISA definition of CAS:
> https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.i
> sa#L226
>   System level switch for LSE:
> https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L
> 75
>
>   As you can see we support it by default so you should be able to use
> it with no modification needed
>
>   Kind Regards
>
>   Giacomo
>
>   > -Original Message-
>   > From: Mahita Nagabhiru via gem5-users   >
>   > Sent: 28 September 2021 15:42
>   > To: gem5-users@gem5.org 
>   > Cc: Mahita Nagabhiru   >
>   > Subject: [gem5-users] Support for CAS (compare and swap)
> instruction in
>   > ARM arch
>   >
>   > Hi,
>   >
>   > I am trying to experiment with lock-free data structures and one of
> the key
>   > instructions in my microbenchmarks is CAS (compare and swap)
> instruction. I
>   > need this in ARM architecture; I saw that gem5 page says LSE
> extensions are
>   > supported but I cannot find anything relevant in the "src/" directory
> on a
>   > quick grep except for a line in a config life:
> src/arch/arm/ArmSystem.py. Am I
>   > missing something here? Is there a guideline as to how to add
> support for an
>   > instruction for aarch64 in case it is not present?
>   > Any help would be highly appreciated!
>   >
>   >
>   > --
>   >
>   > Mahita Nagabhiru
>   IMPORTANT NOTICE: The contents of this email and any attachments
> are confidential and may also be privileged. If you are not the intended
> recipient, please notify the sender immediately and do not disclose the
> contents to any other person, use it for any purpose, or store or copy the
> information in any medium. Thank you.
>
>
>
>
> --
>
> Mahita Nagabhiru
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[gem5-users] Re: Support for CAS (compare and swap) instruction in ARM arch

[Giacomo Travaglini via gem5-users]

Hi Mahita,

Yes Armv8.1-LSE is implemented and therefore you should be able to use CAS

ISA definition of CAS: 
https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/insts/amo64.isa#L226
System level switch for LSE: 
https://github.com/gem5/gem5/blob/stable/src/arch/arm/ArmSystem.py#L75

As you can see we support it by default so you should be able to use it with no 
modification needed

Kind Regards

Giacomo

> -Original Message-
> From: Mahita Nagabhiru via gem5-users 
> Sent: 28 September 2021 15:42
> To: gem5-users@gem5.org
> Cc: Mahita Nagabhiru 
> Subject: [gem5-users] Support for CAS (compare and swap) instruction in
> ARM arch
>
> Hi,
>
> I am trying to experiment with lock-free data structures and one of the key
> instructions in my microbenchmarks is CAS (compare and swap) instruction. I
> need this in ARM architecture; I saw that gem5 page says LSE extensions are
> supported but I cannot find anything relevant in the "src/" directory on a
> quick grep except for a line in a config life: src/arch/arm/ArmSystem.py. Am I
> missing something here? Is there a guideline as to how to add support for an
> instruction for aarch64 in case it is not present?
> Any help would be highly appreciated!
>
>
> --
>
> Mahita Nagabhiru
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[gem5-users] Re: syscall perf_event_open (#241) unimplemented

[Giacomo Travaglini via gem5-users]

Hi

It can be implemented in SE mode, but that would require us to 
implement/emulate perf_events in gem5

Is there a specific reason why you need to use perf_events in SE mode? Have you 
considered gathering statistics
Through the gem5 ops?

Kind Regards

Giacomo

> -Original Message-
> From: walt...@yahoo.com 
> Sent: 23 September 2021 16:45
> To: gem5 users mailing list 
> Cc: Giacomo Travaglini 
> Subject: Re: [gem5-users] Re: syscall perf_event_open (#241)
> unimplemented
>
> Hi Giacomo,
>
>
> Thanks for your reply.
>
> Is there any reason for implementing it in full system simulation only?
>
> Can we implement it in SE mode?
>
> Best regards.
>
> On Thursday, September 23, 2021, 11:04:42 AM GMT+3, Giacomo Travaglini
> via gem5-users  wrote:
>
>
> Hi
>
> It has been fixed for full-system simulation (the patch you are referring to 
> is
> providing visibility of the PMU to the linux kernel), But the syscall in SE 
> mode
> is still un-implemented.
>
> Kind Regards
>
> Giacomo
>
>
>
> > -Original Message-
> > From: walt_90--- via gem5-users  > <mailto:gem5-users@gem5.org> >
> > Sent: 22 September 2021 20:06
> > To: Gem5 Users Mailing List  > <mailto:gem5-users@gem5.org> >
> > Cc: walt...@yahoo.com <mailto:walt...@yahoo.com>
> > Subject: [gem5-users] syscall perf_event_open (#241) unimplemented
> >
> > I got the following error while trying to run a binary with se.py
> >
> > build/ARM/sim/syscall_emul.cc:66: fatal: syscall perf_event_open
> > (#241) unimplemented.
> > Memory Usage: 703864 KBytes
> >
> > I am using the latest version of gem5 on Ubuntu 18.04.
> >
> >
> >
> > I read the related threads titled:
> >
> >
> > [gem5-users] Using perf_event with the ARM PMU inside gem5 on Linux
> >
> > gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement
> ArmPMU DTB
> > generation
> >
> >
> > According to my understanding to these threads, this problem have been
> > fixed, am I correct?
> >
> > Thanks.
>
> IMPORTANT NOTICE: The contents of this email and any attachments are
> confidential and may also be privileged. If you are not the intended 
> recipient,
> please notify the sender immediately and do not disclose the contents to any
> other person, use it for any purpose, or store or copy the information in any
> medium. Thank you.
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[gem5-users] Re: syscall perf_event_open (#241) unimplemented

[Giacomo Travaglini via gem5-users]

Hi

It has been fixed for full-system simulation (the patch you are referring to is 
providing visibility of the PMU to the linux kernel),
But the syscall in SE mode is still un-implemented.

Kind Regards

Giacomo


> -Original Message-
> From: walt_90--- via gem5-users 
> Sent: 22 September 2021 20:06
> To: Gem5 Users Mailing List 
> Cc: walt...@yahoo.com
> Subject: [gem5-users] syscall perf_event_open (#241) unimplemented
>
> I got the following error while trying to run a binary with se.py
>
> build/ARM/sim/syscall_emul.cc:66: fatal: syscall perf_event_open (#241)
> unimplemented.
> Memory Usage: 703864 KBytes
>
> I am using the latest version of gem5 on Ubuntu 18.04.
>
>
>
> I read the related threads titled:
>
>
> [gem5-users] Using perf_event with the ARM PMU inside gem5 on Linux
>
> gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement ArmPMU
> DTB generation
>
>
> According to my understanding to these threads, this problem have been
> fixed, am I correct?
>
> Thanks.
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[gem5-users] Re: Accelerator as PIO device writing back to main memory

[Giacomo Travaglini via gem5-users]

Hi Andreas,

Could you provide us more information about the platform you are using?
More specifically

1) Are you using any configs/example/arm based script?
2) Which bus is connected to the device DMA port?

You need a cache between the device and the coherent bus. This is why we 
usually instantiate a IO cache
between the iobus and the membus [1]

Kind Regards

Giacomo

[1]: 
https://github.com/gem5/gem5/blob/stable/configs/example/arm/devices.py#L392


> -Original Message-
> From: diavastos--- via gem5-users 
> Sent: 13 September 2021 13:42
> To: gem5-users@gem5.org
> Cc: diavas...@gmail.com
> Subject: [gem5-users] Accelerator as PIO device writing back to main
> memory
>
> Hi all,
>
> I implemented an accelerator as a PIO device in the latest version of gem5
> and I am having issues with accessing the main memory for write operations.
> Reading from main memory works correctly.
>
> I used as an example an old entry "gem5-accel" that implements a Daxpy
> accelerator (as far as I saw even more recent implementations use a similar
> way to access main memory). My implementations for data transfer are
> more or less the same as the example but writing back to main memory
> doesn't work and I get the following runtime error:
>
> gem5.opt: build/ARM/mem/snoop_filter.cc:224:
> std::pair, Cycles>
> SnoopFilter::lookupSnoop(const Packet*): Assertion `cpkt->isWriteback() ||
> cpkt->req->isUncacheable() || (cpkt->isInvalidate() == cpkt-
> >needsWritable()) || cpkt->req->isCacheMaintenance()' failed.
>
> If I manually change the Packet type (just to avoid this error) to
> MemCmd::WritebackDirty instead of the standard MemCmd::WriteReq, the
> simulation continues with no error but the data are not actually written back
> to main memory.
>
> Any ideas from anyone would be greatly appreciated! Or if there are other
> examples I can follow to do the implementation
>
> Many thanks,
> andreas
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[gem5-users] Re: Problem with SIMD instructions execution in se mode when ISA is ARM

[Giacomo Travaglini via gem5-users]

Hi Gelin,

I understand the confusion.

Even if there are no SIMD operations, you are issuing FP operations and those 
are using vector elements as
single and double precision scalar registers are elements of the SIMD vector 
registers

Kind Regards

Giacomo

> -Original Message-
> From: Gelin Fu via gem5-users 
> Sent: 01 September 2021 04:17
> To: gem5-users@gem5.org
> Cc: Gelin Fu <20153...@cqu.edu.cn>
> Subject: [gem5-users] Problem with SIMD instructions execution in se mode
> when ISA is ARM
>
> Hi, all. I am trying to run some experiments about sparse matrix 
> multiplication,
> and it is mainly about float multiplication and addition.
> To ensure the compiler doesn't vectorize the source code, I compile this
> source code with GCC flag " -march=armv8-a+nosimd+nosve " .this should
> indicate that my assembly code doesn't have any SIMD instructions. Besides,
> I objdump the elf file to ensure that there are no SIMD instructions.
> The questions are:
> I use rename flag to observe the rename stage situation. Hoever, most of
> rename stage stall is because rename map has 0 free entries. More
> specifically, the numFreeVecEntries is always zero, such as :
> 1539442000: system.cpu.rename: [tid:0] Free IQ: 29, Free ROB: 97, Free LQ:
> 26, Free SQ: 48, FreeRM 0(64 192 0 14 625)
> 1539442000: system.cpu.rename: [tid:0] 0 instructions not yet in ROB
> 1539442000: system.cpu.rename: calcFreeLQEntries: free lqEntries: 26,
> loadsInProgress: 0, loads dispatchedToLQ: 0
> 1539442000: system.cpu.rename: [tid:0] Stall: RenameMap has 0 free entries.
> 1539442000: system.cpu.rename: [tid:0] Blocking.
>   However, I did not use SIMD instruction, so I am confused why the vector
> entry in rename stage can be used. And it seems to be the bottleneck of
> rename stage efficiency.
> The command lines are:
> ../../../build/ARM/gem5.opt ../../../configs/example/se.py \
> --cpu-type=O3_ARM_v7a_3 --cpu-clock=1GHz \ --mem-type DDR3_1600_8x8
> --mem-size 16GB \ --num-cpu 1 \ -c
> "/home/fugelin/Work/Research/gem5/gem5_git/se_files/spmv/bin/spmv_c
> sr.elf" \ --caches --l2cache --l1i_size 64kB --l1d_size 64kB --l2_size 256kB 
> --
> l1i_assoc 4 --l1d_assoc 4 --l2_assoc 8 --cacheline_size 128 The output in 
> stats
> are:
> system.cpu.iq.FU_type_0::No_OpClass 1  0.03%  0.03% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::IntAlu  2036 52.38% 52.41% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::IntMult0  0.00% 52.41% # 
> Type of FU
> issued
> system.cpu.iq.FU_type_0::IntDiv 0  0.00% 52.41% # 
> Type of FU
> issued
> system.cpu.iq.FU_type_0::FloatAdd   0  0.00% 52.41% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::FloatCmp   0  0.00% 52.41% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::FloatCvt   0  0.00% 52.41% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::FloatMult  0  0.00% 52.41% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 376  9.67% 62.08% # 
> Type
> of FU issued
> system.cpu.iq.FU_type_0::FloatDiv   0  0.00% 62.08% # 
> Type of FU
> issued
> system.cpu.iq.FU_type_0::FloatMisc  0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::FloatSqrt  0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdAdd0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0  0.00% 62.08% # 
> Type
> of FU issued
> system.cpu.iq.FU_type_0::SimdAlu0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdCmp0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdCvt0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdMisc   0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdMult   0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc0  0.00% 62.08% # 
> Type
> of FU issued
> system.cpu.iq.FU_type_0::SimdShift  0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc   0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdDiv0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdSqrt   0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd   0  0.00% 62.08% # 
> Type
> of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu   0  0.00% 62.08% # 
> Type of
> FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp   0  0.00% 

[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

This is great Pedro! Thanks for the pointers, other KVM users might find it 
useful.

Regarding the Linux Kernel question, there is no preferred version from our 
side.
You can even build a vanilla arm64 kernel and it should just work. IIRC we 
provided support until 5.8 in gem5 v21.0

Kind Regards

Giacomo

> -Original Message-
> From: Pedro Becker via gem5-users 
> Sent: 01 September 2021 11:24
> To: gem5-users@gem5.org
> Cc: Pedro Becker 
> Subject: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Hi all,
>
> First of all, thank you Giacomo for the support, I finally got KVM + arm +
> multiple cores working! Kernel 4.14 worked, btw.
>
> Just a list of things I had to do, in case someone else ends up in the same
> situation I did.
>
> For the MSR (immediate) undefined instruction, the solution goes as
> Giacomo pointed out: re-build the arm kernel and unselect the UAO from it.
> After cloning the gem5 arm kernel repo and `make gem5_defconfig` one can
> make menuconfig -> kernel features -> ARM v8.2 architectural features ->
> unselect the UAO option. build the kernel and use it.
>
> After I still got the following problem when restoring from a kvm taken
> checkpoint:
>
> [5.681321] INFO: rcu_preempt self-detected stall on CPU
> [5.681326]0-...: (1 ticks this GP) idle=646/141/0
> softirq=330/330 fqs=0
> [5.681330] (t=549009 jiffies g=-144 c=-145 q=14)
> [5.681336] rcu_preempt kthread starved for 549009 jiffies!
> g18446744073709551472 c18446744073709551471 f0x0 RCU_GP_WAIT_FQS(3)
> ->state=0x402 ->cpu=0
> [5.681342] rcu_preempt I0 8  2 0x0020
> ...
>
> But this problem vanished when I used the simulated gic (my host cpu is
> ARMv8, and does not have gic2 supported by gem5). For that, one can
> combine the `--cpu-type kvm` flag with the `--kvm-userspace-gic`
> (fs_bigLITTLE.py, gem5 version 21.1.0.0) when creating checkpoints.
>
> Regards,
> Pedro.
> ___
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[gem5-users] Re: SE ARM C stdio fseek() function invokes a failed writeBlob in port_proxy.hh

[Giacomo Travaglini via gem5-users]

Thanks Deric,

I wonder if it is linked to this problem:

https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-1074

What happens if you cross-compile for aarch64?

Kind Regards

Giacomo


> -Original Message-
> From: Deric Cheung via gem5-users 
> Sent: 16 August 2021 15:25
> To: gem5 users mailing list 
> Cc: Deric Cheung 
> Subject: [gem5-users] Re: SE ARM C stdio fseek() function invokes a failed
> writeBlob in port_proxy.hh
>
> Using --debug-flag=Exec I have also produced an execution trace of the
> binary:
> https://gist.github.com/Icohedron/1920d7b0130d8348d509038a10122c23
>
> On Sun, Aug 15, 2021 at 6:46 PM Deric Cheung   > wrote:
>
>
>   I'm trying to write and run some file IO code for ARM, but I
> encounter a fatal error when trying to run this simple C program:
>
>   test.c:
>   ```c
>   #include 
>
>   int main(int argc, char **argv)
>   {
>   FILE *input = fopen(argv[1], "rb");
>   if (input == NULL)
>   {
>   printf("Error reading file: %s\n", argv[1]);
>   return 1;
>   }
>   fseek(input, 0L, SEEK_END);
>   long int size = ftell(input);
>   fseek(input, 0L, SEEK_SET);
>   return 0;
>   }
>   ```
>
>   Binary (test.arm) compiled using command: arm-linux-gnueabihf-gcc
> -static -o test.arm -std=gnu99 test.c
>
>   Run output:
>   ```
>
>   $ build/ARM/gem5.opt configs/example/se.py -c test.arm -o
> hashmark/500.txtbuild/ARM/base/statistics.hh:277: warn: One of the stats is
> a legacy stat. Legacy stat is a stat that does not belong to any 
> statistics::Group.
> Legacy stat is deprecated.
>   gem5 Simulator System.  http://gem5.org
>   gem5 is copyrighted software; use the --copyright option for details.
>
>   gem5 version 21.1.0.0
>   gem5 compiled Aug 11 2021 16:16:59
>   gem5 started Aug 15 2021 18:33:07
>   gem5 executing on Shiva, pid 6082
>   command line: build/ARM/gem5.opt configs/example/se.py -c
> test.arm -o hashmark/500.txt
>
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   Global frequency set at 1 ticks per second
>   warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.
>   build/ARM/mem/mem_interface.cc:791: warn: DRAM device
> capacity (8192 Mbytes) does not match the address range assigned (512
> Mbytes)
>   0: system.remote_gdb: listening for remote gdb on port 7000
>    REAL SIMULATION 
>   build/ARM/sim/simulate.cc:107: info: Entering event queue @ 0.
> Starting simulation...
>   build/ARM/sim/mem_state.cc:443: info: Increasing stack size by one
> page.
>   build/ARM/sim/syscall_emul.cc:73: warn: ignoring syscall mprotect(...)
>   build/ARM/mem/port_proxy.hh:195: fatal: writeBlob(0x1cde, ...)
> failed
>   Memory Usage: 650296 KBytes
>   ```
>
>   I can confirm that the `fopen()` call completes successfully. The
> `fseek` and `ftell` functions incur the fatal failed writeBlob error.
>
>   A backtrace of the error is here:
> https://gist.github.com/Icohedron/8fb339fccf323c9813d79dd466ae4f66
>
>
>   Operating System: Debian 11
>   gcc-arm-linux-gnueabihf version: 4:10.2.1-1
>

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[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

Hi Pedro,

The MSR (immediate) is the software interface for modifying the PSTATE of the 
PE.
In this case the instruction is trying to change the PSTATE.UAO field, which is 
not implemented in gem5

This is why you are not able to restore the checkpoint in atomic. Implementing 
UAO should fix it.
I can try to allocate some time to do it myself.

Other options in the meantime could be to check if there is an UAO option in 
the kconfig and disable it

Kind Regards

Giacomo

> -Original Message-
> From: Pedro Becker via gem5-users 
> Sent: 30 August 2021 12:47
> To: gem5-users@gem5.org
> Cc: Pedro Becker 
> Subject: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Hi Giacomo,
>
> KVM indeed worked in x86, but my target application would eventually hang
> with O3CPU because gem5-X86 does not guarantee the atomicity of
> synchronization variables in multithreaded programs with the classic memory
> system (needed by KVM).
>
> So I'm once again considering gem5+ARM, because I know that at least my
> multi-threaded program would work properly in full-system. Hence, I'd like
> to try to fix this unimplemented instruction, as you mentioned. Could you
> provide me some help on how to do that?
>
> Let me tell you what I've been trying recently:
>
> First I should say that the ARM machine I have is in fact an NVIDIA Jetson
> AGX Xavier with 8-core ARM v8.2. The OS on the boards is an NVIDIA-specific
> Linux version (based on ubuntu 18) and I thought that, perhaps, their
> modifications could be causing KVM to trigger an instruction that is not found
> in a 'regular' Ubuntu host. So I had prepared a ubuntu docker container to
> run gem5+kvm on the board, and see if that would make any difference. But
> not really. I get a similar (yet smaller/cut-out) output from the terminal 
> when
> I try to restore from a KVM-taken checkpoint into the atomic CPU:
>
>
> ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --big-cpus 2 --
> little-cpus 0 --cpu-type atomic --disk /scratch/pedro/ubuntu-18.04-arm64-
> 8gb.img --kernel /scratch/pedro/aarch-system-
> 20210904/binaries/vmlinux.arm64 --bootscript configs/boot/my_script.rcS --
> restore-from m5out/cpt.8185197130500
>
> [5.841787] Internal error: undefined instruction: 0 [#1] PREEMPT SMP
> [5.841790] Modules linked in:
> [5.841795] CPU: 1 PID: 83 Comm: kworker/1:2 Not tainted 4.18.0+ #1
> [5.841798] Hardware name: V2P-CA15 (DT)
>
>
> So I proceed to use DFLAGS, as you suggested, to check what was the
> undefined instruction. For that I added the `--debug-flags=Faults` in the
> previous command. This returned me the following:
>
> .
> .
> .
> system.terminal: Listening for connections on port 3456
> system.realview.uart1.device: Listening for connections on port 3457
> system.realview.uart2.device: Listening for connections on port 3458
> system.realview.uart3.device: Listening for connections on port 3459
> 0: system.remote_gdb: listening for remote gdb on port 7000
> 0: system.remote_gdb: listening for remote gdb on port 7001
> build/ARM/dev/arm/energy_ctrl.cc:249: warn: Existing EnergyCtrl, but no
> enabled DVFSHandler found.
> build/ARM/sim/simulate.cc:104: info: Entering event queue @
> 8185197130500.  Starting simulation...
> 8185197140500: IRQ: Invoking Fault (AArch64 target EL):IRQ cpsr:0x404003c5
> PC:0xff8008179f28 elr:0xff8008179f28 newVec: 0xff8008081a80
> 8185197353000: IRQ: Invoking Fault (AArch64 target EL):IRQ cpsr:0x80c003c5
> PC:0xff800872e848 elr:0xff800872e848 newVec: 0xff8008081a80
> 8185210545000: Undefined Instruction: Invoking Fault (AArch64 target
> EL):Undefined Instruction cpsr:0x604003c5 PC:0xff80080863cc
> elr:0xff80080863cc newVec: 0xff8008081a00 inst: 0xd500417f
> 8185229553500: Undefined Instruction: Invoking Fault (AArch64 target
> EL):Undefined Instruction cpsr:0x604003c5 PC:0xff800816fbd4
> elr:0xff800816fbd4 newVec: 0xff8008081a00 inst: 0xd500417f
> 8185295569000: ArmSev Flush: Invoking ArmSev Fault
> 8185621086500: ArmSev Flush: Invoking ArmSev Fault
> 8185946604000: ArmSev Flush: Invoking ArmSev Fault
> 8186272121000: ArmSev Flush: Invoking ArmSev Fault
>
> (I killed gem5 at this point, this "ArmSev Flush" message was being repeated
> and the terminal output was already there).
>
> So I went to look directly at the instruction `inst: 0xd500417f` -> 1101 0101
>   0100 0001 0111  (which is the same in both lines reporting
> undefined instruction).
>
> After searching in the reference manual for armv8
> (https://developer.arm.com/documentation/ddi0487/gb/) I think it is the
> MSR (immediate) instruction (at C6.2.195 in the manual).
>
> And then I found different matches for 'msr' in the file
> src/arch/arm/isa/formats/aarch64.isa. However, I'm not very familiar with
> the instruction and possible implications of implementing it..
>
> Do you have any suggestions for me on where to start and if it is indeed
> doable? Any other relevant information 

[gem5-users] Re: atomic translation error in ARM FS Mode

[Giacomo Travaglini via gem5-users]

Hi Burak,

This is a python configuration problem. You need to make sure the table walker 
port is connected.
Please double check the ArmMMU.walkerPorts() method is called in the FS script

Kind Regards

Giacomo

> -Original Message-
> From: Burak Öçalan via gem5-users 
> Sent: 22 August 2021 14:06
> To: gem5-users@gem5.org
> Cc: Burak Öçalan 
> Subject: [gem5-users] atomic translation error in ARM FS Mode
>
> Hello. I am trying to atomically translate some virtual addresses in my
> prefetcher. The function I have defined for this purpose is:
>
> Addr BFS::translateAddr(Addr vaddr, PacketPtr ) {
> DPRINTF(BFS, "Entered translateAddr with vaddr: %#x\n", vaddr);
> RequestPtr req = std::make_shared(
> vaddr, blkSize, 0, requestorId, 0, pkt->req->contextId());
>
> Fault f = tlb->translateAtomic(req,
>cache->system->threads[req->contextId()],
>BaseTLB::Read);
>
> if ( f != NoFault )
> DPRINTF(BFS, "BFS Translation Failed.\n");
> else
> {
> DPRINTF(BFS, "BFS translation succeded with paddr: %#x\n", req-
> >getPaddr());
> }
> return req->getPaddr();
> }
>
> When executing this code in ARM SE mode,  everything works fine. But in FS
> mode, I get this error:
> fatal: system.cpu.mmu.dtb.walker.dma: Unconnected port!
>
> I am sharing the last portion of the debug output with TLB flag:
> 1343690404500: system.cpu.dcache.prefetcher: Entered translateAddr with
> vaddr: 0x532d00
> 1343690404500: system.cpu.mmu.dtb: translateFs addr 0x532d00, mode 0,
> st2 0, scr 0 sctlr 0x3475d91d flags 0 tranType 0x0
> 1343690404500: system.cpu.mmu.dtb: TLB Miss: Starting hardware table
> walker for 0x532d00(91:0)
> 1343690404500: system.cpu.mmu.dtb.walker: Beginning table walk for
> address 0x532d00, TCR: 0x32b5593519
> 1343690404500: system.cpu.mmu.dtb.walker:  - Selecting TTBR0 (AArch64)
>
> I am sure that my vaddr is a valid address.
>
> Can you please help me understanding the cause of the error? Thanks a lot.
> ___
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[gem5-users] Re: SE ARM: Assertion error in rename_map.hh on call to pthread_create using m5threads

[Giacomo Travaglini via gem5-users]

Hi Deric,

This is a known issue.
You can work around the problem in two different ways:

1) Cross-compile your program for aarch64
2) Hardcode the ISA.highestELIs64 to false as you are effectively 
cross-compiling for AArch32

Kind Regards

Giacomo

> -Original Message-
> From: Deric Cheung via gem5-users 
> Sent: 16 August 2021 15:19
> To: gem5 users mailing list 
> Cc: Deric Cheung 
> Subject: [gem5-users] Re: SE ARM: Assertion error in rename_map.hh on call
> to pthread_create using m5threads
>
> Here is the complete Exec trace as well, running it with --debug-flags=Exec:
> https://gist.github.com/Icohedron/4d1fef84b4266a5945cb707ab990bde4
>
> On Sun, Aug 15, 2021 at 10:48 PM Deric Cheung   > wrote:
>
>
>   I wrote a small program to test pthreads using the m5threads library
> on an ARM O3CPU using syscall emulation. However, when running the
> program, an assertion error is encountered which prevents it from executing.
>
>   Source code of the program (threads.c):
>   ```c
>   #include 
>   #include 
>
>   void *doWork(void *arg) {
>   printf("do work\n");
>   }
>
>   int main(int argc, char **argv) {
>   pthread_t thread;
>   int error = pthread_create(, NULL, doWork, NULL);
>   if (error == 0) {
>   pthread_join(thread, NULL);
>   } else {
>   printf("pthread_create error %d\n",error);
>   }
>   return 0;
>   }
>   ```
>
>
>   Makefile used to compile it
>   ```Makefile
>   CCLOC= /arm-gem5-linux-gnueabi/bin/
>   CC = $(CCLOC)arm-gem5-linux-gnueabi-gcc
>   CPP = $(CCLOC)arm-gem5-linux-gnueabi-g++
>   OPTS = -g -O3 -march=armv7-a -marm
>
>   all: threads.arm
>
>   threads.arm: threads.o pthread.o
>   $(CPP) $(OPTS) -static -o threads.arm threads.o pthread.o
>
>   clean:
>   -rm *.o *.arm
>
>   threads.o: threads.c
>   $(CC) $(OPTS) -std=gnu99 -c threads.c
>
>   pthread.o:
>   $(CC) $(OPTS) -c m5threads/pthread.c -o pthread.o
>   ```
>
>
>   Command and output:
>   ```
>   $build/ARM/gem5.opt configs/example/se.py --num-cpus 2 --cpu-
> type O3CPU --caches -c thread-test/threads.arm
> build/ARM/base/statistics.hh:277: warn: One of the stats is a legacy stat.
> Legacy stat is a stat that does not belong to any statistics::Group. Legacy 
> stat
> is deprecated.
>   gem5 Simulator System.  http://gem5.org
>   gem5 is copyrighted software; use the --copyright option for details.
>
>   gem5 version 21.1.0.0
>   gem5 compiled Aug 12 2021 21:55:38
>   gem5 started Aug 15 2021 22:39:29
>   gem5 executing on uc14, pid 2265762
>   command line: build/ARM/gem5.opt configs/example/se.py --num-
> cpus 2 --cpu-type O3CPU --caches -c thread-test/threads.arm
>
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   warn: membus.slave is deprecated. `slave` is now called
> `cpu_side_ports`
>   Global frequency set at 1 ticks per second
>   warn: No dot file generated. Please install pydot to generate the dot
> file and pdf.
>   build/ARM/mem/mem_interface.cc:791: warn: DRAM device
> capacity (8192 Mbytes) does not match the address range assigned (512
> Mbytes)
>   0: system.remote_gdb: listening for remote gdb on port 7000
>    REAL SIMULATION 
>   build/ARM/sim/simulate.cc:107: info: Entering event queue @ 0.
> Starting simulation...
>   build/ARM/arch/arm/regs/misc.cc:334: warn: CP14 unimplemented
> crn[14], opc1[7], crm[15], opc2[7]
>   build/ARM/sim/power_state.cc:105: warn: PowerState: Already in
> the requested power state, request ignored
>   build/ARM/arch/arm/isa.hh:658: warn: User mode does not have
> SPSR
>   build/ARM/arch/arm/isa.hh:658: warn: User mode does not have
> SPSR
>   gem5.opt: build/ARM/cpu/o3/rename_map.hh:280:
> gem5::PhysRegId* gem5::o3::UnifiedRenameMap::lookup(const
> gem5::RegId&) const: Assertion `vecMode == enums::Elem' failed.
>   Program aborted at tick 10204500
>   --- BEGIN LIBC BACKTRACE ---
>   build/ARM/gem5.opt(+0x55ef70)[0x55b186d5ef70]
>   build/ARM/gem5.opt(+0x59807e)[0x55b186d9807e]
>   /lib/x86_64-linux-gnu/libpthread.so.0(+0x153c0)[0x7fcba3b9a3c0]
>   /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xcb)[0x7fcba313d18b]
>   

[gem5-users] Re: VExpress_GEM5_V1, Ethernet, and BARs

[Giacomo Travaglini via gem5-users]

That is correct, you should just recompile the DTB; no need to recompile gem5

Kind Regards

Giacomo

> -Original Message-
> From: Md Rubel Ahmed via gem5-users 
> Sent: 31 July 2021 10:05
> To: gem5-users@gem5.org
> Cc: Md Rubel Ahmed 
> Subject: [gem5-users] VExpress_GEM5_V1, Ethernet, and BARs
>
> Hi,
> I was trying to get ethernet working on my FS simulation, but facing this
> problem as follows:
>
> fatal: system.iobus has two ports responding within range
> [0x8000:0x8002]:
> system.ethernet.pio
> system.iocache.cpu_side_port
>
>
> I changed the third word as discussed in the previous emails of this thread
> accordingly.
>
> old 70: <0x0200 0x0 0x0  0x0 0x4000  0x0 0x4000>; new 70:
> <0x0200 0x0 0x0  0x0 0x4000  0x0 0x0>;
>
>
>
>
> How I added the ethernet(in FSconfig.py):
> else:
> self.pci_ide = IdeController(disks=disks)
> pci_devices.append(self.pci_ide)
>
> # Added ethernet by rubel
>
> self.ethernet = IGbE_e1000()
> pci_devices.append(self.ethernet)
>
>
>
> The command I executed:
> ./build/ARM/gem5.opt --debug-flags=Drain,VGIC,Ethernet
> configs/example/fs.py --kernel=vmlinux --machine-
> type=VExpress_GEM5_V1 --dtb-
> file=/home/rubel/gem5/system/arm/dt/armv7_gem5_v1_1cpu.dtb --num-
> cpus=1 --cpu-type=TimingSimpleCPU --disk-image=gem5_ubuntu16.img --
> caches --l2cache --mem-size=4GB --l1i_size=16kB --l1d_size=64kB --
> l2_size=256kB
>
> I believe I don't need to REBUILD gem5 for these changes. I am using a very
> recent version of gem5(ea7d012c00e857ef999b88a8ec2bde801a1f).
>
> So my question is, did I interpreted the word thing correctly? Do I need to
> rebuild gem5 for these changes?
>
> Any help is highly appreciated.
>
>
> Regards,
> Rubel Ahmed
>

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[gem5-users] Re: Adding ArmTLB to prefetchers

[Giacomo Travaglini via gem5-users]

Hi,

> -Original Message-
> From: Burak Öçalan via gem5-users 
> Sent: 27 July 2021 17:05
> To: gem5-users@gem5.org
> Cc: Burak Öçalan 
> Subject: [gem5-users] Adding ArmTLB to prefetchers
>
> Hi.
>
> I'm working on Indirect Memory Prefetcher. This prefetcher requires a TLB to
> work correctly. As far as I understand, I need to add the TLB manually.
>
>
> In x86 simulations, I simply create a new X86TLB and give it to the prefetcher
> in Prefetcher.py file. In SE mode it works, this is enough for the prefetcher 
> to
> make functional translations. I didn't try FS mode but additional things must
> be done I guess.
>
>
> However, I can't do the same thing in ARM simulations. When I try to create a
> new ArmTLB and give it to the prefetcher, it gives this error:
>
> fatal: fatal condition !stage2Mmu occurred: Table walker must have a valid
> stage-2 MMU
>
> My question is; what is the correct way of adding TLB's to prefetchers for x86
> and ARM ISAs, which will work for both FS and SE simulations?
>
> Thanks a lot and have a great day.

You don't need to create a new TLB. You should rather link the prefetcher to 
the existing one (the mmu.dtb)
As I am assuming you are using the stable branch, this means doing something 
like

prefetcher = IndirectMemoryPrefetcher(...)
prefetcher.registerTLB(cpu.mmu.dtb)

Let me know if this works

Kind regards

Giacomo
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[gem5-users] Re: How to set data breakpoints/watchpoints in FS/SE modes

[Giacomo Travaglini via gem5-users]

Hi Preet

> -Original Message-
> From: Preet Derasari via gem5-users 
> Sent: 24 July 2021 17:05
> To: gem5-users@gem5.org
> Cc: Preet Derasari 
> Subject: [gem5-users] How to set data breakpoints/watchpoints in FS/SE
> modes
>
> Hi!
>
> I am trying to figure out ways in which I can use gem5's pre-existing
> SimObjects to set data watchpoints/breakpoints. If there exist no SimObjects
> to do that I can also create my own but for that, I need to understand the
> concept of data watchpoints.

We do support Self-Hosted watchpoints and breakpoints in Arm [1]
Self hosted means there is no external debugger controlling the PE: the debug 
code is executed by the PE itself.

>
> Can anyone help me with either of these? For example, if there is an address
> that the simulated CPU is requesting the data for via the MemReq SimObject,
> I want to throw an exception when this happens and execute another piece
> of code. (basically something like the ARM DS-5 debugger functionality). Any
> help is much appreciated.

You could reuse the existing Self Hosted debug implementation. To configure 
your breakpoints/watchpoints you might want to run your program under GDB

>
>
>
>
> Thank you. Regards,
>
> Preet.

Kind Regards

Giacomo

[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/self_debug.hh

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[gem5-users] Re: 4-core ARM with fs.py and fs_bigLITTLE.py

[Giacomo Travaglini via gem5-users]

Hi Majid,

Out of curiosity, are you sure the configuration is the same? Could you try to 
rebuild the bootloader in system/arm/bootloader/arm64 and make sure the config 
script is pointing to it?
(Either with M5_PATH or by using the --bootloader option)

Please let me know if this works

Kind Regards

Giacomo

> -Original Message-
> From: Majid Jalili via gem5-users 
> Sent: 21 July 2021 05:44
> To: gem5 users mailing list 
> Cc: Majid Jalili 
> Subject: [gem5-users] 4-core ARM with fs.py and fs_bigLITTLE.py
>
> Hi,
>
> I am using the following commands for the fs.py and fs_bigLITTLE.py:
>
> ./build/ARM/gem5.opt ./configs/example/fs.py --caches --mem-size=64GB -
> -kernel /home/cc/disks/binaries/vmlinux.arm64 --disk
> /home/cc/disks/disks/ubuntu-18.04-arm64-docker_big.img -n 4 --machine-
> type VExpress_GEM5_V1
>
>
>
> ./build/ARM/gem5.opt ./configs/example/arm/fs_bigLITTLE.py --caches --
> mem kernel /home/cc/disks/binaries/vmlinux.arm64 --disk
> /home/cc/disks/disks/ubuntu-18.04-a
> ig.img --machine-type VExpress_GEM5_V1 --big-cpus 4 --little-cpus 0
>
>
> When I run the lscpu command, I would see 1 CPU for fs.py and 4 CPUs for
> the  fs_bigLITTLE.py.
> I was trying to figure out why the first script can bring only one CPU up, and
> the other all 4 CPUs, but has no success.
> I made sure all four CPUs are created in the config files.
>
> Thanks!
> Majid
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[gem5-users] Re: PCI Express on gem5

[Giacomo Travaglini via gem5-users]

Hi Nikos,

The author submitted a partial implementation to gerrit (Simply modelling a 
PCIe Link) some time ago:

https://gem5-review.googlesource.com/c/public/gem5/+/13024

A Root Complex and PCI Express Switch implementation was supposed to be 
uploaded but this never happened as far as I know.
If you are really interested I suggest you to contact the author. It would be 
nice if we could upstream that contribution

Please keep us posted

Kind Regards

Giacomo


> -Original Message-
> From: Νικόλαος Ταμπουρατζής via gem5-users 
> Sent: 12 July 2021 16:17
> To: gem5-users 
> Cc: Νικόλαος Ταμπουρατζής 
> Subject: [gem5-users] PCI Express on gem5
>
>
> Dear gem5 community,
>
> I have successfully connected the two gem5s through Gigabit PCI e1000 card
> on ARM FS. However, I would like to use a faster card (more than
> gigabit) based on PCI-E instead of PCI. Is there any work on this? I found 
> this
> work: https://www.ideals.illinois.edu/handle/2142/101569
> but unfortunately I can not find the source code of this. I will appreciate 
> it if
> anyone may help me.
>
> Thank you in advance,
> Nikos
> ___
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[gem5-users] Re: SSH on ARM Full System

[Giacomo Travaglini via gem5-users]

Hi Nikolaos, this is great!

>
> I would like to connect one gem5 to another through ssh (because I
> would like to use MPI).
>
> I have installed the openssh-client packet through qemu but I get the
> above connection refused. After that, I installed the openssh-server
> through qemu, but it is not booted after 2 hours (it installed a
> number of packets):


Do you mean that you install the packages in the disk image via qemu and you 
later try to reboot with the augmented disk image in gem5?
If that is the case I wonder if you can try to do the same with gem5-KVM 
(requiring an aarch64 host). You then create a checkpoint after boot so that 
you don't need to bringup your "heavy" userspace in gem5

Kind Regards

Giacomo


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[gem5-users] Re: How to find the address range of an ARM IO device

[Giacomo Travaglini via gem5-users]

Hi,

> -Original Message-
> From: Md Rubel Ahmed via gem5-users 
> Sent: 05 July 2021 22:24
> To: gem5 users mailing list 
> Cc: Md Rubel Ahmed 
> Subject: [gem5-users] How to find the address range of an ARM IO device
>
> Greetings,
>
> I was trying to get the address range of each device in the arm device tree.
>
> In gem5/src/dev/arm/RealView.py , I find many off-chip device like uart
> below:
>
> uart = Pl011(pio_addr=0x1c09, interrupt=ArmSPI(num=37))
>
>
> I am interested to know the memory-mapped address (address range) of
> this device.

For the uart you mentioned, the base address is the pio_addr, and the range 
size is 0x1000 [1].
To understand in general the src/dev/ code, you could either grep for pioAddr 
and pioSize in C++, which is how the range is usually stored
in a device object, or you could have a look at the getAddrRanges virtual 
method, which is how a device notifies its memory map to an interconnect

Alternatively, I posted a contribution some time ago [2] which made gem5 draw 
the entire RealView memory map at runtime.
It hasn't been merged yet

> I found additional information below about the off-chip device address but
> facing hard times understanding the relation (if any) between them. Any
> pointer is highly appreciated.
>
> # Ranges based on excluding what is part of on-chip I/O (gic,
> # a9scu)
> _off_chip_ranges = [AddrRange(0x2F00, size='16MiB'),
> AddrRange(0x3000, size='256MiB'),
> AddrRange(0x4000, size='512MiB'),
> AddrRange(0x1800, size='64MiB'),
> AddrRange(0x1C00, size='64MiB')]
>
>
>
> Thanks,
> Md Rubel Ahmed
>
>
> Graduate Student, Dept. of CSE
>
> University of South Fl​orida, Tampa, FL

Kind regards

Giacomo

[1]: https://github.com/gem5/gem5/blob/stable/src/dev/arm/pl011.cc#L54
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/41317/3

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[gem5-users] Re: System() and RubySystem()

[Giacomo Travaglini via gem5-users]

Hi Javed,

You are correct in your assumptions. I believe the confusion arises from the 
overuse of the "System" keyword. As a summary,
The System class (defined in src/sim/system.hh) is the child of the Root node 
and encompasses most of the simulated models (cpu, memory subsystem, devices, 
etc).

The RubySystem is a child of the System class (system.ruby = RubySystem() adds 
the RubySystem to the SimObject hierarchy under the system node).
In other words, the RubySystem is a subsystem, whose only purpose is to parent 
ruby memory models. It is not a replacement for the System class nor a 
different implementation

Kind regards

Giacomo

> -Original Message-
> From: Javed Osmany via gem5-users 
> Sent: 16 June 2021 11:17
> To: gem5 users mailing list 
> Cc: Javed Osmany 
> Subject: [gem5-users] FW: System() and RubySystem()
>
> Hello
>
>
>
> Wondering if any help to clear up the issues listed in my previous email?
>
>
>
> Tks
>
> JO
>
>
>
> From: Javed Osmany
> Sent: 14 June 2021 14:18
> To: gem5 users mailing list 
> Cc: Javed Osmany 
> Subject: System() and RubySystem()
>
>
>
> Hello
>
>
>
> Trying to understand the following:
>
>
>
> So in example config scripts I see the following:
>
>
>
> system = System() // Is this then instantiating the default overall
> system ??
>
>
>
> Now, I understand that there are two types of memory system, namely
> classic and Ruby.
>
>
>
> And then if "-ruby" is specified on the command line, the script Ruby.py is
> called.
>
> Within Ruby.py, the function creat_system() is called and in Ruby.py (lines
> 193 - 194), we have the code
>
>
>
>system.ruby = Ruby.System() // Is this then instantiating the Ruby
> memory system within the overall System() ??
>
>ruby= system.ruby // This is then just an alias ??
>
>
>
>
>
> Thanks in advance.
>
> J.Osmany

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[gem5-users] Re: Arm bitLITTLE config

[Giacomo Travaglini via gem5-users]

Hi Javed

> -Original Message-
> From: Javed Osmany via gem5-users 
> Sent: 09 June 2021 15:01
> To: gem5 users mailing list 
> Cc: Javed Osmany 
> Subject: [gem5-users] Arm bitLITTLE config
>
> Hello
>
>
>
> The system I would like to model consists of three clusters [Big, Middle, 
> Little]
>
> Each cluster can have different CPU types and either private or shared L2
> cache.
>
>
>
> Can the config/example/arm/fs_bigLITTLE.py config
>
> 1)  Support three different clusters?

Not out of the box. But bear in mind that gem5 configs are in general meant to 
be example configs to be
extended by users to reflect own hardware organizations

>
> 2)  If the answer to 1) is no, is it possible to extend it to model three
> different clusters

Yes, it shouldn't be that complicated

>
> a.   If extension is possible, any insight into how to achieve this would 
> be
> much appreciated

Gem5 standard library (m5) doesn't really have a notion of a cluster. You can 
add an extra cluster by adapting the fs_bigLITTLE script. No C++ change and no 
recompilation is likely needed

>
> 3)  As the name implies (fs_bigLITTLE.py) this config needs to be run in 
> Full
> System mode.
>
> a.   Is there a version of bigLITTLE config that can be run in SE mode?


No there isn't, but we should probably consider adding it

>
>i.  I am 
> trying to run the PARSEC benchmarks
> and would like to run in SE mode to study coherence performance.
>
>
>
> Thanks in advance
>
>
>
> JO

Kind regards

Giacomo

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[gem5-users] Re: Variable Definitions

[Giacomo Travaglini via gem5-users]

Hi Jason,

At a certain point I should really come up with an ISA documentation to upload 
on gem5.org
Anyway, those are magic operands defined in the operands file [1].
(More specifically [2] and [3]).

When the ISA parser detect those magic words, it translates them into an 
appropriate action (generates some C++ code). For example
XDest is an integer destination register and the parser translates it into a 
GPR read [4] in case of:

val = XDest

and in a GPR write [5] in case of

XDest = val

Let me know if this helps

Kind Regards

Giacomo


[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/operands.isa
[2]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/operands.isa#L685
[3}: https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa/operands.isa#L194
[4]: 
https://github.com/gem5/gem5/blob/stable/src/arch/isa_parser/operand_types.py#L199
[5]: 
https://github.com/gem5/gem5/blob/stable/src/arch/isa_parser/operand_types.py#L216

> -Original Message-
> From: Jason Z via gem5-users 
> Sent: 02 June 2021 19:09
> To: gem5-users@gem5.org
> Cc: Jason Z 
> Subject: [gem5-users] Variable Definitions
>
> Hello Everyone,
>
> I am in the process of trying to add a new instruction, so I am trying to make
> sure I understand the code and the things that I need to change/utilize, but I
> was wondering if there was a better way to determine what each of the
> variables are referring to in gem5 as I haven't been able to find where they
> would be defined.
>
> For instance, in the file src/arch/arm/isa/insts/str64.isa, I am looking into 
> the
> variables Mem_ud and XDest_ud to make sure I understand how a store
> works.
>
> I have been piecing together what I can based on the context and searching
> online, but I just wanted to make sure that I'm not going about it the hard
> way or if this is the correct approach by just considering the context they 
> are
> used.
>
> Thank you for your time!
>
> Respectfully,
>
> Jason Z.
> ___
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[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

Thanks Pedro,

It seems like you are getting an undefined instruction. What is probably 
happening is your host CPU having a feature which is not implemented in gem5, 
so when you switch to the guest(gem5) the sandboxing check is skipped and an 
exception is thrown. As you are happy with your current setup, I won't try to 
investigate further. In case you were interested on fixing it in the future, it 
should be relatively easy to debug it via gdb or with DFLAGS (by printing the 
instruction causing the undef exception)

I would be happy to provide further assistance in that case

Kind Regards

Giacomo

> -Original Message-
> From: Pedro Becker via gem5-users 
> Sent: 02 June 2021 10:22
> To: gem5-users@gem5.org
> Cc: Pedro Becker 
> Subject: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Modify guest binary so init script points to init.gem5.addr
>
> Then run:
>
> $ export M5_PATH=/scratch/pedro/aarch-system-20210904
>
> $ ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --big-cpus 2 -
> -little-cpus 0 --cpu-type kvm --disk /scratch/pedro/ubuntu-18.04-arm64-
> 8gb.img --kernel /scratch/pedro/aarch-system-
> 20210904/binaries/vmlinux.arm64 --bootscript configs/boot/my_script.rcS
>
>
>
> Hi again Giacomo, thanks for the suggestions.
>
> I had tried with fs_bigLITTLE.py before as well, although I haven't reported 
> it
> here.
> I just re-run it now to provide you the outputs. Here are the steps I 
> followed:
>
> i) Made sure init script points to init.gem5.addr in the Linux guest binary 
> so I
> can use m5ops with KVM
>
> ii) clear m5out folder to remove any older data rm -rf m5out/*
>
> iii) export the M5_PATH in the terminal
> export M5_PATH=/scratch/pedro/aarch-system-20210904
>
> iv) run kvm multicore (2 cores in this case) script with kvm:
>
> ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --big-cpus 2 --
> little-cpus 0 --cpu-type kvm --disk /scratch/pedro/ubuntu-18.04-arm64-
> 8gb.img --kernel /scratch/pedro/aarch-system-
> 20210904/binaries/vmlinux.arm64 --bootscript configs/boot/my_script.rcS --
> kvm-userspace-gic
>
> v) restore the generated checkpoint with atomic cpu (left the --kvm-
> userspace-gic just in case it kvm is necessary to perform the checkpoint
> restoration)
>
> ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --big-cpus 2 --
> little-cpus 0 --cpu-type atomic --disk /scratch/pedro/ubuntu-18.04-arm64-
> 8gb.img --kernel /scratch/pedro/aarch-system-
> 20210904/binaries/vmlinux.arm64 --restore m5out/cpt.9399620558500 --
> kvm-userspace-gic
> gem5 Simulator System.  http://gem5.org
> gem5 is copyrighted software; use the --copyright option for details.
>
> gem5 version [DEVELOP-FOR-V21.1]
> gem5 compiled May 20 2021 19:51:48
> gem5 started Jun  2 2021 10:53:57
> gem5 executing on agx, pid 1893
> command line: ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py
> --big-cpus 2 --little-cpus 0 --cpu-type atomic --disk /scratch/pedro/ubuntu-
> 18.04-arm64-8gb.img --kernel /scratch/pedro/aarch-system-
> 20210904/binaries/vmlinux.arm64 --restore m5out/cpt.9399620558500 --
> kvm-userspace-gic
>
> Global frequency set at 1 ticks per second
> info: Simulated platform: VExpress_GEM5_V1
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
> info: Restoring from checkpoint m5out/cpt.9399620558500
> warn: No dot file generated. Please install pydot to generate the dot file and
> pdf.
> build/ARM/sim/kernel_workload.cc:43: info: kernel located at:
> /scratch/pedro/aarch-system-20210904/binaries/vmlinux.arm64
> system.vncserver: Listening for connections on port 5900
> system.terminal: Listening for connections on port 3456
> system.realview.uart1.device: Listening for connections on port 3457
> system.realview.uart2.device: Listening for connections on port 3458
> system.realview.uart3.device: Listening for connections on port 3459
> 0: system.remote_gdb: listening for remote gdb on port 7000
> 0: system.remote_gdb: listening for remote gdb on port 7001
> build/ARM/dev/arm/energy_ctrl.cc:249: warn: Existing EnergyCtrl, but no
> enabled DVFSHandler found.
> build/ARM/sim/simulate.cc:104: info: Entering event queue @
> 9400620568500.  Starting simulation...
> simulate() limit reached  @  18446744073709551615
>
>
> Output in m5out/system.terminal
>
> [8.886724] [ cut here ]
> [8.886729] kernel BUG at /work/gem5-
> scripts/submodules/linux/arch/arm64/kernel/entry.S:602!
> 

[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

Hi Pedro,

What happens if you try to simulate the GIC?
Have a look at what we do in fs_bigLITTLE with the --kvm-userspace-gic option.

You should be able to replicate that in fs.py (though I would recommend you to 
switch to the fs_bigLITTLE script if possible  )

Kind Regards

Giacomo

P.S. I am manually able to boot Linux with multiple vCPUs and by generating 
multiple checkpoints
(basically I run for a fixed amount of tick time, I create a checkpoint and 
exit; next run uses --restore with the latest checkpoint)


> -Original Message-
> From: Pedro Becker via gem5-users 
> Sent: 25 May 2021 10:52
> To: gem5-users@gem5.org
> Cc: Pedro Becker 
> Subject: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Hi all,
>
> I'm still trying to make my kvm dependent setup to work, and any help would
> be very much appreciated.
>
> TL;DR; after restoring from arm kvm checkpoints simulation never advances.
> I'd also like to accelerate gem5 simulation with arm kvm but generate
> checkpoints with atomic, so I could restore them in machines where arm kvm
> is not available (x86 servers), but this also does not work.
>
> First, a brief comment on previous help (to make kvm boot work): I was
> comparing my work with the stable (and master) branch(es), but not with
> the develop which had all the modifications Giacomo mentioned. So now I
> paired my repo with the develop, and kvm boot with 8 cores worked out-of-
> the-box, and it boots much faster than any gem5 models. So I discarded the
> modifications I did and stick with the develop branch to avoid introducing
> new errors (even though my modifications were also working).
>
> However, I'm struggling to leverage KVM for checkpointing, because
> simulation never advances when restoring from a kvm checkpoint.
> When using fs.py with --restore-with-cpu ArmV8KvmCPU --cpu-type
> ArmV8KvmCPU flags, the checkpoint is restored but I see no progress in
> output_folder/system.terminal and also gem5 never exits. Seems like the
> simulation gets stuck. (This setup actually does not matter because I need to
> restore from kvm checkpoint to a gem5 model, not from kvm to kvm, but
> just reporting this test I did in case it is useful.)
>
> The same "stuck simulation" thing happens if I use --restore-with-cpu
> ArmV8KvmCPU --cpu-type AtomicSimpleCPU. In this case, I also activated
> the --debug-flag=Exec and observed the code gets stuck at the
> "_raw_spin_lock_irqsave" method from the kernel. (By stuck I mean, more
> than 3 hours without reporting any new info from the debug-flags). Not sure
> what causes this.
>
> Alternatively, I tried also switching CPUs from kvm to AtomicSimpleCPU right
> before creating the checkpoint. Since I had successfully used
> AtomicSimpleCPU to boot gem5 generated/restored checkpoints in the past,
> I know AtomicSimpleCPU checkpoints should work.
> In fact, this scenario would be the best for me because later on, I'd like to
> restore my checkpoints in x86 servers, where ArmV8KvmCPU will not be
> available and I could never --restore-with-cpu ArmV8KvmCPU.
> But restoring from this checkpoint causes " fatal: fatal
> condition !paramInImpl(cp, name, param) occurred: Can't unserialize
> 'system.cpu:_pid' "
>
> My guess for the latter case was that AtomicSimpleCPU was in the
> system.switch_cpu (not in system.cpu) which is not looked up when
> restoring the checkpoint.
>
> So a final attempt I did was to set the AtomicSimpleCPU as the default CPU
> (testsys.cpu in fs.py) and the ArmV8KvmCPU as the switch_cpu
> (testsys.switch_cpus). The idea was to switch cpus right in the start, run 
> with
> kvm most of the time, and switch back to atomic just to generate the
> checkpoints. Like this, system.cpu should be filled with AtomicSimpleCPU
> data, hence I would be able to restore in x86 servers later.
> However gem5 returned a segfault when I assigned "testsys.switch_cpus =
> switch_cpus", after I created the switch_cpus list with kvm models:
>
> switch_cpus = [ArmV8KvmCPU(switched_out=True, cpu_id=(i)) for i in
> range(np)]
> for i in range(np):
> switch_cpus[i].system =  testsys
> switch_cpus[i].workload = testsys.cpu[i].workload
> switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
> switch_cpus[i].isa = testsys.cpu[i].isa
> testsys.switch_cpus = switch_cpus  # this line causes a gem5 
> segfault
> switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in 
> range(np)]
>
> I see that using kvm is very common in different scripts on gem5-resources
> (https://gem5.googlesource.com/public/gem5-resources/), but they all
> seem to use kvm for x86. Is switching to x86 the best solution for my problem?
> Any suggestions on the way I'm setting things up?
>
> Again, thank you very much.
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[gem5-users] Re: Using the CHI protocol for GEM5

[Giacomo Travaglini via gem5-users]

Hi Javed,

> -Original Message-
> From: Javed Osmany via gem5-users 
> Sent: 18 May 2021 14:16
> To: gem5-users@gem5.org
> Cc: Javed Osmany 
> Subject: [gem5-users] Using the CHI protocol for GEM5
>
> Hello
>
>
>
> Previously, when experimenting with MESI or MOESI coherence protocol,
> the approach was to build the gem5.opt for the specific protocol. For
> example
>
>
>
> scons -j4 build/ARM_MESI_3_level/gem5.opt --default=ARM
> PROTOCOL=MESI_Three_Level SLICC_HTML=True
>
>
>
>
>
> I would like to experiment with the CHI protocol. Do I also need to build the
> gem5.opt executable with PROTOCOL=CHI?

Yes, you could explicitly select CHI via the PROTOCOL option, though it is not 
strictly necessary (CHI is the current default for Arm builds):

$rm -rf build -> clean the environment if you were building with another 
protocol
$scons -j4 build/ARM/gem5.opt -> This will build CHI

>
>
>
> Any pointers to where the above is detailed would be appreciated.

I recommend you to have a look at the guide provided by Tiago [1]

>
>
>
> Tks in advance
>
>
>
> JO
>
>

Kind regards

Giacomo

[1]: http://www.gem5.org/documentation/general_docs/ruby/CHI/
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[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

Hi Pedro, glad it worked

> -Original Message-
> From: Pedro Henrique Exenberger Becker 
> Sent: 14 May 2021 10:48
> To: Giacomo Travaglini 
> Cc: gem5 users mailing list 
> Subject: Re: [gem5-users] Re: Boot FS with kvm and multiple cores
>
> Hi Giacomo,
>
>
>
>   --little-cpus option defaults to 1. This means you are effectively
> running with 9 cpus.
>
>   Could you try setting --little-cpus to zero from command line?
>
>
> Yes, this works. Rookie mistake of mine.
>
> At this point, I have already adapted code from fs_bigLITTLE.py script to the
> fs.py script and got it working.
> (For those interested, I "ported" the _build_kvm method and also set the
> root.sim_quantum to 1ms as in the as done in fs_bigLITTLE.py)

I gave a quick look. _build_kvm seems more or less the same.
The problem is in the fs.py sim_quantum:

root.sim_quantum = int(1e9) # 1 ms

This is obviously wrong

And it should align with fs_bigLITTLE.
Are you keen on posting a patch fixing it?

Otherwise I can post it myself (if you don't want to)

Kind Regards

Giacomo


>
> Anyway, thank you for the help!
> Best,
> Pedro.
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[gem5-users] Re: Tracing Instructions in gem5 (re: Adding a New Instruction)

[Giacomo Travaglini via gem5-users]

Hi Jason,

> -Original Message-
> From: jzell001--- via gem5-users 
> Sent: 14 May 2021 00:44
> To: gem5-users@gem5.org
> Cc: jzell...@ucr.edu
> Subject: [gem5-users] Tracing Instructions in gem5 (re: Adding a New
> Instruction)
>
> Hi Everyone,
>
> I am fairly new to gem5, so I apologize if this has already been addressed, 
> but
> I haven't been able to find a solution yet.

Do not worry, every question is welcome here 

>
> I am trying to add a new type of store instruction to gem5 similar to the STG
> instruction from ARM's MTE instructions.
>
> I was wondering if there was a debug flag or an approach using GDB to
> determine what files are used when processing an instruction in gem5.

Do you want to record *every* uprocessor activity on a specific instruction 
(the one you are implementing)?
For example, tracing the lifetime of the instruction within the pipeline.
If that is the case, there's no such thing at the moment in gem5. This is 
because we trace from a uprocessor perspective rather than from an instruction
point of view.

For example, I can turn on/off instruction fetch tracing or decode tracing or 
rename tracing, but this will be done for every instruction
and I cannot easily filter it for a specific instruction only.

You are asking about files and classes. This confuses me a bit. If you just 
want to know which files are used I can tell you most files in the used cpu 
model
subdirectory (e.g. src/cpu/o3) will deal with instruction processing as that's 
the main activity of a uprocessor pipeline.

>
> I am aware of some of the general files that need to be edited, such as:
>
>src/arch/arm/isa/formats/aarch64.isa
>src/arch/arm/isa/templates/mem64.isa
>src/arch/arm/isa/insts/str64.isa
>
> But I would like to be able to see all of these files/functions/classes as 
> they
> are used/touched as an instruction is processed through gem5. For instance,
> seeing what things are accessed when a STR instruction that already is
> implemented in gem5 is being processed.

I have the impression you are merging two different problems in one (correct me 
if I am wrong):
1)  Understanding how the simulator works (this is why you want to trace the 
used classes and files)
2)  Effectively tracing your instruction handling during your workload execution

I believe you should achieve 1 by actually understanding the code plus getting 
an idea on what you really want to trace
about an instruction. Do you really want to trace everything? Maybe you are 
just interested about tracing the architectural results of your store. If 
that's the case no need
to check the cpu subdirectory.
Once you know what you want to trace during your workload execution and where 
the code resides in the repo you can pass to point 2 and effectively add your 
DPRINTFs
to the code.

>
> Any help or advice would be greatly appreciated. Thank you for your time!
>
>
> Respectfully,
>
> Jason Z.
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Hope this helped

Kind Regards

Giacomo
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[gem5-users] Re: Boot FS with kvm and multiple cores

[Giacomo Travaglini via gem5-users]

Hi Pedro

> The main problem I still have is fs_bigLITTLE.py with --big-cpus 8 (I want to
> have an 8-core setup) causes panic:
> info: Using bootloader at address 0x10
> info: Using kernel entry physical address at 0x8008
> info: Loading DTB file: m5out/system.dtb at address 0x8800
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> info: KVM: Coalesced MMIO disabled by config.
> panic: KVM: Failed to create virtual CPU Memory Usage: 2619720 KBytes
> Program aborted at tick 0
> --- BEGIN LIBC BACKTRACE ---
> ./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0x5576c8e090]
> ./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0x55770cbdb4]
> linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x7f9b01e6c0]
> /lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x7f9abe94f8]
> --- END LIBC BACKTRACE ---
> Aborted (core dumped)
>
> I saw some discussion on gem5 supporting gicv2 but not gicv3, but from what
> I read even the former should support up to 8 cores. So I'm not sure this is
> the problem here. Any suggestions?


--little-cpus option defaults to 1. This means you are effectively running with 
9 cpus.
Could you try setting --little-cpus to zero from command line?

>
> Thanks,
> Pedro.
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Kind Regards

Giacomo
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[gem5-users] Re: Qemu equivalent command/simulation to Gem5

[Giacomo Travaglini via gem5-users]

Hi

> -Original Message-
> From: Đức Anh via gem5-users 
> Sent: 11 May 2021 13:34
> To: gem5 users mailing list 
> Cc: Đức Anh 
> Subject: [gem5-users] Qemu equivalent command/simulation to Gem5
>
> Dear all,
>
> I have a Linux kernel v5.10.27 build for arm64 architecture that is runnable 
> on
> Gem5. Now I want to run it on Qemu-system-aarch64, but I haven't figure
> out the proper command and parameters yet. Here is the few things I have
> tried:
> - qemu-system-aarch64 -M vexpress-a15 --cpu cortex-a15 -m 2048 --kernel
> output/vmlinux From the Gem5 source code, I know Gem5 implements Arm
> CoreTile Express A15x2 (V2P-CA15) (from the comment in
> src/dev/arm/RealView.py). It has Cortex-A15. So I chose the parameters like
> above. However, it showed the following error:

That is actually  the name of the daughterboard. It is named after the A15 as 
it should contain the dual core A15 cluster in a *test chip* (Cortex-A15_A7 
MPCore [1])  we don't emulate in gem5.
That doesn't mean your application processor will be an A15.

>
> qemu-system-aarch64: Trying to execute code outside RAM or ROM at
> 0x0400
>
>
> The reason I think is vexpress-a15 and cortex-a15 are arm architecture, not
> arm64. I tried a few other parameters like cortex-a53, cortex-a57, 
> versatileab,
> versatilepb, but all of them do not work.

I am not a QEMU expert, but I have successfully used the virt platform in the 
past.

>
> So how can I run the kernel on Qemu?
>
> And besides, I wonder how Gem5 implements Arm CoreTile Express A15x2
> (ARM arch) and supports ARMv8 (arm64 arch) at the same time?

As I mentioned earlier, we don't simulate any A15 processor within the Arm 
CoreTile Express A15x2 daughterboard.
So the execution mode of your gem5 simulation will automatically be 
arm64/aarch64 (it will be automatically detected by the workload object) 
regardless of the CPU model (microarchitecture) being modelled.

>
> Best regards,
> Duc Anh

Kind Regards

Giacomo

[1]: 
https://developer.arm.com/documentation/ddi0503/i/hardware-description/coretile-express-a15-2-a7-3-daughterboard-architecture
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[gem5-users] Re: Ruby in Arm?

[Giacomo Travaglini via gem5-users]

Hi Adrian,

I don't know to be honest why this is happening in fs.py only.
In general, have you tried to recompile the gem5 bootloader or alternatively to 
download the latest precompiled version? [1]

Kind Regards

Giacomo

[1]: http://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries

> -Original Message-
> From: adrian via gem5-users 
> Sent: 09 May 2021 20:33
> To: gem5-users@gem5.org
> Cc: adrian.barre...@gmail.com
> Subject: [gem5-users] Re: Ruby in Arm?
>
> Hi Giacomo,
>
> Thanks for your response. I've managed to run the simulator with a single
> core. However, I cannot do the same with more than one.
> This is the command I use to boot.
>
> ./build/ARM/gem5.opt --outdir m5out/booted_machine_4
> configs/example/fs.py --kernel=binaries/vmlinux.arm64 --cpu-
> type=AtomicSimpleCPU --num-cpus=4 --mem-size=2GB --disk-image
> disks/gem5-ubuntu16.04-aarch64.img --script
> configs/boot/hack_back_ckpt.rcS
>
> I get the following message in the terminal:
>
> [0.048079] smp: Bringing up secondary CPUs ...
> [1.088619] CPU1: failed to come online
> [1.088622] CPU1: failed in unknown state : 0x0
> [2.145168] CPU2: failed to come online
> [2.145171] CPU2: failed in unknown state : 0x0
> [3.201716] CPU3: failed to come online
> [3.201719] CPU3: failed in unknown state : 0x0
> [3.201737] smp: Brought up 1 node, 1 CPU
>
> I do not get this error when using the fs_bigLITTLE.py file. My gem5 version 
> is
> 21.0.0.0. What could be happening?
>
> Thanks,
> Adrián
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[gem5-users] Re: Ruby in Arm?

[Giacomo Travaglini via gem5-users]

Hi Adrian,

> -Original Message-
> From: adrian via gem5-users 
> Sent: 07 May 2021 09:36
> To: gem5-users@gem5.org
> Cc: adrian.barre...@gmail.com
> Subject: [gem5-users] Ruby in Arm?
>
> Hi guys,
>
> I've always used the classic memory model when running timing simulations
> using Arm, but I'd like to run some experiments using Ruby.
> I've seen some people using it and asking questions about it,  but my current
> version of gem5 shows this warning when enabling it:
>
> "warn: You are trying to use Ruby on ARM, which is not working properly
> yet."

That is a legacy warning from fs.py which has been removed in develop branch by:

https://gem5-review.googlesource.com/c/public/gem5/+/44509

And will be part of gem5 21.1

>
> Can anybody confirm me I can use it or how to properly use it?
>
> I'm employing this command:
>
> "./build/ARM/gem5.opt -d m5out/foo configs/example/fs.py --cpu-
> type=DerivO3CPU --ruby --num-cpus=4 --caches --l2cache --kernel
> binaries/vmlinux.arm64 --restore-with-cpu=DerivO3CPU --dtb
> binaries/armv8_gem5_v1_4cpu.dtb --mem-size=2GB --disk-image
> disks/gem5-ubuntu16.04-aarch64.img -r 1"

That seems a valid command line.
FYI I have added a simpler ARM ruby script in develop to use in lieu of fs.py:

configs/example/arm/ruby_fs.py

That will be also part of 21.1

Kind Regards

Giacomo

>
> Thanks a lot,
> Adrián
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[gem5-users] Re: How to use HTM in gem5-20?

[Giacomo Travaglini via gem5-users]

Yes, that is correct 

Kind Regards

Giacomo

> -Original Message-
> From: Taiyu Zhou via gem5-users 
> Sent: 28 April 2021 13:12
> To: gem5-users@gem5.org
> Cc: Taiyu Zhou 
> Subject: [gem5-users] Re: How to use HTM in gem5-20?
>
> Thank you so much for your reply.
> So, is it gem5-20 has not yet supported HTM for x86?
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[gem5-users] Re: How to use HTM in gem5-20?

[Giacomo Travaglini via gem5-users]

Hi,

Arm has provided an HTM implementation.
I suggest you to have a look at the following blog post by Timothy Hayes (he 
wrote the implementation)

http://www.gem5.org/project/2020/10/27/tme.html

Kind Regards

Giacomo

> -Original Message-
> From: Taiyu Zhou via gem5-users 
> Sent: 28 April 2021 03:12
> To: gem5-users@gem5.org
> Cc: Taiyu Zhou 
> Subject: [gem5-users] How to use HTM in gem5-20?
>
> Hi all,
>
> I read the code in MESI_Three_LEVEL_HTM_*.sm. It seems like gem5-20 has
> supported the HTM.  I want to use HTM in gem5. But I didn't find any ISA
> support in gem5-20, e.g, _xbegin,_xend. Does gem5-20 fully support HTM?
> How can I use it?
>
> Thanks.
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[gem5-users] Re: ARM and opening a file

[Giacomo Travaglini via gem5-users]

FYI the debug flag option is

--debug-flags=SyscallAll

Kind Regards

Giacomo

> -Original Message-
> From: Gabe Black via gem5-users 
> Sent: 21 April 2021 01:20
> To: gem5 users mailing list 
> Cc: Gabe Black 
> Subject: [gem5-users] Re: ARM and opening a file
>
> If this works on x86, the chances are good that the system call
> implementations are fine since they're likely the same between the two, but
> there could be some glue (flag translation, which system calls that are
> hooked up) which is different. You should try enabling the system call
> DPRINTF flags (--debug-flags on the command line) to see what system calls
> are being called, and what they're returning. If a system call which isn't
> implemented is being called, there should be a message about it from gem5.
>
> Gabe
>
> On Tue, Apr 20, 2021 at 1:45 PM Bobby Bruce via gem5-users  us...@gem5.org  > wrote:
>
>
> Hey Majid,
>
> Are you running in FS or SE mode? If you're running in SE mode, I
> don't find this too surprising as not all System calls are currently 
> supported.
>
>
> Kind regards,
> Bobby
> --
>
> Dr. Bobby R. Bruce
> Room 2235,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
>
> web: https://www.bobbybruce.net
>
>
>
> On Wed, Apr 14, 2021 at 8:16 PM Majid Jalili via gem5-users  us...@gem5.org  > wrote:
>
>
> Hi,
>
> When I was running SPEC CPU 2017, in particular 505.mcf_r, I
> noticed that if gem5 should open a file, it will not make any progress. I dig
> into mcf code and found when the read_min function is called the simulation
> freezes.
> Then I started running a simple benchmark as follows, that
> just prints the content of a file:
>
> https://www.geeksforgeeks.org/c-program-print-contents-
> file/
>
>
> For this example, I also run into the same problem. I tried X86
> and everything works just fine
>
> Repo:  I tried both dev and stable
> gcc: aarch64-linux-gnu-gcc-7 aarch64-linux-gnu-gcc-5
>
> Any help is great!
>
>
>
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[gem5-users] Re: Error while installing gem 5

[Giacomo Travaglini via gem5-users]

I believe it just takes a lot of time (I have been noticing the same).
Could you try to wait for completion?

Kind Regards

Giacomo

> -Original Message-
> From: VAIDYA ROHINI VILAS via gem5-users 
> Sent: 20 April 2021 06:32
> To: gem5 users mailing list 
> Cc: VAIDYA ROHINI VILAS 
> Subject: [gem5-users] Re: Error while installing gem 5
>
> Hi,
> No error message is there.
> process just stops at  [   LINK ]   -> ARM/gem5.opt
> 
>
> From: keshav via gem5-users 
> Sent: 20 April 2021 10:48
> To: gem5 users mailing list 
> Cc: keshav 
> Subject: [gem5-users] Re: Error while installing gem 5
>
> Hi,
>
> What's the error message that you get ?
>
> On Tue, 20 Apr, 2021, 10:31 am VAIDYA ROHINI VILAS via gem5-users,
> mailto:gem5-users@gem5.org> > wrote:
>
>
> Hello,
> while building ARM or X86 architecture on gem5 I am using command
> "scons build/X86/gem5.opt -j5" but scons is not yet build successfully. Here 
> ,I
> have attached screenshot where building of ARM stops.
> Please, help me to solve this issue ASAP.
> Thank you.
> 
>
> From: ahmad sedigh via gem5-users   >
> Sent: 19 April 2021 13:31
> To: gem5 users mailing list mailto:gem5-
> us...@gem5.org> >
> Cc: ahmad sedigh   >
> Subject: [gem5-users] Re: Error while installing gem 5
>
> Hello,
> At this stage you should just press enter and continue.
> The warning is negligible.
>
> Ahmad
>
> On Mon, Apr 19, 2021 at 1:55 PM VAIDYA ROHINI VILAS via gem5-
> users mailto:gem5-users@gem5.org> > wrote:
>
>
> Hello ,
> I am trying to download gem5 in my new system having
> ubuntu version 20.04 using "git clone https://github.com/gem5/gem5.git
>  " . I also tried from official
> documentation of gem 5 but while building gem5 using  command  "scons
> build/ARM/gem5.opt -j5"   i am getting error as "Scons: Reading SConscript
> files ...
>
> You're missing the gem5 style or commit message hook.
> These hooks help
> to ensure that your code follows gem5's style rules on git
> commit.
> This script will now install the hook in your .git/hooks/
> directory.
> Press enter to continue, or ctrl-c to abort:  "
> Please help me to solve this error ASAP.
> Thank you.
>
>
>
>
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[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

[Giacomo Travaglini via gem5-users]

Hi Wenqi

> -Original Message-
> From: wq...@utexas.edu 
> Sent: 09 April 2021 23:07
> To: Giacomo Travaglini ; gem5 users mailing
> list 
> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>
> Hi Giacomo,
>
> Thanks for letting me know what the problem is, I am able to verify the
> solution on my end as well :-)
>
> Just curious, as I am not familiar with the arm system, do you always need to
> provide a separate bootloader to boot arm FS simulation in gem5?

You don't if you run a baremetal workload in an arm FS simulation.
If you boot an OS like Linux, then the answer is: it depends, but you need to 
initialize the system somehow.

The default behaviour in fs_bigLITTLE, fs and fs_starter is to use the gem5 
bootloader (very minimal) to boot the OS.
Nothing stops you from using different kinds of bootloaders though. For example 
in the past I have used the aarch64 bootwrapper which
is generating a single image with kernel + bootloader (external) + dtb. Lately 
I have been using GRUB as well.

You could in theory avoid having the extra bootloader binary; one option is to 
embed it in gem5 (I might be wrong but I believe this is what QEMU does), and 
the other is to initialize the platform
on the host side (replicating what the guest bootloader is supposed to do 
before starting executing the kernel). Those two options are currently not 
supported.

> Will the one packed with the kernel work? (I assume when sim x86, it uses
> the bootloader from the kernel).

I believe x86 is implementing one of the two options above

>
> Best,
>
> Wenqi

Kind Regards

Giacomo

>
> On 4/9/21 5:09 AM, Giacomo Travaglini wrote:
> > Hi Wenqi,
> >
> > I have found the problem; in order to fix it you should recompile the
> > bootloaders from system/arm/bootloader/arm64 and replace all of them
> with the ones in M5_PATH/binaries That solves the problem on my side.
> >
> > I am gonna update the guest binaries tarball in gem5.org (I was going
> > to do that anyway after the 21.0 release)
> >
> > Kind Regards
> >
> > Giacomo
> >
> >
> >> -Original Message-
> >> From: Giacomo Travaglini
> >> Sent: 07 April 2021 09:13
> >> To: Wenqi Yin ; gem5 users mailing list  >> us...@gem5.org>
> >> Subject: RE: [gem5-users] Fail to Boot Multicore Arm System with KVM
> >> CPU
> >>
> >> Thanks Wenqi,
> >>
> >> I was about to suggest the same; please feel free to open a JIRA ticket at:
> >>
> >> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/
> >>
> >> Kind Regards
> >>
> >> Giacomo
> >>
> >>> -Original Message-
> >>> From: Wenqi Yin 
> >>> Sent: 07 April 2021 06:40
> >>> To: gem5 users mailing list 
> >>> Cc: Giacomo Travaglini 
> >>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM
> >>> CPU
> >>>
> >>> Hi All,
> >>>
> >>> The problem turns out to be with the recent release v21.0. I rolled
> >>> back to v20.2, it can boot 8+ KVM cpu after applying all the changes
> >> discusses before.
> >>> Shall I report this issue anywhere? If so is there any instructions to do 
> >>> so?
> >>> Thanks
> >>>
> >>> Best,
> >>> Wenqi
> >>>
>  On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:
> 
>  Hi Giacomo,
> 
>  I pasted the perhaps most relevant dmesg output of guest kernel and
>  the
> >>> disassembled dtb file snippet (In this case, I use fs_bigLittle.py
> >>> and boot 4
> >>> vCPU) . Also attached the full dts and dmesg output in case I left
> anything.
>  [0.00] CPU features: GIC system register CPU interface present
> but
> >>> disab
>  led by higher exception level
> 
>  [0.052000] smp: Bringing up secondary CPUs ...
>  [2.004021] random: fast init done
>  [2.132023] CPU1: failed to come online
>  [2.132023] CPU1: failed in unknown state : 0x0
>  [4.244045] CPU2: failed to come online
>  [4.244045] CPU2: failed in unknown state : 0x0
>  [6.356068] CPU3: failed to come online
>  [6.356068] CPU3: failed in unknown state : 0x0
>  [8.468091] CPU4: failed to come online
>  [8.468091] CPU4: failed in unknown state : 0x0
>  [8.468091] smp: Brought up 1 node, 1 CPU
> 
> 
>  cpus {
>   #address-cells = <0x1>;
>   #size-cells = <0x0>;
> 
>   cpu@0 {
>   device_type = "cpu";
>   compatible = "gem5,arm-cpu";
>   reg = <0x0>;
>   enable-method = "spin-table";
>   cpu-release-addr = <0x0 0x87f8>;
>   clock-frequency = <0x773593ff>;
>   phandle = <0xf>;
>   };
> 
>   cpu@1 {
>   device_type = "cpu";
>   compatible = "gem5,arm-cpu";
>   reg = <0x1>;
> 

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

[Giacomo Travaglini via gem5-users]

Hi Wenqi,

I have found the problem; in order to fix it you should recompile the 
bootloaders from system/arm/bootloader/arm64 and replace all of them with the 
ones in M5_PATH/binaries
That solves the problem on my side.

I am gonna update the guest binaries tarball in gem5.org (I was going to do 
that anyway after the 21.0 release)

Kind Regards

Giacomo


> -Original Message-
> From: Giacomo Travaglini
> Sent: 07 April 2021 09:13
> To: Wenqi Yin ; gem5 users mailing list  us...@gem5.org>
> Subject: RE: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>
> Thanks Wenqi,
>
> I was about to suggest the same; please feel free to open a JIRA ticket at:
>
> https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/
>
> Kind Regards
>
> Giacomo
>
> > -Original Message-
> > From: Wenqi Yin 
> > Sent: 07 April 2021 06:40
> > To: gem5 users mailing list 
> > Cc: Giacomo Travaglini 
> > Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM
> > CPU
> >
> > Hi All,
> >
> > The problem turns out to be with the recent release v21.0. I rolled
> > back to v20.2, it can boot 8+ KVM cpu after applying all the changes
> discusses before.
> >
> > Shall I report this issue anywhere? If so is there any instructions to do 
> > so?
> > Thanks
> >
> > Best,
> > Wenqi
> >
> > > On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:
> > >
> > > Hi Giacomo,
> > >
> > > I pasted the perhaps most relevant dmesg output of guest kernel and
> > > the
> > disassembled dtb file snippet (In this case, I use fs_bigLittle.py and
> > boot 4
> > vCPU) . Also attached the full dts and dmesg output in case I left anything.
> > >
> > > [0.00] CPU features: GIC system register CPU interface present but
> > disab
> > > led by higher exception level
> > >
> > > [0.052000] smp: Bringing up secondary CPUs ...
> > > [2.004021] random: fast init done
> > > [2.132023] CPU1: failed to come online
> > > [2.132023] CPU1: failed in unknown state : 0x0
> > > [4.244045] CPU2: failed to come online
> > > [4.244045] CPU2: failed in unknown state : 0x0
> > > [6.356068] CPU3: failed to come online
> > > [6.356068] CPU3: failed in unknown state : 0x0
> > > [8.468091] CPU4: failed to come online
> > > [8.468091] CPU4: failed in unknown state : 0x0
> > > [8.468091] smp: Brought up 1 node, 1 CPU
> > >
> > >
> > > cpus {
> > > #address-cells = <0x1>;
> > > #size-cells = <0x0>;
> > >
> > > cpu@0 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x0>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0xf>;
> > > };
> > >
> > > cpu@1 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x1>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x10>;
> > > };
> > >
> > > cpu@2 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x2>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x11>;
> > > };
> > >
> > > cpu@3 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x3>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x773593ff>;
> > > phandle = <0x12>;
> > > };
> > >
> > > cpu@104 {
> > > device_type = "cpu";
> > > compatible = "gem5,arm-cpu";
> > > reg = <0x104>;
> > > enable-method = "spin-table";
> > > cpu-release-addr = <0x0 0x87f8>;
> > > clock-frequency = <0x3b9ac9ff>;
> > > phandle = <0x13>;
> > > };
> > > };
> > >
> > > best,
> > >
> > > Wenqi
> > >
> > > On 4/6/21 7:35 AM, Giacomo Travaglini wrote:
> > >> Hi Wenqi,
> > >>
> > >> Could you provide us with the booting log of the guest kernel?
> > >>
> > >> Kind Regards
> > >>
> > >> Giacomo
> >