[gem5-users] How do I disable most statistics in the stats.txt under Atomic CPU

[Liyichao via gem5-users]

Hi All:
 In the Atomic CPU, only a function simulation is performed for 
enabling or debugging applications. The performance statistics of the 
architecture are not concerned. Therefore, only a small items are required, 
e.g. number of instructions or cycles.

According to my understanding, each performance measurement item in the code 
may affect the simulation speed. If we can disable statistics items that are 
not concerned in most functional models, the simulation speed may be greatly 
improved. I do not know whether my understanding is correct. If so, does GEM5 
consider the performance statistics switch?

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[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

[Liyichao via gem5-users]

Hi Busnot:
I think the patch fix my problems if I set the SHARE L3 as inclusive, 
but if I set it as exclusive, the problem still exist.

I have left the my problem and config description in the JIRA: 
https://gem5.atlassian.net/browse/GEM5-1185



-邮件原件-
发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2022年2月18日 15:20
收件人: gem5-users@gem5.org
抄送: Gabriel Busnot 
主题: [gem5-users] Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 
5.10 in Ruby-CHI and O3

Hi Liyichao,

You might be in luck! A patch fixing non-HN shared CHI cache has been pushed to 
develop yesterday. You can cherry-pick it here: 
https://gem5-review.googlesource.com/c/public/gem5/+/56810.
You can also have a look at the patch attached to the following issue: 
https://gem5.atlassian.net/browse/GEM5-1185. The patch configures a shared L2 
but it should work about the same for shared L3. Your diff looks OK to me but 
it is hard to be assertive.

If this doesn't work for you, can you please fill a Jira with detailed 
reproduction steps for the bug?

Regards,
Gabriel
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[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

[Liyichao via gem5-users]

Hi Busnot:
I have tried the patch, but it still has the same assert.

 


-邮件原件-
发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2022年2月18日 15:20
收件人: gem5-users@gem5.org
抄送: Gabriel Busnot 
主题: [gem5-users] Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 
5.10 in Ruby-CHI and O3

Hi Liyichao,

You might be in luck! A patch fixing non-HN shared CHI cache has been pushed to 
develop yesterday. You can cherry-pick it here: 
https://gem5-review.googlesource.com/c/public/gem5/+/56810.
You can also have a look at the patch attached to the following issue: 
https://gem5.atlassian.net/browse/GEM5-1185. The patch configures a shared L2 
but it should work about the same for shared L3. Your diff looks OK to me but 
it is hard to be assertive.

If this doesn't work for you, can you please fill a Jira with detailed 
reproduction steps for the bug?

Regards,
Gabriel
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[gem5-users] 答复: Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

[Liyichao via gem5-users]

Hi Busnot:
Thank you very much.
I will have a try with the patch. If it can fix my problem, I will let 
you know.



-邮件原件-
发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2022年2月18日 15:20
收件人: gem5-users@gem5.org
抄送: Gabriel Busnot 
主题: [gem5-users] Re: 答复: Does the gem5 v21.0.1.0 support to bootup with kernel 
5.10 in Ruby-CHI and O3

Hi Liyichao,

You might be in luck! A patch fixing non-HN shared CHI cache has been pushed to 
develop yesterday. You can cherry-pick it here: 
https://gem5-review.googlesource.com/c/public/gem5/+/56810.
You can also have a look at the patch attached to the following issue: 
https://gem5.atlassian.net/browse/GEM5-1185. The patch configures a shared L2 
but it should work about the same for shared L3. Your diff looks OK to me but 
it is hard to be assertive.

If this doesn't work for you, can you please fill a Jira with detailed 
reproduction steps for the bug?

Regards,
Gabriel
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[gem5-users] Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI and O3

[Liyichao via gem5-users]

Hi All:
 Does the gem5 v21.0.1.0 support to bootup with kernel 5.10 in Ruby-CHI 
and O3?
Or if anyone has ever bootup with it?

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[gem5-users] m5 resetstats cannot reset cache statistics

[Liyichao via gem5-users]

Hi All:
 I have found that m5 resetstats cannot reset cache statistics such as 
hit count/miss count/access both in classic and ruby, so I looked into the 
source code, I have found that in Cache-part sourcecode, there is no resetstats 
callback function in it.
Am I right? If so, are there any plans to implement it?
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[gem5-users] 答复: Re: Multithread simulation using gem5 SE mode

[Liyichao via gem5-users]

Hi：
 I have more question:
 Can I run a program with dynamic link on SE?

  My host machine is aarch64, and my program is also an aarch64 ELF, 
the program can find all library on this host machine according to the result 
of “ldd”.

发件人: RTL Insn via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2022年1月26日 14:07
收件人: gem5 users mailing list 
抄送: RTL Insn 
主题: [gem5-users] Re: Multithread simulation using gem5 SE mode

It is not possible to run a multithreaded program in Gem5-SE mode as you need 
an operating system that handles the threads at kernel level. So, full-system 
mode should be used for running any multithreaded programs.

On Wed, Jan 26, 2022 at 3:40 AM Andronicus Samsundar Rajasukumar via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,

I'm trying to run a multithreaded c++ application in SE mode using O3 CPU + 
classic caches + DRAMSim3.

The single thread version of this application runs correctly producing desired 
results.

When I increase the number of threads, I see indeterministic behavior in the 
simulations.

I've gone through many of the queries sent before about simulating 
multithreaded applications and it looks like the SE mode isn't best suited to 
do this. Is this true in the latest 21.2 release as well?

Can I use FS mode for a system with O3CPU+classic caches+DRAMSim3 to test 
multithreaded/multicore applications? I also noticed that it was mentioned in 
one of the posts that classic caches do not support multicore simulation. If 
that is the case, what would be the best methodology to simulate such a system.

Thank you,
Andronicus

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[gem5-users] 答复: Re: restore with O3 hang when "bti" instrution meet

[Liyichao via gem5-users]

Hi Becker:
Thanks for your reply.

Now I have followed your modification, I can see that the "bti" instruction 
has been replaced by "nop", but it always hang here, so do you have any idea?

68338414857000: system.cpu: T0 : 0x7ff7e632d4:   sub   x21, x21, #1936  
  : IntAlu :  D=0x007ff7ff0010
68338414857500: system.cpu: T0 : 0x7ff7e632d8:   ldr   x0, [x21, #208]: 
MemRead :  D=0x02b5 A=0x7ff7ff00e0
68338414857500: system.cpu: T0 : 0x7ff7e632dc:   subs   w1, w0: 
IntAlu :  D=0x
68338414857500: system.cpu: T0 : 0x7ff7e632e0:   b.eq   
 : IntAlu :
68338414857500: system.cpu: T0 : 0x7ff7e632e4:   orr   x1, xzr, x19   : 
IntAlu :  D=0x007ff7f70360
68338414857500: system.cpu: T0 : 0x7ff7e632e8:   movz   w0, #2, #0: 
IntAlu :  D=0x0002
68338414857500: system.cpu: T0 : 0x7ff7e632ec: stp
68338414857500: system.cpu: T0 : 0x7ff7e632ec. 0 :   addxi_uop   ureg0, sp, #48 
: IntAlu :  D=0x007fe770
68338414857500: system.cpu: T0 : 0x7ff7e632ec. 1 :   strxi_uop   x23, [ureg0] : 
MemWrite :  D=0x007ff7f6f000 A=0x7fe770
68338414857500: system.cpu: T0 : 0x7ff7e632ec. 2 :   strxi_uop   x24, [ureg0, 
#8] : MemWrite :  D=0x007ff7f7 A=0x7fe778
68338414858000: system.cpu: T0 : 0x7ff7e632f0:   bl   
<_kernel_size_le_lo32+549610018496> : IntAlu :  D=0x007ff7e632f4
6833841519: system.cpu: T0 : 0x7ff7f0b6c0:   nop  : 
IntAlu :
6833841519: system.cpu: T0 : 0x7ff7f0b6c4:   adrp   x16, #462848  : 
IntAlu :  D=0x007ff7f7c000
6833841519: system.cpu: T0 : 0x7ff7f0b6c8:   ldrb   w16, [w16, #2287] : 
MemRead :  D=0x0001 A=0x7ff7f7c8ef
6833841519: system.cpu: T0 : 0x7ff7f0b6cc:   cbz   w16, 
<_kernel_size_le_lo32+549610018520> : IntAlu :




-邮件原件-
发件人: Pedro Becker via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2022年1月25日 18:16
收件人: gem5-users@gem5.org
抄送: Pedro Becker 
主题: [gem5-users] Re: restore with O3 hang when "bti" instrution meet

Hi Liyuchao, 

I'm assuming you are referring to ARM ISA...
BTI is appearing on your code but it's not implemented. 

"A BTI instruction is used to guard against the execution of instructions that 
are not the intended target of a branch. Outside of a guarded memory region, a 
BTI instruction executes as a NOP. "
(See here: 
https://developer.arm.com/documentation/100076/0100/a64-instruction-set-reference/a64-general-instructions/bti)

My understanding is that if you are not trying to investigate how this guarding 
mechanism works (say, because you are investigating hardware security or 
whatever), you can simply ignore that instruction as if your code is outside of 
a guarded memory region.

So in src/arch/arm/isa/formats/aarch64.isa you can find the bti instruction and 
return a NOP instead of an unimplemented instruction. Something like this:

- return new WarnUnimplemented("bti", machInst);
+ return new NopInst(machInst);

Recompile gem5 and check if it does the trick.
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[gem5-users] 撤回: Re: restore with O3 hang when "bti" instrution meet

[Liyichao via gem5-users]

Liyichao 将撤回邮件“[gem5-users] Re: restore with O3 hang when "bti" instrution 
meet”。
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[gem5-users] 答复: Re: restore with O3 hang when "bti" instrution meet

[Liyichao via gem5-users]

Hi Becker:
Thank for your reply.

When I modify the code like yours, some error when I compile:
scons: Building targets ...
 [ISA DESC] ARM/arch/arm/isa/main.isa -> generated/decoder-g.cc.inc, 
generated/decoder-ns.cc.inc, generated/decode-method.cc.inc, 
generated/decoder.hh, generated/decoder-g.hh.inc, generated/decoder-ns.hh.inc, 
generated/exec-g.cc.inc, generated/exec-ns.cc.inc, generated/decoder.cc, 
generated/inst-constrs-1.cc, generated/inst-constrs-2.cc, 
generated/inst-constrs-3.cc, generated/generic_cpu_exec_1.cc, 
generated/generic_cpu_exec_2.cc, generated/generic_cpu_exec_3.cc, 
generated/generic_cpu_exec_4.cc, generated/generic_cpu_exec_5.cc, 
generated/generic_cpu_exec_6.cc
 [ CXX] ARM/mem/ruby/protocol/Cache_Controller.cc -> .o
 [ CXX] ARM/mem/ruby/protocol/Cache_Wakeup.cc -> .o
 [VER TAGS]  -> ARM/sim/tags.cc
 [ CXX] ARM/sim/tags.cc -> .o
 [ CXX] ARM/arch/arm/generated/inst-constrs-3.cc -> .o
 [ CXX] ARM/arch/arm/generated/inst-constrs-1.cc -> .o
 [ CXX] ARM/arch/arm/generated/inst-constrs-2.cc -> .o
In file included from build/ARM/arch/arm/generated/inst-constrs-3.cc:9:
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr 
ArmISAInst::Aarch64::decodeBranchExcSys(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:90482:12: error: could not 
convert 'ArmISAInst::NopInst(machInst)' from 'ArmISAInst::NopInst' to 
'StaticInstPtr' {aka 'RefCountingPtr'}
90482 | return NopInst(machInst);
  |^
  ||
  |ArmISAInst::NopInst
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr 
ArmISAInst::Aarch64::decodeSmeContigLoadSS(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:99981:26: warning: unused 
variable 'imm' [-Wunused-variable]
99981 | uint64_t imm = (uint64_t) bits(machInst, 3, 0);
  |  ^~~
build/ARM/arch/arm/generated/decoder-ns.cc.inc: In function 'StaticInstPtr 
ArmISAInst::Aarch64::decodeSmeContigStoreSS(ArmISA::ExtMachInst)':
build/ARM/arch/arm/generated/decoder-ns.cc.inc:100042:26: warning: unused 
variable 'imm' [-Wunused-variable]
100042 | uint64_t imm = (uint64_t) bits(machInst, 3, 0);
   |  ^~~
scons: *** [build/ARM/arch/arm/generated/inst-constrs-3.o] Error 1




-邮件原件-
发件人: Pedro Becker via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2022年1月25日 18:16
收件人: gem5-users@gem5.org
抄送: Pedro Becker 
主题: [gem5-users] Re: restore with O3 hang when "bti" instrution meet

Hi Liyuchao, 

I'm assuming you are referring to ARM ISA...
BTI is appearing on your code but it's not implemented. 

"A BTI instruction is used to guard against the execution of instructions that 
are not the intended target of a branch. Outside of a guarded memory region, a 
BTI instruction executes as a NOP. "
(See here: 
https://developer.arm.com/documentation/100076/0100/a64-instruction-set-reference/a64-general-instructions/bti)

My understanding is that if you are not trying to investigate how this guarding 
mechanism works (say, because you are investigating hardware security or 
whatever), you can simply ignore that instruction as if your code is outside of 
a guarded memory region.

So in src/arch/arm/isa/formats/aarch64.isa you can find the bti instruction and 
return a NOP instead of an unimplemented instruction. Something like this:

- return new WarnUnimplemented("bti", machInst);
+ return new NopInst(machInst);

Recompile gem5 and check if it does the trick.
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[gem5-users] restore with O3 hang when "bti" instrution meet

[Liyichao via gem5-users]

Hi All:
 When I use my own filesystem by O3 restore, it will hang when "bti" 
instruction meet. Is this instruction make some error here? My gem5 version is 
v21.0.1.0

309440865500: system.cpu: T0 : 0x7ff7e632ec: stp
60309440865500: system.cpu: T0 : 0x7ff7e632ec. 0 :   addxi_uop   ureg0, sp, #48 
: IntAlu :  D=0x007fe770
60309440865500: system.cpu: T0 : 0x7ff7e632ec. 1 :   strxi_uop   x23, [ureg0] : 
MemWrite :  D=0x007ff7f6f000 A=0x7fe770
60309440865500: system.cpu: T0 : 0x7ff7e632ec. 2 :   strxi_uop   x24, [ureg0, 
#8] : MemWrite :  D=0x007ff7f7 A=0x7fe778
60309440866000: system.cpu: T0 : 0x7ff7e632f0:   bl   
<_kernel_size_le_lo32+549610018496> : IntAlu :  D=0x007ff7e632f4
warn:   instruction 'bti' unimplemented
60309441357500: system.cpu: T0 : 0x7ff7f0b6c0: bti(unimplemented) : 
No_OpClass :
60309441357500: system.cpu: T0 : 0x7ff7f0b6c4:   adrp   x16, #462848  : 
IntAlu :  D=0x007ff7f7c000
60309441357500: system.cpu: T0 : 0x7ff7f0b6c8:   ldrb   w16, [w16, #2287] : 
MemRead :  D=0x0001 A=0x7ff7f7c8ef
60309441357500: system.cpu: T0 : 0x7ff7f0b6cc:   cbz   w16, 
<_kernel_size_le_lo32+549610018520> : IntAlu :

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[gem5-users] Failed to setup KVM memory region on centos7.6 host

[Liyichao via gem5-users]

Hi All:
 I have a problem when I use KVM on aarch64 server with centos 7.6 
while it has no problem on the same aarch64 server with ubuntu18.04/ubuntu20.04.

Gem5 version is v21.2.0.0/v21.1.x.x/v21.0.x.x
Cmd: ./build/ARM/gem5.debug --debug-flags=Kvm ./configs/soc_base/fs.py -n 1 
--kernel=vmlinux-5.3.18-esl --machine-type=VExpress_GEM5_V1 
--disk-image=ubuntu-18.04-arm64-docker.img --mem-channels=2  
--mem-channels-intlv=512 --root=/dev/vda1 --param 
system.realview.gic.gem5_extensions=True 
--bootloader=./system/arm/bootloader/arm64/boot.arm64 --cpu-type=ArmV8KvmCPU  
--mem-size=32GB  --mem-type=SimpleMemory

Use centos7.6:
build/ARM/arch/arm/fs_workload.cc:121: info: Using bootloader at address 0x10
build/ARM/arch/arm/fs_workload.cc:139: info: Using kernel entry physical 
address at 0x8008
build/ARM/arch/arm/linux/fs_workload.cc:97: info: Loading DTB file: 
m5out/system.dtb at address 0x8800
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 8 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0x9675 -> 0x0 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0x9b5d -> 0x400 [size: 
0x4]
  0: system.kvm_vm: Mapping region: 0x0x9475 -> 0x600 [size: 
0x200]
  0: system.kvm_vm: Mapping region: 0x0x9075 -> 0x800 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0x8c75 -> 0xc00 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0x8a75 -> 0x1800 [size: 
0x200]
  0: system.kvm_vm: Mapping region: 0x0x9b5c -> 0x2e00 [size: 
0x8000]
Failed to setup KVM memory region:
build/ARM/cpu/kvm/vm.cc:481: panic: Failed to setup KVM memory region:
Host Address: 0xSize: %ll

Guest Address: 0x   Flags: 0x%x


Use ubuntu20.04:
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: m5out/system.dtb at address 0x8800
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 7 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0xa3887000 -> 0x0 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0xafec4000 -> 0x400 [size: 
0x4]
  0: system.kvm_vm: Mapping region: 0x0x9f887000 -> 0x800 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0x9b887000 -> 0xc00 [size: 
0x400]
  0: system.kvm_vm: Mapping region: 0x0x99887000 -> 0x1800 [size: 
0x200]
  0: system.kvm_vm: Mapping region: 0x0xb121 -> 0x2e00 [size: 
0x8000]
  0: system.kvm_vm: Mapping region: 0x0xfff799887000 -> 0x8000 [size: 
0x8]
info: KVM: Coalesced MMIO disabled by config.
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...


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[gem5-users] isa functionally implementation

[Liyichao via gem5-users]

Hi All:
 I wonder if the semantics of ISA are already implemented in GEM5, but 
whether it actually implements its functionality in the architecture.
For example, the armv8 instruction "ldnp" is defined in the standard that it 
initiates a direct load from the memory and will not be allocated in the cache. 
How do I know whether the ldnp instruction is implemented according to the 
standard function in gem5? Or does gem5 just implement its instruction 
semantics and not really implement its functions?
Are there any tips or guidance on this? Thank you very much.


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[gem5-users] M5OPS problems

[Liyichao via gem5-users]

Hi All:
 I added M5OPS pseudo-instructions to a core computing part of my 
program code, but I now have a problem with M5OPS_RESETSTATS once I execute 
M5OPS_RESETSTATS and then M5OPS_DUMPSTATS. In the dump result, only eight 
system.mem_ctrls statistics are printed (32 mem_ctrls are configured). After 
the GEM5 simulation, the dump result contains 32 system.mem_ctrls statistics. 
If M5OPS_RESETSTATS is not used, the result of multiple dumps is correct.

My gem5 command is :
build/ARM/gem5.fast -d goto_1_m5out/ccopy2.goto ./configs/soc_base/se.py -n 
1 --mem-size=32GB --mem-type=LPDDR5_6400_1x16_BG_BL16 --ruby --cpu-clock=2GHz 
--sys-clock=2GHz --ruby-clock=2GHz --num-hha=4 --ruby-mem-channels=32 
--cpu-type=O3_ARM_1636 
--cmd=/home/l00515693/KSim_LightESL/benchmark/build/ccopy.goto

my gem5 version is v21.0.1.0


Partial Code：

#define M5OPS_RESETSTATS __asm__ __volatile__ ("mov x0, 0; mov x1, 0; .inst 
0XFF000110 | (0x40 << 16);" : : : "x0", "x1");
#define M5OPS_DUMPSTATS __asm__ __volatile__ ("mov x0, 0; mov x1, 0; .inst 
0xFF000110 | (0x41 << 16);" : : : "x0", "x1");
#define M5OPS_DUMP_RESET_STATS __asm__ __volatile__ ("mov x0, 0; mov x1, 0; 
.inst 0xFF000110 | (0x42 << 16);" : : : "x0", "x1");
#define M5OPS_CHECKPOINT __asm__ __volatile__ ("mov x0, 0; mov x1, 0; .inst 
0xFF000110 | (0x43 << 16);" : : : "x0", "x1");
#define M5OPS_EXIT __asm__ __volatile__ ("mov x0, 0; mov x1, 0; .inst 
0xFF000110 | (0x21 << 16);" : : : "x0", "x1");

…

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[gem5-users] 答复: Re: CHI prefetcher on V21

[Liyichao via gem5-users]

OK, let me create a jira issue now:)

-邮件原件-
发件人: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2021年11月10日 19:51
收件人: gem5-users@gem5.org
抄送: Gabriel Busnot 
主题: [gem5-users] Re: CHI prefetcher on V21

Hi,

Prefetch implementation seems unchanged and incomplete since the first release 
of the CHI protocol. In particular, the notifyPf* functions in 
CHI-cache-funcs.sm are still all empty. I am also not aware of any related open 
Jira issues.

Regards,
Gabriel
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[gem5-users] CHI prefetcher on V21

[Liyichao via gem5-users]

Hi All:
 Does latest GEM5 version support prefetcher on Ruby CHI now?

On v21.0.1.0, I think the prefetcher on Ruby CHI does not support well, 
isn't it?

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[gem5-users] Re: m5 pesudo

[Liyichao via gem5-users]

Thanks for your reply.

But when I work on the Gem5 v20.0.0.3，m5 ―addr exit doesn‘t take effect on 
O3，and it just takes affect on KVM in fs.

So on v21.0.1.0， how can I let the m5 exit only takes effect on KVM and does 
not take effect on O3？






李翼超 Li Yichao
Mobile：+86-15858232899
Email：liyic...@huawei.com<mailto:liyic...@huawei.com>


发件人： Jason Lowe-Powermailto:ja...@lowepower.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] m5 pesudo
时间： 2021-11-01 22:56:48

Hello,

The m5 magic operations (either via magic instructions or addresses) will work 
with all CPU models.

Cheers,
Jason

On Sat, Oct 30, 2021 at 8:31 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 Does “m5 --addr 0x1001 exit” take effect in the O3 system?

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[gem5-users] m5 pesudo

[Liyichao via gem5-users]

Hi All:
 Does "m5 --addr 0x1001 exit" take effect in the O3 system?

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[gem5-users] How to config autologin in ubuntu-18.04-arm64-docker.img from GEM5 website

[Liyichao via gem5-users]

Hi All:
 I want to launch gem5 with fs.py, and I don't know the default root 
password of ubuntu-18.04-arm64-docker.img, so how can I config auto-login with 
root user and without password need? Anyone has experience on it?

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[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

[Liyichao via gem5-users]

That’s exactly what you said.

Another problem in system test, if I follow the gem5 system test, there are 
some failed case like this:

Logging call to command: ./build/ARM/gem5.opt -d /tmp/gem5outes8xx6ry -re 
/home/l00515693/KSim_LightESL/tests/gem5/cpu_tests/run.py --cpu=AtomicSimpleCPU 
./tests/gem5/resources/cpu_tests/arm/Bubblesort
Starting Test Suite: cpu_test_AtomicSimpleCPU_Bubblesort-ARM-aarch64-opt
Starting Test Case: cpu_test_AtomicSimpleCPU_Bubblesort-ARM-aarch64-opt
Redirecting stdout to /tmp/gem5outes8xx6ry/simout
Redirecting stderr to /tmp/gem5outes8xx6ry/simerr
Redirecting stdout to /tmp/gem5outes8xx6ry/simout
Redirecting stderr to /tmp/gem5outes8xx6ry/simerr
Test: cpu_test_AtomicSimpleCPU_Bubblesort-ARM-aarch64-opt Failed
Starting Test Case: 
cpu_test_AtomicSimpleCPU_Bubblesort-ARM-aarch64-opt-MatchStdout
Logging call to command: diff /tmp/gem5outes8xx6ry/simout 
/home/l00515693/KSim_LightESL/tests/gem5/cpu_tests/ref/Bubblesort
1a2
> -5

The err output is:
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
panic: panic condition fd < 0 occurred: Failed to open file .
Memory Usage: 635344 KBytes
Program aborted at tick 0


But when I use se.py to execute 
“./tests/gem5/resources/cpu_tests/arm/Bubblesort”, that’s fine:

root@ubuntu-kunpeng920-4: ./build/ARM/gem5.opt ./configs/soc_base/se.py -n 1 
--mem-size=32GB --cpu-type=AtomicSimpleCPU 
--cmd=./tests/gem5/resources/cpu_tests/arm/Bubblesort
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.1.0
gem5 compiled Oct 29 2021 10:58:09
gem5 started Oct 30 2021 14:40:26
gem5 executing on ubuntu-kunpeng920-4, pid 156173
command line: build/ARM/gem5.opt ./configs/soc_base/se.py -n 1 --mem-size=32GB 
--cpu-type=AtomicSimpleCPU --cmd=./tests/gem5/resources/cpu_tests/arm/Bubblesort

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7032
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
-5

发件人: Gabe Black [mailto:gabe.bl...@gmail.com]
发送时间: 2021年10月30日 14:06
收件人: Liyichao 
抄送: gem5 users mailing list 
主题: Re: [gem5-users] Re: How to enable KVM unitest on ARM server

I found it in the revision history. If you're building the "NULL" target, you 
should not set USE_KVM to true. If you do, then it will try to verify that the 
simulated architecture and the host architecture is the same, which is the only 
time KVM will work. This "Info" print out is just telling you that there's a 
mismatch between no ISA and the ARM ISA, and that KVM is not available.

In general, unless it says "error", it's not an error and you don't need to be 
overly concerned about it.

Gabe

On Fri, Oct 29, 2021 at 9:35 PM Liyichao 
mailto:liyic...@huawei.com>> wrote:
If I build gem5.opt of ARM on X86 server, the print “Info: KVM for null not 
supported on arm host.” will also be presented

发件人: Gabe Black via gem5-users 
[mailto:gem5-users@gem5.org<mailto:gem5-users@gem5.org>]
发送时间: 2021年10月29日 11:43
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Gabe Black mailto:gabe.bl...@gmail.com>>
主题: [gem5-users] Re: How to enable KVM unitest on ARM server

Hi, I just grepped through all of gem5's source, and, even ignoring 
capitalization, the string "KVM for" does not appear outside of a couple 
comments. I have no idea where that string is coming from, but it doesn't seem 
to be from gem5 itself.

Gabe

On Thu, Oct 28, 2021 at 8:04 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
My GEM5 V21.1.0.2 running on aarch64 server, but when I compile 
bitunion.test.opt, the compilation print will show “Info: KVM for null not 
supported on arm host.”

scons build/NULL/base/bitunion.test.opt -j120
scons: Reading SConscript files ...
Checking for linker -Wl,--as-needed support... (cached) yes
Warning: While checking protoc version: [Errno 2] No such file or directory: 
'protoc'
Warning: Protocol buffer compiler (protoc) not found.
 Please install protobuf-compiler for tracing support.
Checking for compiler -gz support... (cached) yes
Checking for linker -gz support... (cached) yes
Info: Using Python config: python3-config
Checking

[gem5-users] 答复: Re: How to enable KVM unitest on ARM server

[Liyichao via gem5-users]

If I build gem5.opt of ARM on X86 server, the print “Info: KVM for null not 
supported on arm host.” will also be presented

发件人: Gabe Black via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2021年10月29日 11:43
收件人: gem5 users mailing list 
抄送: Gabe Black 
主题: [gem5-users] Re: How to enable KVM unitest on ARM server

Hi, I just grepped through all of gem5's source, and, even ignoring 
capitalization, the string "KVM for" does not appear outside of a couple 
comments. I have no idea where that string is coming from, but it doesn't seem 
to be from gem5 itself.

Gabe

On Thu, Oct 28, 2021 at 8:04 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
My GEM5 V21.1.0.2 running on aarch64 server, but when I compile 
bitunion.test.opt, the compilation print will show “Info: KVM for null not 
supported on arm host.”

scons build/NULL/base/bitunion.test.opt -j120
scons: Reading SConscript files ...
Checking for linker -Wl,--as-needed support... (cached) yes
Warning: While checking protoc version: [Errno 2] No such file or directory: 
'protoc'
Warning: Protocol buffer compiler (protoc) not found.
 Please install protobuf-compiler for tracing support.
Checking for compiler -gz support... (cached) yes
Checking for linker -gz support... (cached) yes
Info: Using Python config: python3-config
Checking for C header file Python.h... (cached) yes
Checking for C library python3.8... (cached) yes
Checking for C library crypt... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking Python version... (cached) 3.8.5
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file valgrind/valgrind.h... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None... 
(cached) no
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt... 
(cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for char temp; backtrace_symbols_fd((void *), 0, 0) in C library 
None... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file png.h... (cached) yes
Checking for C header file linux/kvm.h... (cached) yes
Checking for C header file linux/if_tun.h... (cached) yes
Checking for member exclude_host in struct perf_event_attr...(cached) yes
Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
Warning: Couldn't find any HDF5 C++ libraries. Disabling HDF5 support.
Checking whether __i386__ is declared... (cached) no
Checking whether __x86_64__ is declared... (cached) no
Warning: Unrecognized architecture for systemc.
Building in /home/l00515693/KSim_LightESL/build/NULL
Variables file /home/l00515693/KSim_LightESL/build/variables/NULL not found,
  using defaults in /home/l00515693/KSim_LightESL/build_opts/NULL
Info: KVM for null not supported on arm host.
scons: done reading SConscript files.
scons: Building targets ...


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[gem5-users] How to enable KVM unitest on ARM server

[Liyichao via gem5-users]

Hi All:
My GEM5 V21.1.0.2 running on aarch64 server, but when I compile 
bitunion.test.opt, the compilation print will show "Info: KVM for null not 
supported on arm host."

scons build/NULL/base/bitunion.test.opt -j120
scons: Reading SConscript files ...
Checking for linker -Wl,--as-needed support... (cached) yes
Warning: While checking protoc version: [Errno 2] No such file or directory: 
'protoc'
Warning: Protocol buffer compiler (protoc) not found.
 Please install protobuf-compiler for tracing support.
Checking for compiler -gz support... (cached) yes
Checking for linker -gz support... (cached) yes
Info: Using Python config: python3-config
Checking for C header file Python.h... (cached) yes
Checking for C library python3.8... (cached) yes
Checking for C library crypt... (cached) yes
Checking for C library pthread... (cached) yes
Checking for C library dl... (cached) yes
Checking for C library util... (cached) yes
Checking for C library m... (cached) yes
Checking Python version... (cached) 3.8.5
Checking for accept(0,0,0) in C++ library None... (cached) yes
Checking for zlibVersion() in C++ library z... (cached) yes
Checking for C header file valgrind/valgrind.h... (cached) no
Checking for clock_nanosleep(0,0,NULL,NULL) in C library None... (cached) yes
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library None... 
(cached) no
Checking for timer_create(CLOCK_MONOTONIC, NULL, NULL) in C library rt... 
(cached) yes
Checking for C library tcmalloc... (cached) yes
Checking for char temp; backtrace_symbols_fd((void *), 0, 0) in C library 
None... (cached) yes
Checking for C header file fenv.h... (cached) yes
Checking for C header file png.h... (cached) yes
Checking for C header file linux/kvm.h... (cached) yes
Checking for C header file linux/if_tun.h... (cached) yes
Checking for member exclude_host in struct perf_event_attr...(cached) yes
Checking for H5Fcreate("", 0, 0, 0) in C library hdf5... (cached) no
Warning: Couldn't find any HDF5 C++ libraries. Disabling HDF5 support.
Checking whether __i386__ is declared... (cached) no
Checking whether __x86_64__ is declared... (cached) no
Warning: Unrecognized architecture for systemc.
Building in /home/l00515693/KSim_LightESL/build/NULL
Variables file /home/l00515693/KSim_LightESL/build/variables/NULL not found,
  using defaults in /home/l00515693/KSim_LightESL/build_opts/NULL
Info: KVM for null not supported on arm host.
scons: done reading SConscript files.
scons: Building targets ...


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[gem5-users] 答复: explaination about command_window in MemCtrl.py

[Liyichao via gem5-users]

Hi all:
 Any one knows?

Best regards
Li Yichao

发件人: Liyichao
发送时间: 2021年10月13日 15:51
收件人: gem5 users mailing list 
抄送: wuhailin 
主题: explaination about command_window in MemCtrl.py

Hi all:
Now I’m working on researching LPDDR5 feature on GEM5.
But I do not clearly know the parameter ”command_window“ in MemCtrl.py, and why 
the default value set to 10ns.

In a workshop vedio for “Memory controller for LPDDR5”, there is a formula 
“maxCommandsPerBurst = burst_length / beats_per_clock”, but I have found in 
code in v21, there is a formula “maxCommandPerWindow = command_window / tCK” in 
MemInterface::setCtrl, what is the difference between “maxCommandsPerBurst” and 
“maxCommandPerWindow”?



Best regards
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[gem5-users] explaination about command_window in MemCtrl.py

[Liyichao via gem5-users]

Hi all:
Now I'm working on researching LPDDR5 feature on GEM5.
But I do not clearly know the parameter "command_window" in MemCtrl.py, and why 
the default value set to 10ns.

In a workshop vedio for "Memory controller for LPDDR5", there is a formula 
"maxCommandsPerBurst = burst_length / beats_per_clock", but I have found in 
code in v21, there is a formula "maxCommandPerWindow = command_window / tCK" in 
MemInterface::setCtrl, what is the difference between "maxCommandsPerBurst" and 
"maxCommandPerWindow"?



Best regards
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[gem5-users] 答复: gem5 v21.1 released!

[Liyichao via gem5-users]

Hi Bruce:
 I see the GEM5 resource mentioned on the GEM5 official website. Are 
all the resources provided in the GEM5 resource based on x86? For example, 
SPEC2017, are there AARCH64-based versions available for these resources?

Best regards,
Liyichao


发件人: Bobby Bruce via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2021年7月29日 8:51
收件人: gem5 Developer List ; gem5 users mailing list 
; gem5-annou...@gem5.org
抄送: Bobby Bruce 
主题: [gem5-users] gem5 v21.1 released!

Dear all,

gem5 v21.1.0.0 has officially been released.

You can use  `git clone 
https://gem5.googlesource.com/public/gem5`
 to obtain the latest release and consult the RELEASE-NOTES.md for a high-level 
overview of significant changes: 
https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md

A special thank you to all our contributors for making this possible. We had 
780 commits from 48 unique contributors over the past few months. It's quite an 
achievement. We look forward to your continued support in our v21.2 release!

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net
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[gem5-users] instrutions statistics

[Liyichao via gem5-users]

Hi Jason:
 Previously, I have seen examples about the increase of kernel-mode 
instructions and user-mode instructions on the GEM5 official website. However, 
I cannot find them on the official website. The web page has been updated. If 
yes, where can I refer to these examples?

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[gem5-users] add an instrution statistics in stats.txt

[Liyichao via gem5-users]

Hi All:

How to add an instruction statistics item to distinguish the number of 
kernel-mode instructions and user-mode instructions?


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[gem5-users] scheduleInstStop use under aarch64 KVM mode

[Liyichao via gem5-users]

Hi All:

 The scheduleInstStop function is used to specify the number of 
instructions to stop the emulation. Currently, my GEM5 emulation under aarch64 
KVM mode is to start 32 cores and then execute an identical binary on each 
core. Then I use the scheduleInstStop function to specify the last core (cpu31) 
to end the simulation of the entire system according to the number of 
instructions I input. For example, I specify cpu31 to emulate 50 million 
instructions, but I understand that the KVM uses the instruction set of the CPU 
on the host side to run. If KVM is used in a multi-core emulation environment, 
will the number of instructions be inaccurate due to kernel-mode thread 
contention related to KVM on the host? Can the scheduleInstStop function be 
modified so that it stops only based on user-mode instructions, and if so, how?


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[gem5-users] Re: 答复: Re: SPEC2017 in FS mode

[Liyichao via gem5-users]

Thank you for your reply.

Any plans to support for aarch64？







发件人： Hoa Nguyenmailto:hoangu...@ucdavis.edu>>
收件人： Liyichaomailto:liyic...@huawei.com>>
抄送： gem5 users mailing listmailto:gem5-users@gem5.org>>
主题： Re: 答复: [gem5-users] Re: SPEC2017 in FS mode
时间： 2021-05-24 19:12:57

Hi Liyichao,

Currently, the spec-2017 image only works with X86.

Regards,
Hoa Nguyen

On 5/20/21, Liyichao  wrote:
> Hi Hoa:
>Is the spec-2017 img just for X86?
>
>  Does it support for AARCH64?Does it support for running with KVM+O3?
>
>
> -邮件原件-
> 发件人: Hoa Nguyen via gem5-users [mailto:gem5-users@gem5.org]
> 发送时间: 2021年5月19日 19:09
> 收件人: gem5 users mailing list 
> 抄送: Hoa Nguyen 
> 主题: [gem5-users] Re: SPEC2017 in FS mode
>
> Hi Victor,
>
> I'm not sure what caused the errors of building the spec benchmarks.
>
> Also, I'm not sure how to prevent the vm from being closed after the builds
> fail. However, there are a few steps can be done to exterminate the disk
> image after the builds fail:
> - In the file src/spec-2017/disk-image/spec-2017/install-spec2017.sh,
> the last line "rm -f /home/gem5/spec2017/result/*" should be removed to keep
> the log generated by spec during benchmark compilation time.
> - When running packer, you can run "./packer build -on-error=abort
> spec-2017/spec-2017.json" to keep the disk image if the disk image building
> process fails.
> - After that, you can mount the disk image and check the log file generated
> by spec.
>
> packer fails due to "output directory already exists". In this case, you'll
> need to remove the "spec-2017/spec-2017-image" folder before starting packer
> again.
>
> Regards,
> Hoa Nguyen
>
> On 5/17/21, Victor Kariofillis via gem5-users  wrote:
>> Hi,
>>
>> I've tried running the SPEC2017 benchmarks in FS mode of gem5 using
>> the instructions/files provided by the gem5 resources page.
>>
>> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stabl
>> e/src/spec-2017
>>
>> I've also followed the step by step instructions in the git repo for
>> gem5-art.
>>
>> https://github.com/darchr/gem5art-experiments/blob/master/README.md
>>
>> Everything works as intended until the benchmarks are supposed to be
>> built.
>> All of them fail with one of the two following errors:
>>
>> 1) Error with make!
>> 2) Error with fdo_make_pass1!
>>
>> First of all, why is this happening? Secondly, the vm closes after the
>> builds fail. I don't have the opportunity to check the make.out files
>> that have more information about the errors. Is there a way to prevent
>> the connection from closing or reopening it again? Running it again
>> with packer fails due to the directory existing already.
>>
>> I'd appreciate any help,
>> Victor
>>
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> to gem5-users-le...@gem5.org
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[gem5-users] Re: Compiling code to run in se mode

[Liyichao via gem5-users]

I think you have to compile with -static in se mode.








发件人： krishnan gosakan via 
gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： krishnan 
gosakanmailto:krishnan.gosa...@gmail.com>>
主题： [gem5-users] Compiling code to run in se mode
时间： 2021-05-24 00:48:11

Hi all,
I hope all are doing well. I just want to know how to compile c code using gcc 
to run it in se mode of gem5. I tried compiling a simple hello world code which 
is exactly similar to the code available in tests/test-progs/hello/src
I compiled it as gcc -o hello hello.c -m32
The above command compiles as 32 bit application.
It doesn't work as expected.
I have attached my code in this mail.

Output:
info: Running on GenuineIntel
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled May 23 2021 20:07:20
gem5 started May 23 2021 22:14:40
gem5 executing on cryptenious, pid 17476
command line: ./build/X86/gem5.opt configs/example/se.py -c ./hello --caches 
--l2cache --mem-size 4096MB --sys-clock 4GHz --l1d_size 32kB --l1i_size 32kB 
--l2_size 256kB --l3_size 8192kB --IcebergEnabled

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (4096 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
Exiting @ tick 3565000 because exiting with last active thread context

The print statement is not working Any help would be highly appreciated.
Thanks in advance.
--
Regards,
Krishnan.
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[gem5-users] Re: Simulation aborts when number of instructions increases due to LSQUnit ERROR

[Liyichao via gem5-users]

I also have met this problem before on v20.0.0.3，for any other test 
binaries，and have no idea about it.
发件人： VEDIKA JITENDRA KULKARNI via 
gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5-usersmailto:gem5-users@gem5.org>>
抄送： VEDIKA JITENDRA KULKARNImailto:ved...@iitg.ac.in>>
主题： [gem5-users] Simulation aborts when number of instructions increases due to 
LSQUnit ERROR
时间： 2021-05-22 15:29:30

Hello,

I want to run gem5 simulation for 40,00,000 insts. It works when benchmarks like
namd and gromacs are used, however I want to use soplex, leslie3d etc (high 
MPKI).

Any workload configuration works for 10,00,000 insts successfully. However, 
when I give
40,00,000 insts it shows the following error:

gem5.opt: build/ALPHA/cpu/o3/lsq_unit.hh:621: Fault 
LSQUnit::read(LSQUnit::LSQRequest*, int)
[with Impl = O3CPUImpl; Fault = std::shared_ptr; 
LSQUnit::LSQRequest = LSQ::LSQRequest]:
Assertion `!load_inst->isExecuted()' failed.

I came across a mail-archive discussing the same problem, but couldn't find a 
solution there. Has anyone
resolved this issue?

I am working with the following configuration

Arch = ALPHA

Number of CPUs = 16, CPU Type = DerivO3CPU

System Clock = 2GHz, Topology = Mesh_XY

L1-Icache = 16kB, 4-way associative

L1-Dcache = 16kB, 4-way associative

L2-Cache = 123kB, 8-way associative

Memory Size = 8GB

Memory System = Ruby, Coherence Protocol = MESI Two Level, Network = Garnet2.0

Thank you,
Vedika.

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[gem5-users] 答复: Re: SPEC2017 in FS mode

[Liyichao via gem5-users]

Hi Hoa:
Is the spec-2017 img just for X86?

 Does it support for AARCH64?Does it support for running with KVM+O3?


-邮件原件-
发件人: Hoa Nguyen via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2021年5月19日 19:09
收件人: gem5 users mailing list 
抄送: Hoa Nguyen 
主题: [gem5-users] Re: SPEC2017 in FS mode

Hi Victor,

I'm not sure what caused the errors of building the spec benchmarks.

Also, I'm not sure how to prevent the vm from being closed after the builds 
fail. However, there are a few steps can be done to exterminate the disk image 
after the builds fail:
- In the file src/spec-2017/disk-image/spec-2017/install-spec2017.sh,
the last line "rm -f /home/gem5/spec2017/result/*" should be removed to keep 
the log generated by spec during benchmark compilation time.
- When running packer, you can run "./packer build -on-error=abort 
spec-2017/spec-2017.json" to keep the disk image if the disk image building 
process fails.
- After that, you can mount the disk image and check the log file generated by 
spec.

packer fails due to "output directory already exists". In this case, you'll 
need to remove the "spec-2017/spec-2017-image" folder before starting packer 
again.

Regards,
Hoa Nguyen

On 5/17/21, Victor Kariofillis via gem5-users  wrote:
> Hi,
>
> I've tried running the SPEC2017 benchmarks in FS mode of gem5 using 
> the instructions/files provided by the gem5 resources page.
>
> https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stabl
> e/src/spec-2017
>
> I've also followed the step by step instructions in the git repo for 
> gem5-art.
>
> https://github.com/darchr/gem5art-experiments/blob/master/README.md
>
> Everything works as intended until the benchmarks are supposed to be built.
> All of them fail with one of the two following errors:
>
> 1) Error with make!
> 2) Error with fdo_make_pass1!
>
> First of all, why is this happening? Secondly, the vm closes after the 
> builds fail. I don't have the opportunity to check the make.out files 
> that have more information about the errors. Is there a way to prevent 
> the connection from closing or reopening it again? Running it again 
> with packer fails due to the directory existing already.
>
> I'd appreciate any help,
> Victor
>
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[gem5-users] test in Atomic is OK but in KVM is panic

[Liyichao via gem5-users]

Hi All:
 I have tested my simple program, if I use AtomicSimple CPU, the result 
is OK, but if I use X86KvmCpu, the result panic:


My simple program source code is:
#include 

int main()
{
unsigned int a = 0;
unsigned long i;
for (i=0;i<1000;i++)
a++;
printf("charlie, charlie, charliel\n");
return 0;
}


 root@ubuntu:/home/l00515693/whl/gem5# ./build/X86/gem5.opt 
configs/example/se.py --cpu-type=AtomicSimpleCPU 
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c 
./test
warn: CheckedInt already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
warn: Enum already exists in allParams. This may be caused by the Python 2.7 
compatibility layer.
warn: ScopedEnum already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 20.0.0.3
gem5 compiled May 13 2021 00:01:52
gem5 started May 14 2021 13:04:12
gem5 executing on ubuntu, pid 9926
command line: ./build/X86/gem5.opt configs/example/se.py 
--cpu-type=AtomicSimpleCPU --checkpoint-dir=/home/l00515693/whl/gem5/m5out/ 
--mem-size=2GB --num-cpus=1 -c ./test

Global frequency set at 1 ticks per second

warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (2048 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
warn: ignoring syscall access(...)
charlie, charlie, charliel




root@ubuntu:/home/l00515693/whl/gem5#
root@ubuntu:/home/l00515693/whl/gem5# ./build/X86/gem5.opt 
configs/example/se.py --cpu-type=X86KvmCPU 
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c 
./test

warn: CheckedInt already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
warn: Enum already exists in allParams. This may be caused by the Python 2.7 
compatibility layer.
warn: ScopedEnum already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 20.0.0.3
gem5 compiled May 13 2021 00:01:52
gem5 started May 14 2021 13:07:56
gem5 executing on ubuntu, pid 14352
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--checkpoint-dir=/home/l00515693/whl/gem5/m5out/ --mem-size=2GB --num-cpus=1 -c 
./test

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (2048 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
warn: CoherentXBar system.membus has no snooping ports attached!
 REAL SIMULATION 
info: KVM: Coalesced MMIO disabled by config.
warn: x86 cpuid family 0x: unimplemented function 2
warn: x86 cpuid family 0x: unimplemented function 3
warn: x86 cpuid family 0x: unimplemented function 4
warn: x86 cpuid family 0x: unimplemented function 5
warn: x86 cpuid family 0x: unimplemented function 6
info: Entering event queue @ 0.  Starting simulation...
warn: kvm-x86: MSR (0x3a) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0xd90) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x48) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x12) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x11) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d01) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d00) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4000) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4001) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4020) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4021) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4100) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4101) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4102) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4103) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4104) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4105) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4003) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4002) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4010) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4080) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x40b0) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4073) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d02) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d03) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x4b564d04) unsupported by gem5. Skipping.
warn: kvm-x86: MSR (0x3b) unsupported by gem5. Skipping.
warn: kvm-x86: MSR 

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

M: Failed to create virtual CPU
Memory Usage: 33838804 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: 
Failed to create virtual CPU”.


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm

   My GEM5 version is master(v21.0.0.0), 
ea7d012c00e857ef999b88a8ec2bde801a1f


./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c "./test"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.0.0
gem5 compiled May 10 2021 03:39:51
gem5 started May 10 2021 03:57:48
gem5 executing on ubuntu, pid 112188
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
panic: KVM: Failed to create virtual CPU
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[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: 
Failed to create virtual CPU”.


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm

   My GEM5 version is master(v21.0.0.0), 
ea7d012c00e857ef999b88a8ec2bde801a1f


./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c "./test"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.0.0
gem5 compiled May 10 2021 03:39:51
gem5 started May 10 2021 03:57:48
gem5 executing on ubuntu, pid 112188
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
panic: KVM: Failed to create virtual CPU
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[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

Hi Jason:

 I find that if I set �Cmem-size < 4GB, there is no error, but when I 
set �Cmem-size=4GB or more than 4GB, the error occurred.



发件人: Liyichao
发送时间: 2021年5月12日 0:26
收件人: Jason Lowe-Power 
抄送: gem5 users mailing list 
主题: RE: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hi Jason：
 I make two tests：

1. I write a test code follow "open /dev/kvm” "create vm” "create vcpu”，it 
has no error；

2.  I put allocate pmem and create vcpu in create_vm function in gem5，not 
outside create_vm，it has no error.


so I suspect if the allocate pmem function in gem5 source has any wrongs？
发件人： Jason Lowe-Powermailto:ja...@lowepower.com>>
收件人： Liyichaomailto:liyic...@huawei.com>>
抄送： gem5 users mailing listmailto:gem5-users@gem5.org>>
主题： Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
时间： 2021-05-11 22:47:19

Hello,

I wonder if you have a maximum number of vcpus set on your host system. 
Otherwise, I can't think of any specific limitation to creating vcpus.

Cheers,
Jason

On Tue, May 11, 2021 at 2:36 AM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Hi Jason:

 I use strace to follow the call stack, I find that the ioctl() with 
KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist.

   ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File exists)


发件人: Liyichao
发送时间: 2021年5月11日 12:54
收件人: 'Jason Lowe-Power' mailto:ja...@lowepower.com>>; gem5 
users mailing list mailto:gem5-users@gem5.org>>
主题: 答复: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hi Jason:
 I have add a DPRINTF in line 559 of vm.cc , it showed “  0: 
system.kvm_vm: *debug vcpuID is 0”

 Any KVM use limitations in X86?


gem5 version 21.0.0.0
gem5 compiled May 11 2021 01:04:20
gem5 started May 11 2021 01:09:26
gem5 executing on ubuntu, pid 53534
command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py 
--cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches 
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB 
--num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
  0: system.cpu: vcpuID is 0
0: system.remote_gdb: listening for remote gdb on port 7000
  0: system.cpu: ActivateContext 0
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 1 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size: 
0x8]
  0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
  0: system.cpu: charlie, vcpuID is 0
  0: system.kvm_vm: vmFD is 5, p1 is 0
  0: system.kvm_vm: *debug vcpuID is 0
panic: KVM: Failed to create virtual CPU
Memory Usage: 33838804 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it s

[gem5-users] Re: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

Hi Jason：
 I make two tests：

1. I write a test code follow "open /dev/kvm” "create vm” "create vcpu”，it 
has no error；

2.  I put allocate pmem and create vcpu in create_vm function in gem5，not 
outside create_vm，it has no error.


so I suspect if the allocate pmem function in gem5 source has any wrongs？
发件人： Jason Lowe-Powermailto:ja...@lowepower.com>>
收件人： Liyichaomailto:liyic...@huawei.com>>
抄送： gem5 users mailing listmailto:gem5-users@gem5.org>>
主题： Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch
时间： 2021-05-11 22:47:19

Hello,

I wonder if you have a maximum number of vcpus set on your host system. 
Otherwise, I can't think of any specific limitation to creating vcpus.

Cheers,
Jason

On Tue, May 11, 2021 at 2:36 AM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Hi Jason:

 I use strace to follow the call stack, I find that the ioctl() with 
KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist.

   ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File exists)


发件人: Liyichao
发送时间: 2021年5月11日 12:54
收件人: 'Jason Lowe-Power' mailto:ja...@lowepower.com>>; gem5 
users mailing list mailto:gem5-users@gem5.org>>
主题: 答复: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hi Jason:
 I have add a DPRINTF in line 559 of vm.cc , it showed “  0: 
system.kvm_vm: *debug vcpuID is 0”

 Any KVM use limitations in X86?


gem5 version 21.0.0.0
gem5 compiled May 11 2021 01:04:20
gem5 started May 11 2021 01:09:26
gem5 executing on ubuntu, pid 53534
command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py 
--cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches 
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB 
--num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
  0: system.cpu: vcpuID is 0
0: system.remote_gdb: listening for remote gdb on port 7000
  0: system.cpu: ActivateContext 0
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 1 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size: 
0x8]
  0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
  0: system.cpu: charlie, vcpuID is 0
  0: system.kvm_vm: vmFD is 5, p1 is 0
  0: system.kvm_vm: *debug vcpuID is 0
panic: KVM: Failed to create virtual CPU
Memory Usage: 33838804 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: 
Failed to create virtual CPU”.


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root ro

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

Hi Jason:

 I use strace to follow the call stack, I find that the ioctl() with 
KVM_CREATE_VCPU returned EEXIST errno, this means the vCPU exist.

   ioctl(5, KVM_CREATE_VCPU, 2)= -1 EEXIST (File exists)


发件人: Liyichao
发送时间: 2021年5月11日 12:54
收件人: 'Jason Lowe-Power' ; gem5 users mailing list 

主题: 答复: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hi Jason:
 I have add a DPRINTF in line 559 of vm.cc , it showed “  0: 
system.kvm_vm: *debug vcpuID is 0”

 Any KVM use limitations in X86?


gem5 version 21.0.0.0
gem5 compiled May 11 2021 01:04:20
gem5 started May 11 2021 01:09:26
gem5 executing on ubuntu, pid 53534
command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py 
--cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches 
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB 
--num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
  0: system.cpu: vcpuID is 0
0: system.remote_gdb: listening for remote gdb on port 7000
  0: system.cpu: ActivateContext 0
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 1 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size: 
0x8]
  0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
  0: system.cpu: charlie, vcpuID is 0
  0: system.kvm_vm: vmFD is 5, p1 is 0
  0: system.kvm_vm: *debug vcpuID is 0
panic: KVM: Failed to create virtual CPU
Memory Usage: 33838804 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: 
Failed to create virtual CPU”.


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm

   My GEM5 version is master(v21.0.0.0), 
ea7d012c00e857ef999b88a8ec2bde801a1f


./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c "./test"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.0.0
gem5 compiled May 10 2021 03:39:51
gem5 started May 10 2021 03:57:48
gem5 executing on ubuntu, pid 112188
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is n

[gem5-users] 答复: Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

Hi Jason:
 I have add a DPRINTF in line 559 of vm.cc , it showed “  0: 
system.kvm_vm: *debug vcpuID is 0”

 Any KVM use limitations in X86?


gem5 version 21.0.0.0
gem5 compiled May 11 2021 01:04:20
gem5 started May 11 2021 01:09:26
gem5 executing on ubuntu, pid 53534
command line: ./build/X86/gem5.opt --debug-flags=Kvm configs/example/se.py 
--cpu-type=X86KvmCPU --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches 
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB 
--num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
  0: system.cpu: vcpuID is 0
0: system.remote_gdb: listening for remote gdb on port 7000
  0: system.cpu: ActivateContext 0
 REAL SIMULATION 
  0: system.kvm_vm: Mapping 1 memory region(s)
  0: system.kvm_vm: Mapping region: 0x0x7f0b007b7000 -> 0x0 [size: 
0x8]
  0: system.kvm_vm: vmFD is 5, p1 is 140724538190576
  0: system.cpu: charlie, vcpuID is 0
  0: system.kvm_vm: vmFD is 5, p1 is 0
  0: system.kvm_vm: *debug vcpuID is 0
panic: KVM: Failed to create virtual CPU
Memory Usage: 33838804 KBytes
Program aborted at tick 0
--- BEGIN LIBC BACKTRACE ---
./build/X86/gem5.opt(_Z15print_backtracev+0x2c)[0x5622a4c15f8c]
./build/X86/gem5.opt(_Z12abortHandleri+0x4a)[0x5622a4c30b6a]
/lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f1305ea6980]
/lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f1304430fb7]
/lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f1304432921]
./build/X86/gem5.opt(+0x6e5cef)[0x5622a3f20cef]
./build/X86/gem5.opt(_ZN5KvmVM10createVCPUEl+0x9ff)[0x5622a4953b8f]
./build/X86/gem5.opt(_ZN10BaseKvmCPU7startupEv+0x9e)[0x5622a494bc8e]
./build/X86/gem5.opt(_ZN9X86KvmCPU7startupEv+0x9)[0x5622a4969509]



发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年5月10日 23:56
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: Re: [gem5-users] Fail to bootup with KVM in se.py on X86 arch

Hmm, I don't immediately know what's going wrong. I would extend the panic on 
line 559 of vm.cc to also print the error code number so you can look it up. I 
believe you can use `errno` like normal after calling `ioctl`. For instance, 
you could add `strerror(errno)` to the panic.

Cheers,
Jason


On Mon, May 10, 2021 at 12:49 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic “KVM: 
Failed to create virtual CPU”.


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm

   My GEM5 version is master(v21.0.0.0), 
ea7d012c00e857ef999b88a8ec2bde801a1f


./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c "./test"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.0.0
gem5 compiled May 10 2021 03:39:51
gem5 started May 10 2021 03:57:48
gem5 executing on ubuntu, pid 112188
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `m

[gem5-users] Fail to bootup with KVM in se.py on X86 arch

[Liyichao via gem5-users]

Hi All:
 I use KVM CPU in se mode on X86 arch, but it showed a panic "KVM: 
Failed to create virtual CPU".


My host is X86 server of Intel 6148 and it can support kvm:
lsmod |grep kvm
kvm_intel 172032  0
kvm   548864  1 kvm_intel
irqbypass  16384  1 kvm

ll /dev/kvm
crwxrwxrwx 1 root root 10, 232 Feb 16 20:40 /dev/kvm

   My GEM5 version is master(v21.0.0.0), 
ea7d012c00e857ef999b88a8ec2bde801a1f


./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c "./test"
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 21.0.0.0
gem5 compiled May 10 2021 03:39:51
gem5 started May 10 2021 03:57:48
gem5 executing on ubuntu, pid 112188
command line: ./build/X86/gem5.opt configs/example/se.py --cpu-type=X86KvmCPU 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --num-cpus=1 -I 5000 -c ./test

warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: tol2bus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
 REAL SIMULATION 
panic: KVM: Failed to create virtual CPU
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[gem5-users] does KVMCPU be supported on aarch64 in SE mode?

[Liyichao via gem5-users]

Hi All:
 I would like to use KVMCPU in SE mode on aarch64 so that I can use 
-fast-forward more quickly to fastforward non-interested instrutions, but I 
have seen that "fatal("KvmCPU can only be used in SE mode with x86")" in se.py, 
so any plans to support it on aarch64?


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[gem5-users] no committedInsts in stats.txt with fastforward option in SE mode

[Liyichao via gem5-users]

Hi All:
   When I simulate with the fastforward and maxinsts parameters in SE mod, I 
only see sim_insts=my fastforward instructions in stats.txt after the maximum 
number of instructions exits. The value of committedInsts is not always 0 in 
switch_cpu.committedInsts, but if fastforward is removed, the value of 
committedInsts is equal to the value of maxinsts.Why?

 My cmd is : ./build/ARM/gem5.opt configs/example/se.py 
--cpu-type=O3_ARM_1620 --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches 
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB 
--l3cache --nvmain-config=./nvmain_public/Config/DRAM_2933_64GB_2CH.config 
--num-cpus=2 --fast-forward=1000 -I 500 -c "./lat_mem_rd;./lat_mem_rd" 
-o "-t 16 4096;-t 16 4096"



gem5 version 20.0.0.3
gem5 compiled May  7 2021 20:22:39
gem5 started May  7 2021 20:45:45
gem5 executing on ubuntu-kunpeng920-4, pid 393218
command line: ./build/ARM/gem5.opt configs/example/se.py --cpu-type=O3_ARM_1620 
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB 
--l2cache --l2_size=32MB --mem-size=32GB --l3cache 
--nvmain-config=./nvmain_public/Config/DRAM_2933_64GB_2CH.config --num-cpus=2 
--fast-forward=1000 -I 500 -c './lat_mem_rd;./lat_mem_rd' -o '-t 16 
4096;-t 16 4096'

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
Switch at instruction count:1000
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
"stride=4096
"stride=4096
Switched CPUS @ tick 3850626395
switching cpus
warn: PowerState: Already in the requested power state, request ignored
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
 REAL SIMULATION 
info: Entering event queue @ 3850626395.  Starting simulation...
Exiting @ tick 3850626395 because a thread reached the max instruction count
gem5 End May  7 2021 20:46:12



final_tick 3850626395   # 
Number of ticks from beginning of simulation (restored from checkpoints and 
never reset)
host_inst_rate  761286818   # 
Simulator instruction rate (inst/s)
host_mem_usage   34016560   # 
Number of bytes of host memory used
host_op_rate757203868   # 
Simulator op (including micro ops) rate (op/s)
host_seconds 0.03   # 
Real time elapsed on the host
host_tick_rate  0   # 
Simulator tick rate (ticks/s)
sim_freq 1   # 
Frequency of simulated ticks
sim_insts2002   # 
Number of instructions simulated
sim_ops  20003100   # 
Number of ops (including micro ops) simulated
sim_seconds 0   # 
Number of seconds simulated
sim_ticks   0

system.cpu0.committedInsts  0   # 
Number of instructions committed
system.cpu0.committedOps0   # 
Number of ops (including micro ops) committed

system.cpu1.committedInsts  0   # 
Number of instructions committed
system.cpu1.committedOps0   # 
Number of ops (including micro ops) committed

system.switch_cpus0.commit.committedInsts0   # 
Number of instructions committed
system.switch_cpus0.commit.committedOps 0   # 
Number of ops (including micro ops) committed

system.switch_cpus1.commit.committedInsts0   # 
Number of instructions committed
system.switch_cpus1.commit.committedOps 0   # 
Number of ops (including micro ops) committed



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[gem5-users] Re: Running gem5 on arm64 linux machine

[Liyichao via gem5-users]

of course！
发件人： Ahmad SB via gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5-usersmailto:gem5-users@gem5.org>>
抄送： ahmad.sb101mailto:ahmad.sb...@gmail.com>>
主题： [gem5-users] Running gem5 on arm64 linux machine
时间： 2021-05-01 02:13:22

Hello
Is it possible to install and run gem5 on a arm64 linux machine?
Thanks in advance.
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[gem5-users] swap partition in GEM5

[Liyichao via gem5-users]

Hi All:

 Currently, I want to test a workload with insufficient memory size, so 
tha it can swap with virtual harddisk. But the filesystem on GEM5 website only 
has a root partition and has not swap partition.

So does GEM5 support bootup a filesystem with swap partition and root 
partition? If does, how can I make the filesystem and how can I boot with the 
filesystem?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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[gem5-users] 答复: 答复: TimingCPU's IPC

[Liyichao via gem5-users]

Hi Jason:

In my config.ini:
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain


[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain

发件人: Jason Lowe-Power [mailto:ja...@lowepower.com]
发送时间: 2021年4月27日 22:34
收件人: gem5 users mailing list 
抄送: Bobby Bruce ; Liyichao 
主题: Re: [gem5-users] 答复: TimingCPU's IPC

Hello,

Check out the config.ini file in m5out/ and see what your CPU clock is actually 
set to. I would guess that the options are not behaving the way you expect 
(well, the way anyone would expect). se.py (and the options in Options.py) is 
pretty fundamentally broken. There are tons of special cases and other things 
that will overwrite options that you pass. There's no guarantee when you say 
"--cpu-clock=2GHz" on the command line that the CPU's clock is actually set to 
2GHz. I strongly suggest using your own configuration files like in Learning 
gem5.

Cheers,
Jason

On Tue, Apr 27, 2021 at 5:58 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
My cmd is ./build/ARM/gem5.opt --debug-flags=Exec configs/example/se.py 
--cpu-type=TimingSimpleCPU -c "/mnt/root/stream" --caches --cpu-clock="2GHz"

The Exec debug output:


3558000: system.cpu: T0 : @strlen+36:   bics   x4, x4, x5: IntAlu : 
 D=0x
83559000: system.cpu: T0 : @strlen+40:   bic   x5, x6, x7 : IntAlu 
:  D=0x808080808080
8356: system.cpu: T0 : @strlen+44:   ccmp   x5, #0, #0, eq: IntAlu 
:  D=0x
83561000: system.cpu: T0 : @strlen+48:   b.eq  : IntAlu :
83562000: system.cpu: T0 : @strlen+52:   csel   x4, x4, x5, cc: IntAlu 
:  D=0x8080808080808000
83563000: system.cpu: T0 : @strlen+56:   movz   x0, #8, #0: IntAlu 
:  D=0x0008
83564000: system.cpu: T0 : @strlen+60:   rev   x4, x4 : IntAlu 
:  D=0x0080808080808080
83565000: system.cpu: T0 : @strlen+64:   clz   x4, x4 : IntAlu 
:  D=0x0008
83566000: system.cpu: T0 : @strlen+68:   csel   x0, xzr, x0, cc   : IntAlu 
:  D=0x
83567000: system.cpu: T0 : @strlen+72:   add   x0, x0, x4, LSR #3 : IntAlu 
:  D=0x0001

1 instrution need 1000 ticks, it means that 1 instrution need 2 cycles, ipc is 
0.5. Is it correct?

发件人: Bobby Bruce [mailto:bbr...@ucdavis.edu<mailto:bbr...@ucdavis.edu>]
发送时间: 2021年4月27日 12:55
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] TimingCPU's IPC

Could you give a bit more info about your configuration here? To be honest, it 
looks like the CPU is just running at 1GHz instead of 2. Is that possible?

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Apr 23, 2021 at 3:52 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a 
program in SE mode with –debug-flags=Exec, in the debug output file, I find 
that one instruction’s tick is incremented by 1000, my cpu frequency is 2 GHz. 
Does that mean that the IPC is 0.5(cycle=1000/500)?
Is the 1IPC is calculated under 1GHz?


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[gem5-users] 答复: TimingCPU's IPC

[Liyichao via gem5-users]

My cmd is ./build/ARM/gem5.opt --debug-flags=Exec configs/example/se.py 
--cpu-type=TimingSimpleCPU -c "/mnt/root/stream" --caches --cpu-clock="2GHz"

The Exec debug output:


3558000: system.cpu: T0 : @strlen+36:   bics   x4, x4, x5: IntAlu : 
 D=0x
83559000: system.cpu: T0 : @strlen+40:   bic   x5, x6, x7 : IntAlu 
:  D=0x808080808080
8356: system.cpu: T0 : @strlen+44:   ccmp   x5, #0, #0, eq: IntAlu 
:  D=0x
83561000: system.cpu: T0 : @strlen+48:   b.eq  : IntAlu :
83562000: system.cpu: T0 : @strlen+52:   csel   x4, x4, x5, cc: IntAlu 
:  D=0x8080808080808000
83563000: system.cpu: T0 : @strlen+56:   movz   x0, #8, #0: IntAlu 
:  D=0x0008
83564000: system.cpu: T0 : @strlen+60:   rev   x4, x4 : IntAlu 
:  D=0x0080808080808080
83565000: system.cpu: T0 : @strlen+64:   clz   x4, x4 : IntAlu 
:  D=0x0008
83566000: system.cpu: T0 : @strlen+68:   csel   x0, xzr, x0, cc   : IntAlu 
:  D=0x
83567000: system.cpu: T0 : @strlen+72:   add   x0, x0, x4, LSR #3 : IntAlu 
:  D=0x0001

1 instrution need 1000 ticks, it means that 1 instrution need 2 cycles, ipc is 
0.5. Is it correct?

发件人: Bobby Bruce [mailto:bbr...@ucdavis.edu]
发送时间: 2021年4月27日 12:55
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: Re: [gem5-users] TimingCPU's IPC

Could you give a bit more info about your configuration here? To be honest, it 
looks like the CPU is just running at 1GHz instead of 2. Is that possible?

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Apr 23, 2021 at 3:52 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a 
program in SE mode with –debug-flags=Exec, in the debug output file, I find 
that one instruction’s tick is incremented by 1000, my cpu frequency is 2 GHz. 
Does that mean that the IPC is 0.5(cycle=1000/500)?
Is the 1IPC is calculated under 1GHz?


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[gem5-users] TimingCPU's IPC

[Liyichao via gem5-users]

Hi All:
 As I know, Atomic or Timing CPU’s IPC is 1 IPC, but when I test a 
program in SE mode with –debug-flags=Exec, in the debug output file, I find 
that one instruction’s tick is incremented by 1000, my cpu frequency is 2 GHz. 
Does that mean that the IPC is 0.5(cycle=1000/500)?
Is the 1IPC is calculated under 1GHz?


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[gem5-users] 答复: How to debug a program in GEM5 FS mode.

[Liyichao via gem5-users]

Thank you very much, Boris.

Let me have a try with it.




-邮件原件-
发件人: Boris Shingarov [mailto:shinga...@labware.com] 
发送时间: 2021年4月22日 15:13
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: Re: How to debug a program in GEM5 FS mode.

Liyichao,

> It is pretty if you would like to give some use guidance or an example with 
> this patch.

If your question is, "How do I apply the patch", first you need to fetch it to 
your local Git clone:

git fetch https://gem5.googlesource.com/public/gem5 refs/changes/85/44685/3

and then switch to the new branch with it:

git checkout -b change-44685 FETCH_HEAD

Now you can build it whatever way you normally do it.  Just for one example 
(assuming ARM, obviously yours can be different):

$ scons build/ARM/gem5.debug

If your question is, how to start using it, well suppose you have this very 
simple buggy program demo.c:

int *x;
int g(void) { return *x; }
int f(void) { return g() + 1; }
int _start() {
   x = (int*) 1;
   return f();
}

For our example of ARM, compile it like so:

$ arm-linux-gnueabi-gcc -O0 -ggdb -c demo.c $ arm-linux-gnueabi-ld -static -o 
demo demo.o

Now, supposing your gem5 directory is pointed to by $G5DIR, start gem5:

$G5DIR/build/ARM/gem5.debug $G5DIR/configs/example/se.py -c demo --wait-gdb=1

This is going to block, waiting for a connection on port 7000.
In another terminal start GDB, load the binary program and connect to gem5:

$ gdb
GNU gdb (GDB) 11.0.50.20210225-git
Copyright (C) 2021 Free Software Foundation, Inc.
...
(gdb) file demo
Reading symbols from demo...
(gdb) target remote localhost:7000
Remote debugging using localhost:7000
_start () at demo.c:4
4   int _start() {

Now it's sitting at the first instruciton; if you try to continue it will 
nicely tell you where the SIGSEGV is:

(gdb) c
Continuing.
Program received signal SIGSEGV, Segmentation fault.
0x000100a4 in g () at demo.c:2
2   int g(void) { return *x; }

(gdb) bt
#0  0x000100a4 in g () at demo.c:2
#1  0x000100c8 in f () at demo.c:3
#2  0x000100f0 in _start () at demo.c:6

Obviously other debuggers work well with this, I gave the example of GDB simply 
because that's standard reference, but the only limit here is your imagination. 
I use my own custom debugger I wrote for my [admittedly weird] needs 
(github://shingarov/SmallRSP if you are curious), a lot of people like Eclipse, 
etc etc.

Hope this helps.

Boris



-----"Liyichao via gem5-users"  wrote: -
To: "Boris Shingarov" , "gem5 users mailing list" 

From: "Liyichao via gem5-users" 
Date: 04/21/2021 04:42AM
Cc: "Gabe Black" , "Liyichao" 
Subject: [gem5-users] : Re: How to debug a program in GEM5 FS 
mode.

Thank for reply, I will try to use it.

It is pretty if you would like to give some use guidance or an example with 
this patch.


--
: Boris Shingarov [mailto:shinga...@labware.com]
: 2021421 16:39
: gem5 users mailing list 
: Liyichao ; Gabe Black 

: Re: [gem5-users] Re: How to debug a program in GEM5 FS mode.

Liyichao,

In fact, our group have been using that change since at least 2014 and it holds 
up in pretty complex debugging scenarios.  I hope it will be merged soon.  I 
would be really interested to hear whether it will help in your scenario.

Boris

-"Gabe Black via gem5-users"  wrote: -
To: "Liyichao" 
From: "Gabe Black via gem5-users" 
Date: 04/21/2021 02:27AM
Cc: "gem5 users mailing list" , "Gabe Black" 

Subject: [gem5-users] Re: How to debug a program in GEM5 FS mode.

Yeah, I don't think gdb in SE mode handles page faults well, but there was 
actually a change proposed very recently which should help improve that. You 
can probably cherry-pick that change locally if you want to try it out.

https://urldefense.proofpoint.com/v2/url?u=https-3A__gem5-2Dreview.googlesource.com_c_public_gem5_-2B_44685=DwIGaQ=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4=xGCMssfB_BUGfSEEKV79FCUDjr9ITBsAG0uN2ZjHsFc=-MUfR7cD0QU9XSD39_UGYJxOY87eIk_--U4M9pAaCP8=
 

Gabe
On Tue, Apr 20, 2021 at 11:16 PM Liyichao  wrote:
 
 
 Thanks Gabe.
 
 I think run gdb inside gem5 is of course a better method but slow speed.
 
 In se modeI also have tried itbut my program in se mode has a 
page fault  panic before segment fault.I think se mode cannot process page 
fault.
 
 
 
 
   
  charlie
 Mobile+86-15858232899
 Emailliyic...@huawei.com
 
 
  
 
 Gabe Black 
 gem5 users mailing list 
 Liyichao 
 Re: [gem5-users] How to debug a program in GEM5 FS 
mode. 
 2021-04-21 14:06:58 
  
 
Hello, Liyichao. While gdb debugging in gem5 is a great tool, it's a bit 
limited as far as the sort of debugging you're talking about. It can see the 
CPU state when you're in user space programs, but it doesn't understand that 
different user  space programs are different things, or know how to look up 
their symbols, etc. It's intended primarily for debu

[gem5-users] 答复: Re: How to debug a program in GEM5 FS mode.

[Liyichao via gem5-users]

Thank for reply, I will try to use it.

It is pretty if you would like to give some use guidance or an example with 
this patch.


-邮件原件-
发件人: Boris Shingarov [mailto:shinga...@labware.com] 
发送时间: 2021年4月21日 16:39
收件人: gem5 users mailing list 
抄送: Liyichao ; Gabe Black 
主题: Re: [gem5-users] Re: How to debug a program in GEM5 FS mode.

Liyichao,

In fact, our group have been using that change since at least 2014 and it holds 
up in pretty complex debugging scenarios.  I hope it will be merged soon.  I 
would be really interested to hear whether it will help in your scenario.

Boris

-"Gabe Black via gem5-users"  wrote: -
To: "Liyichao" 
From: "Gabe Black via gem5-users" 
Date: 04/21/2021 02:27AM
Cc: "gem5 users mailing list" , "Gabe Black" 

Subject: [gem5-users] Re: How to debug a program in GEM5 FS mode.

Yeah, I don't think gdb in SE mode handles page faults well, but there was 
actually a change proposed very recently which should help improve that. You 
can probably cherry-pick that change locally if you want to try it out.

https://gem5-review.googlesource.com/c/public/gem5/+/44685

Gabe
On Tue, Apr 20, 2021 at 11:16 PM Liyichao  wrote:
 
 
 Thanks Gabe.
 
 I think run gdb inside gem5 is of course a better method but slow speed.
 
 In se modeI also have tried itbut my program in se mode has a 
page fault  panic before segment fault.I think se mode cannot process page 
fault.
 
 
 
 
   
  charlie
 Mobile+86-15858232899  
 Emailliyic...@huawei.com
 
 
  
 
 Gabe Black 
 gem5 users mailing list 
 Liyichao 
 Re: [gem5-users] How to debug a program in GEM5 FS 
mode. 
 2021-04-21 14:06:58 
  
 
Hello, Liyichao. While gdb debugging in gem5 is a great tool, it's a bit 
limited as far as the sort of debugging you're talking about. It can see the 
CPU state when you're in user space programs, but it doesn't understand that 
different user  space programs are different things, or know how to look up 
their symbols, etc. It's intended primarily for debugging the kernel, since 
that's frankly a more tractable problem. It would be possible to extend that 
support to give it more insight into what's  going on inside the kernel so it 
can do more in that regard, and while I'd like to do that at some point, that's 
not anything that will happen soon. 

  
If you want to debug a user space program inside gem5, I think your best bet is 
to debug it in SE mode where the only thing running is your program. SE mode is 
more approximate than FS mode and can't run every program, but if it can run 
yours that's probably  what you'll want to do. 

  
Another option would be to run gdb *inside* gem5, as part of the simulation. I 
don't know if anybody has tried that, but then gdb should work like it would on 
a real ARM host, more or less. 

  
Gabe  
 
 
On Tue, Apr 20, 2021 at 7:27 PM Liyichao via gem5-users  
wrote:
   
 
 Hi All:
  I am currently debugging a program with an SVE instruction in the FS 
mode of GEM5. However, a segment error occurs in the program. Therefore, I want 
to locate which instruction is causing the error and check  the contents of the 
register of the error instruction. What are the debugging methods of GEM5 for 
applications in FS mode? Because programs with SVE instructions cannot be 
debugged directly on the ARM server, I want to debug in FS mode of GEM5.
  
 Does the Remote GDB support the preceding operations? Are there detailed 
instructions for REMOTE GDB? The Remote GDB guidance on the GEM5 website is a 
little brief.
  
 TKS.
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[gem5-users] Re: How to debug a program in GEM5 FS mode.

[Liyichao via gem5-users]

Thanks Gabe.

I think run gdb inside gem5 is of course a better method but slow speed.

In se mode，I also have tried it，but my program in se mode has a page fault  
panic before segment fault.I think se mode cannot process page fault.






李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com<mailto:liyic...@huawei.com>


发件人： Gabe Blackmailto:gabe.bl...@gmail.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] How to debug a program in GEM5 FS mode.
时间： 2021-04-21 14:06:58

Hello, Liyichao. While gdb debugging in gem5 is a great tool, it's a bit 
limited as far as the sort of debugging you're talking about. It can see the 
CPU state when you're in user space programs, but it doesn't understand that 
different user space programs are different things, or know how to look up 
their symbols, etc. It's intended primarily for debugging the kernel, since 
that's frankly a more tractable problem. It would be possible to extend that 
support to give it more insight into what's going on inside the kernel so it 
can do more in that regard, and while I'd like to do that at some point, that's 
not anything that will happen soon.

If you want to debug a user space program inside gem5, I think your best bet is 
to debug it in SE mode where the only thing running is your program. SE mode is 
more approximate than FS mode and can't run every program, but if it can run 
yours that's probably what you'll want to do.

Another option would be to run gdb *inside* gem5, as part of the simulation. I 
don't know if anybody has tried that, but then gdb should work like it would on 
a real ARM host, more or less.

Gabe

On Tue, Apr 20, 2021 at 7:27 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:
 I am currently debugging a program with an SVE instruction in the FS 
mode of GEM5. However, a segment error occurs in the program. Therefore, I want 
to locate which instruction is causing the error and check the contents of the 
register of the error instruction. What are the debugging methods of GEM5 for 
applications in FS mode? Because programs with SVE instructions cannot be 
debugged directly on the ARM server, I want to debug in FS mode of GEM5.

Does the Remote GDB support the preceding operations? Are there detailed 
instructions for REMOTE GDB? The Remote GDB guidance on the GEM5 website is a 
little brief.

TKS.
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[gem5-users] How to debug a program in GEM5 FS mode.

[Liyichao via gem5-users]

Hi All:
 I am currently debugging a program with an SVE instruction in the FS 
mode of GEM5. However, a segment error occurs in the program. Therefore, I want 
to locate which instruction is causing the error and check the contents of the 
register of the error instruction. What are the debugging methods of GEM5 for 
applications in FS mode? Because programs with SVE instructions cannot be 
debugged directly on the ARM server, I want to debug in FS mode of GEM5.

Does the Remote GDB support the preceding operations? Are there detailed 
instructions for REMOTE GDB? The Remote GDB guidance on the GEM5 website is a 
little brief.

TKS.
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[gem5-users] 答复: Re: DRAMCTRL self-refresh frequency

[Liyichao via gem5-users]

Sorry, I get the wrong info.

My current tREFI is 3.9us, tXS is 360ns, tRFC is 350ns.


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.

部门：计算系统与组件开发部 [云与计算BG]
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止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
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-邮件原件-
发件人: lsteiner--- via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2021年4月19日 21:27
收件人: gem5-users@gem5.org
抄送: lstei...@rhrk.uni-kl.de
主题: [gem5-users] Re: DRAMCTRL self-refresh frequency

The refresh rate is determined by the parameter tREFI in 
"mem/DRAMInterface.py". However, if you want a refresh rate of 64 ms you cannot 
simply set tREFI to 64 ms. tREFI is the time between two refresh commands, 
while 64 ms usually is the time between two refresh commands to the same DRAM 
cell.  Depending on the selected device size and temperature range you have to 
set different values for tREFI and tRFC. You can find more information in the 
JEDEC standard for DDR4. 

The self-refresh frequency is not determined by the DRAM controller, but by the 
DRAM device itself. This parameter cannot be modified via configuration. The 
only parameter you can modify is tXS (self-refresh exit time). For more 
information you should also take a look at the JEDEC standard.
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[gem5-users] Re: DRAMCTRL self-refresh frequency

[Liyichao via gem5-users]

Thanks。my tRFI is 360ns，my tRFC is 0.682ns






李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com


发件人： lsteiner--- via gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5-usersmailto:gem5-users@gem5.org>>
抄送： lsteinermailto:lstei...@rhrk.uni-kl.de>>
主题： [gem5-users] Re: DRAMCTRL self-refresh frequency
时间： 2021-04-19 21:27:59

The refresh rate is determined by the parameter tREFI in 
"mem/DRAMInterface.py". However, if you want a refresh rate of 64 ms you cannot 
simply set tREFI to 64 ms. tREFI is the time between two refresh commands, 
while 64 ms usually is the time between two refresh commands to the same DRAM 
cell.  Depending on the selected device size and temperature range you have to 
set different values for tREFI and tRFC. You can find more information in the 
JEDEC standard for DDR4.

The self-refresh frequency is not determined by the DRAM controller, but by the 
DRAM device itself. This parameter cannot be modified via configuration. The 
only parameter you can modify is tXS (self-refresh exit time). For more 
information you should also take a look at the JEDEC standard.
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[gem5-users] DRAMCTRL self-refresh frequency

[Liyichao via gem5-users]

Hi all:

 In GEM5, where can I modify the self refresh frequency or refresh rate 
in dramctrl? My DRAM is DDR4 2933MHz.
e.g. I want to modify the self refresh frequency or rate to 32ms or 
64ms(32Hz or 64Hz).


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[gem5-users] The sim_insts in stats.txt under O3 type seems to be wrong

[Liyichao via gem5-users]

Hi all:
 When I use se mode to execute an ELF under O3 type with Exec debug 
flags, the sim_insts in stats.txt is different with the lines of Exec debug 
output file.
 Sim_ints is 94189557, but Exec debug output file has 472187507 lines. I 
have test the same ELF on my aarch64 server with “perf stat -e r11 -e r8:k -e 
r8:u ./redis_0327”, the r8:u is userspace instrution counts, the result is:
1,514,293,116 r11
820,116,727 r8:k
429,128,196 r8:u
Is the count of sim_insts was wrong?It seems that the sim_insts is about a 
fifth less than the actual count of instructions.


My gem5 versiont is 20.0.0.3, my command is
“./build/ARM/gem5.opt --debug-flags=Exec --debug-file=./new_o3_debug_out.txt 
configs/example/se.py --cpu-type=DerivO3CPU --cpu-clock=2.6GHz 
--sys-clock=2.6GHz --caches --l2cache --mem-size=8GB 
--nvmain-config=../../nvmain_public/Config/template_DRAM_2933.config -c 
./redis_0327”

Stats.txt:
final_tick 144144768845 # Number of ticks from beginning of simulation 
(restored from checkpoints and never reset)
host_inst_rate 18845 # Simulator instruction rate (inst/s)
host_mem_usage 8562280 # Number of bytes of host memory used
host_op_rate 24546 # Simulator op (including micro ops) rate (op/s)
host_seconds 4998.02 # Real time elapsed on the host
host_tick_rate 28840391 # Simulator tick rate (ticks/s)
sim_freq 1 # Frequency of simulated ticks
sim_insts 94189557 # Number of instructions simulated
sim_ops 122680518 # Number of ops (including micro ops) simulated
sim_seconds 0.144145 # Number of seconds simulated
sim_ticks 144144768845 # Number of ticks simulated

Exec debug output file:
cat m5out/new_o3_debug_out.txt |wc -l
472187507


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
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[gem5-users] 答复: HLT instrution

[Liyichao via gem5-users]

Hi Giacomo:

When I add armsemihosting in fs.py like this:
438 from m5.objects import ArmSemihosting
439 test_sys.semihosting = ArmSemihosting()
440 Simulation.setWorkCountOptions(test_sys, options)
441 Simulation.run(options, root, test_sys, FutureClass)

I execute my workload with "HLT" instruction, gem5 will crash and show 
the error info below:
 REAL SIMULATION 
info: Entering event queue @ 7060967837385.  Starting simulation...
info: Reporting heap/stack info to guest:
Heap base: 0x8200
Heap limit: 0x47e01
Stack base: 0x48000
Stack limit: 0x47e01
fatal: writeBlob(0x414a38, ...) failed
Memory Usage: 17523372 Kbytes


I have seen that " writeBlob " is called in src/arch/mem/semihosting.cc


-邮件原件-
发件人: Giacomo Travaglini [mailto:giacomo.travagl...@arm.com] 
发送时间: 2021年3月22日 17:30
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: RE: HLT instrution

Hi Liyichao,

That is because Halting of the PE (refer to the External Debug section of the 
Arm architecture reference manual for more info) is not implemented.
The only use of HLT at the moment is as a semihosting call instruction

207 ThreadContext *tc = xc->tcBase();
208 bool have_semi = ArmSystem::haveSemihosting(tc);
209 if (imm == ArmSemihosting::A64Imm && have_semi) {
210 ArmSystem::callSemihosting64(tc);
211 } else if (imm == ArmSemihosting::Gem5Imm && have_semi) {
212 ArmSystem::callSemihosting64(tc, true);
213 } else {
214 // HLT instructions aren't implemented, so treat them as undefined
215 // instructions.
216 fault = std::make_shared(
217 machInst, false, mnemonic);
218 }


Kind Regards

Giacomo

> -----Original Message-
> From: Liyichao via gem5-users 
> Sent: 22 March 2021 03:10
> To: gem5 users mailing list 
> Cc: Liyichao 
> Subject: [gem5-users] HLT instrution
>
> Hi all:
>
>  I wonder how can gem5 process “HLT” instruction in SE/FS mode?
>
>  I have seen that “HLT instructions aren't implemented, so 
> treat them as undefined instructions.” in source code.
>
>
>
>

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[gem5-users] HLT instrution

[Liyichao via gem5-users]

Hi all:
 I wonder how can gem5 process “HLT” instruction in SE/FS mode?
 I have seen that “HLT instructions aren't implemented, so treat them 
as undefined instructions.” in source code.


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[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

[Liyichao via gem5-users]

Queue::ScopedMigration migrate(eventQueue());
setInterrupts(interruptStatus | INT_USED_RING);
}

发件人: Gabe Black [mailto:gabe.bl...@gmail.com<mailto:gabe.bl...@gmail.com>]
发送时间: 2021年3月16日 8:44
收件人: Liyichao mailto:liyic...@huawei.com>>
抄送: gem5 users mailing list mailto:gem5-users@gem5.org>>
主题: Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core

I think what you want to do is in the kick() functions in MmioVirtIO and 
PciVirtIO, you want to declare a ScopedMigration at the start of the function, 
and pass its constructor the result of the eventQueue() method. The SimObject 
class inherits from EventManager and knows what event queue it's supposed to 
use, and that's what eventQueue returns. When you declare a ScopedMigration, it 
will handle the locking correctly and move over to that queue, and when it goes 
out of scope (at the end of the function) it will put everything back.

Please give that a try, and if it works for you (I don't have a way to test it 
myself) put up a review so we can get a fix checked in.

Gabe

On Mon, Mar 15, 2021 at 5:28 PM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Thanks for your explaination.In<https://explaination.In> O3 type with 
multi-core 9P is ok.

发件人： Gabe Blackmailto:gabe.bl...@gmail.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core
时间： 2021-03-16 07:24:15

I haven't looked at the code yet, but this is probably because the v9 
implementation is getting asynchronous input which might be received by one 
thread, which then tries to schedule an event on an event queue associated with 
another queue. Most of the time this is not an issue since gem5 is usually 
single threaded, but when using multiple cores with KVM, each core runs in its 
own thread. There's a way to add events to the event queue in another thread 
safely (ScopedMigration) which I'm assuming the v9 code is not using.

Gabe

On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:

 When I use –vio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, 
but more than 1 core, mount cmd will cause GEM5 crash

 1core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=1 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p
 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p
root@charlie:~# df -h
Filesystem  Size  Used Avail Use% Mounted on
/dev/root   9.9G  3.3G  6.2G  35% /
devtmpfs2.0G  4.0K  2.0G   1% /dev
none4.0K 0  4.0K   0% /sys/fs/cgroup
none396M   52K  396M   1% /run
none5.0M 0  5.0M   0% /run/lock
none2.0G 0  2.0G   0% /run/shm
none100M 0  100M   0% /run/user
gem52.9T  1.8T  989G  65% /mnt/9p



 2core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=2 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p

 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p

GEM5 crash info:
gem5.opt: build/ARM/sim/eventq_impl.hh:40: void 
EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()' 
failed.
Program aborted at tick 476281849910020
--- BEGIN LIBC BACKTRACE ---
./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0xdd24e418]
./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0xdd25efa4]
linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x9fea5688]
/lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x9f6634f8]
--- END LIBC BACKTRACE ---
Aborted (core dumped)

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[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

[Liyichao via gem5-users]

I look into the code, and find that the kick() function in 
VirtIO9PBase::sendRMsg function in fs9p.cc is defined in class VirtIODeviceBase:

class VirtIODeviceBase : public SimObject
{
  public:
typedef uint16_t QueueID;
typedef uint32_t FeatureBits;
/** This is a VirtQueue address as exposed through the low-level
 * interface.\ The address needs to be multiplied by the page size
 * (seems to be hardcoded to 4096 in the spec) to get the real
 * physical address.
 */
typedef uint16_t VirtAddress;
/** Device Type (sometimes known as subsystem ID) */
typedef uint16_t DeviceId;

BitUnion8(DeviceStatus)
Bitfield<7> failed;
Bitfield<2> driver_ok;
Bitfield<1> driver;
Bitfield<0> acknowledge;
EndBitUnion(DeviceStatus)

typedef VirtIODeviceBaseParams Params;
VirtIODeviceBase(Params *params, DeviceId id, size_t config_size,
 FeatureBits features);
virtual ~VirtIODeviceBase();

  public:
/** @{
 * @name SimObject Interfaces
 */
void serialize(CheckpointOut ) const override;
void unserialize(CheckpointIn ) override;
/** @} */

  protected:
/** @{
 * @name Device Model Interfaces
 */

/**
 * Inform the guest of available buffers.
 *
 * When a device model has finished processing incoming buffers
 * (after onNotify has been called), it typically needs to inform
 * the guest that there are new pending outgoing buffers. The
 * method used to inform the guest is transport dependent, but is
 * typically through an interrupt. Device models call this method
 * to tell the transport interface to notify the guest.
 */
void kick() {
assert(transKick);
transKick->process();
};

But not define in MmioVirtIO and PciVirtIO as you mentioned.

So should I declared in the kick() definition?

void kick() {
   EventQueue::ScopedMigration migrate(eventQueue());
assert(transKick);
transKick->process();
};


发件人: Gabe Black [mailto:gabe.bl...@gmail.com]
发送时间: 2021年3月16日 13:55
收件人: Liyichao 
抄送: gem5 users mailing list 
主题: Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core

Yes exactly, did that help?

Gabe

On Mon, Mar 15, 2021 at 10:29 PM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Hi Gabe:
 You mean that the code to be modified just like this?

 void
PciVirtIO::kick()
{
DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
EventQueue::ScopedMigration migrate(eventQueue());
interruptDeliveryPending = true;
intrPost();
}


void
MmioVirtIO::kick()
{
DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
EventQueue::ScopedMigration migrate(eventQueue());
setInterrupts(interruptStatus | INT_USED_RING);
}

发件人: Gabe Black [mailto:gabe.bl...@gmail.com<mailto:gabe.bl...@gmail.com>]
发送时间: 2021年3月16日 8:44
收件人: Liyichao mailto:liyic...@huawei.com>>
抄送: gem5 users mailing list mailto:gem5-users@gem5.org>>
主题: Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core

I think what you want to do is in the kick() functions in MmioVirtIO and 
PciVirtIO, you want to declare a ScopedMigration at the start of the function, 
and pass its constructor the result of the eventQueue() method. The SimObject 
class inherits from EventManager and knows what event queue it's supposed to 
use, and that's what eventQueue returns. When you declare a ScopedMigration, it 
will handle the locking correctly and move over to that queue, and when it goes 
out of scope (at the end of the function) it will put everything back.

Please give that a try, and if it works for you (I don't have a way to test it 
myself) put up a review so we can get a fix checked in.

Gabe

On Mon, Mar 15, 2021 at 5:28 PM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Thanks for your explaination.In<https://explaination.In> O3 type with 
multi-core 9P is ok.


发件人： Gabe Blackmailto:gabe.bl...@gmail.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core
时间： 2021-03-16 07:24:15

I haven't looked at the code yet, but this is probably because the v9 
implementation is getting asynchronous input which might be received by one 
thread, which then tries to schedule an event on an event queue associated with 
another queue. Most of the time this is not an issue since gem5 is usually 
single threaded, but when using multiple cores with KVM, each core runs in its 
own thread. There's a way to add events to the event queue in another thread 
safely (ScopedMigration) which I'm assuming the v9 code is not using.

Gabe

On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:

[gem5-users] 答复: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

[Liyichao via gem5-users]

Hi Gabe:
 You mean that the code to be modified just like this?

 void
PciVirtIO::kick()
{
DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
EventQueue::ScopedMigration migrate(eventQueue());
interruptDeliveryPending = true;
intrPost();
}


void
MmioVirtIO::kick()
{
DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
EventQueue::ScopedMigration migrate(eventQueue());
setInterrupts(interruptStatus | INT_USED_RING);
}

发件人: Gabe Black [mailto:gabe.bl...@gmail.com]
发送时间: 2021年3月16日 8:44
收件人: Liyichao 
抄送: gem5 users mailing list 
主题: Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core

I think what you want to do is in the kick() functions in MmioVirtIO and 
PciVirtIO, you want to declare a ScopedMigration at the start of the function, 
and pass its constructor the result of the eventQueue() method. The SimObject 
class inherits from EventManager and knows what event queue it's supposed to 
use, and that's what eventQueue returns. When you declare a ScopedMigration, it 
will handle the locking correctly and move over to that queue, and when it goes 
out of scope (at the end of the function) it will put everything back.

Please give that a try, and if it works for you (I don't have a way to test it 
myself) put up a review so we can get a fix checked in.

Gabe

On Mon, Mar 15, 2021 at 5:28 PM Liyichao 
mailto:liyic...@huawei.com>> wrote:
Thanks for your explaination.In<https://explaination.In> O3 type with 
multi-core 9P is ok.



发件人： Gabe Blackmailto:gabe.bl...@gmail.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core
时间： 2021-03-16 07:24:15

I haven't looked at the code yet, but this is probably because the v9 
implementation is getting asynchronous input which might be received by one 
thread, which then tries to schedule an event on an event queue associated with 
another queue. Most of the time this is not an issue since gem5 is usually 
single threaded, but when using multiple cores with KVM, each core runs in its 
own thread. There's a way to add events to the event queue in another thread 
safely (ScopedMigration) which I'm assuming the v9 code is not using.

Gabe

On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:

 When I use –vio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, 
but more than 1 core, mount cmd will cause GEM5 crash

 1core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=1 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p
 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p
root@charlie:~# df -h
Filesystem  Size  Used Avail Use% Mounted on
/dev/root   9.9G  3.3G  6.2G  35% /
devtmpfs2.0G  4.0K  2.0G   1% /dev
none4.0K 0  4.0K   0% /sys/fs/cgroup
none396M   52K  396M   1% /run
none5.0M 0  5.0M   0% /run/lock
none2.0G 0  2.0G   0% /run/shm
none100M 0  100M   0% /run/user
gem52.9T  1.8T  989G  65% /mnt/9p



 2core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=2 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p

 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p

GEM5 crash info:
gem5.opt: build/ARM/sim/eventq_impl.hh:40: void 
EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()' 
failed.
Program aborted at tick 476281849910020
--- BEGIN LIBC BACKTRACE ---
./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0xdd24e418]
./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0xdd25efa4]
linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x9fea5688]
/lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x9f6634f8]
--- END LIBC BACKTRACE ---
Aborted (core dumped)

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[gem5-users] Re: gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

[Liyichao via gem5-users]

Thanks for your explaination.In<https://explaination.In> O3 type with 
multi-core 9P is ok.






李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com<mailto:liyic...@huawei.com>


发件人： Gabe Blackmailto:gabe.bl...@gmail.com>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Liyichaomailto:liyic...@huawei.com>>
主题： Re: [gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with 
more than 1 core
时间： 2021-03-16 07:24:15

I haven't looked at the code yet, but this is probably because the v9 
implementation is getting asynchronous input which might be received by one 
thread, which then tries to schedule an event on an event queue associated with 
another queue. Most of the time this is not an issue since gem5 is usually 
single threaded, but when using multiple cores with KVM, each core runs in its 
own thread. There's a way to add events to the event queue in another thread 
safely (ScopedMigration) which I'm assuming the v9 code is not using.

Gabe

On Sun, Mar 7, 2021 at 8:38 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:

 When I use �Cvio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, 
but more than 1 core, mount cmd will cause GEM5 crash

 1core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=1 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p
 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p
root@charlie:~# df -h
Filesystem  Size  Used Avail Use% Mounted on
/dev/root   9.9G  3.3G  6.2G  35% /
devtmpfs2.0G  4.0K  2.0G   1% /dev
none4.0K 0  4.0K   0% /sys/fs/cgroup
none396M   52K  396M   1% /run
none5.0M 0  5.0M   0% /run/lock
none2.0G 0  2.0G   0% /run/shm
none100M 0  100M   0% /run/user
gem52.9T  1.8T  989G  65% /mnt/9p



 2core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=2 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p

 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p

GEM5 crash info:
gem5.opt: build/ARM/sim/eventq_impl.hh:40: void 
EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()' 
failed.
Program aborted at tick 476281849910020
--- BEGIN LIBC BACKTRACE ---
./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0xdd24e418]
./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0xdd25efa4]
linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x9fea5688]
/lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x9f6634f8]
--- END LIBC BACKTRACE ---
Aborted (core dumped)

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[gem5-users] gem5 crash when mount by vio-9p protocol in KVM mode with more than 1 core

[Liyichao via gem5-users]

Hi All:

 When I use –vio-9p with fs_bigLITTLE.py, 1 core the mount cmd was ok, 
but more than 1 core, mount cmd will cause GEM5 crash

 1core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=1 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p
 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p
root@charlie:~# df -h
Filesystem  Size  Used Avail Use% Mounted on
/dev/root   9.9G  3.3G  6.2G  35% /
devtmpfs2.0G  4.0K  2.0G   1% /dev
none4.0K 0  4.0K   0% /sys/fs/cgroup
none396M   52K  396M   1% /run
none5.0M 0  5.0M   0% /run/lock
none2.0G 0  2.0G   0% /run/shm
none100M 0  100M   0% /run/user
gem52.9T  1.8T  989G  65% /mnt/9p



 2core:
 Gem5 cmd: ./build/ARM/gem5.opt --debug-flags=Exec  -d 
/home/l00515693/m5out configs/example/arm/fs_bigLITTLE.py --cpu-type=kvm 
--kernel=vmlinux --machine-type=VExpress_GEM5_V1 
--disk=expanded-aarch64-ubuntu-trusty-headless.img --caches 
--big-cpu-clock=2.6GHz --little-cpu-clock=2.6GHz --big-cpus=2 --little-cpus=0 
--mem-size=4GB --param 'system.realview.gic.gem5_extensions = True' 
--bootscript=./test.rcS --vio-9p

 Mount cmd in guest OS: mount -t 9p -o 
trans=virtio,version=9p2000.L,aname=/home/l00515693/m5out/9p/share gem5 /mnt/9p

GEM5 crash info:
gem5.opt: build/ARM/sim/eventq_impl.hh:40: void 
EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()' 
failed.
Program aborted at tick 476281849910020
--- BEGIN LIBC BACKTRACE ---
./build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0xdd24e418]
./build/ARM/gem5.opt(_Z12abortHandleri+0x5c)[0xdd25efa4]
linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0x9fea5688]
/lib/aarch64-linux-gnu/libc.so.6(raise+0xb0)[0x9f6634f8]
--- END LIBC BACKTRACE ---
Aborted (core dumped)

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[gem5-users] A problem of "Assertion `!load_inst->isExecuted()' failed.”"

[Liyichao via gem5-users]

Hi All:

 When I run a program with 1 core on ARM64 CPU O3 MODEL, I meet a 
problem of “Assertion `!load_inst->isExecuted()' failed.”:



8273246606240: system.N1Cluster.cpus.decode: Processing [tid:0]
8273246606240: system.N1Cluster.cpus.decode: [tid:0] Stall fom Rename stage 
detected.
8273246606240: system.N1Cluster.cpus.decode: [tid:0] Blocking.
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170936] 
PC: (0x423c64=>0x423c68).(0=>1) into decode skidBuffer 7
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170937] 
PC: (0x423c68=>0x423c6c).(0=>1) into decode skidBuffer 8
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170938] 
PC: (0x423c6c=>0x423c70).(0=>1) into decode skidBuffer 9
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170939] 
PC: (0x423c70=>0x423c74).(0=>1) into decode skidBuffer 10
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170940] 
PC: (0x423c74=>0x423c78).(0=>1) into decode skidBuffer 11
8273246606240: system.N1Cluster.cpus.decode: Inserting [tid:0][sn:137170941] 
PC: (0x423c78=>0x423c7c).(0=>1) into decode skidBuffer 12
8273246606240: system.N1Cluster.cpus.iew: Issue: Processing [tid:0]
8273246606240: system.N1Cluster.cpus.iew: [tid:0] Not blocked, so attempting to 
run dispatch.
8273246606240: system.N1Cluster.cpus.iew: Execute: Executing instructions from 
IQ.
8273246606240: system.N1Cluster.cpus.iew: Execute: Processing PC 
(0x423ba8=>0x423bac).(2=>3), [tid:0] [sn:137170924].
8273246606240: global: RegFile: Access to int register 121, has data 
0x7f8aaac658
8273246606240: global: RegFile: Setting int register 132 to 0x7f8aaac658
8273246606240: system.N1Cluster.cpus.iew: Current wb cycle: 0, width: 8, 
numInst: 0
wbActual:0
8273246606240: system.N1Cluster.cpus.iew: Execute: Executing instructions from 
IQ.
8273246606240: system.N1Cluster.cpus.iew: Execute: Processing PC 
(0x423bb4=>0x423bb8).(0=>1), [tid:0] [sn:137170927].
8273246606240: global: RegFile: Access to int register 123, has data 
0x7ff630
8273246606240: global: RegFile: Setting int register 21 to 0x7ff631
8273246606240: system.N1Cluster.cpus.iew: Current wb cycle: 0, width: 8, 
numInst: 1
wbActual:1
8273246606240: system.N1Cluster.cpus.iew: Execute: Executing instructions from 
IQ.
8273246606240: system.N1Cluster.cpus.iew: Execute: Processing PC 
(0x423bb8=>0x423bbc).(0=>1), [tid:0] [sn:137170928].
8273246606240: global: RegFile: Access to int register 34, has data 0
8273246606240: global: RegFile: Access to int register 96, has data 0xd5
8273246606240: global: RegFile: Setting int register 34 to 0
8273246606240: global: RegFile: Setting cc register 695 to 0x1
8273246606240: global: RegFile: Setting cc register 693 to 0
8273246606240: global: RegFile: Setting cc register 694 to 0
8273246606240: system.N1Cluster.cpus.iew: Current wb cycle: 0, width: 8, 
numInst: 2
wbActual:2
8273246606240: system.N1Cluster.cpus.iew: Sending instructions to commit, 
[sn:137170924] PC (0x423ba8=>0x423bac).(2=>3).
8273246606240: system.N1Cluster.cpus.iq: Waking dependents of completed 
instruction.
8273246606240: system.N1Cluster.cpus.iq: Waking any dependents on register 132 
(IntRegClass).
8273246606240: system.N1Cluster.cpus.iew: Setting Destination Register 132 
(IntRegClass)
8273246606240: system.N1Cluster.cpus.iew: Sending instructions to commit, 
[sn:137170927] PC (0x423bb4=>0x423bb8).(0=>1).
8273246606240: system.N1Cluster.cpus.iq: Waking dependents of completed 
instruction.
8273246606240: system.N1Cluster.cpus.iq: Waking any dependents on register 21 
(IntRegClass).
8273246606240: system.N1Cluster.cpus.iew: Setting Destination Register 21 
(IntRegClass)
8273246606240: system.N1Cluster.cpus.iew: Sending instructions to commit, 
[sn:137170928] PC (0x423bb8=>0x423bbc).(0=>1).
8273246606240: system.N1Cluster.cpus.iq: Waking dependents of completed 
instruction.
8273246606240: system.N1Cluster.cpus.iq: Reg 34 [IntRegClass] is pinned, 
skipping
8273246606240: system.N1Cluster.cpus.iq: Waking any dependents on register 695 
(CCRegClass).
8273246606240: system.N1Cluster.cpus.iq: Waking any dependents on register 693 
(CCRegClass).
8273246606240: system.N1Cluster.cpus.iq: Waking any dependents on register 694 
(CCRegClass).
8273246606240: system.N1Cluster.cpus.iew: Setting Destination Register 695 
(CCRegClass)
8273246606240: system.N1Cluster.cpus.iew: Setting Destination Register 693 
(CCRegClass)
8273246606240: system.N1Cluster.cpus.iew: Setting Destination Register 694 
(CCRegClass)
8273246606240: system.N1Cluster.cpus.iq: Attempting to schedule ready 
instructions from the IQ.
8273246606240: system.N1Cluster.cpus.iq: Instruction is ready to issue, putting 
it onto the ready list, PC (0x423a20=>0x423a24).(0=>1) opclass:47 
[sn:137170777].
8273246606240: system.N1Cluster.cpus.iq: Thread 0: Issuing instruction PC 
(0x423a20=>0x423a24).(0=>1) [sn:137170777]
8273246606240: system.N1Cluster.cpus.iew: Processing [tid:0]

[gem5-users] Re: KVM Doesn't Work

[Liyichao via gem5-users]

any plans to support gicv3 for kvm？

currently I use soft gic for kvm，but I think it will slow down the speed of kvm.
发件人： Giacomo 
Travaglinimailto:giacomo.travagl...@arm.com>>
收件人： gem5 users mailing 
listmailto:gem5-users@gem5.org>>;Liyichaomailto:liyic...@huawei.com>>
抄送： Tracy Macmailto:fgzs...@gmail.com>>
主题： RE: [gem5-users] Re: KVM Doesn't Work
时间： 2021-01-27 22:41:54

FYI these patches are merged in the develop branch atm:

https://gem5-review.googlesource.com/c/public/gem5/+/36795
https://gem5-review.googlesource.com/c/public/gem5/+/31218/6/tests/gem5/configs/arm_generic.py

And they should fix your problem (will be part of gem5 21.0)
The second one is just an example; you should add those lines to your config 
script:

if issubclass(self.cpu_class, ArmV8KvmCPU):
GenericTimer.generateDeviceTree = SimObject.generateDeviceTree
system.realview.gic.simulate_gic = True

Would you let me know if these patches alone are enough to solve your problem?

(Commenting Liyichao's changes below)


> -Original Message-
> From: Tracy Mac via gem5-users 
> Sent: 26 January 2021 11:50
> To: Liyichao 
> Cc: gem5 users mailing list ; Tracy Mac
> 
> Subject: [gem5-users] Re: KVM Doesn't Work
>
> Hi Liyichao！
> Thanks, I'll check it out.
>
> On Tue, Jan 26, 2021 at 7:44 PM Liyichao  wrote:
> >
> > You have to modify TIMER and GIC.
> >
> >
> > diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py
> > index ed81b2471..aee15b738 100644
> > --- a/src/dev/arm/GenericTimer.py
> > +++ b/src/dev/arm/GenericTimer.py
> > @@ -98,6 +98,7 @@ Reference:
> >  # value, so this initial value will be discarded
> >  cntfrq = Param.UInt64(0x180, "Value for the CNTFRQ timer
> > register")
> >
> > +'''
> >  def generateDeviceTree(self, state):
> >  node = FdtNode("timer")
> >
> > @@ -115,7 +116,8 @@ Reference:
> >  node.append(self.counter.unproxy(self).generateDtb())
> >
> >  yield node
> > -
> > +'''
> > +
> >  class GenericTimerFrame(PioDevice):
> >  """
> >  Memory-mapped timer frame implementation. Controlled from
> > GenericTimerMem, diff --git a/src/dev/arm/RealView.py
> > b/src/dev/arm/RealView.py index 9ab04725d..3fd0e9168 100644
> > --- a/src/dev/arm/RealView.py
> > +++ b/src/dev/arm/RealView.py
> > @@ -67,8 +67,10 @@ from m5.objects.SMMUv3 import SMMUv3  #
> emulation.
> > Use a GIC model that automatically switches between  # gem5's GIC
> > model and KVM's GIC model if KVM is available.
> >  try:
> > -from m5.objects.KvmGic import MuxingKvmGic
> > -kvm_gicv2_class = MuxingKvmGic
> > +# from m5.objects.KvmGic import MuxingKvmGic
> > +# kvm_gicv2_class = MuxingKvmGic
> > +from m5.objects.KvmGic import Gic400
> > +kvm_gicv2_class = Gic400
> >  except ImportError:
> >  # KVM support wasn't compiled into gem5. Fallback to a
> >  # software-only GIC.
> > diff --git a/src/dev/arm/generic_timer.cc
> > b/src/dev/arm/generic_timer.cc index 458a2eb7a..509153cab 100644
> > --- a/src/dev/arm/generic_timer.cc
> > +++ b/src/dev/arm/generic_timer.cc
> > @@ -289,8 +289,12 @@ ArchTimer::updateCounter()
> >  _interrupt->clear();
> >  }
> >
> > -_control.istatus = 0;
> > -
> > +// _control.istatus = 0;
> > +if (_control.istatus) {
> > +DPRINTF(Timer, "Clearing interrupt\n");
> > +_interrupt->clear();
> > +_control.istatus = 0;
> > +}
> >  if (scheduleEvents()) {
> >  _parent.schedule(_counterLimitReachedEvent,
> >   whenValue(_counterLimit)); diff --git


I am not sure this is needed.
First portion of the snippet is already checking if there is a pending 
interrupt and it is clearing it if that's the case
(clearing irq and setting istatus to zero)

// Clear the interurpt when timers conditions are not met
if (_interrupt->active()) {
DPRINTF(Timer, "Clearing interrupt\n");
_interrupt->clear();
}

_control.istatus = 0;


> > a/util/m5/src/abi/aarch64/SConsopts
> > b/util/m5/src/abi/aarch64/SConsopts
> > index 47ada0209..683c4f2eb 100644
> > --- a/util/m5/src/abi/aarch64/SConsopts
> > +++ b/util/m5/src/abi/aarch64/SConsopts
> > @@ -27,6 +27,7 @@ Import('*')
> >
> >  env['ABI'] = 'aarch64'
> >  get_abi_opt('CROSS_COMPILE', 'aarch64-linux-gnu-')
> > +env.Append(CFLAGS='-DM5OP_ADDR=0x1001')
> >
> >  env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc',
> > default=True)
> >  env['CALL_TYPE']['addr'].impl('m5op_addr.S')
> >
> >

This one is needed to issue memory mapped m5 ops. Gabe refactored the m5 
utility so that you can specify this at
Runtime rather than compile time:

$m5 --addr 0x1001 

I though it was already in 20.1 but I am probably wrong. Again, this will be 
part of gem5-21.0 for sure

Kind Regards

Giacomo


> >
> > -邮件原件-
> > 发件人: Tracy Mac via gem5-users [mailto:gem5-users@gem5.org]
> > 

[gem5-users] 答复: KVM Doesn't Work

[Liyichao via gem5-users]

You have to modify TIMER and GIC.


diff --git a/src/dev/arm/GenericTimer.py b/src/dev/arm/GenericTimer.py
index ed81b2471..aee15b738 100644
--- a/src/dev/arm/GenericTimer.py
+++ b/src/dev/arm/GenericTimer.py
@@ -98,6 +98,7 @@ Reference:
 # value, so this initial value will be discarded
 cntfrq = Param.UInt64(0x180, "Value for the CNTFRQ timer register")
 
+'''
 def generateDeviceTree(self, state):
 node = FdtNode("timer")
 
@@ -115,7 +116,8 @@ Reference:
 node.append(self.counter.unproxy(self).generateDtb())
 
 yield node
-
+'''
+
 class GenericTimerFrame(PioDevice):
 """
 Memory-mapped timer frame implementation. Controlled from GenericTimerMem,
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 9ab04725d..3fd0e9168 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -67,8 +67,10 @@ from m5.objects.SMMUv3 import SMMUv3
 # emulation. Use a GIC model that automatically switches between
 # gem5's GIC model and KVM's GIC model if KVM is available.
 try:
-from m5.objects.KvmGic import MuxingKvmGic
-kvm_gicv2_class = MuxingKvmGic
+# from m5.objects.KvmGic import MuxingKvmGic
+# kvm_gicv2_class = MuxingKvmGic
+from m5.objects.KvmGic import Gic400
+kvm_gicv2_class = Gic400
 except ImportError:
 # KVM support wasn't compiled into gem5. Fallback to a
 # software-only GIC.
diff --git a/src/dev/arm/generic_timer.cc b/src/dev/arm/generic_timer.cc
index 458a2eb7a..509153cab 100644
--- a/src/dev/arm/generic_timer.cc
+++ b/src/dev/arm/generic_timer.cc
@@ -289,8 +289,12 @@ ArchTimer::updateCounter()
 _interrupt->clear();
 }
 
-_control.istatus = 0;
-
+// _control.istatus = 0;
+if (_control.istatus) {
+DPRINTF(Timer, "Clearing interrupt\n");
+_interrupt->clear();
+_control.istatus = 0;
+}
 if (scheduleEvents()) {
 _parent.schedule(_counterLimitReachedEvent,
  whenValue(_counterLimit));
diff --git a/util/m5/src/abi/aarch64/SConsopts 
b/util/m5/src/abi/aarch64/SConsopts
index 47ada0209..683c4f2eb 100644
--- a/util/m5/src/abi/aarch64/SConsopts
+++ b/util/m5/src/abi/aarch64/SConsopts
@@ -27,6 +27,7 @@ Import('*')
 
 env['ABI'] = 'aarch64'
 get_abi_opt('CROSS_COMPILE', 'aarch64-linux-gnu-')
+env.Append(CFLAGS='-DM5OP_ADDR=0x1001')
 
 env['CALL_TYPE']['inst'].impl('m5op.S', 'verify_inst.cc', default=True)
 env['CALL_TYPE']['addr'].impl('m5op_addr.S')



-邮件原件-
发件人: Tracy Mac via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2021年1月26日 19:09
收件人: gem5 users mailing list 
抄送: Tracy Mac 
主题: [gem5-users] KVM Doesn't Work

Hi All
I run the fs.py script in gem5(20.1.0.0), but there is no information in the 
m5term console. I don't know what went wrong.
In gem5(20.0.0.3 develop),kvm can work very well,I have no idea how to change 
the new version.

INFO:
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 20.1.0.2
gem5 compiled Jan 26 2021 17:54:32
gem5 started Jan 26 2021 18:36:35
gem5 executing on ubuntu, pid 28630
command line: ./build/ARM/gem5.opt configs/example/fs.py --cpu-type=ArmV8KvmCPU 
--disk-image=/home/tracy/Desktop/image/aarch-system-20170616/disks/linaro-minimal-aarch64.img
--kernel=/home/tracy/Desktop/vmlinux.euler

warn: iobus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: bridge.master is deprecated. `master` is now called `mem_side_port`
warn: membus.master is deprecated. `master` is now called `mem_side_ports`
warn: bridge.slave is deprecated. `slave` is now called `cpu_side_port`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: iobus.master is deprecated. `master` is now called `mem_side_ports`
warn: iobridge.slave is deprecated. `slave` is now called `cpu_side_port`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: iobridge.master is deprecated. `master` is now called `mem_side_port`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.slave is deprecated. `slave` is now called `cpu_side_ports`
warn: membus.master is deprecated. `master` is now called `mem_side_ports` 
Global frequency set at 1 ticks per second
warn: No dot file generated. Please install pydot to generate the dot file and 
pdf.
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (512 Mbytes)
info: kernel located at: /home/tracy/Desktop/vmlinux.euler
warn: Highest ARM exception-level set to AArch32 but the workload is for 
AArch64. Assuming you wanted these to match.
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3456
system.realview.uart1.device: 

[gem5-users] Re: Using multiple threads on host?

[Liyichao via gem5-users]

You have to use X86_64 host with X86_64 guest if you want to use KVM.






李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com


发件人： bodunhu--- via gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5-usersmailto:gem5-users@gem5.org>>
抄送： bodunhumailto:bodu...@utexas.edu>>
主题： [gem5-users] Re: Using multiple threads on host?
时间： 2021-01-19 05:56:28

I guess I forgot to mention that my host is X86_64 and the simulated 
environment is aarch64 running Linux in full system mode. Does that still apply 
to this scenario?
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[gem5-users] CXL protocol model simulation support schedual in GEM5

[Liyichao via gem5-users]

Hi all:

 We are currently studying the CXL protocol. Do you have a development 
plan for the CXL protocol simulation model in the GEM5 community or have 
developers started to implement the model, including the driver, HOST/DEVICE 
module implementation, and consistency protocol?


TKS!

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[gem5-users] run pre-build binaries of aarch64 with error

[Liyichao via gem5-users]

Hi：
 I run the pre-build binaries of aarch64 test_std_thread , 
test_std_mutex and test_std_condition_variable on an aarch64 ubuntu18.04 OS 
server, which downloaded from 
https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/, I see 
the error execution below:



root@ubuntu:/home/l00515693/gem5_1P1DIE# ./test_std_thread
Hello from thread Hello from thread 1
0
Hello from thread 3
Hello from thread 2
Hello from thread 4
Hello from thread 5
Hello from thread 6
Hello from thread 7
Hello from thread 8
Hello from master thread
Hello from thread 9
terminate called after throwing an instance of 'std::system_error'
  what():  Unknown error -1689677792
Aborted (core dumped)


root@ubuntu:/home/l00515693/gem5_1P1DIE# ./test_std_mutex
terminate called after throwing an instance of 'std::system_error'
  what():  Unknown error -1605062624
Aborted (core dumped)


root@ubuntu:/home/l00515693/gem5_1P1DIE# ./test_std_condition_variable
terminate called without an active exception
Aborted (core dumped)



 By the way, is the binaries test_atomic, 
test_pthread_mutex,test_pthread_create_para and test_pthread_create_seq no 
output after execution? How to calculate the performance of them?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
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[gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

[Liyichao via gem5-users]

Hi：

I have use your Ubuntu 18.04 img to bootup, but I want to know how to 
modify to enable autologin with root and readfile from GEM5, also systemd 
service work normally.

If I cp /init.gem5 to /sbin/init, although it can enable autologin and 
read script from GEM5,but system can not work.



-邮件原件-
发件人: Giacomo Travaglini via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2020年11月30日 16:47
收件人: gem5 users mailing list 
抄送: Giacomo Travaglini 
主题: [gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 
18.04 or GLIBC 2.27

Hi Jiwon

We recently uploaded a prebuilt Ubuntu18.04 on gem5.org:

http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2

Kind Regards

Giacomo

> -Original Message-
> From: Choe, Jiwon via gem5-users 
> Sent: 29 November 2020 04:42
> To: gem5 users mailing list 
> Cc: Choe, Jiwon 
> Subject: [gem5-users] Looking for Linux disk image for 64-bit ARM with 
> Ubuntu
> 18.04 or GLIBC 2.27
>
> Hi all,
>
> I'm looking for a Linux disk image for 64-bit ARM that has GLIBC 
> version 2.27 (Ubuntu 18.04+ I think).
>
> I am trying to run Java JDK that has been compiled on Ubuntu 18.04 
> (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using 
> the disk image that I got from here: 
> http://dist.gem5.org/dist/current/arm/disks/aarch64-
> ubuntu-trusty-headless.img.bz2
>
> But when I try to run java, I get the following error within the simulated 
> system:
> java -version java -version
>
> Error: dl failure on line 604
> Error: failed /usr/lib/jvm/jdk/lib/server/libjvm.so, because 
> /lib/aarch64-linux-
> gnu/libm.so.6: version `GLIBC_2.27' not found (required by
> /usr/lib/jvm/jdk/lib/server/libjvm.so)
>
>
> I think this happens because the disk image that I am using runs 
> Ubuntu 14.04, which has GLIBC 2.19, but I compiled the java executable 
> on Ubuntu 18.04 with GLIBC 2.27.
>
> So, if anyone has a Linux disk image (for 64-bit ARM) that has GLIBC 
> 2.27, or if anyone knows how to upgrade GLIBC on the existing disk 
> image, I would greatly appreciate your help.
>
> Thanks!
> Jiwon
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[gem5-users] 答复: Re: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

[Liyichao via gem5-users]

Hi Gabe:

 This is my cmd, but it doesn’t work well.

root@ubuntu:/home/l00515693/fs-image_fx/disks# losetup -P --find --show 
--offset 32256 expanded-ubuntu-18.04-arm64-docker.img
/dev/loop4
root@ubuntu:/home/l00515693/fs-image_fx/disks#
root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o loop,offset=32256 
/home/l00515693/fs-image_fx/disks/expanded-ubuntu-18.04-arm64-docker.img /media
mount: /media: wrong fs type, bad option, bad superblock on /dev/loop4, missing 
codepage or helper program, or other error.

root@ubuntu:/home/l00515693/fs-image_fx/disks#
root@ubuntu:/home/l00515693/fs-image_fx/disks# losetup -a
/dev/loop1: [64768]:84935347 
(/home/l00515693/fs-image_fx/disks/ubuntu-base-18.04.5-base-arm64.img 
(deleted)), offset 32256
/dev/loop4: [64768]:84935358 
(/home/l00515693/fs-image_fx/disks/expanded-ubuntu-18.04-arm64-docker.img), 
offset 32256
/dev/loop2: [64768]:84935350 
(/home/l00515693/fs-image_fx/disks/ubuntu-base-18.04.5-base-arm64.img), offset 
32256
/dev/loop0: [64768]:84935205 
(/home/l00515693/fs-image_fx/disks/expanded-aarch64-ubuntu-trusty-headless.img),
 offset 32256
/dev/loop3: [64768]:84935353 
(/home/l00515693/fs-image_fx/disks/expanded-ubuntu-base-18.04.5-base-arm64.img),
 offset 32256


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
which
is intended only for the person or entity whose address is listed above. Any 
use of the
information contained herein in any way (including, but not limited to, total 
or partial
disclosure, reproduction, or dissemination) by persons other than the intended
recipient(s) is prohibited. If you receive this e-mail in error, please notify 
the sender by
phone or email immediately and delete it!

发件人: Gabe Black [mailto:gabe.bl...@gmail.com]
发送时间: 2020年12月2日 6:46
收件人: gem5 users mailing list 
抄送: Giacomo Travaglini ; Liyichao 
; Choe, Jiwon 
主题: Re: [gem5-users] Re: 答复: Re: Looking for Linux disk image for 64-bit ARM 
with Ubuntu 18.04 or GLIBC 2.27

That's probably a disk image and not a file system image. You need to tell 
losetup to scan for the partition table with I think the -p option.

Gabe

On Tue, Dec 1, 2020 at 10:02 AM Choe, Jiwon via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
I'm running into the same issue as well.

-Jiwon

On Mon, Nov 30, 2020 at 10:32 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi:
I download the img you mentioned, when I mount it on /media,it's wrong:


root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o 
loop,offset=32256 
/home/l00515693/fs-image_fx/disks/ubuntu-18.04-arm64-docker.img /media/
mount: /media: wrong fs type, bad option, bad superblock on /dev/loop4, missing 
codepage or helper program, or other error.



-邮件原件-
发件人: Giacomo Travaglini via gem5-users 
[mailto:gem5-users@gem5.org<mailto:gem5-users@gem5.org>]
发送时间: 2020年11月30日 16:47
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>>
主题: [gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 
18.04 or GLIBC 2.27

Hi Jiwon

We recently uploaded a prebuilt Ubuntu18.04 on gem5.org<http://gem5.org>:

http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2

Kind Regards

Giacomo

> -Original Message-
> From: Choe, Jiwon via gem5-users 
> mailto:gem5-users@gem5.org>>
> Sent: 29 November 2020 04:42
> To: gem5 users mailing list mailto:gem5-users@gem5.org>>
> Cc: Choe, Jiwon mailto:jiwon_c...@brown.edu>>
> Subject: [gem5-users] Looking for Linux disk image for 64-bit ARM with
> Ubuntu
> 18.04 or GLIBC 2.27
>
> Hi all,
>
> I'm looking for a Linux disk image for 64-bit ARM that has GLIBC
> version 2.27 (Ubuntu 18.04+ I think).
>
> I am trying to run Java JDK that has been compiled on Ubuntu 18.04
> (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using
> the disk image that I got from here:
> http://dist.gem5.org/dist/current/arm/disks/aarch64-
> ubuntu-trusty-headless.img.bz2
>
> But when I try to run java, I get the following error within the simulated 
> system:
> java -version java -version
>
> Error: dl failure on line 604
> Error: failed /usr/lib/jvm/jdk/lib/server/libjvm.so, because
> /lib/aarch64-linux-
> gnu/libm.so.6: version `GLIBC_2.27' not found (required by
> /usr/lib/jvm/jdk/lib/server/libjvm.so)
>
>
> I think this happens because the disk image that I am using runs
> 

[gem5-users] 答复: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

[Liyichao via gem5-users]

Hi Jiwon:


 Have you solved this issue now? If have, would you like to share the 
solution?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
which
is intended only for the person or entity whose address is listed above. Any 
use of the
information contained herein in any way (including, but not limited to, total 
or partial
disclosure, reproduction, or dissemination) by persons other than the intended
recipient(s) is prohibited. If you receive this e-mail in error, please notify 
the sender by
phone or email immediately and delete it!

发件人: Choe, Jiwon [mailto:jiwon_c...@brown.edu]
发送时间: 2020年12月2日 2:02
收件人: gem5 users mailing list 
抄送: Giacomo Travaglini ; Liyichao 

主题: Re: [gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with 
Ubuntu 18.04 or GLIBC 2.27

I'm running into the same issue as well.

-Jiwon

On Mon, Nov 30, 2020 at 10:32 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi:
I download the img you mentioned, when I mount it on /media,it's wrong:


root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o 
loop,offset=32256 
/home/l00515693/fs-image_fx/disks/ubuntu-18.04-arm64-docker.img /media/
mount: /media: wrong fs type, bad option, bad superblock on /dev/loop4, missing 
codepage or helper program, or other error.



-邮件原件-
发件人: Giacomo Travaglini via gem5-users 
[mailto:gem5-users@gem5.org<mailto:gem5-users@gem5.org>]
发送时间: 2020年11月30日 16:47
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>>
主题: [gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 
18.04 or GLIBC 2.27

Hi Jiwon

We recently uploaded a prebuilt Ubuntu18.04 on gem5.org<http://gem5.org>:

http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2

Kind Regards

Giacomo

> -Original Message-
> From: Choe, Jiwon via gem5-users 
> mailto:gem5-users@gem5.org>>
> Sent: 29 November 2020 04:42
> To: gem5 users mailing list mailto:gem5-users@gem5.org>>
> Cc: Choe, Jiwon mailto:jiwon_c...@brown.edu>>
> Subject: [gem5-users] Looking for Linux disk image for 64-bit ARM with
> Ubuntu
> 18.04 or GLIBC 2.27
>
> Hi all,
>
> I'm looking for a Linux disk image for 64-bit ARM that has GLIBC
> version 2.27 (Ubuntu 18.04+ I think).
>
> I am trying to run Java JDK that has been compiled on Ubuntu 18.04
> (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using
> the disk image that I got from here:
> http://dist.gem5.org/dist/current/arm/disks/aarch64-
> ubuntu-trusty-headless.img.bz2
>
> But when I try to run java, I get the following error within the simulated 
> system:
> java -version java -version
>
> Error: dl failure on line 604
> Error: failed /usr/lib/jvm/jdk/lib/server/libjvm.so, because
> /lib/aarch64-linux-
> gnu/libm.so.6: version `GLIBC_2.27' not found (required by
> /usr/lib/jvm/jdk/lib/server/libjvm.so)
>
>
> I think this happens because the disk image that I am using runs
> Ubuntu 14.04, which has GLIBC 2.19, but I compiled the java executable
> on Ubuntu 18.04 with GLIBC 2.27.
>
> So, if anyone has a Linux disk image (for 64-bit ARM) that has GLIBC
> 2.27, or if anyone knows how to upgrade GLIBC on the existing disk
> image, I would greatly appreciate your help.
>
> Thanks!
> Jiwon
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[gem5-users] some error in IDE CONTROLLER when I change the virtioblk to pci ide controller in fs_bigLITTLE.py

[Liyichao via gem5-users]

Hi all:

 When I change the virtioblk to ide in fs_bigLITTLE.py, and in KVM mode 
I setup a ceph with 3 blank disks, and when I write to these disks, some kernel 
message will show:

[  428.264131] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  428.265631] ata1.01: BMDMA stat 0x65
[  428.266131] ata1.01: failed command: WRITE DMA
[  428.267131] ata1.01: cmd ca/00:00:3f:e7:00/00:00:00:00:00/f0 tag 0 dma 
131072 out
[  428.267131]  res 58/01:00:3f:e7:00/00:00:00:00:00/f0 Emask 0x2 (HSM 
violation)
[  428.270131] ata1.01: status: { DRDY DRQ }
[  428.271131] ata1.01: error: { AMNF }
[  428.624634] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  428.626134] ata1.01: BMDMA stat 0x65
[  428.626634] ata1.01: failed command: WRITE DMA
[  428.627634] ata1.01: cmd ca/00:00:3f:e8:00/00:00:00:00:00/f0 tag 0 dma 
131072 out
[  428.627634]  res 58/01:00:3f:e8:00/00:00:00:00:00/f0 Emask 0x2 (HSM 
violation)
[  428.632135] ata1.01: status: { DRDY DRQ }
[  428.632635] ata1.01: error: { AMNF }
[  428.978138] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  428.981638] ata1.01: BMDMA stat 0x65
[  428.982638] ata1.01: failed command: WRITE DMA
[  428.983138] ata1.01: cmd ca/00:00:3f:e8:00/00:00:00:00:00/f0 tag 0 dma 
131072 out
[  428.983138]  res 58/01:00:3f:e8:00/00:00:00:00:00/f0 Emask 0x2 (HSM 
violation)
[  428.986138] ata1.01: status: { DRDY DRQ }
[  428.987138] ata1.01: error: { AMNF }
[  429.926149] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  429.927649] ata1.01: BMDMA stat 0x65
[  429.928149] ata1.01: failed command: WRITE DMA
[  429.929149] ata1.01: cmd ca/00:00:3f:01:01/00:00:00:00:00/f0 tag 0 dma 
131072 out
[  429.929149]  res 58/01:00:3f:01:01/00:00:00:00:00/f0 Emask 0x2 (HSM 
violation)
[  429.932149] ata1.01: status: { DRDY DRQ }
[  429.933149] ata1.01: error: { AMNF }
[  430.270152] ata1.01: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  430.271152] ata1.01: BMDMA stat 0x65
[  430.273652] ata1.01: failed command: WRITE DMA
[  430.274652] ata1.01: cmd ca/00:00:3f:01:01/00:00:00:00:00/f0 tag 0 dma 
131072 out
[  430.274652]  res 58/01:00:3f:01:01/00:00:00:00:00/f0 Emask 0x2 (HSM 
violation)
[  430.277652] ata1.01: status: { DRDY DRQ }
[  430.278152] ata1.01: error: { AMNF }
[  435.214206] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  435.215706] ata1.00: BMDMA stat 0x65
[  435.216206] ata1.00: failed command: WRITE DMA
[  435.217206] ata1.00: cmd ca/00:20:e7:a3:44/00:00:00:00:00/e0 tag 0 dma 16384 

  out
[  435.217206]  res 58/01:20:e7:a3:44/00:00:00:00:00/e0 Emask 0x2 (HSM 
v   
   iolation)
[  435.220206] ata1.00: status: { DRDY DRQ }
[  435.221206] ata1.00: error: { AMNF }
[  435.545209] ata1.00: exception Emask 0x0 SAct 0x0 SErr 0x0 action 0x6 frozen
[  435.546709] ata1.00: BMDMA stat 0x65
[  435.547709] ata1.00: failed command: WRITE DMA
[  435.548709] ata1.00: cmd ca/00:20:e7:a3:44/00:00:00:00:00/e0 tag 0 dma 16384 

  out
[  435.548709]  res 58/01:20:e7:a3:44/00:00:00:00:00/e0 Emask 0x2 (HSM 
v   
   iolation)
[  435.551709] ata1.00: status: { DRDY DRQ }
[  435.552209] ata1.00: error: { AMNF }


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
which
is intended only for the person or entity whose address is listed above. Any 
use of the
information contained herein in any way (including, but not limited to, total 
or partial
disclosure, reproduction, or dissemination) by persons other than the intended
recipient(s) is prohibited. If you receive this e-mail in error, please notify 
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[gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

[Liyichao via gem5-users]

Hi:
I download the img you mentioned, when I mount it on /media,it's wrong:


root@ubuntu:/home/l00515693/fs-image_fx/disks# mount -o 
loop,offset=32256 
/home/l00515693/fs-image_fx/disks/ubuntu-18.04-arm64-docker.img /media/
mount: /media: wrong fs type, bad option, bad superblock on /dev/loop4, missing 
codepage or helper program, or other error.



-邮件原件-
发件人: Giacomo Travaglini via gem5-users [mailto:gem5-users@gem5.org] 
发送时间: 2020年11月30日 16:47
收件人: gem5 users mailing list 
抄送: Giacomo Travaglini 
主题: [gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 
18.04 or GLIBC 2.27

Hi Jiwon

We recently uploaded a prebuilt Ubuntu18.04 on gem5.org:

http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2

Kind Regards

Giacomo

> -Original Message-
> From: Choe, Jiwon via gem5-users 
> Sent: 29 November 2020 04:42
> To: gem5 users mailing list 
> Cc: Choe, Jiwon 
> Subject: [gem5-users] Looking for Linux disk image for 64-bit ARM with 
> Ubuntu
> 18.04 or GLIBC 2.27
>
> Hi all,
>
> I'm looking for a Linux disk image for 64-bit ARM that has GLIBC 
> version 2.27 (Ubuntu 18.04+ I think).
>
> I am trying to run Java JDK that has been compiled on Ubuntu 18.04 
> (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using 
> the disk image that I got from here: 
> http://dist.gem5.org/dist/current/arm/disks/aarch64-
> ubuntu-trusty-headless.img.bz2
>
> But when I try to run java, I get the following error within the simulated 
> system:
> java -version java -version
>
> Error: dl failure on line 604
> Error: failed /usr/lib/jvm/jdk/lib/server/libjvm.so, because 
> /lib/aarch64-linux-
> gnu/libm.so.6: version `GLIBC_2.27' not found (required by
> /usr/lib/jvm/jdk/lib/server/libjvm.so)
>
>
> I think this happens because the disk image that I am using runs 
> Ubuntu 14.04, which has GLIBC 2.19, but I compiled the java executable 
> on Ubuntu 18.04 with GLIBC 2.27.
>
> So, if anyone has a Linux disk image (for 64-bit ARM) that has GLIBC 
> 2.27, or if anyone knows how to upgrade GLIBC on the existing disk 
> image, I would greatly appreciate your help.
>
> Thanks!
> Jiwon
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[gem5-users] how can I use ubuntu kernel 4.15.0 to bootup with fs.py

[Liyichao via gem5-users]

Hi All:
 I use gem5 .config which can bootup successfully with 4.14 kernel 
downloaded from gem5 website, but when I use this .config to compile ubuntu 
18.04.5’s kernel(4.15.0), it can’t bootup with fs.py.


 It hanged here:


root@ubuntu:/home/l00515693/gem5_1P1DIE# ./build/ARM/gem5.opt -d 
/home/l00515693/m5out configs/example/fs.py --cpu-type=ArmV8KvmCPU 
--kernel=vmlinux-4.15.0 -n 1 --machine-type=VExpress_GEM5_V1 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank1.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank2.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank3.img --caches 
--l2cache --l1d_size=64kB --l1i_size=64kB --l2_size=512kB --l1d_assoc=4 
--l1i_assoc=4 --l2_assoc=16 --cacheline_size=64 --cpu-clock=2.6GHz 
--script=script/boot_ceph_1_1P1DIE_ruby.rcS --mem-size=4GB --param 
'system.realview.gic.gem5_extensions = True'

warn: CheckedInt already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
warn: Enum already exists in allParams. This may be caused by the Python 2.7 
compatibility layer.
warn: ScopedEnum already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 version 20.0.0.3
gem5 compiled Oct 26 2020 10:01:48
gem5 started Nov 30 2020 09:27:51
gem5 executing on ubuntu, pid 185766
command line: ./build/ARM/gem5.opt -d /home/l00515693/m5out 
configs/example/fs.py --cpu-type=ArmV8KvmCPU --kernel=vmlinux-4.15.0 -n 1 
--machine-type=VExpress_GEM5_V1 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank1.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank2.img 
--disk-image=expanded-ubuntu-base-18.04.5-base-arm64-blank3.img --caches 
--l2cache --l1d_size=64kB --l1i_size=64kB --l2_size=512kB --l1d_assoc=4 
--l1i_assoc=4 --l2_assoc=16 --cacheline_size=64 --cpu-clock=2.6GHz 
--script=script/boot_ceph_1_1P1DIE_ruby.rcS --mem-size=4GB --param 
'system.realview.gic.gem5_extensions = True'

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (4096 Mbytes)
info: kernel located at: /home/l00515693/fs-image_fx/binaries/vmlinux-4.15.0
warn: Highest ARM exception-level set to AArch32 but the workload is for 
AArch64. Assuming you wanted these to match.
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3456
system.realview.uart1.device: Listening for connections on port 3457
system.realview.uart2.device: Listening for connections on port 3458
system.realview.uart3.device: Listening for connections on port 3459
0: system.remote_gdb: listening for remote gdb on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: /home/l00515693/m5out/system.dtb at address 0x8800
 REAL SIMULATION 
info: KVM: Coalesced MMIO disabled by config.
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: Returning zero for read from miscreg pmintenset_el1
warn: Returning zero for read from miscreg pmintenclr_el1
warn: Returning zero for read from miscreg pmcr_el0
warn: Returning zero for read from miscreg pmcntenset_el0
warn: Returning zero for read from miscreg pmcntenclr_el0
warn: Returning zero for read from miscreg pmovsclr_el0
warn: Returning zero for read from miscreg pmswinc_el0
warn: Returning zero for read from miscreg pmselr_el0
warn: Returning zero for read from miscreg pmccntr_el0
warn: Returning zero for read from miscreg pmuserenr_el0
warn: Returning zero for read from miscreg pmovsset_el0
warn: Returning zero for read from miscreg pmevcntr0_el0
warn: Returning zero for read from miscreg pmevcntr1_el0
warn: Returning zero for read from miscreg pmevcntr2_el0
warn: Returning zero for read from miscreg pmevcntr3_el0
warn: Returning zero for read from miscreg pmevcntr4_el0
warn: Returning zero for read from miscreg pmevcntr5_el0
warn: Returning zero for read from miscreg pmevtyper0_el0
warn: Returning zero for read from miscreg pmevtyper1_el0
warn: Returning zero for read from miscreg pmevtyper2_el0
warn: Returning zero for read from miscreg pmevtyper3_el0
warn: Returning zero for read from miscreg pmevtyper4_el0
warn: Returning zero for read from miscreg pmevtyper5_el0
warn: Returning zero for read from miscreg pmccfiltr_el0
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
25216465738695: system.terminal: attach terminal 0


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]

[gem5-users] how to add more than 1 ide disk in gem5 fullsystem

[Liyichao via gem5-users]

hi all：
 how to add more than 1 ide disks in gem5 fullsystem？

I want to see that sda sdb sdc ... in OS so that I can test some 
distribution application like ceph.





李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com


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[gem5-users] how to enable ubuntu 18.04.5 rootfs in gem5

[Liyichao via gem5-users]

Hi:

 Anyone has experience on enabling Ubuntu 18.04.5 rootfs in gem5? From 
GEM5 website, the guaidance “Creating disk images for full system mode” was 
only suite for older Ubuntu rootfs, like 14.x, but the newer version of Ubuntu 
like 18.04 has many modifications.


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
which
is intended only for the person or entity whose address is listed above. Any 
use of the
information contained herein in any way (including, but not limited to, total 
or partial
disclosure, reproduction, or dissemination) by persons other than the intended
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[gem5-users] can not bootup with "--dual" option

[Liyichao via gem5-users]

Hi All:
 I use “--dual” to bootup with 2 system, but can not bootup them, when 
I delete “--dual”, it can be bootup.

 My cmd is “./build/ARM/gem5.opt  configs/example/fs.py  
--cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1 --machine-type=VExpress_GEM5_V1 
--disk-image=expanded-aarch64-ubuntu-trusty-headless.img --cpu-clock=2.6GHz  
--mem-type=DDR4_2933_16x4_new --mem-size=8GB --dual”

 I use gdb to step, find that the gem5 still not get a event and always 
in doSimLoop()’s loop:


 186 assert(!eventq->empty());
(gdb)
187 assert(curTick() <= eventq->nextTick() &&
(gdb)

190 if (async_event && testAndClearAsyncEvent()) {
(gdb)
216 Event *exit_event = eventq->serviceOne();
(gdb)
217 if (exit_event != NULL) {
(gdb)
186 assert(!eventq->empty());
(gdb)
187 assert(curTick() <= eventq->nextTick() &&
(gdb)
190 if (async_event && testAndClearAsyncEvent()) {
(gdb)
216 Event *exit_event = eventq->serviceOne();
(gdb)
217 if (exit_event != NULL) {
(gdb)
186 assert(!eventq->empty());
(gdb)
187 assert(curTick() <= eventq->nextTick() &&
(gdb)
190 if (async_event && testAndClearAsyncEvent()) {
(gdb)
216 Event *exit_event = eventq->serviceOne();
(gdb)
217 if (exit_event != NULL) {
(gdb)
186 assert(!eventq->empty());
(gdb)


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
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[gem5-users] failed to bootup with dist-gem5.sh on ARM

[Liyichao via gem5-users]

Hi All:
 I use the GEM5 v20.0.0.1 with dist-gem5.sh, my cmd is

“bash $DIST_M5/util/dist/gem5-dist.sh -n 2 -r $DIST_M5/rundir -c 
$DIST_M5/ckptdir -s $DIST_M5/configs/dist/sw.py -f 
$DIST_M5/configs/example/fs.py --fs-args --kernel=$M5_PATH/binaries/vmlinux 
--machine-type=VExpress_GEM5_V1  
--disk-image=$M5_PATH/disks/expanded-aarch64-ubuntu-trusty-headless.img 
--cpu-clock=2GHz --mem-type=DDR4_2933_16x4_new --mem-ranks=4 --mem-size=16GB 
--sys-clock=1600MHz --num-cpus=2 --cpu-type=ArmV8KvmCPU --cf-args 
--ethernet-linkdelay=10us --ethernet-linkspeed=10Gbps -x 
$DIST_M5/build/ARM/gem5.opt --m5-args --debug-flags=DistEthernet”



 But it will fail to bootup with the error log below, any one has some 
experience on it?





root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5/rundir# vim log.0
  1 warn: CheckedInt already exists in allParams. This may be caused by the 
Python 2.7 compatibility layer.
  2 warn: Enum already exists in allParams. This may be caused by the Python 
2.7 compatibility layer.
  3 warn: ScopedEnum already exists in allParams. This may be caused by the 
Python 2.7 compatibility layer.
  4 /usr/local/lib/python2.7/dist-packages/pydot-1.4.1-py2.7.egg/pydot.py:18: 
UserWarning: Couldn't import dot_parser, loading of dot files will not be 
possible.
  5 gem5 Simulator System.  http://gem5.org
  6 gem5 is copyrighted software; use the --copyright option for details.
  7
  8 gem5 version 20.0.0.3
  9 gem5 compiled Nov  9 2020 09:24:56
10 gem5 started Nov  9 2020 16:32:32
11 gem5 executing on ubuntu-kunpeng920-1, pid 14971
12 command line: /home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt -d 
/home/l00515693/gem5_repo/gem5/rundir/m5out.0 --debug-flags=DistEthernet 
/home/l00515693/gem5_repo/gem5/configs/example/fs.py 
--kernel=/home/l00515693/fs-image_fx/binaries/vmlinux 
--machine-type=VExpress_GEM5_V1 
--disk-image=/home/l00515693/fs-image_fx/disks/expanded-aarch64-ubunt
u-trusty-headless.img --cpu-clock=2GHz --mem-type=DDR4_2933_16x4_new 
--mem-ranks=4 --mem-size=16GB --sys-clock=1600MHz --num-cpus=2 
--cpu-type=ArmV8KvmCPU --ethernet-linkdelay=10us 
--ethernet-linkspeed=10Gbps 
--checkpoint-dir=/home/l00515693/gem5_repo/gem5/ckptdir/m5out.0 --dist 
--dist-rank=0 --dist-size=2 --dist-server-name=127.0.0.1 --dist-serv
er-port=2200
13
14 info: Standard input is not a terminal, disabling listeners.
15 Global frequency set at 1 ticks per second
16   0: etherlink: DistEtherLink::DistEtherLink() link delay:1000 
ticksPerByte:800
17   0: global: DistIface() ctor rank:0
18 warn: DRAM device capacity (65536 Mbytes) does not match the address range 
assigned (16384 Mbytes)
19 info: kernel located at: /home/l00515693/fs-image_fx/binaries/vmlinux
20 warn: Highest ARM exception-level set to AArch32 but the workload is for 
AArch64. Assuming you wanted these to match.
21 warn: Sockets disabled, not accepting vnc client connections
22 warn: Sockets disabled, not accepting terminal connections
23   0: etherlink: DistEtherLink::init() called
24   0: global: Connecting to 127.0.0.1:2200
25   0: global: Connected, waiting for ack (distIfaceId:0
26 info: Link okay  (iface:0 -> switch iface:0)
27 info: Next dist synchronisation tick is changed to 52000.
28 info: Dist synchronisation interval is changed to 1000.
29 warn: Sockets disabled, not accepting gdb connections
30 warn: CoherentXBar testsys.membus has no snooping ports attached!
31 info: Using bootloader at address 0x10
32 info: Using kernel entry physical address at 0x8008
33 info: Loading DTB file: 
/home/l00515693/gem5_repo/gem5/rundir/m5out.0/testsys.dtb at address 0x8800
34  REAL SIMULATION 
35   0: etherlink: DistEtherLink::startup() called
36   0: global: DistIface::startup() started
37 gem5 has encountered a segmentation fault!
38
39 --- BEGIN LIBC BACKTRACE ---
40 
/home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(_Z15print_backtracev+0x40)[0xb1837810]
41 /home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(+0x12a41c4)[0xb18481c4]
42 linux-vdso.so.1(__kernel_rt_sigreturn+0x0)[0xa5465688]
43 
/home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(_ZN9DistIface9SyncEvent5startEv+0xc8)[0xb1a1dd08]
44 
/home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(_ZN9DistIface7startupEv+0x1b8)[0xb1a1e590]
45 
/home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(_ZN13DistEtherLink7startupEv+0x2f8)[0xb1a21628]
46 /home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(+0xf637a0)[0xb15077a0]
47 /home/l00515693/gem5_repo/gem5/build/ARM/gem5.opt(+0xd04734)[0xb12a8734]
48 
/usr/lib/aarch64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7278)[0xa5194bd0]
49 --- END LIBC BACKTRACE ---


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

[gem5-users] 答复: Re: Ethernet support for ARM FS simulation

[Liyichao via gem5-users]

hon/_m5/param_IdeController.cc
[SO PyBind] IdeDisk -> ARM/python/_m5/param_IdeDisk.cc
[SO PyBind] NSGigE -> ARM/python/_m5/param_NSGigE.cc
scons: *** [build/ARM/dev/virtio/pci.o] Error 1
scons: building terminated because of errors.
*** Summary of Warnings ***
Warning: Your compiler doesn't support incremental linking and lto at the same 
time, so lto is being disabled. To force lto on anyway, use the --force-lto 
option. That will
 disable partial linking.
Warning: While checking protoc version: [Errno 2] No such file or directory
root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim 
build/ARM/dev/pci/device.hh
root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim 
build/ARM/dev/pci/device.hh




李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
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is intended only for the person or entity whose address is listed above. Any 
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发件人: Gabe Black [mailto:gabe.bl...@gmail.com<mailto:gabe.bl...@gmail.com>]
发送时间: 2020年11月5日 21:19
收件人: gem5 users mailing list mailto:gem5-users@gem5.org>>
抄送: Liyichao mailto:liyic...@huawei.com>>
主题: Re: [gem5-users] Re: Ethernet support for ARM FS simulation

That sounds like the problem I fixed with this CL:

https://gem5-review.googlesource.com/c/public/gem5/+/35516

Gabe

On Thu, Nov 5, 2020 at 4:42 AM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi Gabe:
 I have looked at the email below, I also has the same question. As you 
mentioned, I just modified the FSConfig.py in function makeArmSystem with
“self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
   InterruptLine=1, InterruptPin=1)
pci_devices.append(self.ethernet)” without any modifications in src/***

 and use the latest img and kernel from GEM5 WEBSITE, but when I use 
fs.py to bootup , there is a fatal print “fatal: Unable to find destination for 
[0x4008:0x400c] on system.iobus”.



My cmd is:
./build/ARM/gem5.opt 
--debug-flags=AddrRanges,NoncoherentXBar,DMA,EthernetEEPROM,Ethernet 
configs/example/fs.py  --cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1 
--machine-type=VExpress_GEM5_V1 
--disk-image=expanded-aarch64-ubuntu-trusty-headless.img --cpu-clock=2.6GHz  
--mem-type=DDR4_2933_16x4_new --mem-size=8GB


My GEM5 VERSION is 20.0.0.3






You shouldn't modify your config by changing anything in src/, you should
do that in the config scripts. If you want to add additional devices, they
don't have to be part of the platform object, they just need to be
connected to the right busses, etc.

Gabe

On Fri, Aug 28, 2020 at 12:06 PM HENG ZHUO via gem5-users <
gem5-users@gem5.org<mailto:gem5-users@gem5.org>> wrote:

> Hi all,
>
> I noticed with the recent updates in ARM ISA support, now default machine
> setup is using VExpress_GEM5_V1, which is great, with the 2019 build kernel
> and boot loadert tested and everything. However, I also know that
> VExpress_GEM5 does not support ethernet device. What would be best setup if
> I want to use ethernet device, but with newer built kernel setup?
>
> 1) Shall I add ethernet device to VExpress_GEM5 machine config? This
> should be most ideal case, in terms of simulated system. Assuming I can add
> a new device in the src/dev/arm/RealView.py under VExpress_GEM5_V1. But,
> the dtb is auto generated, seems like I also need to add entry in the
> auto-generated device tree, anyone has any directions on how to add new
> devices in this scenario?
>
> 2) Can I use the old VExpress_EMM64 machine, but with newer build 2019
> kernel and boatload, my guess is not, I would assume the kernel is
> customized based on the machine VExpress_GEM5.
>
> 3) Stick with using older build (2018 build kernel and bootloader), with
> machine VExpress_EMM64. This should be working by default, but losing the
> ability to use more updated kernel and machine config.
>
> Any suggestions, insights would be appreciated!
>
> Best,
> Heng
> ___
> gem5-users mailing list -- gem5-users@gem5.org<mailto:gem5-users@gem5.org>
> To unsubscribe send an email to 
> gem5-users-le...@gem5.org<mail

[gem5-users] Re: Ethernet support for ARM FS simulation

[Liyichao via gem5-users]

Hi Gabe:
 I have looked at the email below, I also has the same question. As you 
mentioned, I just modified the FSConfig.py in function makeArmSystem with
“self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
   InterruptLine=1, InterruptPin=1)
pci_devices.append(self.ethernet)” without any modifications in src/***

 and use the latest img and kernel from GEM5 WEBSITE, but when I use 
fs.py to bootup , there is a fatal print “fatal: Unable to find destination for 
[0x4008:0x400c] on system.iobus”.



My cmd is:
./build/ARM/gem5.opt 
--debug-flags=AddrRanges,NoncoherentXBar,DMA,EthernetEEPROM,Ethernet 
configs/example/fs.py  --cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1 
--machine-type=VExpress_GEM5_V1 
--disk-image=expanded-aarch64-ubuntu-trusty-headless.img --cpu-clock=2.6GHz  
--mem-type=DDR4_2933_16x4_new --mem-size=8GB


My GEM5 VERSION is 20.0.0.3






You shouldn't modify your config by changing anything in src/, you should
do that in the config scripts. If you want to add additional devices, they
don't have to be part of the platform object, they just need to be
connected to the right busses, etc.

Gabe

On Fri, Aug 28, 2020 at 12:06 PM HENG ZHUO via gem5-users <
gem5-users@gem5.org> wrote:

> Hi all,
>
> I noticed with the recent updates in ARM ISA support, now default machine
> setup is using VExpress_GEM5_V1, which is great, with the 2019 build kernel
> and boot loadert tested and everything. However, I also know that
> VExpress_GEM5 does not support ethernet device. What would be best setup if
> I want to use ethernet device, but with newer built kernel setup?
>
> 1) Shall I add ethernet device to VExpress_GEM5 machine config? This
> should be most ideal case, in terms of simulated system. Assuming I can add
> a new device in the src/dev/arm/RealView.py under VExpress_GEM5_V1. But,
> the dtb is auto generated, seems like I also need to add entry in the
> auto-generated device tree, anyone has any directions on how to add new
> devices in this scenario?
>
> 2) Can I use the old VExpress_EMM64 machine, but with newer build 2019
> kernel and boatload, my guess is not, I would assume the kernel is
> customized based on the machine VExpress_GEM5.
>
> 3) Stick with using older build (2018 build kernel and bootloader), with
> machine VExpress_EMM64. This should be working by default, but losing the
> ability to use more updated kernel and machine config.
>
> Any suggestions, insights would be appreciated!
>
> Best,
> Heng
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
___


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
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which
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or partial
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[gem5-users] 答复: Unable to find destination for [0x40000008:0x4000000c] on system.iobus

[Liyichao via gem5-users]

I just add Ethernet object and add it to pci_device, and when I bootup with 
fs.py, NoncoherentXBAR debug print will print

“718298670320: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718306245195: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718313737680: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718321182425: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718328686845: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718336148530: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718343645250: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718351065740: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718358580940: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718366205095: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718373739545: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718381304795: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c09 cmd WriteReq
718388861575: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090018 cmd ReadReq
718396462245: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x1c090030 cmd WriteReq
718406078775: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010004 cmd WriteReq
718413834215: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001000d cmd ReadReq
718421472615: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001000d cmd WriteReq
718428923905: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001 cmd ReadReq
718436368265: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010004 cmd ReadReq
718443582395: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010008 cmd ReadReq
718450858125: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001000c cmd ReadReq
718458413365: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010010 cmd ReadReq
718465770715: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010014 cmd ReadReq
718473428365: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010018 cmd ReadReq
718480856555: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001001c cmd ReadReq
718488332870: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010020 cmd ReadReq
718495823045: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010024 cmd ReadReq
718503233140: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010028 cmd ReadReq
718510630915: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001002c cmd ReadReq
718518363255: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010030 cmd ReadReq
718525891545: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010034 cmd ReadReq
718533463340: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010038 cmd ReadReq
718541059775: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x3001003c cmd ReadReq
718548651205: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010006 cmd ReadReq
718590861065: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x30010004 cmd ReadReq
718606425460: system.iobus: recvAtomic: packet src system.iobus.slave[0] addr 
0x4008 cmd ReadReq
fatal: Unable to find destination for [0x4008:0x400c] on system.iobus, 
-1
Memory Usage: 8866120 KBytes”


My cmd is :

./build/ARM/gem5.opt --debug-flags=NoncoherentXBar configs/example/fs.py 
--dtb-file=./m5out/system.dtb --cpu-type=ArmV8KvmCPU --kernel=vmlinux -n 1 
--machine-type=VExpress_GEM5_V1 
--disk-image=expanded-aarch64-ubuntu-trusty-headless.img --cpu-clock=2.6GHz  
--mem-size=8GB


My modified in FSConfig.py is :

self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
   InterruptLine=1, InterruptPin=1)
pci_devices.append(self.ethernet)

李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] Unable to find destination for [0x40000008:0x4000000c] on system.iobus

[Liyichao via gem5-users]

Hi All:

I just add a ethernet object in dist-bigLITTLE.py on VEXPRESS_GEM5_V1, but 
AddRange debug print “fatal: Unable to find destination for 
[0x4008:0x400c] on system.iobus

So how to config the mem range in RealView.py or in any other code ?
”

The function of create Ethernet is :
def addEthernet(system, options):
# create NIC
dev = IGbE_e1000()
system.attach_pci(dev)
system.ethernet = dev

# create distributed ethernet link
system.etherlink = DistEtherLink(speed = options.ethernet_linkspeed,
 delay = options.ethernet_linkdelay,
 dist_rank = options.dist_rank,
 dist_size = options.dist_size,
 server_name = options.dist_server_name,
 server_port = options.dist_server_port,
 sync_start = options.dist_sync_start,
 sync_repeat = options.dist_sync_repeat)
system.etherlink.int0 = Parent.system.ethernet.interface
if options.etherdump:
system.etherdump = EtherDump(file=options.etherdump)
system.etherlink.dump = system.etherdump


root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5/rundir# tail -f log.0
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x8008
info: Loading DTB file: 
/home/l00515693/gem5_repo/gem5/rundir/m5out.0/system.dtb at address 0x8800
  0: system.etherlink: DistEtherLink::startup() called
  0: global: DistIface::startup() started
  0: global: DistIface::startup() done
info: Dist sync scheduled at 52000 and repeats 1000
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
194293121000: system.iobus: Received range change from slave port 
system.pci_vio_block.pio
194293121000: system.iobus: Adding range [0x2f001000:0x2f001020] for id 16
194293121000: system.iobus: Aggregating address ranges
194293121000: system.iobus: -- Adding range [0xc00:0x1000]
194293121000: system.iobus: -- Adding range [0x1000:0x102c]
194293121000: system.iobus: -- Adding range [0x1c01:0x1c0100d4]
194293121000: system.iobus: -- Adding range [0x1c06:0x1c061000]
194293121000: system.iobus: -- Adding range [0x1c07:0x1c071000]
194293121000: system.iobus: -- Adding range [0x1c09:0x1c091000]
194293121000: system.iobus: -- Adding range [0x1c0a:0x1c0a1000]
194293121000: system.iobus: -- Adding range [0x1c0b:0x1c0b1000]
194293121000: system.iobus: -- Adding range [0x1c0c:0x1c0c1000]
194293121000: system.iobus: -- Adding range [0x1c0f:0x1c0f1000]
194293121000: system.iobus: -- Adding range [0x1c10:0x1c101000]
194293121000: system.iobus: -- Adding range [0x1c13:0x1c131000]
194293121000: system.iobus: -- Adding range [0x1c14:0x1c141000]
194293121000: system.iobus: -- Adding range [0x1c17:0x1c171000]
194293121000: system.iobus: -- Adding range [0x2f001000:0x2f001020]
194293121000: system.iobus: -- Adding range [0x3000:0x4000]
194293121000: system.iobus: -- Adding range [0x8000:0x1]
fatal: Unable to find destination for [0x4008:0x400c] on system.iobus
Memory Usage: 2636564 KBytes


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] How to enable dist-gem5 on GEM5 20.0.0.3 on ARM64

[Liyichao via gem5-users]

Hi All:

 Any one use dist-gem5 to bootup successfully on GEM5 20.0.0.3 on ARM64?

 In dist-gem5 website, the example only shows for arm32, and the 
kernel/img/boot_emm/vexpress_emm is just matched for arm32.


 I want to use the latest 4.14 kernel and 
aarch64-ubuntu-trusty-headless.img from GEM5 website with KVM bootup, how to 
enable it?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
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[gem5-users] Re: How to add a new pcie device on GEM5

[Liyichao via gem5-users]

thanks all，any more better examples are welcome！






李翼超 charlie
Mobile：+86-15858232899
Email：liyic...@huawei.com<mailto:liyic...@huawei.com>


发件人： Pouya Fotouhi via 
gem5-usersmailto:gem5-users@gem5.org>>
收件人： gem5 users mailing listmailto:gem5-users@gem5.org>>
抄送： Gabe Blackmailto:gabe.bl...@gmail.com>>;Pouya 
Fotouhimailto:pfoto...@ucdavis.edu>>
主题： [gem5-users] Re: How to add a new pcie device on GEM5
时间： 2020-10-27 12:52:30

I second Gabe's suggestion. I think the IDE controller is a good starting point 
since it mostly models the controller and passes more complicated (device 
specific) functions to the disks.
I mostly templated based on the IDE controller when we started adding a PCI 
interface for GPU (see WIP here: 
https://gem5-review.googlesource.com/c/amd/gem5/+/23485).

Best,

On Mon, Oct 26, 2020 at 5:59 PM Gabe Black via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
The VirtIO device would be a pretty good example, although it does some unusual 
things as far as determining how big it's BARs are supposed to be. The IDE 
controller is a pretty simple device that's a little more representative in 
that way. A lot of the complexity is in the actual disks themselves, with the 
controller mostly just directing messages from the host to a particular disk.

Gabe

On Thu, Oct 22, 2020 at 6:37 AM Giacomo Travaglini via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi,

I’d recommend having a look at the VirtIO device….
(I don’t know if there are better examples, more experienced people are welcome 
to chime in)

Giacomo

From: Liyichao via gem5-users mailto:gem5-users@gem5.org>>
Sent: 22 October 2020 11:51
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Cc: Liyichao mailto:liyic...@huawei.com>>
Subject: [gem5-users] How to add a new pcie device on GEM5

Hi All:

 Any one has experience on how to add ad new pcie device on GEM5?

 This device can be just a demo device which has only a few basic 
operation like read,write…

 So if I want to add a pcie device,any config I need to realize? Or any 
examples?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com<mailto:liyic...@huawei.com>
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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--
Pouya Fotouhi
PhD Candidate
Department of Electrical and Computer Engineering
University of California, Davis
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[gem5-users] How to add a new pcie device on GEM5

[Liyichao via gem5-users]

Hi All:

 Any one has experience on how to add ad new pcie device on GEM5?

 This device can be just a demo device which has only a few basic 
operation like read,write…

 So if I want to add a pcie device,any config I need to realize? Or any 
examples?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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[gem5-users] Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

[Liyichao via gem5-users]

Hi All:
 I use gem5 20.1 ,and bootup with fs.py and dramsim3 model,but some 
error printed.

 As I know, gem5 20.1 new feature has departed the medium interface 
from memctrl, however, these modifications are only for the DRAM model inside 
gem5, I think external memory Dramsim3 and NVmain do not adapt to these changes.


my script:
./build/ARM/gem5.opt --debug-flags=DRAM -d ./m5out configs/example/fs.py 
--cpu-type=O3_ARM_v7a_3 --kernel=vmlinux -n 2 --machine-type=VExpress_GEM5_V1 
--disk-image=aarch64-ubuntu-trusty-headless.img --bootloader 
./system/arm/bootloader/arm64/boot.arm64 --caches --l2cache 
--checkpoint-dir=./m5out --mem-type=DRAMsim3 --mem-size=2GB

Error:
Traceback (most recent call last):
File "", line 1, in 
File "build/ARM/python/m5/main.py", line 457, in main
exec(filecode, scope)
File "configs/example/fs.py", line 339, in 
test_sys = build_test_system(np)
File "configs/example/fs.py", line 234, in build_test_system
MemConfig.config_mem(options, test_sys)
File "/home/l30005758/upstream/configs/common/MemConfig.py", line 237, in 
config_mem
mem_ctrl.dram = dram_intf
File "build/ARM/python/m5/SimObject.py", line 1337, in _setattr_
value = param.convert(value)
File "build/ARM/python/m5/params.py", line 215, in convert
return self.ptype(value)
TypeError: _init_() takes 1 positional argument but 2 were given
Error setting param MemCtrl.dram to 

李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] Why fs_bigLITTLE.py always use /dev/vda1 as its storage disks device?

[Liyichao via gem5-users]

Hi All:

 How to modify the storage device driver,virtio_blk? As I know, the 
device name using fs.py is /dev/sda1.

 Because I have met a error using fs_bigLITTLE.py when I restore from 
checkpoint, the below print in system.terminal accured, and fs.py will never 
accur.(I have tried to use fs_bigLITTLE.py and fs.py with the same 
kernel/image/dtb)

[cid:image002.png@01D6A650.1C2464F0]


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
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[gem5-users] 答复: How I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model

[Liyichao via gem5-users]

Hi Gabe：

   Thank you for your advice.

   I have seen the “Stats::registerResetCallback function in 
base/statistics.hh”, before executing m5.reset, where could I call the 
“Stats::registerResetCallback” function to register an API provided by 
NVMAIN,or is the calling of “Stats::registerResetCallback” function need to be 
in NVMAIN init process code?

李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
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发件人: Gabe Black [mailto:gabebl...@google.com]
发送时间: 2020年10月13日 13:11
收件人: gem5 users mailing list 
抄送: Liyichao 
主题: Re: [gem5-users] How I can notify the NVMAIN model when I use “m5 
resetstats” so that the NVMAIN model can also reset the stats in its model

Hi Liyichao, you can register a callback with the Stats::registerResetCallback 
function in base/statistics.hh.

Gabe

On Mon, Oct 12, 2020 at 7:15 PM Liyichao via gem5-users 
mailto:gem5-users@gem5.org>> wrote:
Hi All:


   When I use gem5 + O3 based on armv8 with NVMAIN ddr4 model, I want to 
know how I can notify the NVMAIN model when I use “m5 resetstats” so that the 
NVMAIN model can also reset the stats in its model, e.g. bandwidth, latency, 
because I will first run warmup for a few instrutions, when warmup finished I 
reset stats in GEM5, and then go on running the simulation parts.


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[gem5-users] How I can notify the NVMAIN model when I use “m5 resetstats” so that the NVMAIN model can also reset the stats in its model

[Liyichao via gem5-users]

Hi All:


   When I use gem5 + O3 based on armv8 with NVMAIN ddr4 model, I want to 
know how I can notify the NVMAIN model when I use “m5 resetstats” so that the 
NVMAIN model can also reset the stats in its model, e.g. bandwidth, latency, 
because I will first run warmup for a few instrutions, when warmup finished I 
reset stats in GEM5, and then go on running the simulation parts.


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[gem5-users] Are there any ideas to accelerate the speed of m5.checkpoint on disks?

[Liyichao via gem5-users]

Hi All:
 Are there any ideas to accelerate the speed of m5.checkpoint on disks? 
In my NVME ssd , the speed of taking checkpoint is only about 145K/s.

[cid:image001.png@01D68AAD.F3323EE0]


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

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[gem5-users] If multiple GEM5 processes that use the KVM simulation single-core are started at the same time, the performance of each KVM is affected.

[Liyichao via gem5-users]

Hi All:
 I use KVM cpu type to simulate single core, and at the same time I 
started about 10+~20+ KVM cpu, each KVM cpu in one GEM5 process, then the speed 
of per KVM cpu be slowed down heavily.If I just start one KVM cpu in GEM5 
process, the speed was 1.7G instrutions per second.

 Does anyone know why the KVM simulation speed is severely affected 
when multiple GEM5 processes start the KVM CPU at the same time?
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[gem5-users] 答复: Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

[Liyichao via gem5-users]

Hi All:
 Are there any experts who can help me to explain the features of the 
scheduleInstStop() function?


李翼超（Charlie）

华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手　　机：15858232899
电子邮件：liyic...@huawei.com
地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]

 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
This e-mail and its attachments contain confidential information from HUAWEI, 
which
is intended only for the person or entity whose address is listed above. Any 
use of the
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发件人: Liyichao
发送时间: 2020年8月7日 12:12
收件人: 'gem5-users@gem5.org' 
主题: Supplementing experiment Data///答复: How to make scheduleInstStop() function 
to stop simulate at an accurate expected instructions counts for one core 
KVM/ATOMIC/O3 CPU simulation?



Hi All:


I use the scheduleInstStop() function to let the m5.simulate() stop at a point 
instrutions as my ROI start, for example: 1(100M) instrutions, but when 
the simulate stop, I print the instructions from last start simulation to the 
end, the count always exceed my specified instrutions(100M), like 100423403, 
about 0.4% exceeded. If I set to 137579444 in O3 cpu, when simulation stop, 
totalInsts() print 121264766,about 12% instruction number error.



The more detail the CPU is or the less expected instruction we set to 
scheduleInstStop() , the more error rate the result is.

Can the scheduleInstStop() function to stop simulate at an accurate instrutions 
count?



Below is my experiment data:

SP means each ROI segment number

WT means weight each SP

KVM FF INSTS means expected fastforward instrutions  set to shceduleInstsStop 
in KVM CPU and KVM FF INSTS REAL means actural instructions when simulation 
stopped.

Thes same as DETAIL WARMUP INSTS and DETAIL WARMUP INSTS REAL, ROI START REAL

DETAIL SIM INSTS REAL means actural instructions when simulation stopped.



SP


ROI START INSTS


ROI INSTS


WT


GEM5 CPU time(s)


KVM FF INSTS REAL


KVM FF INSTS


KVM FF ERROR


DETAIL WARMUP INSTS REAL


DETAIL WARMUP INSTS


DETAIL WARMUP ERROR  RATE


ROI START REAL


ROI START ERROR


ROI START ERROR RATE


DETAIL SIM INSTS REAL


ROI ERROR


ROI ERROR RATE


253


10178192697


7961215


0.0831


235.37


10168198363


10168192697


0.56%


11769096


1000


17.69%


10179967459


1774762


0.01744%


9765795


1804580


22.67%


489


14993215251


28956263


0.0807


480.69


14985233613


14983215251


0.013471%


12670891


1000


26.71%


14997904504


4689253


0.03128%


31630388


2674125


9.24%


745


20961513684


7952028


0.0831


366.16


20951519275


20951513684


0.27%


10930605


1000


9.31%


20962449880


936196


0.00447%


9196796


1244768


15.65%


747


20985389544


7913399


0.0831


368.9


20976588014


20975389544


0.005714%


13508368


1000


35.08%


20990096382


4706838


0.02243%


8729639


816240


10.31%


1535


36747557633


71903019


0.0489


852.12


36737563780


36737557633


0.17%


13915280


1000


39.15%


36751479060


3921427


0.01067%


76114831


4211812


5.86%


1576


39801482033


72581100


0.0489


986.37


39791620332


39791482033


0.000348%


13898089


1000


38.98%


39805518421


4036388


0.01014%


76712281


4131181


5.69%


1630


41397216547


7969257


0.0831


576.6


41387222182


41387216547


0.14%


14108619


1000


41.09%


41401330801


4114254


0.00994%


12213236


4243979


53.25%


1678


41875758899


7945777


0.0831


578.1


41871459914


41865758899


0.013617%


14214926


1000


42.15%


41885674840


9915941


0.02368%


12108036


4162259


52.38%


1884


46344067975


28927369


0.0807


845.82


46334073500


46334067975


0.12%


11344254


1000


13.44%


46345417754


1349779


0.00291%


31850077


2922708


10.10%


1919


47342402174


28905117


0.0807


805.16


47332436420


47332402174


0.72%


12802266


1000


28.02%


47345238686


2836512


0.00599%


31773934


2868817


9.92%


1926


47542229035


28886691


0.0807


787.53


47534320414


47532229035


0.004400%


12709174


1000


27.09%


47547029588


4800553


0.01010%


31731786


2845095


9.85%


1940


47914392807


28885810


0.0807


761.57


47904398647


47904392807


0.12%


12542440


1000


25.42%


47916941087


2548280


0.00532%


31799566


2913756


10.09%


2756


62457880622


7895848


0.0831


504.08


62447886490


62447880622


0.09%


13888058


1000


38.88%


62461774548

[gem5-users] Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

[Liyichao via gem5-users]

Hi All:


I use the scheduleInstStop() function to let the m5.simulate() stop at a point 
instrutions as my ROI start, for example: 1(100M) instrutions, but when 
the simulate stop, I print the instructions from last start simulation to the 
end, the count always exceed my specified instrutions(100M), like 100423403, 
about 0.4% exceeded. If I set to 137579444 in O3 cpu, when simulation stop, 
totalInsts() print 121264766,about 12% instruction number error.



The more detail the CPU is or the less expected instruction we set to 
scheduleInstStop() , the more error rate the result is.

Can the scheduleInstStop() function to stop simulate at an accurate instrutions 
count?



Below is my experiment data:

SP means each ROI segment number

WT means weight each SP

KVM FF INSTS means expected fastforward instrutions  set to shceduleInstsStop 
in KVM CPU and KVM FF INSTS REAL means actural instructions when simulation 
stopped.

Thes same as DETAIL WARMUP INSTS and DETAIL WARMUP INSTS REAL, ROI START REAL

DETAIL SIM INSTS REAL means actural instructions when simulation stopped.



SP


ROI START INSTS


ROI INSTS


WT


GEM5 CPU time(s)


KVM FF INSTS REAL


KVM FF INSTS


KVM FF ERROR


DETAIL WARMUP INSTS REAL


DETAIL WARMUP INSTS


DETAIL WARMUP ERROR  RATE


ROI START REAL


ROI START ERROR


ROI START ERROR RATE


DETAIL SIM INSTS REAL


ROI ERROR


ROI ERROR RATE


253


10178192697


7961215


0.0831


235.37


10168198363


10168192697


0.56%


11769096


1000


17.69%


10179967459


1774762


0.01744%


9765795


1804580


22.67%


489


14993215251


28956263


0.0807


480.69


14985233613


14983215251


0.013471%


12670891


1000


26.71%


14997904504


4689253


0.03128%


31630388


2674125


9.24%


745


20961513684


7952028


0.0831


366.16


20951519275


20951513684


0.27%


10930605


1000


9.31%


20962449880


936196


0.00447%


9196796


1244768


15.65%


747


20985389544


7913399


0.0831


368.9


20976588014


20975389544


0.005714%


13508368


1000


35.08%


20990096382


4706838


0.02243%


8729639


816240


10.31%


1535


36747557633


71903019


0.0489


852.12


36737563780


36737557633


0.17%


13915280


1000


39.15%


36751479060


3921427


0.01067%


76114831


4211812


5.86%


1576


39801482033


72581100


0.0489


986.37


39791620332


39791482033


0.000348%


13898089


1000


38.98%


39805518421


4036388


0.01014%


76712281


4131181


5.69%


1630


41397216547


7969257


0.0831


576.6


41387222182


41387216547


0.14%


14108619


1000


41.09%


41401330801


4114254


0.00994%


12213236


4243979


53.25%


1678


41875758899


7945777


0.0831


578.1


41871459914


41865758899


0.013617%


14214926


1000


42.15%


41885674840


9915941


0.02368%


12108036


4162259


52.38%


1884


46344067975


28927369


0.0807


845.82


46334073500


46334067975


0.12%


11344254


1000


13.44%


46345417754


1349779


0.00291%


31850077


2922708


10.10%


1919


47342402174


28905117


0.0807


805.16


47332436420


47332402174


0.72%


12802266


1000


28.02%


47345238686


2836512


0.00599%


31773934


2868817


9.92%


1926


47542229035


28886691


0.0807


787.53


47534320414


47532229035


0.004400%


12709174


1000


27.09%


47547029588


4800553


0.01010%


31731786


2845095


9.85%


1940


47914392807


28885810


0.0807


761.57


47904398647


47904392807


0.12%


12542440


1000


25.42%


47916941087


2548280


0.00532%


31799566


2913756


10.09%


2756


62457880622


7895848


0.0831


504.08


62447886490


62447880622


0.09%


13888058


1000


38.88%


62461774548


3893926


0.00623%


11734236


3838388


48.61%




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[gem5-users] How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

[Liyichao via gem5-users]

Hi All:


I use the scheduleInstStop() function to let the m5.simulate() stop at a point 
instrutions as my ROI start, for example: 1(100M) instrutions, but when 
the simulate stop, I print the instructions from last start simulation to the 
end, the count always exceed my specified instrutions(100M), like 100423403, 
about 0.4% exceeded. If I set to 137579444 in O3 cpu, when simulation stop, 
totalInsts() print 121264766,about 12% instruction number error.



The more detail the CPU is or the less expected instruction we set to 
scheduleInstStop() , the more error rate the result is.

Can the scheduleInstStop() function to stop simulate at an accurate instrutions 
count?



___
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