e data structure was freed
by then. When does gem5 free user defined data structures defined within
base.cc <http://base.cc/>?
Thanks in advance.
With regards
Shyam Murthy
Computer Science
UW Madison ___
gem5-users mailing list
gem5-users@g
. You can definitely implement new instructions and
> submit the code for review. There are instructions in the CONTRIBUTING.md
> file in the root of the gem5 source tree.
>
> Gabe
>
> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy
> wrote:
>
>> Apologize for the wrong
): Assertion `flatIndex < TheISA::NumIntRegs'
failed.*
I just wanted to know what I was missing in my implementation for FRNDINT
macroop?
Thanks,
Shyam
On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy
wrote:
> Thanks a lot for the clarification Gabe.
>
> Thanks,
> Shyam
>
> On Sun,
Apologize for the wrong title in my previous email. Correcting.
Thanks,
Shyam
On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy
wrote:
> Hi Gabe,
>
> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
> unimplemented instructions namely *frndint*, *fsqrt* and *fi
Hi Gabe,
As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
unimplemented instructions namely *frndint*, *fsqrt* and *fistp* to name a
few. I see that within the *src/arch/x86/isa/insts/x87/**arithmetic*
folder, there are placeholder files to write implementations for some of
the
Hi Jason,
Any thoughts on this?
Thanks,
Shyam
> On Mar 8, 2019, at 4:26 PM, Shyam Murthy wrote:
>
> Hi All,
>
> When I am running a lot of the SPEC '17 applications on gem5, I am getting a
> warning message that says warn: instruction 'movntdq_Mo_Vo' unimplemented.
Hi All,
When I am running a lot of the SPEC '17 applications on gem5, I am getting
a warning message that says *warn: instruction 'movntdq_Mo_Vo'
unimplemented*. The source code for the binary does not seem to indicate
the usage of the movntdq instruction.
I assume it is the glibc that is using
Hi,
I am using se.py within config/example.
Thanks,
Shyam
> On Mar 11, 2019, at 11:42 PM, SM Farabi Mahmud wrote:
>
> Can you share the configuration file that you're using?
>
> On Fri, Mar 8, 2019, 4:26 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
Hi Gabe,
Any thoughts on the below?
Thanks,
Shyam
> On Apr 13, 2019, at 10:21 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> One additional question, regarding another instruction I was trying to
> implement (FCMOVNBE).
> I thought of emulating a sequence similar what we ha
Hi Jason,
I am trying to hit the start of the ROI for an application and then switch
to the Detailed CPU. For this, I wrote my version of the run function in
Simulation.py. I am able to successfully intercept the start of workbegin,
however I am unable to successfully CPUs.
using movfp for FCMOVNBE. Is there
an alternate microop I can make use of, or should I implement a microop or is
there an alternate workaround?
Thanks,
Shyam
> On Apr 13, 2019, at 6:57 PM, Shyam Murthy wrote:
>
> Hi Gabe,
>
> Thanks for the help with the FRNDINT instruction.
), you could use the mov2fp microop
> to move the newly converted value in an integer microcode only register
> (like t1, for instance) back into an FP register like st(0).
>
> Gabe
>
> On Fri, Apr 5, 2019 at 6:53 PM Shyam Murthy
> wrote:
>
>> Hi Gabe,
>>
>&g
Thanks for the information Ciro.
Thanks,
Shyam
On Sun, May 19, 2019 at 3:07 PM Ciro Santilli
wrote:
> On Sun, May 19, 2019 at 8:04 PM Shyam Murthy
> wrote:
> >
> > Hi Gabe,
> >
> > Within the file src/cpu/o3/iew_impl.hh, there is a call made to execute
> funct
Hi Gabe,
Within the file src/cpu/o3/iew_impl.hh, there is a call made to execute
function within the dynamic inst class (inst->execute()). I was trying to
lookup the function definition for this, but I could only find the function
prototype within src/cpu/o3/dyn_inst.hh (Fault execute()). Where
gt; Hope this helps!
> Gururaj
>
> From: gem5-users on behalf of Gabe Black <
> gabebl...@google.com>
> Reply-To: gem5 users mailing list
> Date: Sunday, June 30, 2019 at 10:42 PM
> To: Shyam Murthy
> Cc: gem5 users mailing list
> Subject: Re: [gem5-users] SPECCPU 20
es have that behavior (so most of
> them), not just lea.
>
> Gabe
>
> On Wed, Jul 31, 2019 at 8:06 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> Thanks Gabe, suppose I’m trying to carry out a data flow analysis on the
> program, then quite
Hi All,
I had a couple of questions about how loads are scheduled in O3 CPU on
gem5. Does the instruction schedule happen for a load expecting a cache
hit? Is there a replay in case of a miss?
I see that code defers memory instructions on a TLB miss. Is there similar
code that handles loads that
ed folks may correct me if I am wrong.
Cheers,
Gururaj
From: gem5-users mailto:gem5-users-boun...@gem5.org>> on behalf of Shyam Murthy
mailto:shyammurth...@gmail.com>>
Reply-To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Date: Friday, August 16, 2019 at 4:50 PM
To: gem5
Hi All,
I had one question regarding write buffers in Classic cache. When we have a
write back operation, the assumption is that we will find an entry to place
the block that is to be written back. There seems to be an assert within
src/mem/cache/write_queue.cc file (*assert(!freeList.empty())*).
Hi Gabe,
Why is that for some of the operations like ld and lea, the decoding logic
within *build/X86/arch/generated/decoder-ns.cc.inc, *the destination
register is also decoded as a src register?
Thanks,
Shyam
___
gem5-users mailing list
understanding something incorrectly?
Thanks,
Shyam
On Tue, Jul 30, 2019 at 2:25 PM Shyam Murthy
wrote:
> Hi Gabe,
>
> Why is that for some of the operations like ld and lea, the decoding logic
> within *build/X86/arch/generated/decoder-ns.cc.inc, *the destination
> register is also d
re either writing all 64 bits or zero extending to 64
> bits in the 32 bit case. That optimization is not implemented, and may or may
> not be realistic.
>
> Gabe
>
> On Tue, Jul 30, 2019 at 2:40 PM Shyam Murthy <mailto:shyammurth...@gmail.com>> wrote:
> The mai
E, Bureau E321, Campus de Beaulieu,
> 35042 Rennes Cedex, France
>
> --
>
> *From: *"Shyam Murthy"
> *To: *"gem5 users mailing list"
> *Sent: *Sunday, June 30, 2019 7:02:37 PM
> *Subject: *[gem5-users] SPECCPU 2006 application crashes on
Hi All,
I am trying to run some of the FP applications from SPECCPU 2006. However,
for some of these applications (like povray, tonto), I get an error that
says:
warn: instruction 'movntdq_Mo_Vo' unimplemented.
I am compiling these applications on my machine, and then running them on
x86 gem5.
/bits/stdlib-float.h:26:1: error: SSE
register return with SSE disabled*
Thanks,
Shyam
On Sun, Jun 30, 2019 at 3:24 PM Shyam Murthy
wrote:
> Hi,
>
> This is slightly different, there is no panic message here. However, this
> instruction is unimplemented, but is required by the applica
t; https://gem5.atlassian.net/browse/GEM5-338
> https://gem5.atlassian.net/browse/GEM5-732
> https://gem5.atlassian.net/browse/GEM5-720
>
> Some of those have been resolved and will be part of the 20.1 release
> (coming in a couple of weeks).
>
> Cheers,
> Jason
>
> On Wed,
Hi,
I was running a few applications on gem5 using the O3CPU model and X86 ISA.
I observed that gem5 reports BTB hits/lookups to be 0. All predicted taken
branches (direct jumps, conditional jumps predicted taken as well as
indirect jumps) consult with the indirect predictor and use up space in
Hi All,
Is there any other target predictor for indirect jumps on gem5 apart from
simple indirect predictor?
Thanks,
Shyam
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