[gem5-users] Build issues using non-default location for dependencies

Hi all, I am trying to build gem5 on a server system (RHEL6) where I don’t have nor will have administrator privileges. Normally that should not pose too much problems, as installing all dependencies can be done in user locations and pointed to using environment variables (as well as reading the

Re: [gem5-users] Build issues using non-default location for dependencies

at all, right? Then why is the build not working? I think this may be a bug somewhere. On Wed, Nov 29, 2017 at 9:44 AM, Timon Evenblij wrote: > Hi all, > > > > I am trying to build gem5 on a server system (RHEL6) where I don’t have > nor will have administrator privileges. Normally

Re: [gem5-users] About multiple cache copies and a related comment called "on the same path to memory"

Hi gjins, To the best of my knowledge, your reasoning is correct. If a packet goes from cpu to the memory, it passes the local caches and then the shared caches on its way to memory. Local caches from other cpu's are not passed, thus meaning they are not on the path to memory. It could be interest

[gem5-users] Regression tests

Hi all, It seems like the regression tests don't pass at all in the recent gem5 builds? Are they still being used/developed or are they all outdated? The wiki page about the regression tests is a little old (2015), so I thought I'd ask it over here. Regards

[gem5-users] Configuration visualizer

Hi all, I thought I once came across a tool to visualize the configuration used for a simulation in gem5, but I didn't look into it at the moment. Right now, this would be very useful, especially to visualize the configuration used for the memory hierarchy (i.e. how all memory objects are connecte

Re: [gem5-users] Configuration visualizer

low. > [image: 본문 이미지 1] > > Best regards > > Haeyoon Cho > > 2018-01-03 23:06 GMT+09:00 Timon Evenblij : > >> Hi all, >> >> I thought I once came across a tool to visualize the configuration used >> for a simulation in gem5, but I didn't look into it

[gem5-users] Switching between Fastforwarding, Warmup, Detailed: Sampling long benchmarks

Hi all, I have some questions regarding the switching of CPU models during simulation. The se.py script provides some useful options, but does not seem to offer me what I (and with my I guess a lof others) want: The ability to sample a long benchmark by alternating between fastforwarding (the atom

Re: [gem5-users] Switching between Fastforwarding, Warmup, Detailed: Sampling long benchmarks

; Basically, you'll have to call m5.switchCpus from your own script or from > a modified se.py. The documentation for this isn't great. The code is > probably your best bet. The code for switching CPUs is in > src/python/m5/simulate.py. > > Let us know if you have more que

[gem5-users] Simulation on multiple cores

Hi all, I have been reading into using multiple threads for a system simulation, but so far, the only existing option is dist-gem5, but this limits the parallel simulation to distributed systems if I am correct. Am I missing something or are all simulations where 1 (multicore or not) machine is si

[gem5-users] Different cacheline size for instruction cache

Hi all, I'd like to model an L1 instruction cache with a smaller cache line size then the rest of the caches (L1 data cache, L2 cache, ...). After searching a little bit, it seems like the cacheline size is specified system-wide, and questions related to different cache line sizes for L2 caches ha

[gem5-users] M5threads and a detailed cpu model (O3 and Minor)

Hi all, I am looking into simulating some multithreaded benchmarks in se mode. I compiled m5threads both for x86 and arm. Running binaries linked to m5threads works fine natively, as well as when simulating a processor in the atomic model. However, when simulating an* out-of-order detailed model *

[gem5-users] Full-system restoring from checkpoint with different runscript

Hi all, A quick question: Is it possible to restore from a checkpoint with a different runscript then used during the first boot? This way, I could run a lot of benchmarks without losing time waiting for gem5 to boot. I know I could boot interactively and then checkpoint, but restoring then requir

[gem5-users] adding benchmarks to disk images results in unreadable inode blocks

Hi all, I have some issues regarding full-system simulation. I want to add some benchmarks to an image file so I can run them. I can resize an image file, mount it, add (cross)compiled benchmarks to it, e.g. parsec without problems. But when I boot gem5 on that disk image, trying to run a benchmar

Re: [gem5-users] Full-system restoring from checkpoint with different runscript

seems to be working, but I want to be sure I don't run into issues because of this. Regards Timon On Wed, Mar 21, 2018 at 4:47 PM, Ciro Santilli wrote: > On Wed, Mar 21, 2018 at 10:12 AM, Timon Evenblij > wrote: > > Hi all, > > > > A quick question: Is it possible

Re: [gem5-users] adding benchmarks to disk images results in unreadable inode blocks

module-cheat/tree/ > 29908dffb2726b0819fdf95240ae513dddb8af48#parsec-benchmark > and never encountered those problems. > > Please also provide more detailed reproduction steps if you can. > > On Fri, Mar 23, 2018 at 1:45 PM, Timon Evenblij > wrote: > > Hi all, >

Re: [gem5-users] Full-system restoring from checkpoint with different runscript

second disk with the workloads on it. > > Jason > > On Fri, Mar 23, 2018 at 7:18 AM Timon Evenblij > wrote: > >> Thanks, the hack_back script works great! >> Another follow up question, can we resume checkpoints with different disk >> images? I guess th

[gem5-users] PARSEC illegal instruction

Hi all, So I cross-compiled some parsec bechmarks, e.g. ferret. First I tried putting them in the disk image that gem5 uses to boot, but that did not work out (inodes were not readable or something, see my other mail thread). Jason suggested then to use a second disk image and add it to the simula

[gem5-users] cache bank contention

Hi all, I have some questions regarding how gem5 models cache banks. In fact, I cannot find that gem5 models cache banks at all. Is this true? Why this is important: It looks as of right now that gem5 caches can process all requests in parallel, unless the requests go to the same cache block. Thi

Re: [gem5-users] cache measurement within FS emulation

Hi Andreas, You can just call /sbin/m5 dumpresetstats from within your runscript before each benchmark. The dumped stats will contain all cache related metrics. regards Timon On Thu, May 3, 2018 at 3:52 PM Andreas Konopik wrote: > Dear gem5-devs, > > I would like to start, stop and output cac

Re: [gem5-users] How to attach multiple disk images a simulation with gem5 fs.py?

With fs.py, I had it working at some point with a small ugly hack to FSConfig.py I think. It is on another machine so I cannot check right now. I will probably make a cleaner way of doing this in the near future. However, the same method did not apply to a custom full-system script I am working on

Re: [gem5-users] How to attach multiple disk images a simulation with gem5 fs.py?

2018 at 6:43 AM Ciro Santilli > wrote: > >> Thanks for confirming, >> >> Feel free to CC me directly if you end up submitting a patch. >> >> On Fri, Jun 15, 2018 at 1:37 PM, Timon Evenblij > > wrote: >> >>> With fs.py, I had it working at som

[gem5-users] Full system determinism

Hi all, I recently ran some parsec benchmarks on ARM in full-system mode, to evaluate the performance hit of a couple of scenarios using a cache with higher latencies. However, I found that in some cases, the performance increased instead of decreased (up to 20% lower execution time!), while runn

Re: [gem5-users] Cache Management

Hi Abishek, No, for this case, MSHRs (miss status handling registers) exists. These are registers that keep track of missed cache accesses (in your case packet 1 that misses in L1), so the cache can be freed to reply to other accesses (packet 2) while waiting for the answer of the miss (packet 1 g

Re: [gem5-users] Cache Management

t; update contents in memory ? > > On Thu, Aug 2, 2018 at 4:04 AM Timon Evenblij > wrote: > >> Hi Abishek, >> >> No, for this case, MSHRs (miss status handling registers) exists. These >> are registers that keep track of missed cache accesses (in your case pac

Re: [gem5-users] Checkpoint Creation in SE mode

Hi Sakshi, I did not check completely, but at first sight you are misinterpreting the --restore-with-cpu option. https://stackoverflow.com/questions/49011096/how-to-switch-cpu-models-in-gem5-after-restoring-a-checkpoint-and-then-observe-t has information on what it does: use --restore-with-cpu onl

Re: [gem5-users] Doubling system clock freq doesn't halve simulated time?

Hi, I could be mistaken but I would say there are still some (perhaps default) latency parameters in your configuration that use a time-based value instead of a cycle-based value, or use a cycle-based value that is based on a different clock. The main memory comes to mind first, as this often has