[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason: Thank you for your reply, thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hi Zhen,
Sorry for missing your previous message.
(1) I think the biggest difference is that the former does not implement a
port for each bank, is it right?
- I guess it assumes that the banks are the bottlenecks not the ports. It
assumes that the banks are distributed and have separate ports, IIRC.
For the L1TagArrayRead... If the transition reads both the I-cache tag and
the L1 tag, then yes. I don't have a definitive answer for you. It depends
on how you want to model the performance.
Cheers,
Jason
On Sat, Jan 23, 2021 at 4:07 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:
> Hello Jason:
> I have tag every transition in the cache controller (i.e.,
> MESI_Three_Level-L0cache.sm) with the required resources, but there is
> something wrong, during the
> implementation of the L0 multi-bank, I have doubt whether need to add L1
> RequestType? It also means require L1 cache resources.
> for example:
> transition(I, Ifetch, Inst_IS) {ITagArrayRead}{
> pp_allocateICacheBlock;
> i_allocateTBE;
> a_issueGETS;
> uu_profileInstMiss;
> po_observeMiss;
> k_popMandatoryQueue;
> debugTransition1;
> }
> Instruction fetch missed in the L0, should I add L1TagArrayRead like this:
> transition(I, Ifetch, Inst_IS) {ITagArrayRead, L1TagArrayRead}
>
> Looking forward to your reply.
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[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason:
I have tag every transition in the cache controller (i.e.,
MESI_Three_Level-L0cache.sm) with the required resources, but there is
something wrong, during the
implementation of the L0 multi-bank, I have doubt whether need to add L1
RequestType? It also means require L1 cache resources.
for example:
transition(I, Ifetch, Inst_IS) {ITagArrayRead}{
pp_allocateICacheBlock;
i_allocateTBE;
a_issueGETS;
uu_profileInstMiss;
po_observeMiss;
k_popMandatoryQueue;
debugTransition1;
}
Instruction fetch missed in the L0, should I add L1TagArrayRead like this:
transition(I, Ifetch, Inst_IS) {ITagArrayRead, L1TagArrayRead}
Looking forward to your reply.
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[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason:
Comparing resource stalls to model banking with "real banking",
(1) I think the biggest difference is that the former does not implement a port
for each bank, is it right?
(2) I have read MOESI_AMD_Base-corepaire.sm that you have mentioned, during the
implementing L0 multi-bank, I have doubt whether need to add L1 RequestType?
(In part of the transition of L0cache, the tagarray or dataarray of L1 should
be accessed?)
enumeration(RequestType, desc="To communicate stats from transitions to
recordStats") {
IDataArrayRead,desc="Read the data array";
IDataArrayWrite, desc="Write the data array";
ITagArrayRead, desc="Read the data array";
ITagArrayWrite,desc="Write the data array";
DDataArrayRead,desc="Read the data array";
DDataArrayWrite, desc="Write the data array";
DTagArrayRead, desc="Read the data array";
DTagArrayWrite,desc="Write the data array";
for example, should I add L1DataArrayRead ?
Looking forward to your reply.
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[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello, (1) Yes, I believe so. (2) I thought MOESI_hammer was annotated, but it doesn't look like (huh...). However, AMD MOESI Base is annotated. See all of the transition in the core-pair file, for instance: https://gem5.googlesource.com/public/gem5/+/refs/tags/v20.1.0.0/src/mem/ruby/protocol/MOESI_AMD_Base-CorePair.sm#2480 Cheers, Jason On Thu, Oct 29, 2020 at 5:54 AM zhen bang via gem5-users < gem5-users@gem5.org> wrote: > Hello Jason: > (1) Can I use resource stalls to simulate the multi-bank implementation of > L0 and L1, and model L2 a distributed cache? By the way, the > implementation of L2 multi-bank in gem5 is not interleaving (multi-bank), > right? > (2) "add annotations to the transitions in the L0 and L1 cache", I am not > sure how this should be done, could you give me an example? > > Looking forward to your reply. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason: (1) Can I use resource stalls to simulate the multi-bank implementation of L0 and L1, and model L2 a distributed cache? By the way, the implementation of L2 multi-bank in gem5 is not interleaving (multi-bank), right? (2) "add annotations to the transitions in the L0 and L1 cache", I am not sure how this should be done, could you give me an example? Looking forward to your reply. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello,
For (1), yes. You can set this *in the python configuration file*. You
should not modify the SimObject description file to change a default
parameter.
For (2), yes, that's exactly where you should modify.
Cheers,
Jason
On Wed, Oct 28, 2020 at 9:47 AM zhen bang via gem5-users <
gem5-users@gem5.org> wrote:
> Hello Jason:
> I would use the resource stalls to model banking, I have read
> src/mem/ruby/structures/Rubycache.py and
> src/mem/ruby/structures/BankedArray.cc
> (1) I have seen
> dataArrayBanks = Param.Int(1, "Number of banks for the data array")
> tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
>
> If I want to configure multiple banks, can I directly modify these
> parameters?
>
> (2) To extend the BankedCache implementation to model arbitrary address
> interleaving, which files or functions should I modify?
> Should I modify the following function in
> src/mem/ruby/structures/BankedArray.cc?
> unsigned int
> BankedArray::mapIndexToBank(int64_t idx)
> {
> if (banks == 1) {
> return 0;
> }
> return idx % banks;
> }
>
> Looking forward to your reply.
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[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason:
I would use the resource stalls to model banking, I have read
src/mem/ruby/structures/Rubycache.py and src/mem/ruby/structures/BankedArray.cc
(1) I have seen
dataArrayBanks = Param.Int(1, "Number of banks for the data array")
tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
If I want to configure multiple banks, can I directly modify these parameters?
(2) To extend the BankedCache implementation to model arbitrary address
interleaving, which files or functions should I modify?
Should I modify the following function in
src/mem/ruby/structures/BankedArray.cc?
unsigned int
BankedArray::mapIndexToBank(int64_t idx)
{
if (banks == 1) {
return 0;
}
return idx % banks;
}
Looking forward to your reply.
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[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason: Resource stall, you mean there is only one bank, but we use resource stall to implement interleaving bank? I want to config multi banks of L0 and L1 to improve the parallelism of cache，and the number of banks can point by defined L0_bank_number arguments in .py scripy，if I want to do this, should I implement "real" banking? If I want to implement "real" banking, I should add L0_select_number_bits refer to L1_select_number_bits？I have been added L0_select_number_bits, but L1 becomes shared cache, no more private for one cpu. Maybe the reason is that I connect L0 to ruby network. As I know, bank interleaving is a basic multi banks cache solution. But I don't know how to define bank index，and how to find data when config multi banks? For example, how a set associate cache bank stores data? A bank store a complete cache line or just a few bytes? If the cache line is 8 bytes and the private L0 is divided into four banks, does each bank store only 2 bytes of data? I wonder whether multi-bank L0 and L1 cache will affect the MESI Coherence Protocol ? I fell doubt about the details, Looking forward to your reply. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
In this case, I would use the resource stalls to model banking. You can extend the BankedCache implementation to model arbitrary address interleaving, if that's important to your model. To do this, you'll have to add annotations to the transitions in the L0 and L1 cache, but this should be easier than implementing "real" banking. Cheers, Jason On Wed, Oct 21, 2020 at 8:20 AM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > Hello Jason: > I want to configure L0 and L1 as Multi-Banking (Interleaving) Caches , > considering L0 and L1 are private, so I have two questions: > (1). If L0 and L1 are configured as multiple banks, do I need to connect > L0 to the ruby network? > > (2). To configure multiple banks, should I need to add a cache controller > for each bank? > > Looking forward to your reply. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello Jason: I want to configure L0 and L1 as Multi-Banking (Interleaving) Caches , considering L0 and L1 are private, so I have two questions: (1). If L0 and L1 are configured as multiple banks, do I need to connect L0 to the ruby network? (2). To configure multiple banks, should I need to add a cache controller for each bank? Looking forward to your reply. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Configure multi-bank cache in ruby mode with MESI coherence protocol
Hello, It depends on how you want to model banking. If you just want to set and limit the bandwidth to a cache, you can use the "resourceStalls = true" option on the RubyCache object and set the tag and data array values. You will also have to tag every transition in the cache controller (i.e., MESI_Two_Level-L2cache.sm) with the required resources (see MOESI_hammer for an example). If you want to model a distributed cache, then you can configure your "L2" caches to have a slice of the address range and update the "mapAddressToRange" function to map the addresses to the correct distributed caches. This could be as simple as setting the l2_select_num_bits parameter on the "L1" caches. Cheers, Jason On Wed, Oct 14, 2020 at 7:15 PM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > I want to implement multi-bank cache in ruby mode， and I use the > MESI_Three_Level protocol to maintain the consistency of the three-level > cache. Which scripts should I modify to realize multi-bank cache ？ > > （1) Do I need to modify all the .sm files in src/mem/ruby/protocol/, such > as, MESI_Three_Level-L0cache.sm , L1cache.sm > To Modify variables such as out_msg.Dest in the above script ? > > (2） Or the implementation of multi-bank cache is independent of the > protocol and should not be modified in the above script ？ > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
