This is also needed to fix failing IGT test case kms_cursor_crc on ICL.
On Tue, 2019-03-05 at 17:26 -0800, Aditya Swarup wrote:
> Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
> to passthrough FB pixels unmodified across pipe. This fixes the
> failures
> for DP link layer
== Series Details ==
Series: series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
URL : https://patchwork.freedesktop.org/series/57628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12388
Summary
Hi José,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.0 next-20190305]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
== Series Details ==
Series: series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
URL : https://patchwork.freedesktop.org/series/57628/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/psr: Remove PSR2 FIXME
Okay!
Commit:
Hi José,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.0 next-20190305]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
== Series Details ==
Series: drm/i915/icl: Remove alpha support protection
URL : https://patchwork.freedesktop.org/series/57609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12382_full
Summary
Other features like PSR2 also needs to be disabled while getting CRC
so lets rename ips_force_disable to crc_enabled, drop all this checks
for pipe A and HSW and BDW and make it generic and
hsw_compute_ips_config() will take care of all the checks removed
from here.
v2: Renaming and parameter
The support for PSR2 was polished, IGT tests for PSR2 was added and
it was tested performing regular user workloads like browsing,
editing documents and compiling Linux, so it is time to enable it by
default and enjoy even more power-savings.
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
All of this checks are redudant and can be removed as the if bellow
already takes care when there is no changes in the state.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 12
1 file changed, 4
When PSR2 is active aka after the number of frames programmed in
PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
interruptions causing IGT tests to fail due timeout.
This same behavior don't happen with PSR1, as soon as pipe CRC is
enabled it blocks PSR1 activation so CRC
If PSR is active when pipe CRC is enabled the CRC calculations will
be inhibit by the transition to low power states that PSR brings.
So lets for a PSR exit and as soon as pipe CRC is enabled it will
block PSR activation avoid CRC timeouts when running IGT tests.
Cc: Dhinakaran Pandiyan
Cc:
If has_psr is set it means that CRTC has a EDP panel attached so it
can be dropped, also has_psr is better than check for EDP output
alone as it will avoid set mode_changed when PSR is not supported in
panel or with current modeset.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Reviewed-by: Rodrigo
In any commit, intel_modeset_pipe_config() will initialilly clear
and then recalculate most of the pipe states but it leave intel
specific color features states in reset state.
If after intel_pipe_config_compare() is detected that a fastset is
possible it will mark update_pipe as true and unsed
Now we are checking sink capabilities when probing PSR DPCD register
and then dynamically checking in if new state is compatible with PSR
in, so this FIXME can be dropped.
Reviewed-by: Dhinakaran Pandiyan
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
Forcing a specific CRTC to the eDP connector was causing the
intel_psr_fastset_force() to mark mode_chaged in the wrong and
disabled CRTC causing no update in the PSR state.
Looks like our internal state track do not clear output_types and
has_psr in the disabled CRTCs, not sure if this is the
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/57607/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12381_full
== Series Details ==
Series: drm/i915: Use i915_global_register() (rev2)
URL : https://patchwork.freedesktop.org/series/57605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12380_full
Summary
---
== Series Details ==
Series: drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
URL : https://patchwork.freedesktop.org/series/57619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12387
== Series Details ==
Series: drm/i915/icl: split pll functions
URL : https://patchwork.freedesktop.org/series/57618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12386
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915: Populate pipe_offsets[] & co. accurately
URL : https://patchwork.freedesktop.org/series/57600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12378_full
Summary
== Series Details ==
Series: series starting with [v2] drm/i915/guc: Fixing error code for WOPCM
initialization (rev2)
URL : https://patchwork.freedesktop.org/series/57551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12385
Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
to passthrough FB pixels unmodified across pipe. This fixes the failures
for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
(Lineage #1605353570)
Cc: Clint Taylor
Cc: Mika Kahola
Cc: Jani Nikula
Signed-off-by:
This allows us to share the icl_pll_enable() between the different types
of PLL while allowing the caller to differentiate how to write the
registers.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 --
1 file changed, 8 insertions(+), 10
Like was done for MG and combo, now finish the per-type split of the
vfunc by moving TBT out of the combo functions. Now we can completely
remove icl_pll_id_to_enable_reg() since each PLL type pass as all the
information via arguments.
Signed-off-by: Lucas De Marchi
---
Let's start using the vfuncs to differentiate MG and Combo PLLs. The end
goal is to decouple the type of the PLL from the IDs since the latter
are likely to change from one platform to another. This also makes the
code easier to read by not having lots of if/else chains on leaf
functions.
This is only used in intel_display() and shouldn't be needed there.
We don't want to keep converting from pll id to pll type so just remove
the function.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 5 -
2 files
Like was done in the enable case, split the implementation of the
disable for MG and Combo PLLs.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git
This should achieve a similar goal as in
https://patchwork.freedesktop.org/patch/287567/?series=57116=1,
decoupling the PLL ids from the type.
I actually prefer the other implementation in which we can use the
pll_info struct to store the info about the pll rather than spreading
that across
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
v2: change the final return code in i915_pci_probe() to ENODEV
instead of the specific wopcm change. - Daniele
Cc: Daniele
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12384
On 3/5/19 2:06 PM, Daniele Ceraolo Spurio wrote:
On 3/5/19 2:05 PM, Daniele Ceraolo Spurio wrote:
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57615/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/vbt: Parse
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57615/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6bfff5b6e1e0 drm/i915/vbt: Parse and use the
A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.
v2: replacing enum to numerical usec time (Jani)
BSpec: 20131
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de
This will make hsw_activate_psr1() more easy to read and will make
future modification to TPS registers more easy to review and read.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 56 +++-
1 file changed, 33
TPS4 support was added to PSR because HBR3/PSR spec was not closed
when ICL was freezed so if HBR3 was supported by PSR, ICL would
already be ready but it was not added to spec so lets always
disable TPS4.
v3: Missed ";" SPANK SPANK SPANK!!!
BSpec: 17524
Cc: Dhinakaran Pandiyan
Signed-off-by:
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57614/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK
== Series Details ==
Series: drm/i915/icl: Remove alpha support protection
URL : https://patchwork.freedesktop.org/series/57609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12382
Summary
---
A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.
v2: replacing enum to numerical usec time (Jani)
BSpec: 20131
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de
TPS4 support was added to PSR because HBR3/PSR spec was not closed
when ICL was freezed so if HBR3 was supported by PSR, ICL would
already be ready but it was not added to spec so lets always
disable TPS4.
BSpec: 17524
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
This will make hsw_activate_psr1() more easy to read and will make
future modification to TPS registers more easy to review and read.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 56 +++-
1 file changed, 33
On Tue, Mar 05, 2019 at 02:11:53PM -0800, José Roberto de Souza wrote:
> Now with the watermarks fixes merged, Icelake is stable enough to
> have the alpha support protection flag removed.
>
> We have a few ICL machines in our CI and it is mostly green with
> failures in tests that will not
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/57607/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12381
Summary
== Series Details ==
Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the
engine's mask
URL : https://patchwork.freedesktop.org/series/57595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5706_full -> Patchwork_12375_full
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/57607/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/cml: Add CML PCI IDS
Okay!
Commit: drm/i915/cml:
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/57607/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b6b26a8b48bc drm/i915/cml: Add CML PCI IDS
-:41: ERROR:COMPLEX_MACRO: Macros with complex
== Series Details ==
Series: drm/i915: Use i915_global_register() (rev2)
URL : https://patchwork.freedesktop.org/series/57605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12380
Summary
---
Now with the watermarks fixes merged, Icelake is stable enough to
have the alpha support protection flag removed.
We have a few ICL machines in our CI and it is mostly green with
failures in tests that will not impact future linux installations.
Also there is no warnings, errors, flickering or
On 3/5/19 2:05 PM, Daniele Ceraolo Spurio wrote:
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
To clarify, we want to
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
To clarify, we want to silence this:
Cc: Daniele Ceraolo Spurio
Cc:
== Series Details ==
Series: drm/i915: Use i915_global_register()
URL : https://patchwork.freedesktop.org/series/57605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12379
Summary
---
**SUCCESS**
From: Anusha Srivatsa
Comet Lake is a Intel Processor containing Gen9
Intel HD Graphics. This patch adds the initial set of
PCI IDs. Comet Lake comes off of Coffee Lake - adding
the IDs to Coffee Lake ID list.
More support and features will be in the patches that follow.
v2: Split IDs
From: Anusha Srivatsa
Comet Lake PCH is based off of Cannon Point(CNP).
Add PCI ID for Comet Lake PCH.
v2: Code cleanup (DK)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
2
Rather than manually add every new global into each hook, use
i915_global_register() function and keep a list of registered globals to
invoke instead.
However, I haven't found a way for random drivers to add an .init table
to avoid having to manually add ourselves to i915_globals_init() each
== Series Details ==
Series: drm/i915: Populate pipe_offsets[] & co. accurately
URL : https://patchwork.freedesktop.org/series/57600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12378
Summary
---
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Do not temporarily disable the
DPLL on i830
URL : https://patchwork.freedesktop.org/series/57598/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12377
== Series Details ==
Series: drm/i915: Remove last traces of exec-id (GEM_BUSY)
URL : https://patchwork.freedesktop.org/series/57588/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5705_full -> Patchwork_12374_full
Summary
On Tue, Mar 05, 2019 at 03:23:48PM +0200, Jani Nikula wrote:
On Mon, 04 Mar 2019, Jani Nikula wrote:
On Mon, 04 Mar 2019, Ville Syrjälä wrote:
On Fri, Mar 01, 2019 at 05:14:05PM -0800, Lucas De Marchi wrote:
This register was placed in the middle of the PP_STATUS definition. Move
it down
Rather than manually add every new global into each hook, use
i915_global_register() function and keep a list of registered globals to
invoke instead.
However, I haven't found a way for random drivers to add an .init table
to avoid having to manually add ourselves to i915_globals_init() each
Quoting Dale B Stimson (2019-03-05 20:46:51)
> CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced
> by its absence from the kernel whitelist for Gen11 combined with the
> successful execution on ICL of the tests added by your recent patch
> "i915/gem_ctx_isolation: Sanitycheck
CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced
by its absence from the kernel whitelist for Gen11 combined with the
successful execution on ICL of the tests added by your recent patch
"i915/gem_ctx_isolation: Sanitycheck nonpriv access".
-Dale
On 2019-03-05 19:00:49, Chris
== Series Details ==
Series: series starting with [1/6] drm/i915: Force GPU idle on suspend
URL : https://patchwork.freedesktop.org/series/57597/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12376
On Tue, Mar 05, 2019 at 09:46:29PM +0200, Jani Nikula wrote:
> On Tue, 05 Mar 2019, Lucas De Marchi wrote:
> > On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote:
> >>On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote:
> >>> On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
> Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
> register isn't there, and use i915_mmio_reg_valid() instead of repeating
> the condition all over the place.
>
> Use INVALID_MMIO_REG explicitly for documentation
On Tue, Mar 05, 2019 at 03:52:14PM +0200, Jani Nikula wrote:
> PPS locking is a thing on pre-DDI, up to and including CPT and PPT.
>
> The PPS divisor register exists up to gen 9 BC, replaced by a field in
> the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on.
>
> Commit
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
register isn't there, and use i915_mmio_reg_valid() instead of repeating
the condition all over the place.
Use INVALID_MMIO_REG explicitly for documentation
== Series Details ==
Series: series starting with [1/6] drm/i915: Force GPU idle on suspend
URL : https://patchwork.freedesktop.org/series/57597/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Force GPU idle on suspend
Okay!
Commit:
On Tue, 05 Mar 2019, Lucas De Marchi wrote:
> On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote:
>>On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote:
>>> On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote:
>>> > On Tue, 05 Mar 2019, Lucas De Marchi wrote:
>>> >
From: Ville Syrjälä
At some point people have started to assume that
pipe_offsets[] & co. are only populated for pipes and whatnot
that actually exist. That is in fact not currently true, but
we can easily make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 146
Quoting Tvrtko Ursulin (2019-03-05 18:17:35)
>
> On 05/03/2019 18:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
> >>>/*
> >>> * Similarly the preempt context must always be available so that
> >>> - * we can interrupt the engine at any time.
> >>> +
From: Ville Syrjälä
Let's just always enable the DVO 2x clock on i830. This way we don't
have to track if DVO is being used or not. The spec does suggest we
should disable the clock when it isn't needed, but this does appear
to work just fine.
This removes another crtc->config usage.
v2: Split
From: Ville Syrjälä
The current code clears the DPLL register entirely when re-enabling
VGA mode temporarily during the DPLL enable sequence. On i830 we want to
keep the DPLLs on all the time, so let's not do this temporary
disabling.
The current code does work, so this doesn't seem super
Quoting Chris Wilson (2019-03-05 16:33:21)
> Quoting Tvrtko Ursulin (2019-03-05 16:16:01)
> >
> > On 01/03/2019 14:03, Chris Wilson wrote:
> > > Instead of passing the gem_context and engine to find the instance of
> > > the intel_context to use, pass around the intel_context instead. This is
> >
Currently we assume that we know the order in which requests run and so
can determine if we need to reissue a switch-to-kernel-context prior to
idling. That assumption does not hold for the future, so instead of
tracking which barriers have been used, simply determine if we have ever
switched away
We can no longer assume execution ordering, and in particular we cannot
assume which context will execute last. One side-effect of this is that
we cannot determine if the kernel-context is resident on the GPU, so
remove the routines that claimed to do so.
Signed-off-by: Chris Wilson
---
To facilitate the next patch to allow preemptible kernels not to incur
the wrath of hangcheck, we need to ensure that we can still suspend and
shutdown. That is we will not be able to rely on hangcheck to terminate
a blocking kernel and instead must manually do so ourselves. The
advantage is that
We can reduce the switch-to-kernel-context selftest to operate as a loop
and so trivially test another state transition (that of idle->busy).
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 80 ---
1 file changed, 35 insertions(+), 45 deletions(-)
When the system idles, we switch to the kernel context as a defensive
measure (no users are harmed if the kernel context is lost). Currently,
we issue a switch to kernel context and then come back later to see if
the kernel context is still current and the system is idle. However,
if we are no
We load a context (the kernel context) on both module load and resume in
order to initialise some logical state onto the GPU. We can use the same
routine for both operations, which will become more useful as we
refactor rc6/rps enabling.
Signed-off-by: Chris Wilson
---
Quoting Rafael Antognolli (2019-03-05 17:30:00)
> On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote:
> > We assumed that the default preemption granularity is fine for ICL.
> > Unfortunately, it turns out that some drivers don't support mid-thread
> > preemption for compute
Quoting Dale B Stimson (2019-03-05 01:03:08)
> @@ -132,30 +136,49 @@ static const struct named_register {
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> + { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
> + {
> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Tuesday, March 5, 2019 8:09 PM
> To: C, Ramalingam ; intel-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; daniel.vet...@ffwll.ch; Shankar, Uma
>
> Subject: Re: [Intel-gfx]
== Series Details ==
Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the
engine's mask
URL : https://patchwork.freedesktop.org/series/57595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5706 -> Patchwork_12375
On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote:
On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote:
On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote:
> On Tue, 05 Mar 2019, Lucas De Marchi wrote:
> > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula
Quoting Michał Winiarski (2019-03-05 12:48:27)
> There are still some cases where userspace needs to change the
> preemption granularity for compute workloads. Let's whitelist the
> per-ctx granularity control register to allow it.
>
> Signed-off-by: Michał Winiarski
> Cc: Anuj Phogat
> Cc:
On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote:
> On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote:
> > On Tue, 05 Mar 2019, Lucas De Marchi wrote:
> > > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula wrote:
> > > > On Mon, 04 Mar 2019, Rodrigo Vivi wrote:
> >
On Tue, Mar 05, 2019 at 05:43:15PM +, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 331e7a678fb7..79913b06f455 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -252,7 +252,7 @@ static
== Series Details ==
Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the
engine's mask
URL : https://patchwork.freedesktop.org/series/57595/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Store the BIT(engine->id)
== Series Details ==
Series: series starting with [1/2] drm/i915: Just check the vebox IIR regardless
URL : https://patchwork.freedesktop.org/series/57583/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5703_full -> Patchwork_12372_full
== Series Details ==
Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the
engine's mask
URL : https://patchwork.freedesktop.org/series/57595/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
578fc9439fec drm/i915: Store the BIT(engine->id) as the
Quoting Chris Wilson (2019-03-05 16:45:32)
> Quoting Tvrtko Ursulin (2019-03-05 16:27:34)
> >
> > On 01/03/2019 14:03, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
> > > b/drivers/gpu/drm/i915/intel_engine_types.h
> > > index 5ec6e72d0ffb..546b790871ad 100644
Quoting Tvrtko Ursulin (2019-03-05 18:13:34)
>
> intel_engine.h in 3...2...1.. ;)
As soon as we have a good name for the legacy submission method. At the
moment, my favorites are:
gen2_submission.c / legacy_submission.c (actually that's winning again)
gen8_submission.c / execlists_submission.c
On 05/03/2019 18:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
/*
* Similarly the preempt context must always be available so that
- * we can interrupt the engine at any time.
+ * we can interrupt the engine at any time. However, as preemption
+
On 05/03/2019 18:03, Chris Wilson wrote:
To find the active request, we need only search along the individual
engine for the right request. This does not require touching any global
GEM state, so move it into the engine compartment.
Signed-off-by: Chris Wilson
---
On 05/03/2019 18:03, Chris Wilson wrote:
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use
Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
> > /*
> >* Similarly the preempt context must always be available so that
> > - * we can interrupt the engine at any time.
> > + * we can interrupt the engine at any time. However, as preemption
> > + * is optional, we
On 01/03/2019 14:03, Chris Wilson wrote:
Each engine acquires a pin on the kernel contexts (normal and preempt)
so that the logical state is always available on demand. Keep track of
each engines pin by storing the returned pointer on the engine for quick
access.
Signed-off-by: Chris Wilson
Small simplification to set all bits in the dirty mask rather than
lookup the exact mask of populated engines. The bits for the engines
that do not exist are unused and so can safely set and then ignored.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
To find the active request, we need only search along the individual
engine for the right request. This does not require touching any global
GEM state, so move it into the engine compartment.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 3 --
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
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