Re: [Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

On Fri, Aug 11, 2017 at 4:39 PM, Rodrigo Vivi wrote: > WC is apparently not an option for CNL+ on GTT here. > Trying to use it we get hard hangs. > > Credits-to: Ben Widawsky forgot to CC relavant people for possible reviews: Cc: Joonas Cc:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

== Series Details == Series: drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well. URL : https://patchwork.freedesktop.org/series/28702/ State : success == Summary == Series 28702v1 drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915/gen10+: use the SKL code for reading WM latencies (rev2)

== Series Details == Series: series starting with [1/6] drm/i915/gen10+: use the SKL code for reading WM latencies (rev2) URL : https://patchwork.freedesktop.org/series/28586/ State : success == Summary == Series 28586v2 Series without cover letter

[Intel-gfx] [PATCH] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well.

WC is apparently not an option for CNL+ on GTT here. Trying to use it we get hard hangs. Credits-to: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [Intel-gfx] [PATCH 2/8] drm: Don't update property values for atomic drivers

Hi Daniel, On Tuesday 25 Jul 2017 10:01:16 Daniel Vetter wrote: > Atomic drivers only use the property value store for immutable (i.e. > can't be set by userspace, but the kernel can still adjust it) > properties. The only tricky part is the removal of the update in >

Re: [Intel-gfx] [PATCH 2/2] drm/i915: Introduce intel_hpd_pin function.

merged to dinq. thanks for the reviews and ideas On Fri, Aug 11, 2017 at 11:26 AM, Rodrigo Vivi wrote: > The idea is to have an unique place to decide the pin-port > per platform. > > So let's create this function now without any functional > change. Just adding together

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Simplify hpd pin to port (rev4)

== Series Details == Series: series starting with [1/2] drm/i915: Simplify hpd pin to port (rev4) URL : https://patchwork.freedesktop.org/series/28261/ State : success == Summary == Series 28261v4 Series without cover letter

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

merged to dinq. thanks for the review. On Thu, Aug 10, 2017 at 3:45 PM, Rodrigo Vivi wrote: > Different from SKL we don't need ctrl1 and cfgcr2, but > we need to dump cfgcr0 and cfgcr1 instead. > > v2: rebase and commit message > > Cc: Clint Taylor

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered (rev2)

== Series Details == Series: series starting with [v2,1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered (rev2) URL : https://patchwork.freedesktop.org/series/28667/ State : success == Summary == Series 28667v2 Series without cover letter

[Intel-gfx] [PATCH 2/2] drm/i915: Introduce intel_hpd_pin function.

The idea is to have an unique place to decide the pin-port per platform. So let's create this function now without any functional change. Just adding together code from hdmi and dp together. v2: Add missing pin for port A. v3: Fix typo on subject. Avoid behaviour change so add WARN_ON and

[Intel-gfx] [PATCH 1/2] drm/i915: Simplify hpd pin to port

We will soon need to make that pin port association per platform, so let's try to simplify it beforehand. Also we are moving the backwards port to pin here as well so let's use a standardized way. One extra possibility here would be to add a MISSING_CASE along with PORT_NONE, but I don't want to

[Intel-gfx] [PATCH v2 1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

DPCD 600h - SET_POWER & SET_DP_PWR_VOLTAGE defines power state 101 = Set Main-Link for local Sink device and all downstream Sink devices to D3 (power-down mode), keep AUX block fully powered, ready to reply within a Response Timeout period of 300us. This state is useful in a MST dock + MST

Re: [Intel-gfx] [maintainer-tools PATCH 3/4] dim: remove af and anf aliases

On Fri, Aug 11, 2017 at 06:03:24PM +0300, Jani Nikula wrote: > We don't generally apply patches to the drm-intel-fixes or > drm-intel-next-fixes trees, we cherry-pick instead, so the aliases are > unnecessary. great! this always confused me honestly, but I thought you were the one using this

Re: [Intel-gfx] [maintainer-tools PATCH 4/4] dim: fix list-aliases to not include itself

On Fri, Aug 11, 2017 at 06:03:25PM +0300, Jani Nikula wrote: > dim list-aliases lists "list-aliases" as being an alias of > "list-aliases". This is because the temporary subcmd variable reference > is erroneously included in the list. Unset it. I got confused with to many list-aliases

Re: [Intel-gfx] [maintainer-tools PATCH 2/4] dim: remove dim cherry-pick-branch subcommand

Reviewed-by: Rodrigo Vivi On Fri, Aug 11, 2017 at 06:03:23PM +0300, Jani Nikula wrote: > Demote dim_cherry_pick_branch to an internal function. It's too > specialized (at least for now) to be useful for anything other than as a > helper for the cherry-pick-fixes and

Re: [Intel-gfx] [maintainer-tools PATCH 1/4] doc: add documentation for dim commit-add-tag

Reviewed-by: Rodrigo Vivi On Fri, Aug 11, 2017 at 06:03:22PM +0300, Jani Nikula wrote: > Reported by 'make mancheck'. > > Signed-off-by: Jani Nikula > --- > dim.rst | 4 > 1 file changed, 4 insertions(+) > > diff --git a/dim.rst b/dim.rst

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

On 08/11/2017 12:49 AM, Lofstedt, Marta wrote: -Original Message- From: Taylor, Clinton A Sent: Thursday, August 10, 2017 8:50 PM To: intel-gfx@lists.freedesktop.org Cc: Taylor, Clinton A ; Vetter, Daniel ; Lofstedt, Marta

Re: [Intel-gfx] [PATCH v3 00/28] DRM API Conversions

On Fri, Aug 11, 2017 at 02:24:19PM +, Deucher, Alexander wrote: > > -Original Message- > > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > > Of Cihangir Akturk > > Sent: Friday, August 11, 2017 8:33 AM > > Cc: de...@driverdev.osuosl.org;

[Intel-gfx] [maintainer-tools PATCH 4/4] dim: fix list-aliases to not include itself

dim list-aliases lists "list-aliases" as being an alias of "list-aliases". This is because the temporary subcmd variable reference is erroneously included in the list. Unset it. Signed-off-by: Jani Nikula --- dim | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dim

[Intel-gfx] [maintainer-tools PATCH 2/4] dim: remove dim cherry-pick-branch subcommand

Demote dim_cherry_pick_branch to an internal function. It's too specialized (at least for now) to be useful for anything other than as a helper for the cherry-pick-fixes and cherry-pick-next-fixes subcommands. As a side effect, fixes mancheck for missing documentation for the subcommand.

[Intel-gfx] [maintainer-tools PATCH 1/4] doc: add documentation for dim commit-add-tag

Reported by 'make mancheck'. Signed-off-by: Jani Nikula --- dim.rst | 4 1 file changed, 4 insertions(+) diff --git a/dim.rst b/dim.rst index 8b4653aacbda..802c776e03f9 100644 --- a/dim.rst +++ b/dim.rst @@ -204,6 +204,10 @@ apply [*git am arguments*]

Re: [Intel-gfx] [PATCH] drm/i915/fbc: only update no_fbc_reason when active

On Fri, Aug 11, 2017 at 11:36:15AM +0100, Chris Wilson wrote: > Quoting Daniel Vetter (2017-08-11 09:04:18) > > On Fri, Aug 11, 2017 at 09:23:27AM +0200, Daniel Vetter wrote: > > > In our snb farm in CI we have plenty of underruns, but not enough > > > stolen memory to enable fbc. Which means

Re: [Intel-gfx] [PATCH] dim: Jari as QA lead

>On Fri, 11 Aug 2017, Daniel Vetter wrote: > > Cc: "Tahvanainen, Jari" > > Signed-off-by: Daniel Vetter > > --- > > dim | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/dim b/dim > >

Re: [Intel-gfx] [PATCH] dim: Jari as QA lead

On Fri, 11 Aug 2017, Daniel Vetter wrote: > Cc: "Tahvanainen, Jari" > Signed-off-by: Daniel Vetter > --- > dim | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/dim b/dim > index

Re: [Intel-gfx] [PATCH v3 00/28] DRM API Conversions

> -Original Message- > From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf > Of Cihangir Akturk > Sent: Friday, August 11, 2017 8:33 AM > Cc: de...@driverdev.osuosl.org; linux-arm-...@vger.kernel.org; intel- > g...@lists.freedesktop.org; linux-ker...@vger.kernel.org;

[Intel-gfx] [PATCH] dim: Jari as QA lead

Cc: "Tahvanainen, Jari" Signed-off-by: Daniel Vetter --- dim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dim b/dim index 2b377cb3a3f3..4a4c1adb2c68 100755 --- a/dim +++ b/dim @@ -89,7 +89,7 @@

[Intel-gfx] [PATCH][drm-next] drm/i915: make structure intel_sprite_plane_funcs static

From: Colin Ian King The structure intel_sprite_plane_funcs is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'intel_sprite_plane_funcs' was not declared. Should it be static? Signed-off-by: Colin Ian

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm: add retries for lspcon status check

== Series Details == Series: series starting with [1/2] drm: add retries for lspcon status check URL : https://patchwork.freedesktop.org/series/28684/ State : success == Summary == Series 28684v1 Series without cover letter

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_mmap_write_crc: Add drmModeDirtyFB after dirtying fb

Acked-by: Marta Lofstedt > -Original Message- > From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com] > Sent: Thursday, August 10, 2017 3:42 PM > To: intel-gfx@lists.freedesktop.org > Cc: Maarten Lankhorst ;

[Intel-gfx] [PATCH 2/2] drm/i915: Don't give up waiting on INVALID_MODE

Our current logic to read LSPCON's current mode, stops retries and breaks wait-loop, if it gets LSPCON_MODE_INVALID as return from the core function. This doesn't allow us to try reading the mode again. This patch removes this condition and allows retries reading the currnt mode until timeout.

[Intel-gfx] [PATCH 1/2] drm: add retries for lspcon status check

It's an observation during some CI tests that few LSPCON chips respond slow while system is under load, and need some delay while reading current mode status using i2c-over-aux channel. This patch: - Adds few retries and delays before declaring a read failure from LSPCON hardware. - Changes the

Re: [Intel-gfx] [PATCH igt] igt: Add a test to precheck status of kernel taints

Quoting Jani Nikula (2017-08-11 14:15:50) > On Fri, 11 Aug 2017, Chris Wilson wrote: > > Many times an error may occur before the start of igt, leaving the > > system in a less-than-optimal debugging state (e.g. an oops turning off > > lockdep). Flag such occasions by

[Intel-gfx] ✓ Fi.CI.BAT: success for igt: Add a test to precheck status of kernel taints

== Series Details == Series: igt: Add a test to precheck status of kernel taints URL : https://patchwork.freedesktop.org/series/28683/ State : success == Summary == IGT patchset tested on top of latest successful build 1385b31d9371fae02af2fd8adb0d9ea86a5bb0f2 tests/igt_command_line: Ignore

Re: [Intel-gfx] [PATCH igt] igt: Add a test to precheck status of kernel taints

On Fri, 11 Aug 2017, Chris Wilson wrote: > Many times an error may occur before the start of igt, leaving the > system in a less-than-optimal debugging state (e.g. an oops turning off > lockdep). Flag such occasions by checking /proc/sys/kernel/tainted. Hmm, which flag

[Intel-gfx] [PATCH igt] igt: Add a test to precheck status of kernel taints

Many times an error may occur before the start of igt, leaving the system in a less-than-optimal debugging state (e.g. an oops turning off lockdep). Flag such occasions by checking /proc/sys/kernel/tainted. Signed-off-by: Chris Wilson --- tests/Makefile.sources | 1 +

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] lib: Add some syncobj helpers

== Series Details == Series: series starting with [1/4] lib: Add some syncobj helpers URL : https://patchwork.freedesktop.org/series/28666/ State : success == Summary == IGT patchset tested on top of latest successful build 1385b31d9371fae02af2fd8adb0d9ea86a5bb0f2 tests/igt_command_line:

[Intel-gfx] [PATCH v3 11/28] drm/i915: switch to drm_*_get(), drm_*_put() helpers

Use drm_*_get() and drm_*_put() helpers instead of drm_*_reference() and drm_*_unreference() helpers. drm_*_reference() and drm_*_unreference() functions are just compatibility alias for drm_*_get() and drm_*_put() and should not be used by new code. So convert all users of compatibility

[Intel-gfx] [PATCH v3 00/28] DRM API Conversions

Changes since v2: - Patch series is based on *drm-misc-next* as suggested by Sean Paul. - Dropped patch 05 (drm/atmel-hlcdc) and patch 25 (drm/vc4) from v2, since they were already pulled in the drm-misc-next Changes since v1: - This time patches were generated with coccinelle instead of my

[Intel-gfx] ✓ Fi.CI.BAT: success for tests/kms: increase max threshold time for edid read (rev5)

== Series Details == Series: tests/kms: increase max threshold time for edid read (rev5) URL : https://patchwork.freedesktop.org/series/28399/ State : success == Summary == IGT patchset tested on top of latest successful build 1385b31d9371fae02af2fd8adb0d9ea86a5bb0f2 tests/igt_command_line:

Re: [Intel-gfx] [PATCH 1/3] drm/i915/perf: Initialise dynamic sysfs group before creation

On 10/08/17 18:57, Chris Wilson wrote: Another case where we need to call sysfs_attr_init() to setup the internal lockdep class prior to use: [9.325229] BUG: key 880168bc7bb0 not in .data! [9.325240] DEBUG_LOCKS_WARN_ON(1) [9.325250] [ cut here ] [

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vbt: ignore extraneous child devices for a port

== Series Details == Series: drm/i915/vbt: ignore extraneous child devices for a port URL : https://patchwork.freedesktop.org/series/28681/ State : success == Summary == Series 28681v1 drm/i915/vbt: ignore extraneous child devices for a port

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Keep a small stash of preallocated WC pages

Quoting Joonas Lahtinen (2017-08-11 08:34:02) > On ke, 2017-07-26 at 14:25 +0100, Chris Wilson wrote: > > - if (vm->pt_kmap_wc) > > - set_pages_array_wb(vm->free_pages.pages, > > -    pagevec_count(>free_pages)); > > + /* When we use WC,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split obj->cache_coherent to track r/w (rev4)

== Series Details == Series: drm/i915: Split obj->cache_coherent to track r/w (rev4) URL : https://patchwork.freedesktop.org/series/28641/ State : success == Summary == Series 28641v4 drm/i915: Split obj->cache_coherent to track r/w

[Intel-gfx] [PATCH] drm/i915/vbt: ignore extraneous child devices for a port

Ever since we've parsed VBT child devices, starting from 6acab15a7b0d ("drm/i915: use the HDMI DDI buffer translations from VBT"), we've ignored the child device information if more than one child device references the same port. The rationale for this seems lost in time. Since commit

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Handle full s64 precision for wait-ioctl (rev2)

== Series Details == Series: drm/i915: Handle full s64 precision for wait-ioctl (rev2) URL : https://patchwork.freedesktop.org/series/28420/ State : success == Summary == Series 28420v2 drm/i915: Handle full s64 precision for wait-ioctl

Re: [Intel-gfx] [PATCH v2] drm/i915: Split obj->cache_coherent to track r/w

Quoting Chris Wilson (2017-08-11 11:11:31) > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 5fa44767c29e..9d808838a1ba 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@

[Intel-gfx] [PATCH v4] drm/i915: Split obj->cache_coherent to track r/w

Another month, another story in the cache coherency saga. This time, we come to the realisation that i915_gem_object_is_coherent() has been reporting whether we can read from the target without requiring a cache invalidate; but we were using it in places for testing whether we could write into the

[Intel-gfx] [PATCH v2] drm/i915: Handle full s64 precision for wait-ioctl

The wait-ioctl is optionally supplied a timeout with nanosecond precision in a s64 field. We use nsecs_to_jiffies64() to convert that into the jiffies consumed by the scheduler, but internally nsecs_to_jiffies64() does not guard against overflow (as it's purpose is for use by the scheduler and not

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Split obj->cache_coherent to track r/w (rev3)

== Series Details == Series: drm/i915: Split obj->cache_coherent to track r/w (rev3) URL : https://patchwork.freedesktop.org/series/28641/ State : failure == Summary == Series 28641v3 drm/i915: Split obj->cache_coherent to track r/w

Re: [Intel-gfx] [PATCH] drm/i915/fbc: only update no_fbc_reason when active

Quoting Daniel Vetter (2017-08-11 09:04:18) > On Fri, Aug 11, 2017 at 09:23:27AM +0200, Daniel Vetter wrote: > > In our snb farm in CI we have plenty of underruns, but not enough > > stolen memory to enable fbc. Which means every time there's an > > underrun the no_fbc_reason swichtes to something

Re: [Intel-gfx] [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

Quoting Joonas Lahtinen (2017-08-11 10:51:26) > Configurations like virtualized environments may support only 48 bit > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting > the relationship of the two feature bits. Did the gvt patches land in dinq? After that, I say we just kill

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Disconnect 32 and 48 bit ppGTT support

== Series Details == Series: drm/i915: Disconnect 32 and 48 bit ppGTT support URL : https://patchwork.freedesktop.org/series/28676/ State : success == Summary == Series 28676v1 drm/i915: Disconnect 32 and 48 bit ppGTT support

[Intel-gfx] [PATCH v3] drm/i915: Split obj->cache_coherent to track r/w

Another month, another story in the cache coherency saga. This time, we come to the realisation that i915_gem_object_is_coherent() has been reporting whether we can read from the target without requiring a cache invalidate; but we were using it in places for testing whether we could write into the

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_frontbuffer_tracking: increase FBC wait timeout to 5s

Paulo, my currently conclusion in https://bugs.freedesktop.org/show_bug.cgi?id=101623 is that the more than 2 second wait for enable_fbs only occurs when changing between draw domains, typically between blt and mmap_cpu. To me this appear to be way too long time, but I am no expert here. I

[Intel-gfx] [PATCH v2] drm/i915: Split obj->cache_coherent to track r/w

Another month, another story in the cache coherency saga. This time, we come to the realisation that i915_gem_object_is_coherent() has been reporting whether we can read from the target without requiring a cache invalidate; but we were using it in places for testing whether we could write into the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/fbc: only update no_fbc_reason when active

== Series Details == Series: drm/i915/fbc: only update no_fbc_reason when active URL : https://patchwork.freedesktop.org/series/28674/ State : success == Summary == Series 28674v1 drm/i915/fbc: only update no_fbc_reason when active

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered

== Series Details == Series: series starting with [1/2] drm/dp: Bit definition for D3 power state that keeps AUX fully powered URL : https://patchwork.freedesktop.org/series/28667/ State : success == Summary == Series 28667v1 Series without cover letter

[Intel-gfx] [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

Configurations like virtualized environments may support only 48 bit ppGTT without supporting 32 bit ppGTT. Support this by disconnecting the relationship of the two feature bits. Cc: Tina Zhang Cc: Chris Wilson Cc: Zhi Wang

Re: [Intel-gfx] [PATCH v9 2/3] drm/i915: Enable guest i915 full ppgtt functionality

On to, 2017-08-10 at 07:41 +0800, Tina Zhang wrote: > Enable the guest i915 full ppgtt functionality when host can provide this > capability. vgt_caps is introduced to guest i915 driver to get the vgpu > capabilities from the device model. VGT_CPAS_FULL_PPGTT is one of the > capabilities type to

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Keep a small stash of preallocated WC pages

On Wed, 26 Jul 2017, Chris Wilson wrote: > We use WC pages for coherent writes into the ppGTT on !llc > architectuures. However, to create a WC page requires a stop_machine(), > i.e. is very slow. To compensate we currently keep a per-vm cache of > recently freed pages,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/cnl: Dump the right pll registers when dumping pipe config.

== Series Details == Series: drm/i915/cnl: Dump the right pll registers when dumping pipe config. URL : https://patchwork.freedesktop.org/series/28665/ State : success == Summary == Series 28665v1 drm/i915/cnl: Dump the right pll registers when dumping pipe config.

Re: [Intel-gfx] [PATCH 3/4] drm: Only lastclose on unload for legacy drivers

On Thu, Aug 03, 2017 at 01:52:55PM -0400, Alex Deucher wrote: > On Thu, Aug 3, 2017 at 9:54 AM, Daniel Vetter wrote: > > On Thu, Aug 3, 2017 at 1:17 AM, Daniel Vetter > > wrote: > >> On Wed, Aug 2, 2017 at 10:50 PM, Alex Deucher

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with drm/i915/cnl: Add allowed DP rates for Cannonlake. (rev2)

== Series Details == Series: series starting with drm/i915/cnl: Add allowed DP rates for Cannonlake. (rev2) URL : https://patchwork.freedesktop.org/series/26952/ State : success == Summary == Series 26952v2 Series without cover letter

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Split pin mapping into per platform functions (rev2)

== Series Details == Series: drm/i915: Split pin mapping into per platform functions (rev2) URL : https://patchwork.freedesktop.org/series/27965/ State : success == Summary == Series 27965v2 drm/i915: Split pin mapping into per platform functions

Re: [Intel-gfx] [maintainer-tools PATCH 0/4] dim: shellcheck fixes

On Fri, 11 Aug 2017, Daniel Vetter wrote: > On Thu, Aug 10, 2017 at 05:08:12PM +0300, Jani Nikula wrote: >> Thou shalt not push dim patches before passing 'make check'. > > On the series: > > Reviewed-by: Daniel Vetter Thanks, pushed. BR, Jani. > >>

Re: [Intel-gfx] [PATCH i-g-t 1/5] Add support for subtest-specific documentation

On Thu, Aug 10, 2017 at 01:26:47PM +0300, Petri Latvala wrote: > The current documentation for tests is limited to a single string per > test binary. This patch adds support for documenting individual > subtests. > > The syntax for subtest documentation is: > >igt_document_subtest("Frob

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable FBC for non X-tiled FBs (rev6)

== Series Details == Series: drm/i915: Enable FBC for non X-tiled FBs (rev6) URL : https://patchwork.freedesktop.org/series/21264/ State : success == Summary == Series 21264v6 drm/i915: Enable FBC for non X-tiled FBs https://patchwork.freedesktop.org/api/1.0/series/21264/revisions/6/mbox/

Re: [Intel-gfx] [PATCH] drm/i915: Split obj->cache_coherent to track r/w

On to, 2017-08-10 at 17:20 +0100, Chris Wilson wrote: > Another month, another story in the cache coherency saga. This time, we > come to the realisation that i915_gem_object_is_coherent() has been > reporting whether we can read from the target without requiring a cache > invalidate; but we were

Re: [Intel-gfx] [PATCH] drm/i915/fbc: only update no_fbc_reason when active

On Fri, Aug 11, 2017 at 09:23:27AM +0200, Daniel Vetter wrote: > In our snb farm in CI we have plenty of underruns, but not enough > stolen memory to enable fbc. Which means every time there's an > underrun the no_fbc_reason swichtes to something that makes > kms_frontbuffer_tracking fail instead

Re: [Intel-gfx] [maintainer-tools PATCH 0/4] dim: shellcheck fixes

On Thu, Aug 10, 2017 at 05:08:12PM +0300, Jani Nikula wrote: > Thou shalt not push dim patches before passing 'make check'. On the series: Reviewed-by: Daniel Vetter > > Cc: Daniel Vetter > Cc: Maarten Lankhorst

Re: [Intel-gfx] [PATCH i-g-t] pm_rps: Extended testcases with checking PMINTRMSK register value

On Thu, Aug 10, 2017 at 02:20:27PM +0100, Chris Wilson wrote: > Quoting Katarzyna Dec (2017-08-10 14:06:15) > > In addition to checking whether the frequency is in correct range > > for certain scenario, we can also verify whether PM interrupts are > > masked correctly. > > What does correctly

[Intel-gfx] [bug report] drm/i915/gvt: Update MMIO handle policy to compatible KBL platform.

Hello Xu Han, The patch 5cf5fe8f729b: "drm/i915/gvt: Update MMIO handle policy to compatible KBL platform." from Mar 29, 2017, leads to the following static checker warning: drivers/gpu/drm/i915/gvt/handlers.c:2855 init_skl_mmio_info() '0x6 | 0x4' has '0x4' set on both sides

Re: [Intel-gfx] [PATCH v4 i-g-t] tests/kms: increase max threshold time for edid read

> -Original Message- > From: Taylor, Clinton A > Sent: Thursday, August 10, 2017 8:50 PM > To: intel-gfx@lists.freedesktop.org > Cc: Taylor, Clinton A ; Vetter, Daniel > ; Lofstedt, Marta > Subject: [PATCH v4

Re: [Intel-gfx] [PATCH 07/16] drm/i915: Trim struct_mutex hold duration for i915_gem_free_objects

On ke, 2017-07-26 at 14:26 +0100, Chris Wilson wrote: > We free objects in bulk after they wait for their RCU grace period. > Currently, we take struct_mutex and unbind all the objects. This can lead > to a long lock duration during which time those objects have their pages > unfreeable (i.e. the

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Keep a small stash of preallocated WC pages

On ke, 2017-07-26 at 14:25 +0100, Chris Wilson wrote: > We use WC pages for coherent writes into the ppGTT on !llc > architectuures. However, to create a WC page requires a stop_machine(), > i.e. is very slow. To compensate we currently keep a per-vm cache of > recently freed pages, but we still

Re: [Intel-gfx] [PATCH] drm/i915: Split obj->cache_coherent to track r/w

Op 10-08-17 om 18:20 schreef Chris Wilson: > Another month, another story in the cache coherency saga. This time, we > come to the realisation that i915_gem_object_is_coherent() has been > reporting whether we can read from the target without requiring a cache > invalidate; but we were using it in

[Intel-gfx] [PATCH] drm/i915/fbc: only update no_fbc_reason when active

In our snb farm in CI we have plenty of underruns, but not enough stolen memory to enable fbc. Which means every time there's an underrun the no_fbc_reason swichtes to something that makes kms_frontbuffer_tracking fail instead of skip, adding massive amounts of additional noise to igt test runs.

Re: [Intel-gfx] [PATCH] drm/i915: Handle full s64 precision for wait-ioctl

On la, 2017-08-05 at 20:47 +0100, Chris Wilson wrote: > Quoting Chris Wilson (2017-08-05 20:19:24) > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -4144,6 +4144,12 @@ static inline unsigned long > > msecs_to_jiffies_timeout(const unsigned int m) > >   > >  static inline unsigned long

Re: [Intel-gfx] [PATCH] drm/i915: Handle full s64 precision for wait-ioctl

On la, 2017-08-05 at 20:19 +0100, Chris Wilson wrote: > The wait-ioctl is optionally supplied a timeout with nanosecond > precision in a s64 field. We use nsecs_to_jiffies64() to convert that > into the jiffies consumed by the scheduler, but internally > nsecs_to_jiffies64() does not guard against

Re: [Intel-gfx] [PATCH 5/6] drm/i915/gen10: implement gen 10 watermarks calculations

Hi, On Thursday 10 August 2017 02:22 AM, Rodrigo Vivi wrote: From: Paulo Zanoni They're slightly different than the gen 9 calculations. v2: Remove TODO comment. Code matches recent spec. Cc: Mahesh Kumar Cc: Maarten Lankhorst