Re: [Intel-gfx] [PATCH] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
This is also needed to fix failing IGT test case kms_cursor_crc on ICL.
On Tue, 2019-03-05 at 17:26 -0800, Aditya Swarup wrote:
> Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
> to passthrough FB pixels unmodified across pipe. This fixes the
> failures
> for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
> (Lineage #1605353570)
>
> Cc: Clint Taylor
> Cc: Mika Kahola
> Cc: Jani Nikula
Reviewed-by: Mika Kahola
> Signed-off-by: Aditya Swarup
> ---
> WA for ICL DP compliance. It fixes failing test in igt for crc
> mismatch
> wrt cursor plane. Can be searched using Lineage #1605353570.
>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 8 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c9b868347481..4713fbb3e021 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7663,6 +7663,7 @@ enum {
> #define _PIPEB_CHICKEN 0x71038
> #define _PIPEC_CHICKEN 0x72038
> #define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
> +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
> #define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe,
> _PIPEA_CHICKEN,\
> _PIPEB_CHICKEN)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index d852cb282060..92be3476fef1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3970,7 +3970,13 @@ static void icl_set_pipe_chicken(struct
> intel_crtc *crtc)
>* and rounding for per-pixel values 00 and 0xff
>*/
> tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
> -
> + /*
> + * Display WA # 1605353570: icl
> + * Set the pixel rounding bit to 1 for allowing
> + * passthrough of Frame buffer pixels unmodified
> + * across pipe
> + */
> + tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
> I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> }
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
== Series Details ==
Series: series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
URL : https://patchwork.freedesktop.org/series/57628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12388
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57628/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12388 that come from known issues:
### IGT changes ###
Issues hit
* igt@kms_frontbuffer_tracking@basic:
- fi-byt-clapper: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@cursor_plane_move:
- fi-whl-u: PASS -> FAIL [fdo#107383] +3
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12388
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12388: b47c5668b993c7f46fedd5d2f4185633e4bf48cf @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b47c5668b993 drm/i915: Enable PSR2 by default
0351b3626e46 drm/i915: Force PSR exit when getting pipe CRC
1098eda1010e drm/i915: Drop redundant checks to update PSR state
107f2d29e13c drm/i915: Disable PSR2 while getting pipe CRC
ca535036359a drm/i915/crc: Make IPS workaround generic
b44ee7a5d070 drm/i915/psr: Drop test for EDP in CRTC when forcing commit
d04169730a46 drm/i915: Compute and commit color features in fastsets
8cc93ba346d5 drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
3fad93a4257c drm/i915/psr: Remove PSR2 FIXME
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12388/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
Hi José,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.0 next-20190305]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-i915-vbt-Parse-and-use-the-new-field-with-PSR2-TP2-3-wakeup-time/20190306-140524
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x019-201909 (attached as .config)
compiler: gcc-8 (Debian 8.3.0-2) 8.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:10,
from include/linux/list.h:9,
from include/linux/async.h:16,
from drivers/gpu/drm/i915/intel_drv.h:28,
from drivers/gpu/drm/i915/intel_psr.c:55:
drivers/gpu/drm/i915/intel_psr.c: In function 'psr1_tps_regs_val_get':
>> include/linux/compiler.h:58:2: error: expected ';' before 'if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~
include/linux/compiler.h:56:23: note: in expansion of macro '__trace_if'
#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
^~
drivers/gpu/drm/i915/intel_psr.c:446:2: note: in expansion of macro 'if'
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
^~
--
In file included from include/linux/kernel.h:10,
from include/linux/list.h:9,
from include/linux/async.h:16,
from drivers/gpu//drm/i915/intel_drv.h:28,
from drivers/gpu//drm/i915/intel_psr.c:55:
drivers/gpu//drm/i915/intel_psr.c: In function 'psr1_tps_regs_val_get':
>> include/linux/compiler.h:58:2: error: expected ';' before 'if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~
include/linux/compiler.h:56:23: note: in expansion of macro '__trace_if'
#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
^~
drivers/gpu//drm/i915/intel_psr.c:446:2: note: in expansion of macro 'if'
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
^~
vim +58 include/linux/compiler.h
2bcd521a Steven Rostedt 2008-11-21 50
2bcd521a Steven Rostedt 2008-11-21 51 #ifdef CONFIG_PROFILE_ALL_BRANCHES
2bcd521a Steven Rostedt 2008-11-21 52 /*
2bcd521a Steven Rostedt 2008-11-21 53 * "Define 'is'", Bill Clinton
2bcd521a Steven Rostedt 2008-11-21 54 * "Define 'if'", Steven Rostedt
2bcd521a Steven Rostedt 2008-11-21 55 */
ab3c9c68 Linus Torvalds 2009-04-07 56 #define if(cond, ...) __trace_if( (cond
, ## __VA_ARGS__) )
ab3c9c68 Linus Torvalds 2009-04-07 57 #define __trace_if(cond) \
b33c8ff4 Arnd Bergmann 2016-02-12 @58 if
(__builtin_constant_p(!!(cond)) ? !!(cond) : \
2bcd521a Steven Rostedt 2008-11-21 59 ({
\
2bcd521a Steven Rostedt 2008-11-21 60 int __r;
\
2bcd521a Steven Rostedt 2008-11-21 61 static struct
ftrace_branch_data\
e04462fb Miguel Ojeda 2018-09-03 62 __aligned(4)
\
e04462fb Miguel Ojeda 2018-09-03 63
__section("_ftrace_branch") \
2bcd521a Steven Rostedt 2008-11-21 64 __f = {
\
2bcd521a Steven Rostedt 2008-11-21 65 .func =
__func__, \
2bcd521a Steven Rostedt 2008-11-21 66 .file =
__FILE__, \
2bcd521a Steven Rostedt 2008-11-21 67 .line =
__LINE__, \
2bcd521a Steven Rostedt 2008-11-21 68 };
\
2bcd521a Steven Rostedt 2008-11-21 69 __r = !!(cond);
\
97e7e4f3 Witold Baryluk 2009-03-17 70
__f.miss_hit[__r]++;\
2bcd521a Steven Rostedt 2008-11-21 71 __r;
\
2bcd521a Steven Rostedt 2008-11-21 72 }))
2bcd521a Steven Rostedt 2008-11-21 73 #endif /* CONFIG_PROFILE_ALL_BRANCHES */
2bcd521a Steven Rostedt 2008-11-21 74
:: The code at line 58 was first introduced by commit
:: b33c8ff4431a343561e2319f17c14286f2aa52e2 tracing: Fix freak link error
caused by branch tracer
:: TO: Arnd Bergmann
:: CC: Steven Rostedt
---
0-DAY kernel test infrastructureOpen Source Techn
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME
== Series Details == Series: series starting with [v5,1/9] drm/i915/psr: Remove PSR2 FIXME URL : https://patchwork.freedesktop.org/series/57628/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/psr: Remove PSR2 FIXME Okay! Commit: drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset Okay! Commit: drm/i915: Compute and commit color features in fastsets Okay! Commit: drm/i915/psr: Drop test for EDP in CRTC when forcing commit Okay! Commit: drm/i915/crc: Make IPS workaround generic Okay! Commit: drm/i915: Disable PSR2 while getting pipe CRC Okay! Commit: drm/i915: Drop redundant checks to update PSR state Okay! Commit: drm/i915: Force PSR exit when getting pipe CRC -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) Commit: drm/i915: Enable PSR2 by default Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH v2 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
Hi José,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v5.0 next-20190305]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-i915-vbt-Parse-and-use-the-new-field-with-PSR2-TP2-3-wakeup-time/20190306-140524
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x006-201909 (attached as .config)
compiler: gcc-8 (Debian 8.3.0-2) 8.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/intel_psr.c: In function 'psr1_tps_regs_val_get':
>> drivers/gpu/drm/i915/intel_psr.c:446:2: error: expected ';' before 'if'
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
^~
vim +446 drivers/gpu/drm/i915/intel_psr.c
0bc12bcb1 Rodrigo Vivi 2014-11-14 437
a5f924097 José Roberto de Souza 2019-03-05 438 static u32
psr1_tps_regs_val_get(struct intel_dp *intel_dp)
0bc12bcb1 Rodrigo Vivi 2014-11-14 439 {
1895759ee Rodrigo Vivi 2018-08-27 440 struct drm_i915_private
*dev_priv = dp_to_i915(intel_dp);
a5f924097 José Roberto de Souza 2019-03-05 441 u32 val = 0;
60e5ffe32 Rodrigo Vivi 2016-02-01 442
715dd286b José Roberto de Souza 2019-03-05 443 if (INTEL_GEN(dev_priv)
>= 11)
715dd286b José Roberto de Souza 2019-03-05 444 val |=
EDP_PSR_TP4_TIME_0US
715dd286b José Roberto de Souza 2019-03-05 445
77312ae8f Vathsala Nagaraju 2018-05-22 @446 if
(dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
77312ae8f Vathsala Nagaraju 2018-05-22 447 val |=
EDP_PSR_TP1_TIME_0us;
77312ae8f Vathsala Nagaraju 2018-05-22 448 else if
(dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
50db13901 Daniel Vetter 2016-05-18 449 val |=
EDP_PSR_TP1_TIME_100us;
77312ae8f Vathsala Nagaraju 2018-05-22 450 else if
(dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
77312ae8f Vathsala Nagaraju 2018-05-22 451 val |=
EDP_PSR_TP1_TIME_500us;
50db13901 Daniel Vetter 2016-05-18 452 else
77312ae8f Vathsala Nagaraju 2018-05-22 453 val |=
EDP_PSR_TP1_TIME_2500us;
50db13901 Daniel Vetter 2016-05-18 454
77312ae8f Vathsala Nagaraju 2018-05-22 455 if
(dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
77312ae8f Vathsala Nagaraju 2018-05-22 456 val |=
EDP_PSR_TP2_TP3_TIME_0us;
77312ae8f Vathsala Nagaraju 2018-05-22 457 else if
(dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
50db13901 Daniel Vetter 2016-05-18 458 val |=
EDP_PSR_TP2_TP3_TIME_100us;
77312ae8f Vathsala Nagaraju 2018-05-22 459 else if
(dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
77312ae8f Vathsala Nagaraju 2018-05-22 460 val |=
EDP_PSR_TP2_TP3_TIME_500us;
50db13901 Daniel Vetter 2016-05-18 461 else
77312ae8f Vathsala Nagaraju 2018-05-22 462 val |=
EDP_PSR_TP2_TP3_TIME_2500us;
50db13901 Daniel Vetter 2016-05-18 463
50db13901 Daniel Vetter 2016-05-18 464 if
(intel_dp_source_supports_hbr2(intel_dp) &&
50db13901 Daniel Vetter 2016-05-18 465
drm_dp_tps3_supported(intel_dp->dpcd))
50db13901 Daniel Vetter 2016-05-18 466 val |=
EDP_PSR_TP1_TP3_SEL;
50db13901 Daniel Vetter 2016-05-18 467 else
50db13901 Daniel Vetter 2016-05-18 468 val |=
EDP_PSR_TP1_TP2_SEL;
50db13901 Daniel Vetter 2016-05-18 469
a5f924097 José Roberto de Souza 2019-03-05 470 return val;
a5f924097 José Roberto de Souza 2019-03-05 471 }
a5f924097 José Roberto de Souza 2019-03-05 472
:: The code at line 446 was first introduced by commit
:: 77312ae8f071fb389d9982ce743b72975990c4d9 drm/i915/psr: vbt change for psr
:: TO: Vathsala Nagaraju
:: CC: Jani Nikula
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/icl: Remove alpha support protection
== Series Details ==
Series: drm/i915/icl: Remove alpha support protection
URL : https://patchwork.freedesktop.org/series/57609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12382_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12382_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@extended-pageflip-hang-newfb-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: PASS -> FAIL [fdo#103232] +3
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-skl: PASS -> FAIL [fdo#103184]
* igt@kms_flip@dpms-vs-vblank-race:
- shard-apl: PASS -> FAIL [fdo#103060]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip_tiling@flip-yf-tiled:
- shard-skl: PASS -> FAIL [fdo#108145]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +38
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +28
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-skl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-apl: NOTRUN -> SKIP [fdo#109271]
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773]
- shard-snb: PASS -> DMESG-WARN [fdo#102365]
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-glk: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: NOTRUN -> FAIL [fdo#104894]
* igt@perf@blocking:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
* igt@runner@aborted:
- shard-apl: NOTRUN -> FAIL [fdo#109383]
Possible fixes
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: SKIP [fdo#109271] -> PASS
* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: DMESG-WARN [fdo#107956] -> PASS
* igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
- shard-skl: FAIL [fdo#104671] -> PASS
* igt@kms_cursor_crc@cursor-256x85-offscreen:
- shard-skl: FAIL [fdo#103232] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +2
* igt@kms_cursor_crc@cursor-alpha-opaque:
- shard-apl: FAIL [fdo#109350] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu:
- shard-skl: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-skl: FAIL [fdo#105682] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-skl: FAIL [fdo#103167] / [fdo#105682] -> PASS
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: FAIL [fdo#107815] / [fdo#108145] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
- shard-glk: FAIL [fdo#99912] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-apl: FAIL [fdo#103166] -> PASS +1
{name}: This
[Intel-gfx] [PATCH v5 5/9] drm/i915/crc: Make IPS workaround generic
Other features like PSR2 also needs to be disabled while getting CRC
so lets rename ips_force_disable to crc_enabled, drop all this checks
for pipe A and HSW and BDW and make it generic and
hsw_compute_ips_config() will take care of all the checks removed
from here.
v2: Renaming and parameter changes to the functions that prepares the
commit (Ville)
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 10 --
drivers/gpu/drm/i915/intel_drv.h | 3 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 47 +++
3 files changed, 29 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9312b3f35eb0..b3a5d8462251 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6751,7 +6751,13 @@ static bool hsw_compute_ips_config(struct
intel_crtc_state *crtc_state)
if (!hsw_crtc_state_ips_capable(crtc_state))
return false;
- if (crtc_state->ips_force_disable)
+ /*
+* When IPS gets enabled, the pipe CRC changes. Since IPS gets
+* enabled and disabled dynamically based on package C states,
+* user space can't make reliable use of the CRCs, so let's just
+* completely disable it.
+*/
+ if (crtc_state->crc_enabled)
return false;
/* IPS should be fine as long as at least one plane is enabled. */
@@ -11687,7 +11693,7 @@ clear_intel_crtc_state(struct intel_crtc_state
*crtc_state)
saved_state->shared_dpll = crtc_state->shared_dpll;
saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
saved_state->pch_pfit.force_thru = crtc_state->pch_pfit.force_thru;
- saved_state->ips_force_disable = crtc_state->ips_force_disable;
+ saved_state->crc_enabled = crtc_state->crc_enabled;
if (IS_G4X(dev_priv) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
saved_state->wm = crtc_state->wm;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5412373e2f98..2be64529e4a2 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -999,7 +999,8 @@ struct intel_crtc_state {
struct intel_link_m_n fdi_m_n;
bool ips_enabled;
- bool ips_force_disable;
+
+ bool crc_enabled;
bool enable_fbc;
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 53d4ec68d3c4..af64597c5c6e 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -280,15 +280,15 @@ static int ilk_pipe_crc_ctl_reg(enum
intel_pipe_crc_source *source,
return 0;
}
-static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
- bool enable)
+static void
+intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc, bool enable)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_device *dev = _priv->drm;
- struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
struct intel_crtc_state *pipe_config;
struct drm_atomic_state *state;
struct drm_modeset_acquire_ctx ctx;
- int ret = 0;
+ int ret;
drm_modeset_acquire_init(, 0);
@@ -307,17 +307,9 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private
*dev_priv,
goto put_state;
}
- if (HAS_IPS(dev_priv)) {
- /*
-* When IPS gets enabled, the pipe CRC changes. Since IPS gets
-* enabled and disabled dynamically based on package C states,
-* user space can't make reliable use of the CRCs, so let's just
-* completely disable it.
-*/
- pipe_config->ips_force_disable = enable;
- }
+ pipe_config->crc_enabled = enable;
- if (IS_HASWELL(dev_priv)) {
+ if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {
pipe_config->pch_pfit.force_thru = enable;
if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
pipe_config->pch_pfit.enabled != enable)
@@ -343,8 +335,7 @@ static void hsw_pipe_A_crc_wa(struct drm_i915_private
*dev_priv,
static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
enum pipe pipe,
enum intel_pipe_crc_source *source,
- u32 *val,
- bool set_wa)
+ u32 *val)
{
if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
*source = INTEL_PIPE_CRC_SOURCE_PIPE;
@@ -357,10 +348,6 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private
*dev_priv,
*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
[Intel-gfx] [PATCH v5 9/9] drm/i915: Enable PSR2 by default
The support for PSR2 was polished, IGT tests for PSR2 was added and it was tested performing regular user workloads like browsing, editing documents and compiling Linux, so it is time to enable it by default and enjoy even more power-savings. Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 5d66e7313c75..bae266869c20 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -80,9 +80,6 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, case I915_PSR_DEBUG_DISABLE: case I915_PSR_DEBUG_FORCE_PSR1: return false; - case I915_PSR_DEBUG_DEFAULT: - if (i915_modparams.enable_psr <= 0) - return false; default: return crtc_state->has_psr2; } -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 7/9] drm/i915: Drop redundant checks to update PSR state
All of this checks are redudant and can be removed as the if bellow
already takes care when there is no changes in the state.
Cc: Dhinakaran Pandiyan
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 73453d89a841..d3e3996551c6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -878,15 +878,11 @@ void intel_psr_update(struct intel_dp *intel_dp,
if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
goto unlock;
- if (psr->enabled) {
- if (!enable || psr2_enable != psr->psr2_enabled)
- intel_psr_disable_locked(intel_dp);
- }
+ if (psr->enabled)
+ intel_psr_disable_locked(intel_dp);
- if (enable) {
- if (!psr->enabled || psr2_enable != psr->psr2_enabled)
- intel_psr_enable_locked(dev_priv, crtc_state);
- }
+ if (enable)
+ intel_psr_enable_locked(dev_priv, crtc_state);
unlock:
mutex_unlock(_priv->psr.lock);
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 6/9] drm/i915: Disable PSR2 while getting pipe CRC
When PSR2 is active aka after the number of frames programmed in
PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC
interruptions causing IGT tests to fail due timeout.
This same behavior don't happen with PSR1, as soon as pipe CRC is
enabled it blocks PSR1 activation so CRC calculation continues to
happens normaly.
This patch also set mode_changed as true when PSR is available to
force atomic check functions to compute new PSR state, otherwise PSR2
would not be disabled.
v4: Only setting mode_changed if has_psr is set(Dhinakaran)
v3: Reusing intel_crtc_crc_prepare() and crc_enabled, only setting
mode_changed if it can do PSR.
v2: Changed commit description to describe that PSR2 inhibit CRC
calculations.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/intel_psr.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c
b/drivers/gpu/drm/i915/intel_pipe_crc.c
index af64597c5c6e..c17f02b88453 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -307,6 +307,7 @@ intel_crtc_crc_setup_workarounds(struct intel_crtc *crtc,
bool enable)
goto put_state;
}
+ pipe_config->base.mode_changed = pipe_config->has_psr;
pipe_config->crc_enabled = enable;
if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A) {
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d9f64c362e2..73453d89a841 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp
*intel_dp,
return false;
}
+ if (crtc_state->crc_enabled)
+ return false;
+
return true;
}
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 8/9] drm/i915: Force PSR exit when getting pipe CRC
If PSR is active when pipe CRC is enabled the CRC calculations will
be inhibit by the transition to low power states that PSR brings.
So lets for a PSR exit and as soon as pipe CRC is enabled it will
block PSR activation avoid CRC timeouts when running IGT tests.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 36
1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index d3e3996551c6..5d66e7313c75 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -452,6 +452,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
* frames, we'll go with 9 frames for now
*/
idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+
val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
@@ -851,6 +852,20 @@ void intel_psr_disable(struct intel_dp *intel_dp,
cancel_work_sync(_priv->psr.work);
}
+static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv)
+{
+ /*
+* Display WA #0884: all
+* This documented WA for bxt can be safely applied
+* broadly so we can force HW tracking to exit PSR
+* instead of disabling and re-enabling.
+* Workaround tells us to write 0 to CUR_SURFLIVE_A,
+* but it makes more sense write to the current active
+* pipe.
+*/
+ I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
+}
+
/**
* intel_psr_update - Update PSR state
* @intel_dp: Intel DP
@@ -875,8 +890,13 @@ void intel_psr_update(struct intel_dp *intel_dp,
enable = crtc_state->has_psr && psr_global_enabled(psr->debug);
psr2_enable = intel_psr2_enabled(dev_priv, crtc_state);
- if (enable == psr->enabled && psr2_enable == psr->psr2_enabled)
+ if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) {
+ /* Force a PSR exit when enabling CRC to avoid CRC timeouts */
+ if (crtc_state->crc_enabled && psr->enabled)
+ psr_force_hw_tracking_exit(dev_priv);
+
goto unlock;
+ }
if (psr->enabled)
intel_psr_disable_locked(intel_dp);
@@ -1146,18 +1166,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
/* By definition flush = invalidate + flush */
- if (frontbuffer_bits) {
- /*
-* Display WA #0884: all
-* This documented WA for bxt can be safely applied
-* broadly so we can force HW tracking to exit PSR
-* instead of disabling and re-enabling.
-* Workaround tells us to write 0 to CUR_SURFLIVE_A,
-* but it makes more sense write to the current active
-* pipe.
-*/
- I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0);
- }
+ if (frontbuffer_bits)
+ psr_force_hw_tracking_exit(dev_priv);
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
schedule_work(_priv->psr.work);
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 4/9] drm/i915/psr: Drop test for EDP in CRTC when forcing commit
If has_psr is set it means that CRTC has a EDP panel attached so it
can be dropped, also has_psr is better than check for EDP output
alone as it will avoid set mode_changed when PSR is not supported in
panel or with current modeset.
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6175b1d2e0c8..2d9f64c362e2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -981,9 +981,7 @@ static int intel_psr_fastset_force(struct drm_i915_private
*dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (crtc_state->active &&
- intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
- intel_crtc_state->has_psr) {
+ if (crtc_state->active && intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
crtc_state->mode_changed = true;
break;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 3/9] drm/i915: Compute and commit color features in fastsets
In any commit, intel_modeset_pipe_config() will initialilly clear
and then recalculate most of the pipe states but it leave intel
specific color features states in reset state.
If after intel_pipe_config_compare() is detected that a fastset is
possible it will mark update_pipe as true and unsed mode_changed,
causing the color features state to be kept in reset state and then
latter being committed to hardware disabling the color features.
This issue can be reproduced by any code patch that duplicates the
actual(with color features already enabled) state and only mark
mode_changed as true.
Reviewed-by: Ville Syrjälä
Cc: Ville Syrjälä
Cc: Maarten Lankhorst
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_display.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d852cb282060..9312b3f35eb0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11235,7 +11235,8 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
return ret;
}
- if (mode_changed || crtc_state->color_mgmt_changed) {
+ if (mode_changed || pipe_config->update_pipe ||
+ crtc_state->color_mgmt_changed) {
ret = intel_color_check(pipe_config);
if (ret)
return ret;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 1/9] drm/i915/psr: Remove PSR2 FIXME
Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 75c1a5deebf5..8bed73914876 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -532,11 +532,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, int crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0; - /* -* FIXME psr2_support is messed up. It's both computed -* dynamically during PSR enable, and extracted from sink -* caps during eDP detection. -*/ if (!dev_priv->psr.sink_psr2_support) return false; -- 2.21.0 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v5 2/9] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset
Forcing a specific CRTC to the eDP connector was causing the
intel_psr_fastset_force() to mark mode_chaged in the wrong and
disabled CRTC causing no update in the PSR state.
Looks like our internal state track do not clear output_types and
has_psr in the disabled CRTCs, not sure if this is the expected
behavior or not but in the mean time this fix the issue.
Cc: Maarten Lankhorst
Cc: Dhinakaran Pandiyan
Reviewed-by: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 8bed73914876..6175b1d2e0c8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -981,7 +981,8 @@ static int intel_psr_fastset_force(struct drm_i915_private
*dev_priv)
intel_crtc_state = to_intel_crtc_state(crtc_state);
- if (intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
+ if (crtc_state->active &&
+ intel_crtc_has_type(intel_crtc_state, INTEL_OUTPUT_EDP) &&
intel_crtc_state->has_psr) {
/* Mark mode as changed to trigger a pipe->update() */
crtc_state->mode_changed = true;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/cml: Add CML PCI IDS
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/57607/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12381_full
Summary
---
**SUCCESS**
No regressions found.
Known issues
Here are the changes found in Patchwork_12381_full that come from known
issues:
### IGT changes ###
Issues hit
* igt@gem_exec_big:
- shard-hsw: PASS -> TIMEOUT [fdo#107937]
* igt@i915_pm_rpm@system-suspend-modeset:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107807]
* igt@kms_atomic_transition@3x-modeset-transitions:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6
* igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-newfb-render-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
- shard-snb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145]
* igt@kms_color@pipe-c-degamma:
- shard-apl: PASS -> FAIL [fdo#104782]
* igt@kms_cursor_crc@cursor-128x128-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-skl: NOTRUN -> FAIL [fdo#103232]
* igt@kms_fbcon_fbt@psr:
- shard-skl: NOTRUN -> FAIL [fdo#103833]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-apl: PASS -> FAIL [fdo#103167] +1
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +38
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +46
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +1
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +15
* igt@kms_panel_fitting@legacy:
- shard-skl: NOTRUN -> FAIL [fdo#105456]
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885]
* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: PASS -> FAIL [fdo#108948]
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-snb: PASS -> SKIP [fdo#109271] +6
* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-kbl: PASS -> FAIL [fdo#99912]
* igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm:
- shard-apl: NOTRUN -> FAIL [fdo#104894]
* igt@perf@oa-exponents:
- shard-glk: PASS -> FAIL [fdo#105483]
* igt@perf@short-reads:
- shard-skl: PASS -> FAIL [fdo#103183]
Possible fixes
* igt@i915_pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@kms_cursor_crc@cursor-64x64-sliding:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: FAIL [fdo#103167] -> PASS
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: FAIL [fdo#107815] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
* igt@kms_universal_plane@universal-plane-pipe-c-functional:
- shard-apl: FAIL [fdo#103166] -> PASS +1
Warnings
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-skl: SKIP [fdo#109271] -> INCOMPLETE [fdo#107807]
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: INCOMPLETE [fdo#103665] -> DMESG-FAIL [fdo#105763]
{name}: This element is suppressed. This means it is ignored when computing
the status
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use i915_global_register() (rev2)
== Series Details == Series: drm/i915: Use i915_global_register() (rev2) URL : https://patchwork.freedesktop.org/series/57605/ State : success == Summary == CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12380_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12380_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_pwrite@big-cpu-fbr: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@i915_pm_rpm@fences-dpms: - shard-skl: PASS -> INCOMPLETE [fdo#107807] * igt@kms_atomic_transition@3x-modeset-transitions: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-hang-newfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +5 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a: - shard-snb: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_cursor_crc@cursor-128x128-onscreen: - shard-apl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-onscreen: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_fbcon_fbt@psr: - shard-skl: NOTRUN -> FAIL [fdo#103833] * igt@kms_fence_pin_leak: - shard-snb: PASS -> SKIP [fdo#109271] * igt@kms_flip_tiling@flip-changes-tiling-y: - shard-skl: PASS -> FAIL [fdo#107931] / [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt: - shard-apl: PASS -> FAIL [fdo#103167] * igt@kms_frontbuffer_tracking@fbc-1p-rte: - shard-apl: PASS -> FAIL [fdo#103167] / [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render: - shard-snb: NOTRUN -> SKIP [fdo#109271] +38 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +46 * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw: - shard-skl: PASS -> FAIL [fdo#105682] * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +15 * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt: - shard-skl: PASS -> FAIL [fdo#103167] * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping: - shard-glk: PASS -> FAIL [fdo#108948] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-skl: PASS -> INCOMPLETE [fdo#104108] * igt@kms_plane@plane-position-covered-pipe-a-planes: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane@plane-position-covered-pipe-c-planes: - shard-glk: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_rotation_crc@primary-rotation-270: - shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815] Possible fixes * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait: - shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS * igt@kms_cursor_crc@cursor-alpha-opaque: - shard-apl: FAIL [fdo#109350] -> PASS * igt@kms_cursor_crc@cursor-size-change: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu: - shard-glk: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-skl: FAIL [fdo#103167] / [fdo#105682] -> PASS * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: FAIL [fdo#107815] -> PASS * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: INCOMPLETE [fdo#103665] -> PASS * igt@kms_universal_plane@universal-plane-pipe-c-functional: - shard-apl: FAIL [fdo#103166] -> PASS +1 Warnings * igt@kms_plane@pixel-format-pipe-b-planes: - shard-skl: DMESG-FAIL [fdo#103166] / [fdo#106885] -> FAIL [fdo#103166]
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
== Series Details ==
Series: drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
URL : https://patchwork.freedesktop.org/series/57619/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12387
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57619/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12387 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@i915_selftest@live_hangcheck:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#108044] / [fdo#108744]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7560u: CRASH -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108044]: https://bugs.freedesktop.org/show_bug.cgi?id=108044
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12387
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12387: 8a540d533fd4cea2d10b266728823a0a1ef41657 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8a540d533fd4 drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12387/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: split pll functions
== Series Details ==
Series: drm/i915/icl: split pll functions
URL : https://patchwork.freedesktop.org/series/57618/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12386
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57618/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12386:
### IGT changes ###
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_render_tiled_blits@basic:
- {fi-icl-y}: PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12386 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7560u: CRASH -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12386
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12386: aa1bb01b628e15767e705bdaef5e14b3aa76f96e @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
aa1bb01b628e drm/i915/icl: remove intel_dpll_is_combophy()
c990b01020e4 drm/i915/icl: split combo and tbt pll funcs
afabb4fade35 drm/i915/icl: split combo and mg pll disable
c94f26a3f8e1 drm/i915/icl: use a function pointer for pll_write when enabling
6052e88ffb68 drm/i915/icl: split combo and mg pll enable
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12386/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Populate pipe_offsets[] & co. accurately
== Series Details == Series: drm/i915: Populate pipe_offsets[] & co. accurately URL : https://patchwork.freedesktop.org/series/57600/ State : success == Summary == CI Bug Log - changes from CI_DRM_5708_full -> Patchwork_12378_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12378_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_param@invalid-size-set: - shard-apl: PASS -> INCOMPLETE [fdo#103927] * igt@i915_pm_rpm@pm-tiling: - shard-skl: PASS -> INCOMPLETE [fdo#107807] +1 * igt@kms_atomic_transition@3x-modeset-transitions: - shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +6 * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-hang-newfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_ccs@pipe-a-crc-sprite-planes-basic: - shard-apl: PASS -> FAIL [fdo#106510] / [fdo#108145] * igt@kms_color@pipe-c-degamma: - shard-apl: PASS -> FAIL [fdo#104782] * igt@kms_cursor_crc@cursor-256x85-onscreen: - shard-skl: NOTRUN -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-random: - shard-apl: PASS -> FAIL [fdo#103232] +3 * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: PASS -> FAIL [fdo#102670] * igt@kms_flip@flip-vs-expired-vblank-interruptible: - shard-glk: PASS -> FAIL [fdo#105363] * igt@kms_flip_tiling@flip-yf-tiled: - shard-skl: PASS -> FAIL [fdo#108145] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render: - shard-snb: NOTRUN -> SKIP [fdo#109271] +38 * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt: - shard-skl: NOTRUN -> SKIP [fdo#109271] +28 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt: - shard-apl: NOTRUN -> SKIP [fdo#109271] +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +15 * igt@kms_panel_fitting@legacy: - shard-skl: NOTRUN -> FAIL [fdo#105456] * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] * igt@kms_plane@plane-position-covered-pipe-c-planes: - shard-glk: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc: - shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145] * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: PASS -> FAIL [fdo#107815] * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_rotation_crc@multiplane-rotation-cropping-top: - shard-kbl: PASS -> FAIL [fdo#109016] * igt@kms_rotation_crc@primary-rotation-270: - shard-skl: PASS -> FAIL [fdo#103925] / [fdo#107815] * igt@kms_setmode@basic: - shard-kbl: PASS -> FAIL [fdo#99912] * igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: - shard-apl: NOTRUN -> FAIL [fdo#104894] * igt@tools_test@tools_test: - shard-glk: PASS -> SKIP [fdo#109271] Possible fixes * igt@i915_pm_rc6_residency@rc6-accuracy: - shard-snb: SKIP [fdo#109271] -> PASS * igt@i915_pm_rpm@gem-execbuf-stress-extra-wait: - shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-hsw: DMESG-WARN [fdo#107956] -> PASS * igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge: - shard-skl: FAIL [fdo#104671] -> PASS * igt@kms_cursor_crc@cursor-256x85-offscreen: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-64x64-sliding: - shard-apl: FAIL [fdo#103232] -> PASS +1 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: - shard-apl: FAIL [fdo#103167] -> PASS * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu: - shard-skl: FAIL [fdo#103167] -> PASS +1 * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render: - shard-skl: FAIL [fdo#105682] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc: - shard-skl: FAIL [fdo#103167] / [fdo#105682] -> PASS * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: FAIL [fdo#107815] /
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2] drm/i915/guc: Fixing error code for WOPCM initialization (rev2)
== Series Details ==
Series: series starting with [v2] drm/i915/guc: Fixing error code for WOPCM
initialization (rev2)
URL : https://patchwork.freedesktop.org/series/57551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12385
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57551/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12385 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] /
[fdo#105602]
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@prime_vgem@basic-fence-flip:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +4
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7560u: CRASH -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-pnv-d510 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12385
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12385: bc935ae6ac01df92fdb5e0a45bbd9fa9431c63fe @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc935ae6ac01 drm/i915/guc: Fixing error code for WOPCM initialization
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12385/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Fix CRC mismatch error for DP link layer compliance
Setting the pixel rounding bit to 1 in PIPE_CHICKEN register allows
to passthrough FB pixels unmodified across pipe. This fixes the failures
for DP link layer compliance tests 4.4.1.1, 4.4.1.2 & 4.4.1.3.
(Lineage #1605353570)
Cc: Clint Taylor
Cc: Mika Kahola
Cc: Jani Nikula
Signed-off-by: Aditya Swarup
---
WA for ICL DP compliance. It fixes failing test in igt for crc mismatch
wrt cursor plane. Can be searched using Lineage #1605353570.
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 8 +++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b868347481..4713fbb3e021 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7663,6 +7663,7 @@ enum {
#define _PIPEB_CHICKEN 0x71038
#define _PIPEC_CHICKEN 0x72038
#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7)
+#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15)
#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
_PIPEB_CHICKEN)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d852cb282060..92be3476fef1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3970,7 +3970,13 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc)
* and rounding for per-pixel values 00 and 0xff
*/
tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
-
+ /*
+* Display WA # 1605353570: icl
+* Set the pixel rounding bit to 1 for allowing
+* passthrough of Frame buffer pixels unmodified
+* across pipe
+*/
+ tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
I915_WRITE(PIPE_CHICKEN(pipe), tmp);
}
--
2.17.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/5] drm/i915/icl: use a function pointer for pll_write when enabling
This allows us to share the icl_pll_enable() between the different types
of PLL while allowing the caller to differentiate how to write the
registers.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 3b3de99756d6..5511bc23ea3d 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3118,9 +3118,10 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
static void icl_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
- i915_reg_t enable_reg)
+ i915_reg_t enable_reg,
+ void (*pll_write)(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll))
{
- const enum intel_dpll_id id = pll->info->id;
u32 val;
val = I915_READ(enable_reg);
@@ -3133,12 +3134,9 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
*/
if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE,
PLL_POWER_STATE, 1))
- DRM_ERROR("PLL %d Power not enabled\n", id);
+ DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
- if (intel_dpll_is_combophy(id) || id == DPLL_ID_ICL_TBTPLL)
- icl_dpll_write(dev_priv, pll);
- else
- icl_mg_pll_write(dev_priv, pll);
+ pll_write(dev_priv, pll);
/*
* DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3152,7 +3150,7 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, PLL_LOCK,
1)) /* 600us actually. */
- DRM_ERROR("PLL %d not locked\n", id);
+ DRM_ERROR("PLL %d not locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
}
@@ -3162,7 +3160,7 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
{
i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
- icl_pll_enable(dev_priv, pll, enable_reg);
+ icl_pll_enable(dev_priv, pll, enable_reg, icl_dpll_write);
}
static void mg_pll_enable(struct drm_i915_private *dev_priv,
@@ -3171,7 +3169,7 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
i915_reg_t enable_reg =
MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
- icl_pll_enable(dev_priv, pll, enable_reg);
+ icl_pll_enable(dev_priv, pll, enable_reg, icl_mg_pll_write);
}
static void icl_pll_disable(struct drm_i915_private *dev_priv,
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/5] drm/i915/icl: split combo and tbt pll funcs
Like was done for MG and combo, now finish the per-type split of the
vfunc by moving TBT out of the combo functions. Now we can completely
remove icl_pll_id_to_enable_reg() since each PLL type pass as all the
information via arguments.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 63 ++-
1 file changed, 42 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index d334dd9bcae6..d26e6f41cb30 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2956,16 +2956,6 @@ icl_get_dpll(struct intel_crtc *crtc, struct
intel_crtc_state *crtc_state,
return pll;
}
-static i915_reg_t icl_pll_id_to_enable_reg(enum intel_dpll_id id)
-{
- if (intel_dpll_is_combophy(id))
- return CNL_DPLL_ENABLE(id);
- else if (id == DPLL_ID_ICL_TBTPLL)
- return TBT_PLL_ENABLE;
-
- return MG_PLL_ENABLE(icl_pll_id_to_tc_port(id));
-}
-
static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
@@ -3030,7 +3020,8 @@ static bool mg_pll_get_hw_state(struct drm_i915_private
*dev_priv,
static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
-struct intel_dpll_hw_state *hw_state)
+struct intel_dpll_hw_state *hw_state,
+i915_reg_t enable_reg)
{
const enum intel_dpll_id id = pll->info->id;
intel_wakeref_t wakeref;
@@ -3042,7 +3033,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
if (!wakeref)
return false;
- val = I915_READ(icl_pll_id_to_enable_reg(id));
+ val = I915_READ(enable_reg);
if (!(val & PLL_ENABLE))
goto out;
@@ -3055,6 +3046,21 @@ static bool icl_pll_get_hw_state(struct drm_i915_private
*dev_priv,
return ret;
}
+static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll,
+ struct intel_dpll_hw_state *hw_state)
+{
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state,
+ CNL_DPLL_ENABLE(pll->info->id));
+}
+
+static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll,
+struct intel_dpll_hw_state *hw_state)
+{
+ return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
+}
+
static void icl_dpll_write(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3158,9 +3164,14 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+ icl_pll_enable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id),
+ icl_dpll_write);
+}
- icl_pll_enable(dev_priv, pll, enable_reg, icl_dpll_write);
+static void tbt_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE, icl_dpll_write);
}
static void mg_pll_enable(struct drm_i915_private *dev_priv,
@@ -3212,9 +3223,13 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+ icl_pll_disable(dev_priv, pll, CNL_DPLL_ENABLE(pll->info->id));
+}
- icl_pll_disable(dev_priv, pll, enable_reg);
+static void tbt_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
}
static void mg_pll_disable(struct drm_i915_private *dev_priv,
@@ -3248,10 +3263,16 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
hw_state->mg_pll_tdc_coldst_bias);
}
-static const struct intel_shared_dpll_funcs icl_pll_funcs = {
+static const struct intel_shared_dpll_funcs combo_pll_funcs = {
.enable = combo_pll_enable,
.disable = combo_pll_disable,
- .get_hw_state = icl_pll_get_hw_state,
+ .get_hw_state = combo_pll_get_hw_state,
+};
+
+static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
+ .enable = tbt_pll_enable,
+ .disable = tbt_pll_disable,
+ .get_hw_state = tbt_pll_get_hw_state,
};
static const struct
[Intel-gfx] [PATCH 1/5] drm/i915/icl: split combo and mg pll enable
Let's start using the vfuncs to differentiate MG and Combo PLLs. The end
goal is to decouple the type of the PLL from the IDs since the latter
are likely to change from one platform to another. This also makes the
code easier to read by not having lots of if/else chains on leaf
functions.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e4ec73d415d9..3b3de99756d6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3117,10 +3117,10 @@ static void icl_mg_pll_write(struct drm_i915_private
*dev_priv,
}
static void icl_pll_enable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ i915_reg_t enable_reg)
{
const enum intel_dpll_id id = pll->info->id;
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
u32 val;
val = I915_READ(enable_reg);
@@ -3157,6 +3157,23 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
/* DVFS post sequence would be here. See the comment above. */
}
+static void combo_pll_enable(struct drm_i915_private *dev_priv,
+struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+}
+
+static void mg_pll_enable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_enable(dev_priv, pll, enable_reg);
+}
+
static void icl_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
@@ -3218,13 +3235,13 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
}
static const struct intel_shared_dpll_funcs icl_pll_funcs = {
- .enable = icl_pll_enable,
+ .enable = combo_pll_enable,
.disable = icl_pll_disable,
.get_hw_state = icl_pll_get_hw_state,
};
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
- .enable = icl_pll_enable,
+ .enable = mg_pll_enable,
.disable = icl_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915/icl: remove intel_dpll_is_combophy()
This is only used in intel_display() and shouldn't be needed there.
We don't want to keep converting from pll id to pll type so just remove
the function.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_display.c | 3 ---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 5 -
2 files changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d852cb282060..c2558231dcb2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9592,9 +9592,6 @@ static void icelake_get_ddi_pll(struct drm_i915_private
*dev_priv,
temp = I915_READ(DPCLKA_CFGCR0_ICL) &
DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-
- if (WARN_ON(!intel_dpll_is_combophy(id)))
- return;
} else if (intel_port_is_tc(dev_priv, port)) {
id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
} else {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index d26e6f41cb30..5147e0cabb58 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2649,11 +2649,6 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port
tc_port)
return tc_port + DPLL_ID_ICL_MGPLL1;
}
-bool intel_dpll_is_combophy(enum intel_dpll_id id)
-{
- return id == DPLL_ID_ICL_DPLL0 || id == DPLL_ID_ICL_DPLL1;
-}
-
static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
u32 *target_dco_khz,
struct intel_dpll_hw_state *state)
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5] drm/i915/icl: split combo and mg pll disable
Like was done in the enable case, split the implementation of the
disable for MG and Combo PLLs.
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 5511bc23ea3d..d334dd9bcae6 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -3173,10 +3173,9 @@ static void mg_pll_enable(struct drm_i915_private
*dev_priv,
}
static void icl_pll_disable(struct drm_i915_private *dev_priv,
- struct intel_shared_dpll *pll)
+ struct intel_shared_dpll *pll,
+ i915_reg_t enable_reg)
{
- const enum intel_dpll_id id = pll->info->id;
- i915_reg_t enable_reg = icl_pll_id_to_enable_reg(id);
u32 val;
/* The first steps are done by intel_ddi_post_disable(). */
@@ -3193,7 +3192,7 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
/* Timeout is actually 1us. */
if (intel_wait_for_register(dev_priv, enable_reg, PLL_LOCK, 0, 1))
- DRM_ERROR("PLL %d locked\n", id);
+ DRM_ERROR("PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
@@ -3207,7 +3206,24 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
*/
if (intel_wait_for_register(dev_priv, enable_reg, PLL_POWER_STATE, 0,
1))
- DRM_ERROR("PLL %d Power not disabled\n", id);
+ DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
+}
+
+static void combo_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg = icl_pll_id_to_enable_reg(pll->info->id);
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
+}
+
+static void mg_pll_disable(struct drm_i915_private *dev_priv,
+ struct intel_shared_dpll *pll)
+{
+ i915_reg_t enable_reg =
+ MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+
+ icl_pll_disable(dev_priv, pll, enable_reg);
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3234,13 +3250,13 @@ static void icl_dump_hw_state(struct drm_i915_private
*dev_priv,
static const struct intel_shared_dpll_funcs icl_pll_funcs = {
.enable = combo_pll_enable,
- .disable = icl_pll_disable,
+ .disable = combo_pll_disable,
.get_hw_state = icl_pll_get_hw_state,
};
static const struct intel_shared_dpll_funcs mg_pll_funcs = {
.enable = mg_pll_enable,
- .disable = icl_pll_disable,
+ .disable = mg_pll_disable,
.get_hw_state = mg_pll_get_hw_state,
};
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 0/5] drm/i915/icl: split pll functions
This should achieve a similar goal as in https://patchwork.freedesktop.org/patch/287567/?series=57116=1, decoupling the PLL ids from the type. I actually prefer the other implementation in which we can use the pll_info struct to store the info about the pll rather than spreading that across several functions. It's not a strong preference though. Anyway, this should be sufficient to allow future platforms to share common functions. Warning: this is only build-tested... I want to confirm if this is the way to go. Lucas De Marchi (5): drm/i915/icl: split combo and mg pll enable drm/i915/icl: use a function pointer for pll_write when enabling drm/i915/icl: split combo and mg pll disable drm/i915/icl: split combo and tbt pll funcs drm/i915/icl: remove intel_dpll_is_combophy() drivers/gpu/drm/i915/intel_display.c | 3 - drivers/gpu/drm/i915/intel_dpll_mgr.c | 127 ++ 2 files changed, 87 insertions(+), 43 deletions(-) -- 2.20.1 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915/guc: Fixing error code for WOPCM initialization
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
v2: change the final return code in i915_pci_probe() to ENODEV
instead of the specific wopcm change. - Daniele
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/i915_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c42c5ccf38fe..f962b5c0b3c1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -778,7 +778,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const
struct pci_device_id *ent)
err = i915_driver_load(pdev, ent);
if (err)
- return err;
+ return i915_error_injected() ? -ENODEV : err;
if (i915_inject_load_failure()) {
i915_pci_remove(pdev);
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
== Series Details ==
Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field
with PSR2 TP2/3 wakeup time
URL : https://patchwork.freedesktop.org/series/57615/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12384
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57615/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12384 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: PASS -> INCOMPLETE [fdo#109831]
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: PASS -> SKIP [fdo#109271]
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-byt-j1900: PASS -> FAIL [fdo#108800]
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
- fi-skl-6770hq: PASS -> FAIL [fdo#108511]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] /
[fdo#105602]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831
Participating hosts (47 -> 39)
--
Missing(8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bwr-2160 fi-icl-u3 fi-byt-n2820 fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12384
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12384: 409676aab5a3ff1670d9fe33719825659217a536 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
409676aab5a3 drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
e5ba837d0010 drm/i915/psr: Move logic to get TPS registers values to another
function
6bfff5b6e1e0 drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup
time
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12384/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Fixing error code for WOPCM initialization
On 3/5/19 2:06 PM, Daniele Ceraolo Spurio wrote:
On 3/5/19 2:05 PM, Daniele Ceraolo Spurio wrote:
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
To clarify, we want to silence this:
forgot to paste the log...
<4> [381.569479] i915: probe of :00:02.0 failed with error -7
Daniele
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..a651557e6e4e 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -169,7 +169,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(!wopcm->size);
if (i915_inject_load_failure())
- return -E2BIG;
+ return -ENODEV;
Would it be better to just change the final return code in
i915_pci_probe() to ENODEV?
i.e.
err = i915_driver_load(pdev, ent);
if (err)
return i915_error_injected() ? -ENODEV : err;
This way we can test that the possible error codes (E2BIG in this
case) don't hit issues in dedicated cases during onion unwinding.
Daniele
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
Okay this approach seems to provide a wider fix. Will make this change.
Thanks for the review.
Sujaritha
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
== Series Details == Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time URL : https://patchwork.freedesktop.org/series/57615/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time -drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) Commit: drm/i915/psr: Move logic to get TPS registers values to another function -O:drivers/gpu/drm/i915/intel_psr.c:449:27: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_psr.c:454:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:481:27: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:486:23: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_psr.c:486:23: warning: expression using sizeof(void) Commit: drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
== Series Details == Series: series starting with [v3,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time URL : https://patchwork.freedesktop.org/series/57615/ State : warning == Summary == $ dim checkpatch origin/drm-tip 6bfff5b6e1e0 drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time -:65: WARNING:LONG_LINE: line over 100 characters #65: FILE: drivers/gpu/drm/i915/intel_bios.c:786: + dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = dev_priv->vbt.psr.tp2_tp3_wakeup_time_us; total: 0 errors, 1 warnings, 0 checks, 63 lines checked e5ba837d0010 drm/i915/psr: Move logic to get TPS registers values to another function 409676aab5a3 drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.
v2: replacing enum to numerical usec time (Jani)
BSpec: 20131
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 25 +
drivers/gpu/drm/i915/intel_psr.c | 8
drivers/gpu/drm/i915/intel_vbt_defs.h | 3 +++
4 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff039750069d..661dce6ccb90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,7 @@ struct intel_vbt_data {
enum psr_lines_to_wait lines_to_wait;
int tp1_wakeup_time_us;
int tp2_tp3_wakeup_time_us;
+ int psr2_tp2_tp3_wakeup_time_us;
} psr;
struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..ecc352ec7715 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -760,6 +760,31 @@ parse_psr(struct drm_i915_private *dev_priv, const struct
bdb_header *bdb)
dev_priv->vbt.psr.tp1_wakeup_time_us =
psr_table->tp1_wakeup_time * 100;
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
psr_table->tp2_tp3_wakeup_time * 100;
}
+
+ if (bdb->version >= 226) {
+ u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+
+ wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+ switch (wakeup_time) {
+ case 0:
+ wakeup_time = 500;
+ break;
+ case 1:
+ wakeup_time = 100;
+ break;
+ case 3:
+ wakeup_time = 50;
+ break;
+ default:
+ case 2:
+ wakeup_time = 2500;
+ break;
+ }
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+ } else {
+ /* Reusing PSR1 wakeup time for PSR2 in older VBTs */
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us =
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
+ }
}
static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 75c1a5deebf5..831f345b4ad8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -511,12 +511,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
- dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+ if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+ else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us;
else
val |= EDP_PSR2_TP2_TIME_2500us;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index bf3662ad5fed..fdbbb9a53804 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,6 +772,9 @@ struct psr_table {
/* TP wake up time in multiple of 100 */
u16 tp1_wakeup_time;
u16 tp2_tp3_wakeup_time;
+
+ /* PSR2 TP2/TP3 wakeup time for 16 panels */
+ u32 psr2_tp2_tp3_wakeup_time;
} __packed;
struct bdb_psr {
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
This will make hsw_activate_psr1() more easy to read and will make
future modification to TPS registers more easy to review and read.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 56 +++-
1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 831f345b4ad8..2fa2f4c9c935 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct intel_dp
*intel_dp)
drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
}
-static void hsw_activate_psr1(struct intel_dp *intel_dp)
+static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 max_sleep_time = 0x1f;
- u32 val = EDP_PSR_ENABLE;
-
- /* Let's use 6 as the minimum to cover all known cases including the
-* off-by-one issue that HW has in some cases.
-*/
- int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
- /* sink_sync_latency of 8 means source has to wait for more than 8
-* frames, we'll go with 9 frames for now
-*/
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
- val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
-
- val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
- if (IS_HASWELL(dev_priv))
- val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
-
- if (dev_priv->psr.link_standby)
- val |= EDP_PSR_LINK_STANDBY;
+ u32 val = 0;
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
- val |= EDP_PSR_TP1_TIME_0us;
+ val |= EDP_PSR_TP1_TIME_0us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
@@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
val |= EDP_PSR_TP1_TIME_2500us;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
- val |= EDP_PSR_TP2_TP3_TIME_0us;
+ val |= EDP_PSR_TP2_TP3_TIME_0us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
@@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
+ return val;
+}
+
+static void hsw_activate_psr1(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 max_sleep_time = 0x1f;
+ u32 val = EDP_PSR_ENABLE;
+
+ /* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
+*/
+ int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+
+ /* sink_sync_latency of 8 means source has to wait for more than 8
+* frames, we'll go with 9 frames for now
+*/
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+
+ val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+ if (IS_HASWELL(dev_priv))
+ val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
+
+ if (dev_priv->psr.link_standby)
+ val |= EDP_PSR_LINK_STANDBY;
+
+ val |= psr1_tps_regs_val_get(intel_dp);
+
if (INTEL_GEN(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
TPS4 support was added to PSR because HBR3/PSR spec was not closed
when ICL was freezed so if HBR3 was supported by PSR, ICL would
already be ready but it was not added to spec so lets always
disable TPS4.
v3: Missed ";" SPANK SPANK SPANK!!!
BSpec: 17524
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_psr.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 16ce9c609c65..a7697909e0c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4205,6 +4205,8 @@ enum {
#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
+#define EDP_PSR_TP4_TIME_SHIFT (6) /* ICL+ */
+#define EDP_PSR_TP4_TIME_0US (3 << EDP_PSR_TP4_TIME_SHIFT)
/* ICL+ */
#define EDP_PSR_TP1_TIME_500us (0 << 4)
#define EDP_PSR_TP1_TIME_100us (1 << 4)
#define EDP_PSR_TP1_TIME_2500us (2 << 4)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2fa2f4c9c935..c70d735f5b93 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
+ if (INTEL_GEN(dev_priv) >= 11)
+ val |= EDP_PSR_TP4_TIME_0US;
+
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
== Series Details == Series: series starting with [v2,1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time URL : https://patchwork.freedesktop.org/series/57614/ State : failure == Summary == CALLscripts/checksyscalls.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/gpu/drm/i915/intel_psr.o drivers/gpu/drm/i915/intel_psr.c: In function ‘psr1_tps_regs_val_get’: drivers/gpu/drm/i915/intel_psr.c:448:2: error: expected ‘;’ before ‘if’ if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0) ^~ scripts/Makefile.build:276: recipe for target 'drivers/gpu/drm/i915/intel_psr.o' failed make[4]: *** [drivers/gpu/drm/i915/intel_psr.o] Error 1 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm/i915' failed make[3]: *** [drivers/gpu/drm/i915] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu/drm' failed make[2]: *** [drivers/gpu/drm] Error 2 scripts/Makefile.build:492: recipe for target 'drivers/gpu' failed make[1]: *** [drivers/gpu] Error 2 Makefile:1043: recipe for target 'drivers' failed make: *** [drivers] Error 2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Remove alpha support protection
== Series Details ==
Series: drm/i915/icl: Remove alpha support protection
URL : https://patchwork.freedesktop.org/series/57609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12382
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57609/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12382 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] /
[fdo#105602]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
Warnings
* igt@i915_selftest@live_contexts:
- fi-icl-u3: DMESG-FAIL [fdo#108569] -> INCOMPLETE [fdo#108569]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-kbl-7500u fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12382
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12382: 847153c76c51d756fe985e879b00f59310028cee @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
847153c76c51 drm/i915/icl: Remove alpha support protection
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12382/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time
A new field with the training pattern(TP) wakeup time for PSR2 was
added to VBT, so lets use it when available otherwise it will
fallback to PSR1 wakeup time.
v2: replacing enum to numerical usec time (Jani)
BSpec: 20131
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_bios.c | 25 +
drivers/gpu/drm/i915/intel_psr.c | 8
drivers/gpu/drm/i915/intel_vbt_defs.h | 3 +++
4 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff039750069d..661dce6ccb90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,7 @@ struct intel_vbt_data {
enum psr_lines_to_wait lines_to_wait;
int tp1_wakeup_time_us;
int tp2_tp3_wakeup_time_us;
+ int psr2_tp2_tp3_wakeup_time_us;
} psr;
struct {
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index b508d8a735e0..ecc352ec7715 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -760,6 +760,31 @@ parse_psr(struct drm_i915_private *dev_priv, const struct
bdb_header *bdb)
dev_priv->vbt.psr.tp1_wakeup_time_us =
psr_table->tp1_wakeup_time * 100;
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us =
psr_table->tp2_tp3_wakeup_time * 100;
}
+
+ if (bdb->version >= 226) {
+ u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time;
+
+ wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3;
+ switch (wakeup_time) {
+ case 0:
+ wakeup_time = 500;
+ break;
+ case 1:
+ wakeup_time = 100;
+ break;
+ case 3:
+ wakeup_time = 50;
+ break;
+ default:
+ case 2:
+ wakeup_time = 2500;
+ break;
+ }
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time;
+ } else {
+ /* Reusing PSR1 wakeup time for PSR2 in older VBTs */
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us =
dev_priv->vbt.psr.tp2_tp3_wakeup_time_us;
+ }
}
static void parse_dsi_backlight_ports(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 75c1a5deebf5..831f345b4ad8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -511,12 +511,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
- if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&
- dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)
+ if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 &&
+ dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50)
val |= EDP_PSR2_TP2_TIME_50us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
+ else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR2_TP2_TIME_100us;
- else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
+ else if (dev_priv->vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500)
val |= EDP_PSR2_TP2_TIME_500us;
else
val |= EDP_PSR2_TP2_TIME_2500us;
diff --git a/drivers/gpu/drm/i915/intel_vbt_defs.h
b/drivers/gpu/drm/i915/intel_vbt_defs.h
index bf3662ad5fed..fdbbb9a53804 100644
--- a/drivers/gpu/drm/i915/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/intel_vbt_defs.h
@@ -772,6 +772,9 @@ struct psr_table {
/* TP wake up time in multiple of 100 */
u16 tp1_wakeup_time;
u16 tp2_tp3_wakeup_time;
+
+ /* PSR2 TP2/TP3 wakeup time for 16 panels */
+ u32 psr2_tp2_tp3_wakeup_time;
} __packed;
struct bdb_psr {
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR
TPS4 support was added to PSR because HBR3/PSR spec was not closed
when ICL was freezed so if HBR3 was supported by PSR, ICL would
already be ready but it was not added to spec so lets always
disable TPS4.
BSpec: 17524
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_psr.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 16ce9c609c65..a7697909e0c9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4205,6 +4205,8 @@ enum {
#define EDP_PSR_TP2_TP3_TIME_100us (1 << 8)
#define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8)
#define EDP_PSR_TP2_TP3_TIME_0us (3 << 8)
+#define EDP_PSR_TP4_TIME_SHIFT (6) /* ICL+ */
+#define EDP_PSR_TP4_TIME_0US (3 << EDP_PSR_TP4_TIME_SHIFT)
/* ICL+ */
#define EDP_PSR_TP1_TIME_500us (0 << 4)
#define EDP_PSR_TP1_TIME_100us (1 << 4)
#define EDP_PSR_TP1_TIME_2500us (2 << 4)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2fa2f4c9c935..b67520b5fd3c 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -442,6 +442,9 @@ static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 val = 0;
+ if (INTEL_GEN(dev_priv) >= 11)
+ val |= EDP_PSR_TP4_TIME_0US
+
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
val |= EDP_PSR_TP1_TIME_0us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
This will make hsw_activate_psr1() more easy to read and will make
future modification to TPS registers more easy to review and read.
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_psr.c | 56 +++-
1 file changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 831f345b4ad8..2fa2f4c9c935 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct intel_dp
*intel_dp)
drm_dp_dpcd_writeb(_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
}
-static void hsw_activate_psr1(struct intel_dp *intel_dp)
+static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 max_sleep_time = 0x1f;
- u32 val = EDP_PSR_ENABLE;
-
- /* Let's use 6 as the minimum to cover all known cases including the
-* off-by-one issue that HW has in some cases.
-*/
- int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
-
- /* sink_sync_latency of 8 means source has to wait for more than 8
-* frames, we'll go with 9 frames for now
-*/
- idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
- val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
-
- val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
- if (IS_HASWELL(dev_priv))
- val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
-
- if (dev_priv->psr.link_standby)
- val |= EDP_PSR_LINK_STANDBY;
+ u32 val = 0;
if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
- val |= EDP_PSR_TP1_TIME_0us;
+ val |= EDP_PSR_TP1_TIME_0us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
val |= EDP_PSR_TP1_TIME_100us;
else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
@@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
val |= EDP_PSR_TP1_TIME_2500us;
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
- val |= EDP_PSR_TP2_TP3_TIME_0us;
+ val |= EDP_PSR_TP2_TP3_TIME_0us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
val |= EDP_PSR_TP2_TP3_TIME_100us;
else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
@@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
+ return val;
+}
+
+static void hsw_activate_psr1(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 max_sleep_time = 0x1f;
+ u32 val = EDP_PSR_ENABLE;
+
+ /* Let's use 6 as the minimum to cover all known cases including the
+* off-by-one issue that HW has in some cases.
+*/
+ int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+
+ /* sink_sync_latency of 8 means source has to wait for more than 8
+* frames, we'll go with 9 frames for now
+*/
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+
+ val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
+ if (IS_HASWELL(dev_priv))
+ val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
+
+ if (dev_priv->psr.link_standby)
+ val |= EDP_PSR_LINK_STANDBY;
+
+ val |= psr1_tps_regs_val_get(intel_dp);
+
if (INTEL_GEN(dev_priv) >= 8)
val |= EDP_PSR_CRC_ENABLE;
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915/icl: Remove alpha support protection
On Tue, Mar 05, 2019 at 02:11:53PM -0800, José Roberto de Souza wrote:
> Now with the watermarks fixes merged, Icelake is stable enough to
> have the alpha support protection flag removed.
>
> We have a few ICL machines in our CI and it is mostly green with
> failures in tests that will not impact future linux installations.
> Also there is no warnings, errors, flickering or any visual defects
> while doing ordinary tasks like browsing and editing documents in a
> dual monitor setup.
>
> As a reminder i915.alpha_support was created to protect
> future linux installation's iso images that might contain a
> kernel from the enabling time of the new platform. Without this
> protection most of linux installation was recommending
> nomodeset option during installation that was getting stick
> there after installation.
>
> Specifically, alpha support says nothing about the development
> state of the hardware, and everything about the state of the
> driver in a kernel release.
>
> This is semantically no different from the old
> preliminary_hw_support flag, but the old one was all too often
> interpreted as (preliminary hw) support instead of the intended
> (preliminary) hw support, and it was misleading for everyone.
> Hence the rename.
>
> Reference: https://intel-gfx-ci.01.org/tree/drm-tip/fi-icl-y.html
This view is great. It is unfortunate we cannot save this and
this link will be invalid in few runs.
> Reference: https://intel-gfx-ci.01.org/tree/drm-tip/shard-iclb.html
This picture doesn't help, but taking your word, and the BAT results
and quoting Jani Saarinen: "Nice improvement here what comes to passes..."
Old: f2-icl-u total:262 pass:107 dwarn:98 dfail:0 fail:1 skip:55
time:429s
f2-icl-u total:263 pass:222 dwarn:9 dfail:0 fail:3 skip:29
time:339s
Old: f2-icl-y total:262 pass:105 dwarn:98 dfail:0 fail:4 skip:54
time:430s
f2-icl-y total:476 pass:225 dwarn:7 dfail:0 fail:4 skip:240
time:470s
Reviewed-by: Rodrigo Vivi
> Cc: James Ausmus
> Cc: Jani Saarinen
> Cc: Paulo Zanoni
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_pci.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index c42c5ccf38fe..527bd1ceb9ac 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -658,7 +658,6 @@ static const struct intel_device_info
> intel_cannonlake_info = {
> static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ICELAKE),
> - .is_alpha_support = 1,
> .engine_mask =
> BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> };
> --
> 2.21.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/cml: Add CML PCI IDS
== Series Details == Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS URL : https://patchwork.freedesktop.org/series/57607/ State : success == Summary == CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12381 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57607/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12381 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_module_load@reload-with-fault-injection: - fi-kbl-7560u: PASS -> INCOMPLETE [fdo#109831] Possible fixes * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109831]: https://bugs.freedesktop.org/show_bug.cgi?id=109831 Participating hosts (47 -> 39) -- Missing(8): fi-kbl-7567u fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-skl-6600u Build changes - * Linux: CI_DRM_5708 -> Patchwork_12381 CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12381: bb45861c21cfbb5b726d0f276b7ed7b73b9a7798 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == bb45861c21cf drm/i915/cml: Introduce Comet Lake PCH b6b26a8b48bc drm/i915/cml: Add CML PCI IDS == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12381/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
== Series Details == Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask URL : https://patchwork.freedesktop.org/series/57595/ State : success == Summary == CI Bug Log - changes from CI_DRM_5706_full -> Patchwork_12375_full Summary --- **SUCCESS** No regressions found. Known issues Here are the changes found in Patchwork_12375_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_pread@stolen-normal: - shard-skl: NOTRUN -> SKIP [fdo#109271] +19 * igt@i915_pm_rpm@gem-execbuf: - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] * igt@kms_busy@basic-flip-d: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-skl: PASS -> DMESG-WARN [fdo#107956] - shard-kbl: PASS -> DMESG-WARN [fdo#107956] * igt@kms_chv_cursor_fail@pipe-c-256x256-right-edge: - shard-skl: PASS -> FAIL [fdo#104671] * igt@kms_cursor_crc@cursor-64x21-random: - shard-apl: PASS -> FAIL [fdo#103232] +2 * igt@kms_cursor_crc@cursor-64x64-suspend: - shard-apl: PASS -> FAIL [fdo#103191] / [fdo#103232] * igt@kms_cursor_crc@cursor-alpha-transparent: - shard-skl: PASS -> FAIL [fdo#109350] * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_draw_crc@draw-method-xrgb-render-xtiled: - shard-glk: PASS -> FAIL [fdo#107791] * igt@kms_flip_tiling@flip-changes-tiling: - shard-skl: PASS -> FAIL [fdo#108303] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff: - shard-apl: PASS -> FAIL [fdo#103167] +1 * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-apl: NOTRUN -> SKIP [fdo#109271] +1 * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-skl: NOTRUN -> FAIL [fdo#108145] +1 * igt@kms_rotation_crc@multiplane-rotation: - shard-kbl: PASS -> INCOMPLETE [fdo#103665] * igt@perf_pmu@rc6: - shard-kbl: PASS -> SKIP [fdo#109271] Possible fixes * igt@gem_workarounds@suspend-resume: - shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS * igt@kms_ccs@pipe-b-crc-primary-rotation-180: - shard-skl: FAIL [fdo#107725] -> PASS * igt@kms_chv_cursor_fail@pipe-a-64x64-top-edge: - shard-skl: FAIL [fdo#104671] -> PASS * igt@kms_color@pipe-c-legacy-gamma: - shard-skl: FAIL [fdo#104782] -> PASS * igt@kms_cursor_crc@cursor-128x128-dpms: - shard-apl: FAIL [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-128x128-offscreen: - shard-skl: FAIL [fdo#103232] -> PASS * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: FAIL [fdo#105363] -> PASS * igt@kms_flip_tiling@flip-to-yf-tiled: - shard-skl: FAIL [fdo#107931] -> PASS * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: FAIL [fdo#105682] -> PASS * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite: - shard-skl: FAIL [fdo#103167] -> PASS +1 * igt@kms_plane@plane-position-covered-pipe-b-planes: - shard-glk: FAIL [fdo#103166] -> PASS * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-apl: FAIL [fdo#108145] -> PASS * igt@kms_plane_multiple@atomic-pipe-b-tiling-none: - shard-apl: FAIL [fdo#103166] -> PASS +4 * igt@kms_setmode@basic: - shard-kbl: FAIL [fdo#99912] -> PASS * igt@kms_vblank@pipe-a-ts-continuation-modeset-rpm: - shard-apl: FAIL [fdo#104894] -> PASS [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894 [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363 [fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682 [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725 [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773 [fdo#107791]: https://bugs.freedesktop.org/show_bug.cgi?id=107791 [fdo#107803]:
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/cml: Add CML PCI IDS
== Series Details == Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS URL : https://patchwork.freedesktop.org/series/57607/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/cml: Add CML PCI IDS Okay! Commit: drm/i915/cml: Introduce Comet Lake PCH -drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/cml: Add CML PCI IDS
== Series Details == Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS URL : https://patchwork.freedesktop.org/series/57607/ State : warning == Summary == $ dim checkpatch origin/drm-tip b6b26a8b48bc drm/i915/cml: Add CML PCI IDS -:41: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #41: FILE: include/drm/i915_pciids.h:377: +#define INTEL_CML_GT1_IDS(info)\ + INTEL_VGA_DEVICE(0x9BA1, info), \ + INTEL_VGA_DEVICE(0x9BAA, info), \ + INTEL_VGA_DEVICE(0x9BAB, info), \ + INTEL_VGA_DEVICE(0x9BAC, info), \ + INTEL_VGA_DEVICE(0x9BA0, info), \ + INTEL_VGA_DEVICE(0x9BA5, info), \ + INTEL_VGA_DEVICE(0x9BA8, info), \ + INTEL_VGA_DEVICE(0x9BA4, info), \ + INTEL_VGA_DEVICE(0x9BA2, info) -:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #41: FILE: include/drm/i915_pciids.h:377: +#define INTEL_CML_GT1_IDS(info)\ + INTEL_VGA_DEVICE(0x9BA1, info), \ + INTEL_VGA_DEVICE(0x9BAA, info), \ + INTEL_VGA_DEVICE(0x9BAB, info), \ + INTEL_VGA_DEVICE(0x9BAC, info), \ + INTEL_VGA_DEVICE(0x9BA0, info), \ + INTEL_VGA_DEVICE(0x9BA5, info), \ + INTEL_VGA_DEVICE(0x9BA8, info), \ + INTEL_VGA_DEVICE(0x9BA4, info), \ + INTEL_VGA_DEVICE(0x9BA2, info) -:53: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #53: FILE: include/drm/i915_pciids.h:389: +#define INTEL_CML_GT2_IDS(info)\ + INTEL_VGA_DEVICE(0x9BC1, info), \ + INTEL_VGA_DEVICE(0x9BCA, info), \ + INTEL_VGA_DEVICE(0x9BCB, info), \ + INTEL_VGA_DEVICE(0x9BCC, info), \ + INTEL_VGA_DEVICE(0x9BC0, info), \ + INTEL_VGA_DEVICE(0x9BC5, info), \ + INTEL_VGA_DEVICE(0x9BC8, info), \ + INTEL_VGA_DEVICE(0x9BC4, info), \ + INTEL_VGA_DEVICE(0x9BC2, info) -:53: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #53: FILE: include/drm/i915_pciids.h:389: +#define INTEL_CML_GT2_IDS(info)\ + INTEL_VGA_DEVICE(0x9BC1, info), \ + INTEL_VGA_DEVICE(0x9BCA, info), \ + INTEL_VGA_DEVICE(0x9BCB, info), \ + INTEL_VGA_DEVICE(0x9BCC, info), \ + INTEL_VGA_DEVICE(0x9BC0, info), \ + INTEL_VGA_DEVICE(0x9BC5, info), \ + INTEL_VGA_DEVICE(0x9BC8, info), \ + INTEL_VGA_DEVICE(0x9BC4, info), \ + INTEL_VGA_DEVICE(0x9BC2, info) -:64: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #64: FILE: include/drm/i915_pciids.h:400: +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info) -:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #64: FILE: include/drm/i915_pciids.h:400: +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info) total: 3 errors, 0 warnings, 3 checks, 51 lines checked bb45861c21cf drm/i915/cml: Introduce Comet Lake PCH ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use i915_global_register() (rev2)
== Series Details ==
Series: drm/i915: Use i915_global_register() (rev2)
URL : https://patchwork.freedesktop.org/series/57605/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12380
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57605/revisions/2/mbox/
Known issues
Here are the changes found in Patchwork_12380 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529]
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33
* igt@prime_vgem@basic-fence-flip:
- fi-ilk-650: PASS -> FAIL [fdo#104008]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#104008]: https://bugs.freedesktop.org/show_bug.cgi?id=104008
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108654]: https://bugs.freedesktop.org/show_bug.cgi?id=108654
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
Participating hosts (47 -> 41)
--
Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus fi-snb-2600
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12380
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12380: 660fc43c5f670066093edad2df5d1266c6a804e5 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
660fc43c5f67 drm/i915: Use i915_global_register()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12380/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915/icl: Remove alpha support protection
Now with the watermarks fixes merged, Icelake is stable enough to
have the alpha support protection flag removed.
We have a few ICL machines in our CI and it is mostly green with
failures in tests that will not impact future linux installations.
Also there is no warnings, errors, flickering or any visual defects
while doing ordinary tasks like browsing and editing documents in a
dual monitor setup.
As a reminder i915.alpha_support was created to protect
future linux installation's iso images that might contain a
kernel from the enabling time of the new platform. Without this
protection most of linux installation was recommending
nomodeset option during installation that was getting stick
there after installation.
Specifically, alpha support says nothing about the development
state of the hardware, and everything about the state of the
driver in a kernel release.
This is semantically no different from the old
preliminary_hw_support flag, but the old one was all too often
interpreted as (preliminary hw) support instead of the intended
(preliminary) hw support, and it was misleading for everyone.
Hence the rename.
Reference: https://intel-gfx-ci.01.org/tree/drm-tip/fi-icl-y.html
Reference: https://intel-gfx-ci.01.org/tree/drm-tip/shard-iclb.html
Cc: James Ausmus
Cc: Jani Saarinen
Cc: Paulo Zanoni
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_pci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c42c5ccf38fe..527bd1ceb9ac 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -658,7 +658,6 @@ static const struct intel_device_info intel_cannonlake_info
= {
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
PLATFORM(INTEL_ICELAKE),
- .is_alpha_support = 1,
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
};
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Fixing error code for WOPCM initialization
On 3/5/19 2:05 PM, Daniele Ceraolo Spurio wrote:
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
To clarify, we want to silence this:
forgot to paste the log...
<4> [381.569479] i915: probe of :00:02.0 failed with error -7
Daniele
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..a651557e6e4e 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -169,7 +169,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(!wopcm->size);
if (i915_inject_load_failure())
- return -E2BIG;
+ return -ENODEV;
Would it be better to just change the final return code in
i915_pci_probe() to ENODEV?
i.e.
err = i915_driver_load(pdev, ent);
if (err)
return i915_error_injected() ? -ENODEV : err;
This way we can test that the possible error codes (E2BIG in this case)
don't hit issues in dedicated cases during onion unwinding.
Daniele
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Fixing error code for WOPCM initialization
On 3/4/19 4:55 PM, Sujaritha Sundaresan wrote:
Replacing the -E2BIG error code return for WOPCM
initialization with -ENODEV. This will prevent the pci from
picking this up as a warning during fault injection testing.
To clarify, we want to silence this:
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Sujaritha Sundaresan
---
drivers/gpu/drm/i915/intel_wopcm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index f82a415ea2ba..a651557e6e4e 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -169,7 +169,7 @@ int intel_wopcm_init(struct intel_wopcm *wopcm)
GEM_BUG_ON(!wopcm->size);
if (i915_inject_load_failure())
- return -E2BIG;
+ return -ENODEV;
Would it be better to just change the final return code in
i915_pci_probe() to ENODEV?
i.e.
err = i915_driver_load(pdev, ent);
if (err)
return i915_error_injected() ? -ENODEV : err;
This way we can test that the possible error codes (E2BIG in this case)
don't hit issues in dedicated cases during onion unwinding.
Daniele
if (guc_fw_size >= wopcm->size) {
DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use i915_global_register()
== Series Details == Series: drm/i915: Use i915_global_register() URL : https://patchwork.freedesktop.org/series/57605/ State : success == Summary == CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12379 Summary --- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/57605/revisions/1/mbox/ Known issues Here are the changes found in Patchwork_12379 that come from known issues: ### IGT changes ### Issues hit * igt@i915_module_load@reload-with-fault-injection: - fi-kbl-7567u: PASS -> DMESG-WARN [fdo#105602] / [fdo#108529] +1 * igt@i915_pm_rpm@module-reload: - fi-kbl-7567u: PASS -> DMESG-WARN [fdo#108529] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-7567u: PASS -> DMESG-FAIL [fdo#105079] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c: - fi-kbl-7567u: PASS -> SKIP [fdo#109271] +33 * igt@kms_pipe_crc_basic@read-crc-pipe-b: - fi-byt-clapper: PASS -> FAIL [fdo#107362] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - fi-blb-e6850: NOTRUN -> INCOMPLETE [fdo#107718] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@i915_pm_rpm@module-reload: - fi-kbl-7560u: CRASH -> PASS * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_frontbuffer_tracking@basic: - fi-icl-u3: FAIL [fdo#103167] -> PASS * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079 [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (47 -> 41) -- Missing(6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus Build changes - * Linux: CI_DRM_5708 -> Patchwork_12379 CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12379: 9f0d6f6166e052777db105d5958df10b243f2764 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 9f0d6f6166e0 drm/i915: Use i915_global_register() == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12379/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915/cml: Add CML PCI IDS
From: Anusha Srivatsa
Comet Lake is a Intel Processor containing Gen9
Intel HD Graphics. This patch adds the initial set of
PCI IDs. Comet Lake comes off of Coffee Lake - adding
the IDs to Coffee Lake ID list.
More support and features will be in the patches that follow.
v2: Split IDs according to GT. (Rodrigo)
Cc: Rodrigo Vivi
Cc: Lucas De Marchi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
include/drm/i915_pciids.h | 31 ++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index a9211c370cd1..63ca4ffcad8a 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -723,6 +723,8 @@ static const struct pci_device_id pciidlist[] = {
INTEL_WHL_U_GT2_IDS(_coffeelake_gt2_info),
INTEL_AML_CFL_GT2_IDS(_coffeelake_gt2_info),
INTEL_WHL_U_GT3_IDS(_coffeelake_gt3_info),
+ INTEL_CML_GT1_IDS(_coffeelake_gt1_info),
+ INTEL_CML_GT2_IDS(_coffeelake_gt2_info),
INTEL_CNL_IDS(_cannonlake_info),
INTEL_ICL_11_IDS(_icelake_11_info),
{0, 0, 0}
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index d2fad7b0fcf6..e9ed75ac8252 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -373,6 +373,34 @@
#define INTEL_AML_CFL_GT2_IDS(info) \
INTEL_VGA_DEVICE(0x87CA, info)
+/* CML GT1 */
+#define INTEL_CML_GT1_IDS(info)\
+ INTEL_VGA_DEVICE(0x9BA1, info), \
+ INTEL_VGA_DEVICE(0x9BAA, info), \
+ INTEL_VGA_DEVICE(0x9BAB, info), \
+ INTEL_VGA_DEVICE(0x9BAC, info), \
+ INTEL_VGA_DEVICE(0x9BA0, info), \
+ INTEL_VGA_DEVICE(0x9BA5, info), \
+ INTEL_VGA_DEVICE(0x9BA8, info), \
+ INTEL_VGA_DEVICE(0x9BA4, info), \
+ INTEL_VGA_DEVICE(0x9BA2, info)
+
+/* CML GT2 */
+#define INTEL_CML_GT2_IDS(info)\
+ INTEL_VGA_DEVICE(0x9BC1, info), \
+ INTEL_VGA_DEVICE(0x9BCA, info), \
+ INTEL_VGA_DEVICE(0x9BCB, info), \
+ INTEL_VGA_DEVICE(0x9BCC, info), \
+ INTEL_VGA_DEVICE(0x9BC0, info), \
+ INTEL_VGA_DEVICE(0x9BC5, info), \
+ INTEL_VGA_DEVICE(0x9BC8, info), \
+ INTEL_VGA_DEVICE(0x9BC4, info), \
+ INTEL_VGA_DEVICE(0x9BC2, info)
+
+#define INTEL_CML_IDS(info) \
+ INTEL_CML_GT1_IDS(info), \
+ INTEL_CML_GT2_IDS(info)
+
#define INTEL_KBL_IDS(info) \
INTEL_KBL_GT1_IDS(info), \
INTEL_KBL_GT2_IDS(info), \
@@ -436,7 +464,8 @@
INTEL_WHL_U_GT1_IDS(info), \
INTEL_WHL_U_GT2_IDS(info), \
INTEL_WHL_U_GT3_IDS(info), \
- INTEL_AML_CFL_GT2_IDS(info)
+ INTEL_AML_CFL_GT2_IDS(info), \
+ INTEL_CML_IDS(info)
/* CNL */
#define INTEL_CNL_IDS(info) \
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] drm/i915/cml: Introduce Comet Lake PCH
From: Anusha Srivatsa
Comet Lake PCH is based off of Cannon Point(CNP).
Add PCI ID for Comet Lake PCH.
v2: Code cleanup (DK)
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1b2f5a6f8c25..e787c999b2c6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -188,6 +188,10 @@ intel_pch_type(const struct drm_i915_private *dev_priv,
unsigned short id)
DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
return PCH_CNP;
+ case INTEL_PCH_CMP_DEVICE_ID_TYPE:
+ DRM_DEBUG_KMS("Found Comet Lake LP PCH (CMP)\n");
+ WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
+ return PCH_CNP;
case INTEL_PCH_ICP_DEVICE_ID_TYPE:
DRM_DEBUG_KMS("Found Ice Lake PCH\n");
WARN_ON(!IS_ICELAKE(dev_priv));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 453af7438e67..55298e19e740 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -530,7 +530,7 @@ enum intel_pch {
PCH_LPT,/* Lynxpoint/Wildcatpoint PCH */
PCH_SPT,/* Sunrisepoint PCH */
PCH_KBP,/* Kaby Lake PCH */
- PCH_CNP,/* Cannon Lake PCH */
+ PCH_CNP,/* Cannon/Comet Lake PCH */
PCH_ICP,/* Ice Lake PCH */
PCH_NOP,/* PCH without south display */
};
@@ -2552,6 +2552,7 @@ static inline unsigned int i915_sg_segment_size(void)
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE0x9D80
+#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
--
2.21.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use i915_global_register()
Rather than manually add every new global into each hook, use
i915_global_register() function and keep a list of registered globals to
invoke instead.
However, I haven't found a way for random drivers to add an .init table
to avoid having to manually add ourselves to i915_globals_init() each
time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 28 ++---
drivers/gpu/drm/i915/i915_active.h | 4 --
drivers/gpu/drm/i915/i915_gem_context.c | 28 ++---
drivers/gpu/drm/i915/i915_gem_context.h | 4 --
drivers/gpu/drm/i915/i915_gem_object.c | 28 ++---
drivers/gpu/drm/i915/i915_gem_object.h | 4 --
drivers/gpu/drm/i915/i915_globals.c | 82 -
drivers/gpu/drm/i915/i915_globals.h | 19 ++
drivers/gpu/drm/i915/i915_request.c | 36 ++-
drivers/gpu/drm/i915/i915_request.h | 4 --
drivers/gpu/drm/i915/i915_scheduler.c | 32 ++
drivers/gpu/drm/i915/i915_scheduler.h | 4 --
drivers/gpu/drm/i915/i915_vma.c | 28 ++---
drivers/gpu/drm/i915/i915_vma.h | 4 --
14 files changed, 171 insertions(+), 134 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index d9f6471ac16c..863ae12707ba 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_active.h"
+#include "i915_globals.h"
#define BKL(ref) (&(ref)->i915->drm.struct_mutex)
@@ -17,6 +18,7 @@
* nodes from a local slab cache to hopefully reduce the fragmentation.
*/
static struct i915_global_active {
+ struct i915_global base;
struct kmem_cache *slab_cache;
} global;
@@ -285,21 +287,27 @@ void i915_active_retire_noop(struct i915_active_request
*active,
#include "selftests/i915_active.c"
#endif
-int __init i915_global_active_init(void)
+static void i915_global_active_shrink(void)
{
- global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
- if (!global.slab_cache)
- return -ENOMEM;
-
- return 0;
+ kmem_cache_shrink(global.slab_cache);
}
-void i915_global_active_shrink(void)
+static void i915_global_active_exit(void)
{
- kmem_cache_shrink(global.slab_cache);
+ kmem_cache_destroy(global.slab_cache);
}
-void i915_global_active_exit(void)
+static struct i915_global_active global = { {
+ .shrink = i915_global_active_shrink,
+ .exit = i915_global_active_exit,
+} };
+
+int __init i915_global_active_init(void)
{
- kmem_cache_destroy(global.slab_cache);
+ global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_cache)
+ return -ENOMEM;
+
+ i915_global_register();
+ return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 5fbd9102384b..8142a334b37b 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -419,8 +419,4 @@ void i915_active_fini(struct i915_active *ref);
static inline void i915_active_fini(struct i915_active *ref) { }
#endif
-int i915_global_active_init(void);
-void i915_global_active_shrink(void);
-void i915_global_active_exit(void);
-
#endif /* _I915_ACTIVE_H_ */
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1e3211e909f1..b9f321947982 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -88,6 +88,7 @@
#include
#include
#include "i915_drv.h"
+#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
@@ -95,6 +96,7 @@
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_context {
+ struct i915_global base;
struct kmem_cache *slab_luts;
} global;
@@ -1423,21 +1425,27 @@ int __i915_gem_context_pin_hw_id(struct
i915_gem_context *ctx)
#include "selftests/i915_gem_context.c"
#endif
-int __init i915_global_context_init(void)
+static void i915_global_context_shrink(void)
{
- global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
- if (!global.slab_luts)
- return -ENOMEM;
-
- return 0;
+ kmem_cache_shrink(global.slab_luts);
}
-void i915_global_context_shrink(void)
+static void i915_global_context_exit(void)
{
- kmem_cache_shrink(global.slab_luts);
+ kmem_cache_destroy(global.slab_luts);
}
-void i915_global_context_exit(void)
+static struct i915_global_context global = { {
+ .shrink = i915_global_context_shrink,
+ .exit = i915_global_context_exit,
+} };
+
+int __init i915_global_context_init(void)
{
- kmem_cache_destroy(global.slab_luts);
+ global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
+ if (!global.slab_luts)
+ return -ENOMEM;
+
+ i915_global_register();
+ return 0;
}
diff --git
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Populate pipe_offsets[] & co. accurately
== Series Details ==
Series: drm/i915: Populate pipe_offsets[] & co. accurately
URL : https://patchwork.freedesktop.org/series/57600/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12378
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57600/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12378 that come from known issues:
### IGT changes ###
Issues hit
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7567u: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] /
[fdo#108529] +1
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: PASS -> SKIP [fdo#109271]
* igt@i915_pm_rpm@basic-rte:
- fi-bsw-kefka: PASS -> FAIL [fdo#108800]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +2
* igt@runner@aborted:
- fi-kbl-7567u: NOTRUN -> FAIL [fdo#105602]
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7560u: CRASH -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12378
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12378: b9022656feb690e6c4765c4904ac7a1a73a95b20 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b9022656feb6 drm/i915: Populate pipe_offsets[] & co. accurately
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12378/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915: Do not temporarily disable the DPLL on i830
== Series Details == Series: series starting with [v2,1/2] drm/i915: Do not temporarily disable the DPLL on i830 URL : https://patchwork.freedesktop.org/series/57598/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12377 Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12377 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12377, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/57598/revisions/1/mbox/ Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12377: ### IGT changes ### Possible regressions * igt@i915_module_load@reload-with-fault-injection: - fi-kbl-7560u: PASS -> INCOMPLETE Known issues Here are the changes found in Patchwork_12377 that come from known issues: ### IGT changes ### Issues hit * igt@gem_exec_suspend@basic-s3: - fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718] * igt@i915_selftest@live_execlists: - fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] * igt@runner@aborted: - fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720] Possible fixes * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +1 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622 [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720 Participating hosts (47 -> 40) -- Missing(7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-ivb-3520m fi-bdw-samus Build changes - * Linux: CI_DRM_5708 -> Patchwork_12377 CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12377: 048987dd7fdb1f37537299e3d587a81bdd432279 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 048987dd7fdb drm/i915: Simplify i830 DVO 2x clock handling 9c6f3a854085 drm/i915: Do not temporarily disable the DPLL on i830 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12377/ ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove last traces of exec-id (GEM_BUSY)
== Series Details == Series: drm/i915: Remove last traces of exec-id (GEM_BUSY) URL : https://patchwork.freedesktop.org/series/57588/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5705_full -> Patchwork_12374_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12374_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12374_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12374_full: ### IGT changes ### Possible regressions * igt@gem_busy@extended-blt: - shard-glk: PASS -> FAIL +10 - shard-snb: PASS -> FAIL +3 * igt@gem_busy@extended-bsd: - shard-skl: PASS -> FAIL +10 * igt@gem_busy@extended-parallel-bsd2: - shard-kbl: PASS -> FAIL +15 * igt@gem_busy@extended-parallel-vebox: - shard-apl: PASS -> FAIL +11 * igt@gem_busy@extended-render: - shard-hsw: PASS -> FAIL +7 * igt@gem_busy@extended-semaphore-render: - shard-skl: NOTRUN -> FAIL * igt@gem_busy@extended-semaphore-vebox: - shard-iclb: PASS -> FAIL +3 Warnings * igt@runner@aborted: - shard-iclb: ( 7 FAIL ) [fdo#109467] -> FAIL Known issues Here are the changes found in Patchwork_12374_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@stolen-invalid-flag: - shard-iclb: NOTRUN -> SKIP [fdo#109277] * igt@gem_ctx_isolation@vecs0-none: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +1 * igt@gem_exec_parallel@bsd1: - shard-skl: NOTRUN -> SKIP [fdo#109271] +47 * igt@gem_mocs_settings@mocs-reset-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] * igt@gem_wait@write-busy-bsd2: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +5 * igt@kms_busy@basic-modeset-e: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1 * igt@kms_busy@extended-modeset-hang-newfb-render-c: - shard-skl: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-render-f: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-e: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3 * igt@kms_busy@extended-modeset-hang-oldfb-with-reset-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +1 * igt@kms_busy@extended-pageflip-hang-newfb-render-a: - shard-apl: PASS -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-pageflip-hang-newfb-render-b: - shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] +1 * igt@kms_ccs@pipe-b-crc-primary-rotation-180: - shard-iclb: NOTRUN -> FAIL [fdo#107725] * igt@kms_chamelium@dp-hpd-after-suspend: - shard-iclb: NOTRUN -> SKIP [fdo#109284] +1 * igt@kms_chv_cursor_fail@pipe-a-64x64-top-edge: - shard-skl: PASS -> FAIL [fdo#104671] * igt@kms_color@pipe-c-legacy-gamma: - shard-skl: PASS -> FAIL [fdo#104782] * igt@kms_content_protection@legacy: - shard-kbl: NOTRUN -> FAIL [fdo#108597] / [fdo#108739] * igt@kms_cursor_crc@cursor-128x128-offscreen: - shard-skl: PASS -> FAIL [fdo#103232] * igt@kms_cursor_crc@cursor-256x85-sliding: - shard-iclb: NOTRUN -> FAIL [fdo#103232] +1 * igt@kms_cursor_crc@cursor-64x21-sliding: - shard-apl: PASS -> FAIL [fdo#103232] +3 * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy: - shard-iclb: NOTRUN -> SKIP [fdo#109274] +3 * igt@kms_dp_dsc@basic-dsc-enable-edp: - shard-iclb: NOTRUN -> SKIP [fdo#109349] * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled: - shard-skl: PASS -> FAIL [fdo#103184] * igt@kms_fbcon_fbt@psr-suspend: - shard-iclb: NOTRUN -> FAIL [fdo#103833] * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible: - shard-kbl: NOTRUN -> SKIP [fdo#109271] +39 * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: PASS -> FAIL [fdo#105363] * igt@kms_flip@wf_vblank-ts-check-interruptible: - shard-kbl: PASS -> DMESG-WARN [fdo#103558] / [fdo#105602] +23 * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render: - shard-skl: PASS -> FAIL [fdo#105682] * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: - shard-apl: PASS -> FAIL [fdo#103167] +5 *
Re: [Intel-gfx] [PATCH 2/2] drm/i915: fix placement of ICP_PP_CONTROL
On Tue, Mar 05, 2019 at 03:23:48PM +0200, Jani Nikula wrote:
On Mon, 04 Mar 2019, Jani Nikula wrote:
On Mon, 04 Mar 2019, Ville Syrjälä wrote:
On Fri, Mar 01, 2019 at 05:14:05PM -0800, Lucas De Marchi wrote:
This register was placed in the middle of the PP_STATUS definition. Move
it down together with PP_CONTROL and fix the aligment of the bit
definition (as per documentation it should be 2 spaces instead of 1).
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b868347481..bbbc0649a180 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4692,17 +4692,6 @@ enum {
#define _PP_STATUS 0x61200
#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
#define PP_ON(1 << 31)
-
-#define _PP_CONTROL_1 0xc7204
-#define _PP_CONTROL_2 0xc7304
-#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
- _PP_CONTROL_2)
-#define POWER_CYCLE_DELAY_MASK(0x1f << 4)
-#define POWER_CYCLE_DELAY_SHIFT 4
-#define VDD_OVERRIDE_FORCE(1 << 3)
-#define BACKLIGHT_ENABLE (1 << 2)
-#define PWR_DOWN_ON_RESET (1 << 1)
-#define PWR_STATE_TARGET (1 << 0)
/*
* Indicates that all dependencies of the panel are on:
*
@@ -4728,6 +4717,17 @@ enum {
#define PP_SEQUENCE_STATE_ON_S1_3(0xb << 0)
#define PP_SEQUENCE_STATE_RESET (0xf << 0)
+#define _PP_CONTROL_1 0xc7204
+#define _PP_CONTROL_2 0xc7304
+#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
+ _PP_CONTROL_2)
+#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
+#define POWER_CYCLE_DELAY_SHIFT 4
+#define VDD_OVERRIDE_FORCE (1 << 3)
+#define BACKLIGHT_ENABLE (1 << 2)
+#define PWR_DOWN_ON_RESET(1 << 1)
+#define PWR_STATE_TARGET (1 << 0)
This entire register looks 100% redundant. Just nuke the whole thing?
Needed in the future?
D'oh, missed the PPS base thing. Nuke it.
But ICP_PP_CONTROL() is also unused. Should I nuke it as well?
Lucas De Marchi
BR,
Jani.
BR,
Jani.
+
#define _PP_CONTROL0x61204
#define PP_CONTROL(pps_idx)_MMIO_PPS(pps_idx, _PP_CONTROL)
#define PANEL_UNLOCK_REGS (0xabcd << 16)
--
2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Use i915_global_register()
Rather than manually add every new global into each hook, use
i915_global_register() function and keep a list of registered globals to
invoke instead.
However, I haven't found a way for random drivers to add an .init table
to avoid having to manually add ourselves to i915_globals_init() each
time.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 28 +++-
drivers/gpu/drm/i915/i915_active.h | 2 -
drivers/gpu/drm/i915/i915_gem_context.c | 28 +++-
drivers/gpu/drm/i915/i915_gem_context.h | 2 -
drivers/gpu/drm/i915/i915_gem_object.c | 28 +++-
drivers/gpu/drm/i915/i915_gem_object.h | 2 -
drivers/gpu/drm/i915/i915_globals.c | 59 +
drivers/gpu/drm/i915/i915_globals.h | 11 +
drivers/gpu/drm/i915/i915_request.c | 36 +--
drivers/gpu/drm/i915/i915_request.h | 2 -
drivers/gpu/drm/i915/i915_scheduler.c | 32 +-
drivers/gpu/drm/i915/i915_scheduler.h | 2 -
drivers/gpu/drm/i915/i915_vma.c | 28 +++-
drivers/gpu/drm/i915/i915_vma.h | 2 -
14 files changed, 156 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i915/i915_active.c
index d9f6471ac16c..863ae12707ba 100644
--- a/drivers/gpu/drm/i915/i915_active.c
+++ b/drivers/gpu/drm/i915/i915_active.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_active.h"
+#include "i915_globals.h"
#define BKL(ref) (&(ref)->i915->drm.struct_mutex)
@@ -17,6 +18,7 @@
* nodes from a local slab cache to hopefully reduce the fragmentation.
*/
static struct i915_global_active {
+ struct i915_global base;
struct kmem_cache *slab_cache;
} global;
@@ -285,21 +287,27 @@ void i915_active_retire_noop(struct i915_active_request
*active,
#include "selftests/i915_active.c"
#endif
-int __init i915_global_active_init(void)
+static void i915_global_active_shrink(void)
{
- global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
- if (!global.slab_cache)
- return -ENOMEM;
-
- return 0;
+ kmem_cache_shrink(global.slab_cache);
}
-void i915_global_active_shrink(void)
+static void i915_global_active_exit(void)
{
- kmem_cache_shrink(global.slab_cache);
+ kmem_cache_destroy(global.slab_cache);
}
-void i915_global_active_exit(void)
+static struct i915_global_active global = { {
+ .shrink = i915_global_active_shrink,
+ .exit = i915_global_active_exit,
+} };
+
+int __init i915_global_active_init(void)
{
- kmem_cache_destroy(global.slab_cache);
+ global.slab_cache = KMEM_CACHE(active_node, SLAB_HWCACHE_ALIGN);
+ if (!global.slab_cache)
+ return -ENOMEM;
+
+ i915_global_register();
+ return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 5fbd9102384b..575c01846875 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -420,7 +420,5 @@ static inline void i915_active_fini(struct i915_active
*ref) { }
#endif
int i915_global_active_init(void);
-void i915_global_active_shrink(void);
-void i915_global_active_exit(void);
#endif /* _I915_ACTIVE_H_ */
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 1e3211e909f1..b9f321947982 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -88,6 +88,7 @@
#include
#include
#include "i915_drv.h"
+#include "i915_globals.h"
#include "i915_trace.h"
#include "intel_lrc_reg.h"
#include "intel_workarounds.h"
@@ -95,6 +96,7 @@
#define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
static struct i915_global_context {
+ struct i915_global base;
struct kmem_cache *slab_luts;
} global;
@@ -1423,21 +1425,27 @@ int __i915_gem_context_pin_hw_id(struct
i915_gem_context *ctx)
#include "selftests/i915_gem_context.c"
#endif
-int __init i915_global_context_init(void)
+static void i915_global_context_shrink(void)
{
- global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
- if (!global.slab_luts)
- return -ENOMEM;
-
- return 0;
+ kmem_cache_shrink(global.slab_luts);
}
-void i915_global_context_shrink(void)
+static void i915_global_context_exit(void)
{
- kmem_cache_shrink(global.slab_luts);
+ kmem_cache_destroy(global.slab_luts);
}
-void i915_global_context_exit(void)
+static struct i915_global_context global = { {
+ .shrink = i915_global_context_shrink,
+ .exit = i915_global_context_exit,
+} };
+
+int __init i915_global_context_init(void)
{
- kmem_cache_destroy(global.slab_luts);
+ global.slab_luts = KMEM_CACHE(i915_lut_handle, 0);
+ if (!global.slab_luts)
+ return -ENOMEM;
+
+ i915_global_register();
+ return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.h
Re: [Intel-gfx] [PATCH i-g-t v4 1/1] gem_ctx_isolation.c - Gen11 enabling for context isolation test
Quoting Dale B Stimson (2019-03-05 20:46:51) > CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced > by its absence from the kernel whitelist for Gen11 combined with the > successful execution on ICL of the tests added by your recent patch > "i915/gem_ctx_isolation: Sanitycheck nonpriv access". Everything seems in order :) Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4 1/1] gem_ctx_isolation.c - Gen11 enabling for context isolation test
CS_CHICKEN1 is not privileged anymore (as of Gen11), as evidenced
by its absence from the kernel whitelist for Gen11 combined with the
successful execution on ICL of the tests added by your recent patch
"i915/gem_ctx_isolation: Sanitycheck nonpriv access".
-Dale
On 2019-03-05 19:00:49, Chris Wilson wrote:
> Quoting Dale B Stimson (2019-03-05 01:03:08)
> > @@ -132,30 +136,49 @@ static const struct named_register {
> > { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> > { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
> >
> > + { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
> > + { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
>
> CS_CHICKEN1 is still privileged? At least I'm push a patch to add it to
> the whitelist for gen11.
> -Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/6] drm/i915: Force GPU idle on suspend
== Series Details ==
Series: series starting with [1/6] drm/i915: Force GPU idle on suspend
URL : https://patchwork.freedesktop.org/series/57597/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5708 -> Patchwork_12376
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_12376 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_12376, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57597/revisions/1/mbox/
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_12376:
### IGT changes ###
Possible regressions
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: PASS -> INCOMPLETE
Known issues
Here are the changes found in Patchwork_12376 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_psr@primary_mmap_gtt:
- fi-blb-e6850: NOTRUN -> SKIP [fdo#109271] +27
Possible fixes
* igt@gem_mmap@basic-small-bo:
- {fi-icl-y}: DMESG-WARN -> PASS
* igt@kms_busy@basic-flip-a:
- fi-gdg-551: FAIL [fdo#103182] -> PASS
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: INCOMPLETE [fdo#107718] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (47 -> 42)
--
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5708 -> Patchwork_12376
CI_DRM_5708: afd34c5dec857362de91fb3044f09d90e83ad6a5 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4871: 8feb147562ba1b364615ddacd44c3846f0250d37 @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12376: 42fdf4a267c58c93b6807fb30b36b18a1ff8c4e1 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
42fdf4a267c5 drm/i915: Remove has-kernel-context
823e94d07bb4 drm/i915: Reduce presumption of request ordering for barriers
7964a35ec0a2 drm/i915: Refactor common code to load initial power context
c14f7b604b57 drm/i915: Do a synchronous switch-to-kernel-context on idling
fdad81655cfc drm/i915/selftests: Improve switch-to-kernel-context checking
26b215786f6a drm/i915: Force GPU idle on suspend
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12376/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE
On Tue, Mar 05, 2019 at 09:46:29PM +0200, Jani Nikula wrote: > On Tue, 05 Mar 2019, Lucas De Marchi wrote: > > On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote: > >>On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote: > >>> On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote: > >>> > On Tue, 05 Mar 2019, Lucas De Marchi wrote: > >>> > > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula wrote: > >>> > > > On Mon, 04 Mar 2019, Rodrigo Vivi wrote: > >>> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > >>> > > > > b/drivers/gpu/drm/i915/intel_dp.c > >>> > > > > index e1a051c0fbfe..acd2336bb214 100644 > >>> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > >>> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > >>> > > > > @@ -949,8 +949,8 @@ static void intel_pps_get_registers(struct > >>> > > > > intel_dp *intel_dp, > >>> > > > > regs->pp_stat = PP_STATUS(pps_idx); > >>> > > > > regs->pp_on = PP_ON_DELAYS(pps_idx); > >>> > > > > regs->pp_off = PP_OFF_DELAYS(pps_idx); > >>> > > > > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > >>> > > > > - !HAS_PCH_ICP(dev_priv)) > >>> > > > > + if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE && > >>> > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_CNP) > >>> > > > > >>> > > > This is not right, starts to require PCH. > >>> > > > >>> > > But in those cases INTEL_PCH_TYPE() will return either NONE or NOP. > >>> > > >>> > Exactly. Non-PCH platforms before CNP should match, but won't. > >>> > >>> yeah, right. I misread the !IS_GEN9_LP(). > >> > >>ouch... indeed. > >>probably this explains failure on ci for bsw and byt > >> > >>options: > >> > >>1. if (!IS_GEN9_LP(dev_priv) && !(INTEL_PCH_TYPE(dev_priv) >= 10)) > > > > 10? I think you meant PCH_CNP > > > >> > >>2. if (INTEL_GEN(dev_priv) <= 8 || IS_GEN9_BC(dev_priv)) > >> > >>3. other ideas? > > > > "all PCHs before CNP, excluding GEN9_LP": > > > > if (INTEL_PCH_TYPE(dev_priv) < PCH_CNP && !IS_GEN9_LP(dev_priv)) > > See the series I mentioned upthread [1], it reverses the condition > making this easier to write anyway. Thanks a lot! I will make a v2 on top of yours and resend after it gets pushed. > > BR, > Jani. > > > [1] https://patchwork.freedesktop.org/series/57579/ > > > > > > > > Lucas De Marchi > > > >> > >>> > >>> Lucas De Marchi > >>> > >>> > > >>> > BR, > >>> > Jani. > >>> > > >>> > > >>> > -- > >>> > Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
> Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
> register isn't there, and use i915_mmio_reg_valid() instead of repeating
> the condition all over the place.
>
> Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
> value is unchanged from 0.
great clean up. Thanks for that.
Reviewed-by: Rodrigo Vivi
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_dp.c | 73 ++---
> 1 file changed, 39 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e0f421e76305..f40b3342d82a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp
> *intel_dp,
> regs->pp_stat = PP_STATUS(pps_idx);
> regs->pp_on = PP_ON_DELAYS(pps_idx);
> regs->pp_off = PP_OFF_DELAYS(pps_idx);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> - !HAS_PCH_ICP(dev_priv))
> +
> + /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> + HAS_PCH_ICP(dev_priv))
> + regs->pp_div = INVALID_MMIO_REG;
> + else
> regs->pp_div = PP_DIVISOR(pps_idx);
> }
>
> @@ -6420,7 +6424,7 @@ static void
> intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq
> *seq)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> + u32 pp_on, pp_off, pp_ctl;
> struct pps_registers regs;
>
> intel_pps_get_registers(intel_dp, );
> @@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
> struct edp_power_seq *seq)
>
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> - !HAS_PCH_ICP(dev_priv)) {
> - pp_div = I915_READ(regs.pp_div);
> - }
>
> /* Pull timing values out of registers */
> seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
> @@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
> struct edp_power_seq *seq)
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv)) {
> + if (i915_mmio_reg_valid(regs.pp_div)) {
> + u32 pp_div;
> +
> + pp_div = I915_READ(regs.pp_div);
> +
> + seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> + PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> +
> + } else {
> seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
> - } else {
> - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> -PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> }
> }
>
> @@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> intel_dp *intel_dp,
> bool force_disable_vdd)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - u32 pp_on, pp_off, pp_div, port_sel = 0;
> + u32 pp_on, pp_off, port_sel = 0;
> int div = dev_priv->rawclk_freq / 1000;
> struct pps_registers regs;
> enum port port = dp_to_dig_port(intel_dp)->base.port;
> @@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct
> intel_dp *intel_dp,
> (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
>(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> - /* Compute the divisor for the pp clock, simply match the Bspec
> - * formula. */
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> - HAS_PCH_ICP(dev_priv)) {
> - pp_div = I915_READ(regs.pp_ctrl);
> - pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> - << BXT_POWER_CYCLE_DELAY_SHIFT);
> - } else {
> - pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> - << PANEL_POWER_CYCLE_DELAY_SHIFT);
> - }
>
> /* Haswell doesn't have any port selection bits for the panel
>* power sequencer any more. */
> @@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct
> intel_dp *intel_dp,
>
> I915_WRITE(regs.pp_on, pp_on);
> I915_WRITE(regs.pp_off, pp_off);
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
> -
Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: deconflate PPS unlock from divisor register
On Tue, Mar 05, 2019 at 03:52:14PM +0200, Jani Nikula wrote:
> PPS locking is a thing on pre-DDI, up to and including CPT and PPT.
>
> The PPS divisor register exists up to gen 9 BC, replaced by a field in
> the control register starting from gen 9 LP, i.e. BXT, GLK, and CNP on.
>
> Commit b0a08bec9631 ("drm/i915/bxt: eDP Panel Power sequencing") stopped
> using the divisor register, but inadvertently conflated the PPS unlock
> in the change. No longer doing the unlocking was the right thing to do,
> however we should've stopped already at LPT (or DDI platforms).
>
> Deconflate the two.
>
> Arguably this could be moved away from here altogether, but this is the
> minimally intrusive change for now.
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Rodrigo Vivi
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e1a051c0fbfe..e0f421e76305 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6425,15 +6425,16 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
> struct edp_power_seq *seq)
>
> intel_pps_get_registers(intel_dp, );
>
> - /* Workaround: Need to write PP_CONTROL with the unlock key as
> - * the very first thing. */
> pp_ctl = ironlake_get_pp_control(intel_dp);
>
> + /* Ensure PPS is unlocked */
> + if (!HAS_DDI(dev_priv))
> + I915_WRITE(regs.pp_ctrl, pp_ctl);
> +
> pp_on = I915_READ(regs.pp_on);
> pp_off = I915_READ(regs.pp_off);
> if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
> !HAS_PCH_ICP(dev_priv)) {
> - I915_WRITE(regs.pp_ctrl, pp_ctl);
> pp_div = I915_READ(regs.pp_div);
> }
>
> --
> 2.20.1
>
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/dp: use single point of truth for PPS divisor register
On Tue, Mar 05, 2019 at 03:52:15PM +0200, Jani Nikula wrote:
Set pp_div field of struct pps_registers to INVALID_MMIO_REG when the
register isn't there, and use i915_mmio_reg_valid() instead of repeating
the condition all over the place.
Use INVALID_MMIO_REG explicitly for documentation purposes, even if the
value is unchanged from 0.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
Reviewed-by: Lucas De Marchi
Lucas De Marchi
---
drivers/gpu/drm/i915/intel_dp.c | 73 ++---
1 file changed, 39 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e0f421e76305..f40b3342d82a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -949,8 +949,12 @@ static void intel_pps_get_registers(struct intel_dp
*intel_dp,
regs->pp_stat = PP_STATUS(pps_idx);
regs->pp_on = PP_ON_DELAYS(pps_idx);
regs->pp_off = PP_OFF_DELAYS(pps_idx);
- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
- !HAS_PCH_ICP(dev_priv))
+
+ /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
+ HAS_PCH_ICP(dev_priv))
+ regs->pp_div = INVALID_MMIO_REG;
+ else
regs->pp_div = PP_DIVISOR(pps_idx);
}
@@ -6420,7 +6424,7 @@ static void
intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
+ u32 pp_on, pp_off, pp_ctl;
struct pps_registers regs;
intel_pps_get_registers(intel_dp, );
@@ -6433,10 +6437,6 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
struct edp_power_seq *seq)
pp_on = I915_READ(regs.pp_on);
pp_off = I915_READ(regs.pp_off);
- if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
- !HAS_PCH_ICP(dev_priv)) {
- pp_div = I915_READ(regs.pp_div);
- }
/* Pull timing values out of registers */
seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
@@ -6451,13 +6451,17 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp,
struct edp_power_seq *seq)
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv)) {
+ if (i915_mmio_reg_valid(regs.pp_div)) {
+ u32 pp_div;
+
+ pp_div = I915_READ(regs.pp_div);
+
+ seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
+
+ } else {
seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
- } else {
- seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
}
}
@@ -6582,7 +6586,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
bool force_disable_vdd)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- u32 pp_on, pp_off, pp_div, port_sel = 0;
+ u32 pp_on, pp_off, port_sel = 0;
int div = dev_priv->rawclk_freq / 1000;
struct pps_registers regs;
enum port port = dp_to_dig_port(intel_dp)->base.port;
@@ -6621,19 +6625,6 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
- /* Compute the divisor for the pp clock, simply match the Bspec
-* formula. */
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv)) {
- pp_div = I915_READ(regs.pp_ctrl);
- pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
- << BXT_POWER_CYCLE_DELAY_SHIFT);
- } else {
- pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
- << PANEL_POWER_CYCLE_DELAY_SHIFT);
- }
/* Haswell doesn't have any port selection bits for the panel
* power sequencer any more. */
@@ -6660,19 +6651,33 @@ intel_dp_init_panel_power_sequencer_registers(struct
intel_dp *intel_dp,
I915_WRITE(regs.pp_on, pp_on);
I915_WRITE(regs.pp_off, pp_off);
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
- HAS_PCH_ICP(dev_priv))
- I915_WRITE(regs.pp_ctrl, pp_div);
- else
+
+ /*
+* Compute the divisor for the
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Force GPU idle on suspend
== Series Details == Series: series starting with [1/6] drm/i915: Force GPU idle on suspend URL : https://patchwork.freedesktop.org/series/57597/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Force GPU idle on suspend Okay! Commit: drm/i915/selftests: Improve switch-to-kernel-context checking Okay! Commit: drm/i915: Do a synchronous switch-to-kernel-context on idling Okay! Commit: drm/i915: Refactor common code to load initial power context Okay! Commit: drm/i915: Reduce presumption of request ordering for barriers -drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3549:16: warning: expression using sizeof(void) Commit: drm/i915: Remove has-kernel-context Okay! ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE
On Tue, 05 Mar 2019, Lucas De Marchi wrote: > On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote: >>On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote: >>> On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote: >>> > On Tue, 05 Mar 2019, Lucas De Marchi wrote: >>> > > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula wrote: >>> > > > On Mon, 04 Mar 2019, Rodrigo Vivi wrote: >>> > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c >>> > > > > b/drivers/gpu/drm/i915/intel_dp.c >>> > > > > index e1a051c0fbfe..acd2336bb214 100644 >>> > > > > --- a/drivers/gpu/drm/i915/intel_dp.c >>> > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c >>> > > > > @@ -949,8 +949,8 @@ static void intel_pps_get_registers(struct >>> > > > > intel_dp *intel_dp, >>> > > > > regs->pp_stat = PP_STATUS(pps_idx); >>> > > > > regs->pp_on = PP_ON_DELAYS(pps_idx); >>> > > > > regs->pp_off = PP_OFF_DELAYS(pps_idx); >>> > > > > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && >>> > > > > - !HAS_PCH_ICP(dev_priv)) >>> > > > > + if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE && >>> > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_CNP) >>> > > > >>> > > > This is not right, starts to require PCH. >>> > > >>> > > But in those cases INTEL_PCH_TYPE() will return either NONE or NOP. >>> > >>> > Exactly. Non-PCH platforms before CNP should match, but won't. >>> >>> yeah, right. I misread the !IS_GEN9_LP(). >> >>ouch... indeed. >>probably this explains failure on ci for bsw and byt >> >>options: >> >>1. if (!IS_GEN9_LP(dev_priv) && !(INTEL_PCH_TYPE(dev_priv) >= 10)) > > 10? I think you meant PCH_CNP > >> >>2. if (INTEL_GEN(dev_priv) <= 8 || IS_GEN9_BC(dev_priv)) >> >>3. other ideas? > > "all PCHs before CNP, excluding GEN9_LP": > > if (INTEL_PCH_TYPE(dev_priv) < PCH_CNP && !IS_GEN9_LP(dev_priv)) See the series I mentioned upthread [1], it reverses the condition making this easier to write anyway. BR, Jani. [1] https://patchwork.freedesktop.org/series/57579/ > > > Lucas De Marchi > >> >>> >>> Lucas De Marchi >>> >>> > >>> > BR, >>> > Jani. >>> > >>> > >>> > -- >>> > Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Populate pipe_offsets[] & co. accurately
From: Ville Syrjälä
At some point people have started to assume that
pipe_offsets[] & co. are only populated for pipes and whatnot
that actually exist. That is in fact not currently true, but
we can easily make it so.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_pci.c | 146 +++-
1 file changed, 104 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c42c5ccf38fe..9e610e4bdd7d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -35,7 +35,37 @@
#define PLATFORM(x) .platform = (x), .platform_mask = BIT(x)
#define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1)
-#define GEN_DEFAULT_PIPEOFFSETS \
+#define I845_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ }
+
+#define I9XX_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ }
+
+#define IVB_PIPE_OFFSETS \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ }
+
+#define HSW_PIPE_OFFSETS \
.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
@@ -49,7 +79,7 @@
[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
}
-#define GEN_CHV_PIPEOFFSETS \
+#define CHV_PIPE_OFFSETS \
.pipe_offsets = { \
[TRANSCODER_A] = PIPE_A_OFFSET, \
[TRANSCODER_B] = PIPE_B_OFFSET, \
@@ -61,11 +91,30 @@
[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
}
-#define CURSOR_OFFSETS \
- .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET,
CHV_CURSOR_C_OFFSET }
+#define I845_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ }
+
+#define I9XX_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = CURSOR_B_OFFSET, \
+ }
+
+#define CHV_CURSOR_OFFSETS \
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = CURSOR_B_OFFSET, \
+ [PIPE_C] = CHV_CURSOR_C_OFFSET, \
+ }
#define IVB_CURSOR_OFFSETS \
- .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET,
IVB_CURSOR_C_OFFSET }
+ .cursor_offsets = { \
+ [PIPE_A] = CURSOR_A_OFFSET, \
+ [PIPE_B] = IVB_CURSOR_B_OFFSET, \
+ [PIPE_C] = IVB_CURSOR_C_OFFSET, \
+ }
#define BDW_COLORS \
.color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
@@ -85,7 +134,25 @@
#define GEN_DEFAULT_PAGE_SIZES \
.page_sizes = I915_GTT_PAGE_SIZE_4K
-#define GEN2_FEATURES \
+#define I830_FEATURES \
+ GEN(2), \
+ .is_mobile = 1, \
+ .num_pipes = 2, \
+ .display.has_overlay = 1, \
+ .display.cursor_needs_physical = 1, \
+ .display.overlay_needs_physical = 1, \
+ .display.has_gmch = 1, \
+ .gpu_reset_clobbers_display = true, \
+ .hws_needs_physical = 1, \
+ .unfenced_needs_alignment = 1, \
+ .engine_mask = BIT(RCS0), \
+ .has_snoop = true, \
+ .has_coherent_ggtt = false, \
+ I9XX_PIPE_OFFSETS, \
+ I9XX_CURSOR_OFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES
+
+#define I845_FEATURES \
GEN(2), \
.num_pipes = 1, \
.display.has_overlay = 1, \
@@ -97,34 +164,28 @@
.engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
- GEN_DEFAULT_PIPEOFFSETS, \
- GEN_DEFAULT_PAGE_SIZES, \
- CURSOR_OFFSETS
+ I845_PIPE_OFFSETS, \
+ I845_CURSOR_OFFSETS, \
+ GEN_DEFAULT_PAGE_SIZES
static const struct intel_device_info intel_i830_info = {
- GEN2_FEATURES,
+ I830_FEATURES,
PLATFORM(INTEL_I830),
- .is_mobile = 1,
- .display.cursor_needs_physical = 1,
- .num_pipes = 2, /* legal, last one wins */
};
static const struct intel_device_info intel_i845g_info = {
- GEN2_FEATURES,
+ I845_FEATURES,
PLATFORM(INTEL_I845G),
};
static const struct intel_device_info intel_i85x_info = {
- GEN2_FEATURES,
+ I830_FEATURES,
PLATFORM(INTEL_I85X),
- .is_mobile = 1,
- .num_pipes = 2, /* legal, last one wins */
-
Re: [Intel-gfx] [PATCH 31/38] drm/i915: Track the pinned kernel contexts on each engine
Quoting Tvrtko Ursulin (2019-03-05 18:17:35)
>
> On 05/03/2019 18:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
> >>>/*
> >>> * Similarly the preempt context must always be available so that
> >>> - * we can interrupt the engine at any time.
> >>> + * we can interrupt the engine at any time. However, as preemption
> >>> + * is optional, we allow it to fail.
> >>> */
> >>> - if (i915->preempt_context) {
> >>> - ce = intel_context_pin(i915->preempt_context, engine);
> >>> - if (IS_ERR(ce)) {
> >>> - ret = PTR_ERR(ce);
> >>> - goto err_unpin_kernel;
> >>> - }
> >>> - }
> >>> + if (i915->preempt_context)
> >>> + pin_context(i915->preempt_context, engine,
> >>> + >preempt_context);
> >>
> >> You lost the failure path here. I suspect deliberately? But I am not
> >> convinced we want to silently lose preemption when keeping the failure
> >> path is so easy.
> >
> > The failure path kills the module. Whereas we can quite happily survive
> > without preemption.
>
> Yes it is hard to decide what is worse, modprobe failure which never
> happens, or change in performance profile which also never happens. :)
>
> For something so unlikely I'd rather see it fail than silently change
> behaviour. Perhaps it has some relevance during development and platform
> bringup if nowhere else.
I err on the opposite side, keep going at all costs so that the user
isn't scaring at a blank screen of doom. It's not exactly a silent
failure, we tell anyone who asks that preemption is enabled :)
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2 2/2] drm/i915: Simplify i830 DVO 2x clock handling
From: Ville Syrjälä
Let's just always enable the DVO 2x clock on i830. This way we don't
have to track if DVO is being used or not. The spec does suggest we
should disable the clock when it isn't needed, but this does appear
to work just fine.
This removes another crtc->config usage.
v2: Split the DPLL enable sequence change to a separate patch
Reviewed-by: Chris Wilson #v1
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 60 +++-
1 file changed, 14 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9ee313b42e1e..72c8d0b61672 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1441,19 +1441,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
}
}
-static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
-{
- struct intel_crtc *crtc;
- int count = 0;
-
- for_each_intel_crtc(_priv->drm, crtc) {
- count += crtc->base.state->active &&
- intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
- }
-
- return count;
-}
-
static void i9xx_enable_pll(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state)
{
@@ -1468,19 +1455,6 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
assert_panel_unlocked(dev_priv, crtc->pipe);
- /* Enable DVO 2x clock on both PLLs if necessary */
- if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
- /*
-* It appears to be important that we don't enable this
-* for the current pipe before otherwise configuring the
-* PLL. No idea how this should be handled if multiple
-* DVO outputs are enabled simultaneosly.
-*/
- dpll |= DPLL_DVO_2X_MODE;
- I915_WRITE(DPLL(!crtc->pipe),
- I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
- }
-
/*
* Apparently we need to have VGA mode enabled prior to changing
* the P1/P2 dividers. Otherwise the DPLL will keep using the old
@@ -1519,16 +1493,6 @@ static void i9xx_disable_pll(const struct
intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- /* Disable DVO 2x clock on both PLLs if necessary */
- if (IS_I830(dev_priv) &&
- intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO) &&
- !intel_num_dvo_pipes(dev_priv)) {
- I915_WRITE(DPLL(PIPE_B),
- I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
- I915_WRITE(DPLL(PIPE_A),
- I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
- }
-
/* Don't disable pipe or pipe PLLs if needed */
if (IS_I830(dev_priv))
return;
@@ -7493,7 +7457,19 @@ static void i8xx_compute_dpll(struct intel_crtc *crtc,
dpll |= PLL_P2_DIVIDE_BY_4;
}
- if (!IS_I830(dev_priv) &&
+ /*
+* Bspec:
+* "[Almador Errata}: For the correct operation of the muxed DVO pins
+* (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data,
+* GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock
+* Enable) must be set to “1” in both the DPLL A Control Register
+* (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)."
+*
+* For simplicity We simply keep both bits always enabled in
+* both DPLLS. The spec says we should disable the DVO 2X clock
+* when not needed, but this seems to work fine in practice.
+*/
+ if (IS_I830(dev_priv) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
dpll |= DPLL_DVO_2X_MODE;
@@ -8217,14 +8193,6 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
- /*
-* DPLL_DVO_2X_MODE must be enabled for both DPLLs
-* on 830. Filter it out here so that we don't
-* report errors due to that.
-*/
- if (IS_I830(dev_priv))
- pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
-
pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
} else {
@@ -15616,7 +15584,7 @@ void i830_enable_pipe(struct drm_i915_private
*dev_priv, enum pipe pipe)
pipe_name(pipe), clock.vco, clock.dot);
fp = i9xx_dpll_compute_fp();
- dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) |
+
[Intel-gfx] [PATCH v2 1/2] drm/i915: Do not temporarily disable the DPLL on i830
From: Ville Syrjälä The current code clears the DPLL register entirely when re-enabling VGA mode temporarily during the DPLL enable sequence. On i830 we want to keep the DPLLs on all the time, so let's not do this temporary disabling. The current code does work, so this doesn't seem super important. But I prefer that we make the behaviour 100% consistent. v2: Split this change the DVO 2x clocking patch Reviewed-by: Chris Wilson #v1 Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_display.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d852cb282060..9ee313b42e1e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1486,8 +1486,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc, * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - I915_WRITE(reg, 0); - + I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); I915_WRITE(reg, dpll); /* Wait for the clocks to stabilize. */ -- 2.19.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 26/38] drm/i915: Pass around the intel_context
Quoting Chris Wilson (2019-03-05 16:33:21)
> Quoting Tvrtko Ursulin (2019-03-05 16:16:01)
> >
> > On 01/03/2019 14:03, Chris Wilson wrote:
> > > Instead of passing the gem_context and engine to find the instance of
> > > the intel_context to use, pass around the intel_context instead. This is
> > > useful for the next few patches, where the intel_context is no longer a
> > > direct lookup.
> > >
> > > Signed-off-by: Chris Wilson
> > > ---
> > > @@ -1314,9 +1314,10 @@ __execlists_update_reg_state(struct
> > > intel_engine_cs *engine,
> > > regs[CTX_RING_TAIL + 1] = ring->tail;
> > >
> > > /* RPCS */
> > > - if (engine->class == RENDER_CLASS)
> > > - regs[CTX_R_PWR_CLK_STATE + 1] = gen8_make_rpcs(engine->i915,
> > > ->sseu);
> > > + if (engine->class == RENDER_CLASS) {
> > > + regs[CTX_R_PWR_CLK_STATE + 1] =
> > > + gen8_make_rpcs(engine->i915, >sseu);
> > > + }
> >
> > Rebasing artifact I guess.
>
> I must have slipped :-p
>
> > > @@ -2659,7 +2660,7 @@ static u32 intel_lr_indirect_ctx_offset(struct
> > > intel_engine_cs *engine)
> > > }
> > >
> > > static void execlists_init_reg_state(u32 *regs,
> > > - struct i915_gem_context *ctx,
> > > + struct intel_context *ce,
> > >struct intel_engine_cs *engine,
> >
> > I can't remember if separate engine param is needed since now there's
> > ce->engine. Maybe it comes useful later.
>
> We could even initialise ce->ring, or just pull that
> ce->gem_context->ring_size.
>
> I didn't have a good reason to keep engine, nor a good enough reason to
> kill it -- although having ce is enough of a change I guess.
Ah, yes there was. It's for virtual engine.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/6] drm/i915: Reduce presumption of request ordering for barriers
Currently we assume that we know the order in which requests run and so
can determine if we need to reissue a switch-to-kernel-context prior to
idling. That assumption does not hold for the future, so instead of
tracking which barriers have been used, simply determine if we have ever
switched away from the kernel context by using the engine and before
idling ensure that all engines that have been used since the last idle
are synchronously switched back to the kernel context for safety (and
else of shrinking memory while idle).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 13 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 66 +--
drivers/gpu/drm/i915/i915_gem_context.h | 3 +-
drivers/gpu/drm/i915/i915_gem_evict.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 1 +
drivers/gpu/drm/i915/intel_engine_cs.c| 5 ++
.../gpu/drm/i915/selftests/i915_gem_context.c | 3 +-
.../gpu/drm/i915/selftests/igt_flush_test.c | 2 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 4 ++
10 files changed, 28 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 36c71d1b5538..d288b0bdc1ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1994,6 +1994,7 @@ struct drm_i915_private {
struct list_head active_rings;
struct list_head closed_vma;
+ unsigned long active_engines;
u32 active_requests;
/**
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0918a8709c38..f9afe6a300b4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2844,9 +2844,10 @@ static void assert_kernel_context_is_current(struct
drm_i915_private *i915)
}
}
-static bool switch_to_kernel_context_sync(struct drm_i915_private *i915)
+static bool switch_to_kernel_context_sync(struct drm_i915_private *i915,
+ unsigned long mask)
{
- if (i915_gem_switch_to_kernel_context(i915))
+ if (i915_gem_switch_to_kernel_context(i915, mask))
return false;
if (i915_gem_wait_for_idle(i915,
@@ -2861,7 +2862,8 @@ static bool switch_to_kernel_context_sync(struct
drm_i915_private *i915)
static bool load_power_context(struct drm_i915_private *i915)
{
- if (!switch_to_kernel_context_sync(i915))
+ /* Force loading the kernel context on all engines */
+ if (!switch_to_kernel_context_sync(i915, -1))
return false;
/*
@@ -2909,7 +2911,8 @@ i915_gem_idle_work_handler(struct work_struct *work)
if (!gt->active_requests && !work_pending(>idle_work.work)) {
++gt->active_requests; /* don't requeue idle */
- if (!switch_to_kernel_context_sync(i915)) {
+ if (!switch_to_kernel_context_sync(i915,
+ i915->gt.active_engines)) {
dev_err(i915->drm.dev,
"Failed to idle engines, declaring wedged!\n");
GEM_TRACE_DUMP();
@@ -4368,7 +4371,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
* state. Fortunately, the kernel_context is disposable and we do
* not rely on its state.
*/
- if (!switch_to_kernel_context_sync(i915)) {
+ if (!switch_to_kernel_context_sync(i915, i915->gt.active_engines)) {
/* Forcibly cancel outstanding work and leave the gpu quiet. */
i915_gem_set_wedged(i915);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
b/drivers/gpu/drm/i915/i915_gem_context.c
index 80bc9f985db9..0183d1473001 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -702,63 +702,10 @@ last_request_on_engine(struct i915_timeline *timeline,
return NULL;
}
-static bool engine_has_kernel_context_barrier(struct intel_engine_cs *engine)
-{
- struct drm_i915_private *i915 = engine->i915;
- const struct intel_context * const ce =
- to_intel_context(i915->kernel_context, engine);
- struct i915_timeline *barrier = ce->ring->timeline;
- struct intel_ring *ring;
- bool any_active = false;
-
- lockdep_assert_held(>drm.struct_mutex);
- list_for_each_entry(ring, >gt.active_rings, active_link) {
- struct i915_request *rq;
-
- rq = last_request_on_engine(ring->timeline, engine);
- if (!rq)
- continue;
-
- any_active = true;
-
- if (rq->hw_context == ce)
- continue;
-
- /*
-* Was this request submitted after the previous
-* switch-to-kernel-context?
-
[Intel-gfx] [PATCH 6/6] drm/i915: Remove has-kernel-context
We can no longer assume execution ordering, and in particular we cannot
assume which context will execute last. One side-effect of this is that
we cannot determine if the kernel-context is resident on the GPU, so
remove the routines that claimed to do so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.h | 13 ---
drivers/gpu/drm/i915/i915_gem.c | 18 --
drivers/gpu/drm/i915/i915_gem_evict.c | 16 +++--
drivers/gpu/drm/i915/intel_engine_cs.c | 31 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 -
5 files changed, 3 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.h
b/drivers/gpu/drm/i915/i915_active.h
index 5fbd9102384b..a049ccd478c6 100644
--- a/drivers/gpu/drm/i915/i915_active.h
+++ b/drivers/gpu/drm/i915/i915_active.h
@@ -108,19 +108,6 @@ i915_active_request_set_retire_fn(struct
i915_active_request *active,
active->retire = fn ?: i915_active_retire_noop;
}
-static inline struct i915_request *
-__i915_active_request_peek(const struct i915_active_request *active)
-{
- /*
-* Inside the error capture (running with the driver in an unknown
-* state), we want to bend the rules slightly (a lot).
-*
-* Work is in progress to make it safer, in the meantime this keeps
-* the known issue from spamming the logs.
-*/
- return rcu_dereference_protected(active->request, 1);
-}
-
/**
* i915_active_request_raw - return the active request
* @active - the active tracker
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index f9afe6a300b4..6555b692e0d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2827,23 +2827,6 @@ i915_gem_retire_work_handler(struct work_struct *work)
round_jiffies_up_relative(HZ));
}
-static void assert_kernel_context_is_current(struct drm_i915_private *i915)
-{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (i915_reset_failed(i915))
- return;
-
- i915_retire_requests(i915);
-
- for_each_engine(engine, i915, id) {
-
GEM_BUG_ON(__i915_active_request_peek(>timeline.last_request));
- GEM_BUG_ON(engine->last_retired_context !=
- to_intel_context(i915->kernel_context, engine));
- }
-}
-
static bool switch_to_kernel_context_sync(struct drm_i915_private *i915,
unsigned long mask)
{
@@ -2856,7 +2839,6 @@ static bool switch_to_kernel_context_sync(struct
drm_i915_private *i915,
HZ / 10))
return false;
- assert_kernel_context_is_current(i915);
return true;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c
b/drivers/gpu/drm/i915/i915_gem_evict.c
index 7d8e90dfca84..060f5903544a 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -38,25 +38,15 @@ I915_SELFTEST_DECLARE(static struct igt_evict_ctl {
static bool ggtt_is_idle(struct drm_i915_private *i915)
{
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- if (i915->gt.active_requests)
- return false;
-
- for_each_engine(engine, i915, id) {
- if (!intel_engine_has_kernel_context(engine))
- return false;
- }
-
- return true;
+ return !i915->gt.active_requests;
}
static int ggtt_flush(struct drm_i915_private *i915)
{
int err;
- /* Not everything in the GGTT is tracked via vma (otherwise we
+ /*
+* Not everything in the GGTT is tracked via vma (otherwise we
* could evict as required with minimal stalling) so we are forced
* to idle the GPU and explicitly retire outstanding requests in
* the hopes that we can then remove contexts and the like only
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 18174f808fd8..8e326556499e 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1090,37 +1090,6 @@ bool intel_engines_are_idle(struct drm_i915_private
*i915)
return true;
}
-/**
- * intel_engine_has_kernel_context:
- * @engine: the engine
- *
- * Returns true if the last context to be executed on this engine, or has been
- * executed if the engine is already idle, is the kernel context
- * (#i915.kernel_context).
- */
-bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
-{
- const struct intel_context *kernel_context =
- to_intel_context(engine->i915->kernel_context, engine);
- struct i915_request *rq;
-
- lockdep_assert_held(>i915->drm.struct_mutex);
-
- if (!engine->context_size)
- return true;
-
- /*
-* Check the last context seen by
[Intel-gfx] [PATCH 1/6] drm/i915: Force GPU idle on suspend
To facilitate the next patch to allow preemptible kernels not to incur
the wrath of hangcheck, we need to ensure that we can still suspend and
shutdown. That is we will not be able to rely on hangcheck to terminate
a blocking kernel and instead must manually do so ourselves. The
advantage is that we can apply more pressure!
As we now perform a GPU reset to clean up any residual kernels, we leave
the GPU in an unknown state and in particular can not talk to the GuC
before we reinitialise it following resume. For example, we no longer
need to tell the GuC to suspend itself, as it is already reset.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c67369bd145b..334854cfe6cc 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3122,13 +3122,6 @@ int i915_gem_wait_for_idle(struct drm_i915_private *i915,
lockdep_assert_held(>drm.struct_mutex);
- if (GEM_SHOW_DEBUG() && !timeout) {
- /* Presume that timeout was non-zero to begin with! */
- dev_warn(>drm.pdev->dev,
-"Missed idle-completion interrupt!\n");
- GEM_TRACE_DUMP();
- }
-
err = wait_for_engines(i915);
if (err)
return err;
@@ -4378,11 +4371,12 @@ int i915_gem_suspend(struct drm_i915_private *i915)
I915_WAIT_INTERRUPTIBLE |
I915_WAIT_LOCKED |
I915_WAIT_FOR_IDLE_BOOST,
-MAX_SCHEDULE_TIMEOUT);
- if (ret && ret != -EIO)
+HZ / 5);
+ if (ret == -EINTR)
goto err_unlock;
- assert_kernel_context_is_current(i915);
+ /* Forcibly cancel outstanding work and leave the gpu quiet. */
+ i915_gem_set_wedged(i915);
}
i915_retire_requests(i915); /* ensure we flush after wedging */
@@ -4397,15 +4391,11 @@ int i915_gem_suspend(struct drm_i915_private *i915)
*/
drain_delayed_work(>gt.idle_work);
- intel_uc_suspend(i915);
-
/*
* Assert that we successfully flushed all the work and
* reset the GPU back to its idle, low power state.
*/
- WARN_ON(i915->gt.awake);
- if (WARN_ON(!intel_engines_are_idle(i915)))
- i915_gem_set_wedged(i915); /* no hope, discard everything */
+ GEM_BUG_ON(i915->gt.awake);
intel_runtime_pm_put(i915, wakeref);
return 0;
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/6] drm/i915/selftests: Improve switch-to-kernel-context checking
We can reduce the switch-to-kernel-context selftest to operate as a loop
and so trivially test another state transition (that of idle->busy).
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/selftests/i915_gem_context.c | 80 ---
1 file changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 30111c004eb6..6d2a3122dfb3 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -1493,63 +1493,55 @@ static int __igt_switch_to_kernel_context(struct
drm_i915_private *i915,
{
struct intel_engine_cs *engine;
unsigned int tmp;
- int err;
+ int pass;
GEM_TRACE("Testing %s\n", __engine_name(i915, engines));
- for_each_engine_masked(engine, i915, engines, tmp) {
- struct i915_request *rq;
+ for (pass = 0; pass < 4; pass++) { /* Once busy; once idle; repeat */
+ bool from_idle = pass & 1;
+ int err;
- rq = i915_request_alloc(engine, ctx);
- if (IS_ERR(rq))
- return PTR_ERR(rq);
+ if (!from_idle) {
+ for_each_engine_masked(engine, i915, engines, tmp) {
+ struct i915_request *rq;
- i915_request_add(rq);
- }
+ rq = i915_request_alloc(engine, ctx);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
- err = i915_gem_switch_to_kernel_context(i915);
- if (err)
- return err;
-
- for_each_engine_masked(engine, i915, engines, tmp) {
- if (!engine_has_kernel_context_barrier(engine)) {
- pr_err("kernel context not last on engine %s!\n",
- engine->name);
- return -EINVAL;
+ i915_request_add(rq);
+ }
}
- }
- err = i915_gem_wait_for_idle(i915,
-I915_WAIT_LOCKED,
-MAX_SCHEDULE_TIMEOUT);
- if (err)
- return err;
+ err = i915_gem_switch_to_kernel_context(i915);
+ if (err)
+ return err;
- GEM_BUG_ON(i915->gt.active_requests);
- for_each_engine_masked(engine, i915, engines, tmp) {
- if (engine->last_retired_context->gem_context !=
i915->kernel_context) {
- pr_err("engine %s not idling in kernel context!\n",
- engine->name);
+ if (!from_idle) {
+ err = i915_gem_wait_for_idle(i915,
+I915_WAIT_LOCKED,
+MAX_SCHEDULE_TIMEOUT);
+ if (err)
+ return err;
+ }
+
+ if (i915->gt.active_requests) {
+ pr_err("%d active requests remain after switching to
kernel context, pass %d (%s) on %s engine%s\n",
+ i915->gt.active_requests,
+ pass, from_idle ? "idle" : "busy",
+ __engine_name(i915, engines),
+ is_power_of_2(engines) ? "" : "s");
return -EINVAL;
}
- }
- err = i915_gem_switch_to_kernel_context(i915);
- if (err)
- return err;
+ /* XXX Bonus points for proving we are the kernel context! */
- if (i915->gt.active_requests) {
- pr_err("switch-to-kernel-context emitted %d requests even
though it should already be idling in the kernel context\n",
- i915->gt.active_requests);
- return -EINVAL;
+ mutex_unlock(>drm.struct_mutex);
+ drain_delayed_work(>gt.idle_work);
+ mutex_lock(>drm.struct_mutex);
}
- for_each_engine_masked(engine, i915, engines, tmp) {
- if (!intel_engine_has_kernel_context(engine)) {
- pr_err("kernel context not last on engine %s!\n",
- engine->name);
- return -EINVAL;
- }
- }
+ if (igt_flush_test(i915, I915_WAIT_LOCKED))
+ return -EIO;
return 0;
}
@@ -1593,8 +1585,6 @@ static int igt_switch_to_kernel_context(void *arg)
out_unlock:
GEM_TRACE_DUMP_ON(err);
- if (igt_flush_test(i915, I915_WAIT_LOCKED))
- err = -EIO;
intel_runtime_pm_put(i915, wakeref);
mutex_unlock(>drm.struct_mutex);
--
2.20.1
___
Intel-gfx mailing list
[Intel-gfx] [PATCH 3/6] drm/i915: Do a synchronous switch-to-kernel-context on idling
When the system idles, we switch to the kernel context as a defensive
measure (no users are harmed if the kernel context is lost). Currently,
we issue a switch to kernel context and then come back later to see if
the kernel context is still current and the system is idle. However,
if we are no longer privy to the runqueue ordering, then we have to
relax our assumptions about the logical state of the GPU and the only
way to ensure that the kernel context is currently loaded is by issuing
a request to run after all others, and wait for it to complete all while
preventing anyone else from issuing their own requests.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 14 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 139 --
drivers/gpu/drm/i915/i915_gem_context.c | 4 +
drivers/gpu/drm/i915/selftests/i915_gem.c | 9 +-
5 files changed, 63 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b548c292738c..a4235a4d4309 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -714,8 +714,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ i915_gem_suspend(dev_priv);
i915_gem_fini(dev_priv);
cleanup_modeset:
intel_modeset_cleanup(dev);
@@ -1787,8 +1786,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
- if (i915_gem_suspend(dev_priv))
- DRM_ERROR("failed to idle hardware; continuing to unload!\n");
+ i915_gem_suspend(dev_priv);
drm_atomic_helper_shutdown(dev);
@@ -1896,7 +1894,6 @@ static bool suspend_to_idle(struct drm_i915_private
*dev_priv)
static int i915_drm_prepare(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
- int err;
/*
* NB intel_display_suspend() may issue new requests after we've
@@ -1904,12 +1901,9 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- err = i915_gem_suspend(i915);
- if (err)
- dev_err(>drm.pdev->dev,
- "GEM idle failed, suspend/resume might fail\n");
+ i915_gem_suspend(i915);
- return err;
+ return 0;
}
static int i915_drm_suspend(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ff039750069d..36c71d1b5538 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3028,7 +3028,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags, long timeout);
-int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+void i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
vm_fault_t i915_gem_fault(struct vm_fault *vmf);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 334854cfe6cc..97a02985bc62 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2827,13 +2827,6 @@ i915_gem_retire_work_handler(struct work_struct *work)
round_jiffies_up_relative(HZ));
}
-static inline bool
-new_requests_since_last_retire(const struct drm_i915_private *i915)
-{
- return (READ_ONCE(i915->gt.active_requests) ||
- work_pending(>gt.idle_work.work));
-}
-
static void assert_kernel_context_is_current(struct drm_i915_private *i915)
{
struct intel_engine_cs *engine;
@@ -2842,7 +2835,8 @@ static void assert_kernel_context_is_current(struct
drm_i915_private *i915)
if (i915_reset_failed(i915))
return;
- GEM_BUG_ON(i915->gt.active_requests);
+ i915_retire_requests(i915);
+
for_each_engine(engine, i915, id) {
GEM_BUG_ON(__i915_active_request_peek(>timeline.last_request));
GEM_BUG_ON(engine->last_retired_context !=
@@ -2850,77 +2844,75 @@ static void assert_kernel_context_is_current(struct
drm_i915_private *i915)
}
}
+static bool switch_to_kernel_context_sync(struct drm_i915_private *i915)
+{
+ if (i915_gem_switch_to_kernel_context(i915))
+ return false;
+
+ if (i915_gem_wait_for_idle(i915,
+ I915_WAIT_LOCKED |
+
[Intel-gfx] [PATCH 4/6] drm/i915: Refactor common code to load initial power context
We load a context (the kernel context) on both module load and resume in
order to initialise some logical state onto the GPU. We can use the same
routine for both operations, which will become more useful as we
refactor rc6/rps enabling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 48 -
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 97a02985bc62..0918a8709c38 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2859,6 +2859,22 @@ static bool switch_to_kernel_context_sync(struct
drm_i915_private *i915)
return true;
}
+static bool load_power_context(struct drm_i915_private *i915)
+{
+ if (!switch_to_kernel_context_sync(i915))
+ return false;
+
+ /*
+* Immediately park the GPU so that we enable powersaving and
+* treat it as idle. The next time we issue a request, we will
+* unpark and start using the engine->pinned_default_state, otherwise
+* it is in limbo and an early reset may fail.
+*/
+ __i915_gem_park(i915);
+
+ return true;
+}
+
static void
i915_gem_idle_work_handler(struct work_struct *work)
{
@@ -4443,7 +4459,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
intel_uc_resume(i915);
/* Always reload a context for powersaving. */
- if (i915_gem_switch_to_kernel_context(i915))
+ if (!load_power_context(i915))
goto err_wedged;
out_unlock:
@@ -4608,7 +4624,7 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
struct i915_gem_context *ctx;
struct intel_engine_cs *engine;
enum intel_engine_id id;
- int err;
+ int err = 0;
/*
* As we reset the gpu during very early sanitisation, the current
@@ -4641,19 +4657,12 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
goto err_active;
}
- if (!switch_to_kernel_context_sync(i915)) {
- err = -EIO; /* Caller will declare us wedged */
+ /* Flush the default context image to memory, and enable powersaving. */
+ if (!load_power_context(i915)) {
+ err = -EIO;
goto err_active;
}
- /*
-* Immediately park the GPU so that we enable powersaving and
-* treat it as idle. The next time we issue a request, we will
-* unpark and start using the engine->pinned_default_state, otherwise
-* it is in limbo and an early reset may fail.
-*/
- __i915_gem_park(i915);
-
for_each_engine(engine, i915, id) {
struct i915_vma *state;
void *vaddr;
@@ -4719,19 +4728,10 @@ static int __intel_engines_record_defaults(struct
drm_i915_private *i915)
err_active:
/*
* If we have to abandon now, we expect the engines to be idle
-* and ready to be torn-down. First try to flush any remaining
-* request, ensure we are pointing at the kernel context and
-* then remove it.
+* and ready to be torn-down. The quickest way we can accomplish
+* this is by declaring ourselves wedged.
*/
- if (WARN_ON(i915_gem_switch_to_kernel_context(i915)))
- goto out_ctx;
-
- if (WARN_ON(i915_gem_wait_for_idle(i915,
- I915_WAIT_LOCKED,
- MAX_SCHEDULE_TIMEOUT)))
- goto out_ctx;
-
- i915_gem_contexts_lost(i915);
+ i915_gem_set_wedged(i915);
goto out_ctx;
}
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Default to Thread Group preemption for compute workloads
Quoting Rafael Antognolli (2019-03-05 17:30:00) > On Tue, Mar 05, 2019 at 01:48:26PM +0100, Michał Winiarski wrote: > > We assumed that the default preemption granularity is fine for ICL. > > Unfortunately, it turns out that some drivers don't support mid-thread > > preemption for compute workloads. > > If a workload that doesn't support mid-thread preemption gets mid-thread > > preempted, we're going to observe a GPU hang. > > While I'm here, let's also update the "workaround" naming. > > Yeah, in Mesa we are not implementing the SIP, so we can't do > thread-level preemption yet and need the granularity to be no higher > than thread group level. > > Acked-by: Rafael Antognolli > > > Signed-off-by: Michał Winiarski > > Cc: Anuj Phogat > > Cc: Joonas Lahtinen > > Cc: Matt Roper > > Cc: Rafael Antognolli > > Tested-by: Anuj Phogat > > Reviewed-by: Rodrigo Vivi And pushed, thanks everyone for the testing and reviewed. I've held off on pushing the second patch as we just want to double check that the whitelisting is required. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH i-g-t v4 1/1] gem_ctx_isolation.c - Gen11 enabling for context isolation test
Quoting Dale B Stimson (2019-03-05 01:03:08)
> @@ -132,30 +136,49 @@ static const struct named_register {
> { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
> { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
>
> + { "CTX_PREEMPT", NOCTX /* GEN10 */, RCS0, 0x2248 },
> + { "CS_CHICKEN1", GEN11, RCS0, 0x2580, .masked = true },
CS_CHICKEN1 is still privileged? At least I'm push a patch to add it to
the whitelist for gen11.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 01/10] drm: Add CP content type property
> -Original Message-
> From: Maarten Lankhorst [mailto:maarten.lankho...@linux.intel.com]
> Sent: Tuesday, March 5, 2019 8:09 PM
> To: C, Ramalingam ; intel-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; daniel.vet...@ffwll.ch; Shankar, Uma
>
> Subject: Re: [Intel-gfx] [PATCH 01/10] drm: Add CP content type property
>
> Op 26-02-2019 om 08:36 schreef Ramalingam C:
> > This patch adds a DRM ENUM property to the selected connectors.
> > This property is used for pass the protected content's type from
> > userspace to kernel HDCP authentication.
> >
> > Type of the stream is decided by the protected content providers as
> > Type 0/1.
> >
> > Type 0 content can be rendered on any HDCP protected display wires.
> > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> >
> > So upon a content protection request with Type 1 as Content type from
> > userspace, Kernel will declare success only if the HDCP2.2
> > authentication is successful.
> >
> > Signed-off-by: Ramalingam C
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 10 ++
> > drivers/gpu/drm/drm_connector.c | 64
> +++
> > include/drm/drm_connector.h | 15 +
> > include/uapi/drm/drm_mode.h | 4 +++
> > 4 files changed, 93 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index 4eb81f10bc54..5289486565ce 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -746,6 +746,14 @@ static int
> drm_atomic_connector_set_property(struct drm_connector *connector,
> > return -EINVAL;
> > }
> > state->content_protection = val;
> > + } else if (property == connector->cp_content_type_property) {
> > + if (state->content_protection !=
> > + DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
> > + state->cp_content_type != val) {
> > + DRM_DEBUG_KMS("Disable CP, then change Type\n");
> > + return -EINVAL;
> > + }
> > + state->cp_content_type = val;
>
> You can't add checks in atomic_set_property.
Thanks Maarten for the review.
I am afraid we have the similar check for content_protection, just above this.
>
> Until we have the full state, we can't do any checks. This has to be done in
> the
> .atomic_check() callback.
>
> Lets say atomic commit consists of the following:
> Set Content_Protection to desired.
> Set Content Type to Type 1.
> atomic setprop will fail
>
> Plus the check itself is bogus. We should be able to change HDCP strictness
> without a modeset, the same way we enable and disable HDCP 1.4 with a
> fastset.
This is not modeset mandating, but the sequence of hdcp_disable->change
Type->hdcp_enable from userspace.
Reason is we need to redo the hdcp authenticate with new Type value.
Alternate approach would be kernel performing disable and enable on Type change
request from userspace.
For this we could disable hdcp at intel_hdcp_atomic_check and re-enable with
new Type value at atomic_commit.
I thought it is better to leave the required preparation (disable and enable of
hdcp) to userspace.
But if we prefer to push that into kernel also it is doable. Share your opinion
please.
>
> > } else if (property == connector->colorspace_property) {
> > state->colorspace = val;
> > } else if (property == config->writeback_fb_id_property) { @@ -822,6
> > +830,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> > *val = state->scaling_mode;
> > } else if (property == connector->content_protection_property) {
> > *val = state->content_protection;
> > + } else if (property == connector->cp_content_type_property) {
> > + *val = state->cp_content_type;
> > } else if (property == config->writeback_fb_id_property) {
> > /* Writeback framebuffer is one-shot, write and forget */
> > *val = 0;
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c index 07d65a16c623..5d7738e1e977
> > 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -853,6 +853,13 @@ static const struct drm_prop_enum_list
> hdmi_colorspaces[] = {
> > { DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER, "DCI-
> P3_RGB_Theater" },
> > };
> >
> > +static struct drm_prop_enum_list drm_cp_content_type_enum_list[] = {
> > + { DRM_MODE_CP_CONTENT_TYPE0, "Type 0" },
> > + { DRM_MODE_CP_CONTENT_TYPE1, "Type 1" }, };
> > +
> > +DRM_ENUM_NAME_FN(drm_get_cp_content_type_name,
> > +drm_cp_content_type_enum_list)
> > +
> > /**
> > * DOC: standard connector properties
> > *
> > @@ -958,6 +965,25 @@ static const struct drm_prop_enum_list
> hdmi_colorspaces[] = {
> > * the value transitions from ENABLED to DESIRED. This signifies the link
> > * is no longer protected and
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
== Series Details ==
Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the
engine's mask
URL : https://patchwork.freedesktop.org/series/57595/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5706 -> Patchwork_12375
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://patchwork.freedesktop.org/api/1.0/series/57595/revisions/1/mbox/
Known issues
Here are the changes found in Patchwork_12375 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_basic@cs-sdma:
- fi-kbl-7560u: NOTRUN -> SKIP [fdo#109271] +17
* igt@i915_selftest@live_coherency:
- fi-snb-2600:PASS -> INCOMPLETE [fdo#105411]
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-b:
- fi-gdg-551: PASS -> FAIL [fdo#103182]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
Possible fixes
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-7560u: DMESG-WARN [fdo#106107] -> PASS
- fi-kbl-7567u: DMESG-WARN [fdo#105602] / [fdo#108529] -> PASS +1
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7567u: DMESG-WARN [fdo#108529] -> PASS
- fi-skl-6770hq: FAIL [fdo#108511] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
- fi-kbl-7567u: SKIP [fdo#109271] -> PASS +30
Warnings
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-7567u: DMESG-FAIL [fdo#105079] -> DMESG-WARN [fdo#103558] /
[fdo#105079] / [fdo#105602]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-7567u: SKIP [fdo#109271] -> DMESG-WARN [fdo#103558] /
[fdo#105079] / [fdo#105602] +2
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
Participating hosts (46 -> 42)
--
Additional (1): fi-icl-y
Missing(5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan
fi-bdw-samus
Build changes
-
* Linux: CI_DRM_5706 -> Patchwork_12375
CI_DRM_5706: fac7596f4bfed7dbaa19ce37bbb35bb50234438e @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_4870: ed944b45563c694dc6373bc48dc83b8ba7edb19f @
git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12375: b0f1fb24f5fb91ec589540af114cad4a253faeae @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b0f1fb24f5fb drm/i915: Move find_active_request() to the engine
c0832022cdfc drm/i915/gtt: Mark ALL_ENGINES as dirty on ppGTT modification
578fc9439fec drm/i915: Store the BIT(engine->id) as the engine's mask
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12375/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE
On Tue, Mar 05, 2019 at 10:38:46AM -0800, Rodrigo Vivi wrote: On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote: On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote: > On Tue, 05 Mar 2019, Lucas De Marchi wrote: > > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula wrote: > > > On Mon, 04 Mar 2019, Rodrigo Vivi wrote: > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > > > index e1a051c0fbfe..acd2336bb214 100644 > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > @@ -949,8 +949,8 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, > > > > regs->pp_stat = PP_STATUS(pps_idx); > > > > regs->pp_on = PP_ON_DELAYS(pps_idx); > > > > regs->pp_off = PP_OFF_DELAYS(pps_idx); > > > > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > > > > - !HAS_PCH_ICP(dev_priv)) > > > > + if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE && > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_CNP) > > > > > > This is not right, starts to require PCH. > > > > But in those cases INTEL_PCH_TYPE() will return either NONE or NOP. > > Exactly. Non-PCH platforms before CNP should match, but won't. yeah, right. I misread the !IS_GEN9_LP(). ouch... indeed. probably this explains failure on ci for bsw and byt options: 1. if (!IS_GEN9_LP(dev_priv) && !(INTEL_PCH_TYPE(dev_priv) >= 10)) 10? I think you meant PCH_CNP 2. if (INTEL_GEN(dev_priv) <= 8 || IS_GEN9_BC(dev_priv)) 3. other ideas? "all PCHs before CNP, excluding GEN9_LP": if (INTEL_PCH_TYPE(dev_priv) < PCH_CNP && !IS_GEN9_LP(dev_priv)) Lucas De Marchi Lucas De Marchi > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl: Apply WaEnablePreemptionGranularityControlByUMD
Quoting Michał Winiarski (2019-03-05 12:48:27) > There are still some cases where userspace needs to change the > preemption granularity for compute workloads. Let's whitelist the > per-ctx granularity control register to allow it. > > Signed-off-by: Michał Winiarski > Cc: Anuj Phogat > Cc: Joonas Lahtinen > Cc: Matt Roper > Cc: Rafael Antognolli > Cc: Chris Wilson Trusting that since it was context saved on earlier gen, it remains so. (One more selftest to write.) Reviewed-by: Chris Wilson -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Start using comparative INTEL_PCH_TYPE
On Tue, Mar 05, 2019 at 09:42:22AM -0800, Lucas De Marchi wrote: > On Tue, Mar 05, 2019 at 07:16:47PM +0200, Jani Nikula wrote: > > On Tue, 05 Mar 2019, Lucas De Marchi wrote: > > > On Tue, Mar 05, 2019 at 04:10:04PM +0200, Jani Nikula wrote: > > > > On Mon, 04 Mar 2019, Rodrigo Vivi wrote: > > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c > > > > > b/drivers/gpu/drm/i915/intel_dp.c > > > > > index e1a051c0fbfe..acd2336bb214 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_dp.c > > > > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > > > > @@ -949,8 +949,8 @@ static void intel_pps_get_registers(struct > > > > > intel_dp *intel_dp, > > > > > regs->pp_stat = PP_STATUS(pps_idx); > > > > > regs->pp_on = PP_ON_DELAYS(pps_idx); > > > > > regs->pp_off = PP_OFF_DELAYS(pps_idx); > > > > > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > > > > > - !HAS_PCH_ICP(dev_priv)) > > > > > + if (INTEL_PCH_TYPE(dev_priv) > PCH_NONE && > > > > > + INTEL_PCH_TYPE(dev_priv) < PCH_CNP) > > > > > > > > This is not right, starts to require PCH. > > > > > > But in those cases INTEL_PCH_TYPE() will return either NONE or NOP. > > > > Exactly. Non-PCH platforms before CNP should match, but won't. > > yeah, right. I misread the !IS_GEN9_LP(). ouch... indeed. probably this explains failure on ci for bsw and byt options: 1. if (!IS_GEN9_LP(dev_priv) && !(INTEL_PCH_TYPE(dev_priv) >= 10)) 2. if (INTEL_GEN(dev_priv) <= 8 || IS_GEN9_BC(dev_priv)) 3. other ideas? > > Lucas De Marchi > > > > > BR, > > Jani. > > > > > > -- > > Jani Nikula, Intel Open Source Graphics Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/3] drm/i915/gen11+: First assume next platforms will inherit stuff
On Tue, Mar 05, 2019 at 05:43:15PM +, Tvrtko Ursulin wrote:
diff --git a/drivers/gpu/drm/i915/intel_mocs.c
b/drivers/gpu/drm/i915/intel_mocs.c
index 331e7a678fb7..79913b06f455 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -252,7 +252,7 @@ static bool get_mocs_settings(struct drm_i915_private
*dev_priv,
{
bool result = false;
- if (IS_ICELAKE(dev_priv)) {
+ if (INTEL_GEN(dev_priv) >= 11) {
table->size = ARRAY_SIZE(icelake_mocs_table);
table->table = icelake_mocs_table;
table->n_entries = GEN11_NUM_MOCS_ENTRIES;
Lucas should know if this is OK.
I prefer having it like this and later change if it's different for gen
12. It will make it more consistent on how to add a new one.
Lucas De Marchi
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
== Series Details == Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask URL : https://patchwork.freedesktop.org/series/57595/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Store the BIT(engine->id) as the engine's mask -drivers/gpu/drm/i915/selftests/../i915_drv.h:3567:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3551:16: warning: expression using sizeof(void) Commit: drm/i915/gtt: Mark ALL_ENGINES as dirty on ppGTT modification Okay! Commit: drm/i915: Move find_active_request() to the engine -drivers/gpu/drm/i915/selftests/../i915_drv.h:3551:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3548:16: warning: expression using sizeof(void) ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: Just check the vebox IIR regardless
== Series Details == Series: series starting with [1/2] drm/i915: Just check the vebox IIR regardless URL : https://patchwork.freedesktop.org/series/57583/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5703_full -> Patchwork_12372_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_12372_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12372_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_12372_full: ### IGT changes ### Possible regressions * igt@gem_exec_schedule@fifo-vebox: - shard-iclb: NOTRUN -> DMESG-WARN * igt@gem_exec_schedule@independent-bsd: - shard-iclb: NOTRUN -> DMESG-FAIL * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: NOTRUN -> FAIL +4 * igt@runner@aborted: - shard-iclb: NOTRUN -> ( 8 FAIL ) [fdo#106612] / [fdo#109593] Known issues Here are the changes found in Patchwork_12372_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_isolation@bcs0-s3: - shard-iclb: NOTRUN -> SKIP [fdo#109281] +18 * igt@gem_ctx_isolation@vcs1-reset: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109281] +4 * igt@gem_ctx_param@invalid-param-get: - shard-iclb: NOTRUN -> FAIL [fdo#109559] * igt@gem_ctx_param@invalid-param-set: - shard-skl: NOTRUN -> FAIL [fdo#109674] - shard-iclb: NOTRUN -> FAIL [fdo#109674] * igt@gem_exec_flush@basic-batch-kernel-default-cmd: - shard-iclb: NOTRUN -> SKIP [fdo#109313] * igt@gem_exec_params@no-vebox: - shard-iclb: NOTRUN -> SKIP [fdo#109283] +2 * igt@gem_exec_parse@basic-rejected: - shard-iclb: NOTRUN -> SKIP [fdo#109289] +16 * igt@gem_exec_schedule@preempt-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] +112 * igt@gem_mocs_settings@mocs-reset-ctx-render: - shard-iclb: NOTRUN -> SKIP [fdo#109287] +15 * igt@gem_mocs_settings@mocs-settings-bsd1: - shard-iclb: NOTRUN -> SKIP [fdo#109276] / [fdo#109287] +4 * igt@gem_pwrite@huge-gtt-backwards: - shard-iclb: NOTRUN -> SKIP [fdo#109290] +9 * igt@gem_softpin@evict-snoop: - shard-iclb: NOTRUN -> SKIP [fdo#109312] +1 * igt@gem_stolen@stolen-clear: - shard-iclb: NOTRUN -> SKIP [fdo#109277] +11 * igt@i915_missed_irq: - shard-iclb: NOTRUN -> SKIP [fdo#109503] * igt@i915_pm_lpsp@non-edp: - shard-iclb: NOTRUN -> SKIP [fdo#109301] +3 * igt@i915_pm_rpm@debugfs-read: - shard-skl: NOTRUN -> INCOMPLETE [fdo#107807] * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-iclb: NOTRUN -> SKIP [fdo#109308] +2 * igt@i915_pm_rpm@gem-execbuf: - shard-skl: PASS -> INCOMPLETE [fdo#107803] / [fdo#107807] * igt@i915_pm_rpm@gem-execbuf-stress-pc8: - shard-iclb: NOTRUN -> SKIP [fdo#109506] * igt@i915_pm_rpm@pc8-residency: - shard-iclb: NOTRUN -> SKIP [fdo#109293] * igt@i915_pm_rps@reset: - shard-iclb: NOTRUN -> FAIL [fdo#102250] / [fdo#108059] +1 * igt@i915_pm_sseu@full-enable: - shard-iclb: NOTRUN -> SKIP [fdo#109288] * igt@i915_query@query-topology-known-pci-ids: - shard-iclb: NOTRUN -> SKIP [fdo#109303] * igt@i915_selftest@live_contexts: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108569] * igt@i915_selftest@live_workarounds: - shard-iclb: NOTRUN -> DMESG-FAIL [fdo#108954] * igt@kms_atomic_transition@3x-modeset-transitions: - shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +2 * igt@kms_atomic_transition@5x-modeset-transitions-fencing: - shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] * igt@kms_available_modes_crc@available_mode_test_crc: - shard-iclb: NOTRUN -> FAIL [fdo#106641] * igt@kms_busy@extended-modeset-hang-newfb-render-d: - shard-iclb: NOTRUN -> SKIP [fdo#109278] +45 * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-apl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: - shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] * igt@kms_busy@extended-modeset-hang-oldfb-render-f: - shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +9 * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b: - shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956] +4 * igt@kms_ccs@pipe-a-crc-primary-rotation-180: - shard-iclb: NOTRUN -> FAIL
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
== Series Details == Series: series starting with [1/3] drm/i915: Store the BIT(engine->id) as the engine's mask URL : https://patchwork.freedesktop.org/series/57595/ State : warning == Summary == $ dim checkpatch origin/drm-tip 578fc9439fec drm/i915: Store the BIT(engine->id) as the engine's mask -:1491: CHECK:SPACING: No space is necessary after a cast #1491: FILE: drivers/gpu/drm/i915/intel_device_info.c:741: + BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); total: 0 errors, 0 warnings, 1 checks, 2047 lines checked c0832022cdfc drm/i915/gtt: Mark ALL_ENGINES as dirty on ppGTT modification b0f1fb24f5fb drm/i915: Move find_active_request() to the engine ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 28/38] drm/i915: Store the intel_context_ops in the intel_engine_cs
Quoting Chris Wilson (2019-03-05 16:45:32)
> Quoting Tvrtko Ursulin (2019-03-05 16:27:34)
> >
> > On 01/03/2019 14:03, Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/intel_engine_types.h
> > > b/drivers/gpu/drm/i915/intel_engine_types.h
> > > index 5ec6e72d0ffb..546b790871ad 100644
> > > --- a/drivers/gpu/drm/i915/intel_engine_types.h
> > > +++ b/drivers/gpu/drm/i915/intel_engine_types.h
> > > @@ -351,6 +351,7 @@ struct intel_engine_cs {
> > >
> > > void(*set_default_submission)(struct intel_engine_cs
> > > *engine);
> > >
> > > + const struct intel_context_ops *context;
> >
> > Calling ce_ops / context_ops / hw_context_ops ? Anything but context! :)
>
> cops.
Or khufu (via cheops).
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Move find_active_request() to the engine
Quoting Tvrtko Ursulin (2019-03-05 18:13:34) > > intel_engine.h in 3...2...1.. ;) As soon as we have a good name for the legacy submission method. At the moment, my favorites are: gen2_submission.c / legacy_submission.c (actually that's winning again) gen8_submission.c / execlists_submission.c guc_submission.c intel_ring.[ch] can provide the small bit of common struct intel_ring, and intel_engine.[ch] for the common setup/poking. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 31/38] drm/i915: Track the pinned kernel contexts on each engine
On 05/03/2019 18:10, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
/*
* Similarly the preempt context must always be available so that
- * we can interrupt the engine at any time.
+ * we can interrupt the engine at any time. However, as preemption
+ * is optional, we allow it to fail.
*/
- if (i915->preempt_context) {
- ce = intel_context_pin(i915->preempt_context, engine);
- if (IS_ERR(ce)) {
- ret = PTR_ERR(ce);
- goto err_unpin_kernel;
- }
- }
+ if (i915->preempt_context)
+ pin_context(i915->preempt_context, engine,
+ >preempt_context);
You lost the failure path here. I suspect deliberately? But I am not
convinced we want to silently lose preemption when keeping the failure
path is so easy.
The failure path kills the module. Whereas we can quite happily survive
without preemption.
Yes it is hard to decide what is worse, modprobe failure which never
happens, or change in performance profile which also never happens. :)
For something so unlikely I'd rather see it fail than silently change
behaviour. Perhaps it has some relevance during development and platform
bringup if nowhere else.
Regards,
Tvrtko
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 3/3] drm/i915: Move find_active_request() to the engine
On 05/03/2019 18:03, Chris Wilson wrote:
To find the active request, we need only search along the individual
engine for the right request. This does not require touching any global
GEM state, so move it into the engine compartment.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/i915_gem.c | 45 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 47 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++
5 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08ead854ac2d..ff039750069d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2996,9 +2996,6 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
-struct i915_request *
-i915_gem_find_active_request(struct intel_engine_cs *engine);
-
static inline bool __i915_wedged(struct i915_gpu_error *error)
{
return unlikely(test_bit(I915_WEDGED, >flags));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 69413f99ed04..c67369bd145b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2803,51 +2803,6 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj,
return 0;
}
-static bool match_ring(struct i915_request *rq)
-{
- struct drm_i915_private *dev_priv = rq->i915;
- u32 ring = I915_READ(RING_START(rq->engine->mmio_base));
-
- return ring == i915_ggtt_offset(rq->ring->vma);
-}
-
-struct i915_request *
-i915_gem_find_active_request(struct intel_engine_cs *engine)
-{
- struct i915_request *request, *active = NULL;
- unsigned long flags;
-
- /*
-* We are called by the error capture, reset and to dump engine
-* state at random points in time. In particular, note that neither is
-* crucially ordered with an interrupt. After a hang, the GPU is dead
-* and we assume that no more writes can happen (we waited long enough
-* for all writes that were in transaction to be flushed) - adding an
-* extra delay for a recent interrupt is pointless. Hence, we do
-* not need an engine->irq_seqno_barrier() before the seqno reads.
-* At all other times, we must assume the GPU is still running, but
-* we only care about the snapshot of this moment.
-*/
- spin_lock_irqsave(>timeline.lock, flags);
- list_for_each_entry(request, >timeline.requests, link) {
- if (i915_request_completed(request))
- continue;
-
- if (!i915_request_started(request))
- break;
-
- /* More than one preemptible request may match! */
- if (!match_ring(request))
- break;
-
- active = request;
- break;
- }
- spin_unlock_irqrestore(>timeline.lock, flags);
-
- return active;
-}
-
static void
i915_gem_retire_work_handler(struct work_struct *work)
{
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5f1cdbc9eb5d..3d8020888604 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1411,7 +1411,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
error_record_engine_registers(error, engine, ee);
error_record_engine_execlists(engine, ee);
- request = i915_gem_find_active_request(engine);
+ request = intel_engine_find_active_request(engine);
if (request) {
struct i915_gem_context *ctx = request->gem_context;
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 62a2cc64..555a4590fa23 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1545,7 +1545,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (>link != >timeline.requests)
print_request(m, rq, "\t\tlast ");
- rq = i915_gem_find_active_request(engine);
+ rq = intel_engine_find_active_request(engine);
if (rq) {
print_request(m, rq, "\t\tactive ");
@@ -1712,6 +1712,51 @@ void intel_disable_engine_stats(struct intel_engine_cs *engine)
write_sequnlock_irqrestore(>stats.lock, flags);
}
+static bool match_ring(struct i915_request *rq)
+{
+ struct drm_i915_private *dev_priv = rq->i915;
+ u32 ring = I915_READ(RING_START(rq->engine->mmio_base));
+
+ return ring == i915_ggtt_offset(rq->ring->vma);
+}
+
+struct i915_request *
+intel_engine_find_active_request(struct intel_engine_cs
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
On 05/03/2019 18:03, Chris Wilson wrote:
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.
Reviewed-by: Tvrtko Ursulin
Regards,
Tvrtko
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 44 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 17 +-
drivers/gpu/drm/i915/gvt/handlers.c | 26 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 228 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 21 +-
drivers/gpu/drm/i915/i915_cmd_parser.c| 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_irq.c | 65 ++---
drivers/gpu/drm/i915/i915_pci.c | 39 +--
drivers/gpu/drm/i915/i915_perf.c | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 24 +-
drivers/gpu/drm/i915/i915_reset.c | 47 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 59 ++---
drivers/gpu/drm/i915/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_mocs.c | 12 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 27 +--
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +-
.../drm/i915/selftests/i915_gem_coherency.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 14 +-
drivers/gpu/drm/i915/selftests/intel_guc.c| 4 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 16 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 4 +-
.../drm/i915/selftests/intel_workarounds.c| 4 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
45 files changed, 422 insertions(+), 432 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 35b4ec3f7618..cf4a1ecf6853 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -391,12 +391,12 @@ struct cmd_info {
#define F_POST_HANDLE (1<<2)
u32 flag;
-#define R_RCS (1 << RCS)
-#define R_VCS1 (1 << VCS)
-#define R_VCS2 (1 << VCS2)
+#define R_RCS BIT(RCS0)
+#define R_VCS1 BIT(VCS0)
+#define R_VCS2 BIT(VCS1)
#define R_VCS (R_VCS1 | R_VCS2)
-#define R_BCS (1 << BCS)
-#define R_VECS (1 << VECS)
+#define R_BCS BIT(BCS0)
+#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = {
};
static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
- [RCS] = {
+ [RCS0] = {
_info_mi,
NULL,
NULL,
@@ -569,7 +569,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VCS] = {
+ [VCS0] = {
_info_mi,
NULL,
NULL,
@@ -580,7 +580,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [BCS] = {
+ [BCS0] = {
_info_mi,
NULL,
_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VECS] = {
Re: [Intel-gfx] [PATCH 31/38] drm/i915: Track the pinned kernel contexts on each engine
Quoting Tvrtko Ursulin (2019-03-05 18:07:39)
> > /*
> >* Similarly the preempt context must always be available so that
> > - * we can interrupt the engine at any time.
> > + * we can interrupt the engine at any time. However, as preemption
> > + * is optional, we allow it to fail.
> >*/
> > - if (i915->preempt_context) {
> > - ce = intel_context_pin(i915->preempt_context, engine);
> > - if (IS_ERR(ce)) {
> > - ret = PTR_ERR(ce);
> > - goto err_unpin_kernel;
> > - }
> > - }
> > + if (i915->preempt_context)
> > + pin_context(i915->preempt_context, engine,
> > + >preempt_context);
>
> You lost the failure path here. I suspect deliberately? But I am not
> convinced we want to silently lose preemption when keeping the failure
> path is so easy.
The failure path kills the module. Whereas we can quite happily survive
without preemption.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 31/38] drm/i915: Track the pinned kernel contexts on each engine
On 01/03/2019 14:03, Chris Wilson wrote:
Each engine acquires a pin on the kernel contexts (normal and preempt)
so that the logical state is always available on demand. Keep track of
each engines pin by storing the returned pointer on the engine for quick
access.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 65 ++--
drivers/gpu/drm/i915/intel_engine_types.h| 8 +--
drivers/gpu/drm/i915/intel_guc_ads.c | 3 +-
drivers/gpu/drm/i915/intel_lrc.c | 13 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 5 +-
6 files changed, 45 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 112301560745..0f311752ee08 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -641,12 +641,6 @@ void intel_engines_set_scheduler_caps(struct
drm_i915_private *i915)
i915->caps.scheduler = 0;
}
-static void __intel_context_unpin(struct i915_gem_context *ctx,
- struct intel_engine_cs *engine)
-{
- intel_context_unpin(intel_context_lookup(ctx, engine));
-}
-
struct measure_breadcrumb {
struct i915_request rq;
struct i915_timeline timeline;
@@ -697,6 +691,20 @@ static int measure_breadcrumb_dw(struct intel_engine_cs
*engine)
return dw;
}
+static int pin_context(struct i915_gem_context *ctx,
+ struct intel_engine_cs *engine,
+ struct intel_context **out)
+{
+ struct intel_context *ce;
+
+ ce = intel_context_pin(ctx, engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ *out = ce;
+ return 0;
+}
+
/**
* intel_engines_init_common - initialize cengine state which might require
hw access
* @engine: Engine to initialize.
@@ -711,11 +719,8 @@ static int measure_breadcrumb_dw(struct intel_engine_cs
*engine)
int intel_engine_init_common(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
- struct intel_context *ce;
int ret;
- engine->set_default_submission(engine);
-
/* We may need to do things with the shrinker which
* require us to immediately switch back to the default
* context. This can cause a problem as pinning the
@@ -723,36 +728,34 @@ int intel_engine_init_common(struct intel_engine_cs
*engine)
* be available. To avoid this we always pin the default
* context.
*/
- ce = intel_context_pin(i915->kernel_context, engine);
- if (IS_ERR(ce))
- return PTR_ERR(ce);
+ ret = pin_context(i915->kernel_context, engine,
+ >kernel_context);
+ if (ret)
+ return ret;
/*
* Similarly the preempt context must always be available so that
-* we can interrupt the engine at any time.
+* we can interrupt the engine at any time. However, as preemption
+* is optional, we allow it to fail.
*/
- if (i915->preempt_context) {
- ce = intel_context_pin(i915->preempt_context, engine);
- if (IS_ERR(ce)) {
- ret = PTR_ERR(ce);
- goto err_unpin_kernel;
- }
- }
+ if (i915->preempt_context)
+ pin_context(i915->preempt_context, engine,
+ >preempt_context);
You lost the failure path here. I suspect deliberately? But I am not
convinced we want to silently lose preemption when keeping the failure
path is so easy.
ret = measure_breadcrumb_dw(engine);
if (ret < 0)
- goto err_unpin_preempt;
+ goto err_unpin;
engine->emit_fini_breadcrumb_dw = ret;
- return 0;
+ engine->set_default_submission(engine);
-err_unpin_preempt:
- if (i915->preempt_context)
- __intel_context_unpin(i915->preempt_context, engine);
+ return 0;
-err_unpin_kernel:
- __intel_context_unpin(i915->kernel_context, engine);
+err_unpin:
+ if (engine->preempt_context)
+ intel_context_unpin(engine->preempt_context);
+ intel_context_unpin(engine->kernel_context);
return ret;
}
@@ -765,8 +768,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
*/
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
{
- struct drm_i915_private *i915 = engine->i915;
-
cleanup_status_page(engine);
intel_engine_fini_breadcrumbs(engine);
@@ -776,9 +777,9 @@ void intel_engine_cleanup_common(struct intel_engine_cs
*engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- if (i915->preempt_context)
- __intel_context_unpin(i915->preempt_context, engine);
-
[Intel-gfx] [PATCH 2/3] drm/i915/gtt: Mark ALL_ENGINES as dirty on ppGTT modification
Small simplification to set all bits in the dirty mask rather than
lookup the exact mask of populated engines. The bits for the engines
that do not exist are unused and so can safely set and then ignored.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f447c6564418..dac08d9c3fab 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -792,14 +792,15 @@ static void gen8_initialize_pml4(struct
i915_address_space *vm,
memset_p((void **)pml4->pdps, vm->scratch_pdp, GEN8_PML4ES_PER_PML4);
}
-/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
+/*
+ * PDE TLBs are a pain to invalidate on GEN8+. When we modify
* the page table structures, we mark them dirty so that
* context switching/execlist queuing code takes extra steps
* to ensure that tlbs are flushed.
*/
static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
{
- ppgtt->pd_dirty_engines = INTEL_INFO(ppgtt->vm.i915)->engine_mask;
+ ppgtt->pd_dirty_engines = ALL_ENGINES;
}
/* Removes entries from a single page table, releasing it if it's empty.
--
2.20.1
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/3] drm/i915: Move find_active_request() to the engine
To find the active request, we need only search along the individual
engine for the right request. This does not require touching any global
GEM state, so move it into the engine compartment.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 3 --
drivers/gpu/drm/i915/i915_gem.c | 45 ---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 47 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++
5 files changed, 50 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08ead854ac2d..ff039750069d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2996,9 +2996,6 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
-struct i915_request *
-i915_gem_find_active_request(struct intel_engine_cs *engine);
-
static inline bool __i915_wedged(struct i915_gpu_error *error)
{
return unlikely(test_bit(I915_WEDGED, >flags));
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 69413f99ed04..c67369bd145b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2803,51 +2803,6 @@ i915_gem_object_pwrite_gtt(struct drm_i915_gem_object
*obj,
return 0;
}
-static bool match_ring(struct i915_request *rq)
-{
- struct drm_i915_private *dev_priv = rq->i915;
- u32 ring = I915_READ(RING_START(rq->engine->mmio_base));
-
- return ring == i915_ggtt_offset(rq->ring->vma);
-}
-
-struct i915_request *
-i915_gem_find_active_request(struct intel_engine_cs *engine)
-{
- struct i915_request *request, *active = NULL;
- unsigned long flags;
-
- /*
-* We are called by the error capture, reset and to dump engine
-* state at random points in time. In particular, note that neither is
-* crucially ordered with an interrupt. After a hang, the GPU is dead
-* and we assume that no more writes can happen (we waited long enough
-* for all writes that were in transaction to be flushed) - adding an
-* extra delay for a recent interrupt is pointless. Hence, we do
-* not need an engine->irq_seqno_barrier() before the seqno reads.
-* At all other times, we must assume the GPU is still running, but
-* we only care about the snapshot of this moment.
-*/
- spin_lock_irqsave(>timeline.lock, flags);
- list_for_each_entry(request, >timeline.requests, link) {
- if (i915_request_completed(request))
- continue;
-
- if (!i915_request_started(request))
- break;
-
- /* More than one preemptible request may match! */
- if (!match_ring(request))
- break;
-
- active = request;
- break;
- }
- spin_unlock_irqrestore(>timeline.lock, flags);
-
- return active;
-}
-
static void
i915_gem_retire_work_handler(struct work_struct *work)
{
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5f1cdbc9eb5d..3d8020888604 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1411,7 +1411,7 @@ static void gem_record_rings(struct i915_gpu_state *error)
error_record_engine_registers(error, engine, ee);
error_record_engine_execlists(engine, ee);
- request = i915_gem_find_active_request(engine);
+ request = intel_engine_find_active_request(engine);
if (request) {
struct i915_gem_context *ctx = request->gem_context;
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
b/drivers/gpu/drm/i915/intel_engine_cs.c
index 62a2cc64..555a4590fa23 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1545,7 +1545,7 @@ void intel_engine_dump(struct intel_engine_cs *engine,
if (>link != >timeline.requests)
print_request(m, rq, "\t\tlast ");
- rq = i915_gem_find_active_request(engine);
+ rq = intel_engine_find_active_request(engine);
if (rq) {
print_request(m, rq, "\t\tactive ");
@@ -1712,6 +1712,51 @@ void intel_disable_engine_stats(struct intel_engine_cs
*engine)
write_sequnlock_irqrestore(>stats.lock, flags);
}
+static bool match_ring(struct i915_request *rq)
+{
+ struct drm_i915_private *dev_priv = rq->i915;
+ u32 ring = I915_READ(RING_START(rq->engine->mmio_base));
+
+ return ring == i915_ggtt_offset(rq->ring->vma);
+}
+
+struct i915_request *
+intel_engine_find_active_request(struct intel_engine_cs *engine)
+{
+ struct i915_request *request,
[Intel-gfx] [PATCH 1/3] drm/i915: Store the BIT(engine->id) as the engine's mask
In the next patch, we are introducing a broad virtual engine to encompass
multiple physical engines, losing the 1:1 nature of BIT(engine->id). To
reflect the broader set of engines implied by the virtual instance, lets
store the full bitmask.
v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/)
v3: Tvrtko voted for moah churn so teach everyone to not mention ring
and use $class$instance throughout.
v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and
VCS[0-4] in later gen. We opt to keep the code consistent and use
0-index naming throughout.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 44 ++--
drivers/gpu/drm/i915/gvt/execlist.c | 17 +-
drivers/gpu/drm/i915/gvt/handlers.c | 26 +-
drivers/gpu/drm/i915/gvt/interrupt.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 228 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 21 +-
drivers/gpu/drm/i915/i915_cmd_parser.c| 12 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +-
drivers/gpu/drm/i915/i915_drv.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 22 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c| 14 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 2 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_irq.c | 65 ++---
drivers/gpu/drm/i915/i915_pci.c | 39 +--
drivers/gpu/drm/i915/i915_perf.c | 8 +-
drivers/gpu/drm/i915/i915_pmu.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 24 +-
drivers/gpu/drm/i915/i915_reset.c | 47 ++--
drivers/gpu/drm/i915/intel_device_info.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 6 +-
drivers/gpu/drm/i915/intel_engine_cs.c| 59 ++---
drivers/gpu/drm/i915/intel_guc_ads.c | 2 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 6 +-
drivers/gpu/drm/i915/intel_hangcheck.c| 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_mocs.c | 12 +-
drivers/gpu/drm/i915/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 35 +--
drivers/gpu/drm/i915/intel_ringbuffer.h | 27 +--
drivers/gpu/drm/i915/intel_workarounds.c | 4 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 +-
.../drm/i915/selftests/i915_gem_coherency.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 8 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 14 +-
drivers/gpu/drm/i915/selftests/intel_guc.c| 4 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 16 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c| 4 +-
.../drm/i915/selftests/intel_workarounds.c| 4 +-
drivers/gpu/drm/i915/selftests/mock_engine.c | 1 +
.../gpu/drm/i915/selftests/mock_gem_device.c | 6 +-
45 files changed, 422 insertions(+), 432 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 35b4ec3f7618..cf4a1ecf6853 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -391,12 +391,12 @@ struct cmd_info {
#define F_POST_HANDLE (1<<2)
u32 flag;
-#define R_RCS (1 << RCS)
-#define R_VCS1 (1 << VCS)
-#define R_VCS2 (1 << VCS2)
+#define R_RCS BIT(RCS0)
+#define R_VCS1 BIT(VCS0)
+#define R_VCS2 BIT(VCS1)
#define R_VCS (R_VCS1 | R_VCS2)
-#define R_BCS (1 << BCS)
-#define R_VECS (1 << VECS)
+#define R_BCS BIT(BCS0)
+#define R_VECS BIT(VECS0)
#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
/* rings that support this cmd: BLT/RCS/VCS/VECS */
u16 rings;
@@ -558,7 +558,7 @@ static const struct decode_info decode_info_vebox = {
};
static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
- [RCS] = {
+ [RCS0] = {
_info_mi,
NULL,
NULL,
@@ -569,7 +569,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VCS] = {
+ [VCS0] = {
_info_mi,
NULL,
NULL,
@@ -580,7 +580,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [BCS] = {
+ [BCS0] = {
_info_mi,
NULL,
_info_2d,
@@ -591,7 +591,7 @@ static const struct decode_info
*ring_decode_info[I915_NUM_ENGINES][8] = {
NULL,
},
- [VECS] = {
+ [VECS0] = {
_info_mi,
NULL,
NULL,
@@ -602,7 +602,7 @@ static const struct
