On 17:02-20201203, Jan Kiszka wrote:
> On 03.12.20 16:23, Andrea Bastoni wrote:
> > On 03/12/2020 14:44, Jan Kiszka wrote:
> >> On 03.12.20 13:48, Andrea Bastoni wrote:
> >>> On 03/12/2020 07:36, Jan Kiszka wrote:
> On 27.11.20 12:41, Andrea Bastoni wrote:
> > The SMMUv2 allows filtering
Branch: refs/heads/master
Home: https://github.com/siemens/jailhouse
Commit: 7a3fecfc146052dd154597a0b9e12545ea67afef
https://github.com/siemens/jailhouse/commit/7a3fecfc146052dd154597a0b9e12545ea67afef
Author: Andrea Bastoni
Date: 2020-11-08 (Sun, 08 Nov 2020)
Changed
Branch: refs/heads/next
Home: https://github.com/siemens/jailhouse
Commit: 7a3fecfc146052dd154597a0b9e12545ea67afef
https://github.com/siemens/jailhouse/commit/7a3fecfc146052dd154597a0b9e12545ea67afef
Author: Andrea Bastoni
Date: 2020-11-08 (Sun, 08 Nov 2020)
Changed
Branch: refs/heads/coverity_scan
Home: https://github.com/siemens/jailhouse
Commit: 7a3fecfc146052dd154597a0b9e12545ea67afef
https://github.com/siemens/jailhouse/commit/7a3fecfc146052dd154597a0b9e12545ea67afef
Author: Andrea Bastoni
Date: 2020-11-08 (Sun, 08 Nov 2020)
On 06:30-20201106, Liang Jingyan (M) wrote:
> Dear Jailhouse develop Team,
>
> We are Marelli(Guangzhou) Team, We are now developing TI J7 board, as we
> know, TI use the jailhouse hypervisor with their Cockpit Demo. Now Marelli
> team want to know more detail about the jailhouse hypervisor, we
On 17:57-20201030, 'Nikhil Devshatwar' via Jailhouse wrote:
> Current PVU iommu implementation ignores possible failures in the
> config_commit part. This would allow inconsistent configuration
> to run and may introduce unknown bugs.
>
> Solve this by making sure that the pvu_iomm
For an arm64 CPU, when an exception is taken, the PC of the
CPU is copied in the ELR_ELx. This is useful for debugging which
code path caused the exception.
Modify fill_trap_context to populate ELR_EL2 and dump it as part
of the dump_regs
Signed-off-by: Nikhil Devshatwar
---
Add a new BUG macro in utils which can be used in places
where you don't expect control to reach.
Whenever this happens, the code will intentionally crash
via a null pointer de reference.
Signed-off-by: Nikhil Devshatwar
---
hypervisor/include/jailhouse/utils.h | 2 ++
1 file changed, 2
Current PVU iommu implementation ignores possible failures in the
config_commit part. This would allow inconsistent configuration
to run and may introduce unknown bugs.
Solve this by making sure that the pvu_iommu_config_commit never
fails. Catch the errors early in the mapping phase. Use
On 17:09-20201029, Jan Kiszka wrote:
> On 29.10.20 16:27, Nikhil Devshatwar wrote:
> > On 08:14-20201029, Jan Kiszka wrote:
> >> On 28.10.20 15:14, 'Nikhil Devshatwar' via Jailhouse wrote:
> >>> Current PVU iommu implementation ignores possible failures in the
> &
On 08:14-20201029, Jan Kiszka wrote:
> On 28.10.20 15:14, 'Nikhil Devshatwar' via Jailhouse wrote:
> > Current PVU iommu implementation ignores possible failures in the
> > config_commit part. This would allow inconsistent configuration
> > to run and may introduce unknown
Current PVU iommu implementation ignores possible failures in the
config_commit part. This would allow inconsistent configuration
to run and may introduce unknown bugs.
Solve this by making sure that the pvu_iommu_config_commit never
fails. Catch the errors early in the mapping phase. Use
On 18:33-20201027, Jan Kiszka wrote:
> On 26.10.20 20:52, 'Nikhil Devshatwar' via Jailhouse wrote:
> > Current PVU iommu implementation ignores possible failures in the
> > config_commit part. This would allow inconsistent configuration
> > to run and may introduce unknown
Current PVU iommu implementation ignores possible failures in the
config_commit part. This would allow inconsistent configuration
to run and may introduce unknown bugs.
Solve this by making sure that the pvu_iommu_config_commit never
fails. Catch the errors early in the mapping phase. Use
Add inmate demo cell config for j7200-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo, uart-demo and ivshmem-demo.
Signed-off-by: Nikhil Devshatwar
---
configs/arm64/k3-j7200-evm-inmate-demo.c | 128 +++
1 file changed, 128
J7200 is a new SoC from Texas instruments which is targeted for
automotive networking and Gateway applications.
k3-j7200-evm is the board with this SoC, which is similar to the
k3-j721e-evm evaluation board.
Add support for root cell, baremetal and Linux inmate cell configs
to support this new
Add the linux demo cell config for k3-j7200-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
Add mem_regions and enable interrupts for for main_uart1,
main_sdhci0, gpio interrupt routers and virtual PCI
Signed-off-by: Nikhil Devshatwar
---
k3-j7200-evm is the new evaluation module from Texas Instruments
which has the j7200 SoC. It has a dual coreARM Cortex-A72
CPU cores, 4GiB of RAM, 2x Display ports, 6x UART ports,
5x ethernet ports, SD and eMMC interfaces for storage and
many other connectivity and accelerator devices.
J7200 TRM:
On 02/07/20 5:14 pm, Jan Kiszka wrote:
On 02.07.20 12:03, Peng Fan wrote:
Hi Jan
https://events19.linuxfoundation.org/wp-content/uploads/2018/07/Consolidate-Real-Time-and-HMI-with-ACRN-Hypervisor.pdf
Have you ever see this? Page 13, there is a compare between ACRN and
jailhouse on X86.
On 08/06/20 8:21 pm, Jan Kiszka wrote:
On 08.06.20 16:35, Nikhil Devshatwar wrote:
On 08/06/20 7:54 pm, Jan Kiszka wrote:
On 08.06.20 13:43, Nikhil Devshatwar wrote:
On 08/06/20 4:51 pm, Jan Kiszka wrote:
On 08.06.20 13:16, Jan Kiszka wrote:
On 08.06.20 12:42, nikhil...@ti.com wrote:
On 08/06/20 7:54 pm, Jan Kiszka wrote:
On 08.06.20 13:43, Nikhil Devshatwar wrote:
On 08/06/20 4:51 pm, Jan Kiszka wrote:
On 08.06.20 13:16, Jan Kiszka wrote:
On 08.06.20 12:42, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Add a new IVSHMEM PCIe virtual device for a 2 peer
IVSHMEM
On 08/06/20 4:39 pm, Jan Kiszka wrote:
On 08.06.20 12:42, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Fix errors reported by jailhouse-config-check
Fix overlap of baremetal demos with IVSHMEM.
Remove regions of memory which is already covered as part of
some other memory region.
On 08/06/20 4:43 pm, Jan Kiszka wrote:
On 08.06.20 12:42, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Number of peers available on a platform is different.
Do not hard code the target peer_id used for interrupt.
Parse this from the command line argument.
This de-couples the dependency
On 08/06/20 4:51 pm, Jan Kiszka wrote:
On 08.06.20 13:16, Jan Kiszka wrote:
On 08.06.20 12:42, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Add a new IVSHMEM PCIe virtual device for a 2 peer
IVSHMEM demo communication.
(0 = root cell, 1 = baremetal / linux-demo)
Also add the
On 02/06/20 8:14 pm, Jan Kiszka wrote:
On 27.05.20 14:23, nikhil.nd via Jailhouse wrote:
From: Nikhil Devshatwar
This series fixes few issues with the jailhouse cell
config files. It adds required memory regions for
fixing crashes due to accessing few devices.
Also, remove some obsolete
On 02/06/20 8:16 pm, Jan Kiszka wrote:
On 11.04.20 20:55, Jan Kiszka wrote:
On 11.04.20 20:37, Nikhil Devshatwar wrote:
Hi Jan,
On 11/04/20 11:28 pm, Jan Kiszka wrote:
On 11.04.20 19:25, 'Nikhil Devshatwar' via Jailhouse wrote:
Hi Jan,
On 11/04/20 4:31 pm, Jan Kiszka wrote:
From: Jan
On 27/05/20 8:45 pm, Jan Kiszka wrote:
On 27.05.20 16:55, Nikhil Devshatwar wrote:
On 27/05/20 8:18 pm, Jan Kiszka wrote:
On 27.05.20 16:16, Nikhil Devshatwar wrote:
On 27/05/20 7:38 pm, Jan Kiszka wrote:
On 27.05.20 15:53, Nikhil Devshatwar wrote:
On 27/05/20 7:18 pm, Jan Kiszka
On 27/05/20 8:18 pm, Jan Kiszka wrote:
On 27.05.20 16:16, Nikhil Devshatwar wrote:
On 27/05/20 7:38 pm, Jan Kiszka wrote:
On 27.05.20 15:53, Nikhil Devshatwar wrote:
On 27/05/20 7:18 pm, Jan Kiszka wrote:
On 27.05.20 15:28, Nikhil Devshatwar wrote:
On 27/05/20 6:41 pm, Jan Kiszka
On 27/05/20 7:38 pm, Jan Kiszka wrote:
On 27.05.20 15:53, Nikhil Devshatwar wrote:
On 27/05/20 7:18 pm, Jan Kiszka wrote:
On 27.05.20 15:28, Nikhil Devshatwar wrote:
On 27/05/20 6:41 pm, Jan Kiszka wrote:
On 27.05.20 14:32, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Number of
On 27/05/20 6:55 pm, Jan Kiszka wrote:
On 27.05.20 14:32, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Add a virtual PCI device with IVSHMEM type (id = 1)
Create IVSHMEM regions for 2 peer communication
Enable the vpci_irq for doorbell interrupt
This allows to run the ivshmem-demo
On 27/05/20 7:18 pm, Jan Kiszka wrote:
On 27.05.20 15:28, Nikhil Devshatwar wrote:
On 27/05/20 6:41 pm, Jan Kiszka wrote:
On 27.05.20 14:32, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Number of peers available on a platform is different.
Do not hard code the target peer_id used
On 27/05/20 7:01 pm, Jan Kiszka wrote:
On 27.05.20 14:23, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
PCI kernel framework requires that all the instances in the
device tree either specify the PCIe domain or none does.
Currently, Jailhouse dynamic overlay describes the PCI domain
On 27/05/20 6:58 pm, Jan Kiszka wrote:
On 27.05.20 14:32, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Current IVSHMEM regions are described to be used for ivshmem-net
driver. For standalone ivshmem communication, these regions need to
be added explicitly instead of using the macro.
On 27/05/20 6:41 pm, Jan Kiszka wrote:
On 27.05.20 14:32, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Number of peers available on a platform is different.
Do not hard code the target peer_id used for interrupt.
Parse this from the command line argument.
This de-couples the dependency
On 30/04/20 8:13 pm, Jan Kiszka wrote:
On 30.04.20 15:32, 'Nikhil Devshatwar' via Jailhouse wrote:
On 30/04/20 7:01 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
On 09/03/20 4:52 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
On 09/03/20 4:39 pm, Jan Kiszka wrote:
On 09.03.20 11:12
On 30/04/20 7:01 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
On 09/03/20 4:52 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
On 09/03/20 4:39 pm, Jan Kiszka wrote:
On 09.03.20 11:12, Nikhil Devshatwar wrote:
Hi Henning,
As part of the TI SDK, we were integrating the ivhsmem_uio
On 09/03/20 4:52 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
On 09/03/20 4:39 pm, Jan Kiszka wrote:
On 09.03.20 11:12, Nikhil Devshatwar wrote:
Hi Henning,
As part of the TI SDK, we were integrating the ivhsmem_uio as
external module
from https://github.com/henning-schild-work/ivshmem
Hi Jan,
On 11/04/20 11:28 pm, Jan Kiszka wrote:
On 11.04.20 19:25, 'Nikhil Devshatwar' via Jailhouse wrote:
Hi Jan,
On 11/04/20 4:31 pm, Jan Kiszka wrote:
From: Jan Kiszka
So far, any error returned by a function called by
pvu_iommu_config_commit was ignored, only reported to the console
On 11/04/20 10:55 pm, 'Nikhil Devshatwar' via Jailhouse wrote:
Hi Jan,
On 11/04/20 4:31 pm, Jan Kiszka wrote:
From: Jan Kiszka
So far, any error returned by a function called by
pvu_iommu_config_commit was ignored, only reported to the console. That
would have resulted in an inconsistent
Hi Jan,
On 11/04/20 4:31 pm, Jan Kiszka wrote:
From: Jan Kiszka
So far, any error returned by a function called by
pvu_iommu_config_commit was ignored, only reported to the console. That
would have resulted in an inconsistent configuration being run. Also,
pvu_tlb_alloc and pvu_tlb_chain
Hi,
On 27/03/20 6:43 pm, Peng Fan wrote:
Hi Angelo,
Subject: [RFC] Linux-less boot
Hi Jan, Peng, all,
We currently have a better understanding of Peng's work [1] and manage to
somewhat reproduce his results on another NXP board, the IMX8QM.
Good.
Since you showed interest in this, we
On 09/03/20 4:39 pm, Jan Kiszka wrote:
On 09.03.20 11:12, Nikhil Devshatwar wrote:
Hi Henning,
As part of the TI SDK, we were integrating the ivhsmem_uio as
external module
from https://github.com/henning-schild-work/ivshmem-guest-code
Since the ivshmem changes in the Jailhouse, that
Hi Henning,
As part of the TI SDK, we were integrating the ivhsmem_uio as external
module
from https://github.com/henning-schild-work/ivshmem-guest-code
Since the ivshmem changes in the Jailhouse, that driver no more works
(because of the vendor ID change)
Do you plan to host the updated
On 27/01/20 7:26 pm, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Implement regmap as a unit, Use reg_map_data as book keeping
data structure per cell.
Register a MMIO handler for each regmap region and handle the
mmio access based on the regmap described in the config.
Implement the
On 28/01/20 2:41 am, Jan Kiszka wrote:
On 27.01.20 20:41, Nikhil Devshatwar wrote:
On 27/01/20 10:03 pm, Jan Kiszka wrote:
On 27.01.20 17:13, Nikhil Devshatwar wrote:
On 27/01/20 9:30 pm, Ralf Ramsauer wrote:
On 27/01/2020 15:49, Jan Kiszka wrote:
On 27.01.20 14:56, nikhil.nd via
On 27/01/20 10:03 pm, Jan Kiszka wrote:
On 27.01.20 17:13, Nikhil Devshatwar wrote:
On 27/01/20 9:30 pm, Ralf Ramsauer wrote:
On 27/01/2020 15:49, Jan Kiszka wrote:
On 27.01.20 14:56, nikhil.nd via Jailhouse wrote:
From: Nikhil Devshatwar
This series adds support for partitioning
On 27/01/20 9:30 pm, Ralf Ramsauer wrote:
On 27/01/2020 15:49, Jan Kiszka wrote:
On 27.01.20 14:56, nikhil.nd via Jailhouse wrote:
From: Nikhil Devshatwar
This series adds support for partitioning registers across different
cells
in the Jailhouse. Jailhouse supports partitioning memory
On 27/01/20 7:26 pm, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
Signed-off-by: Nikhil Devshatwar
Ignore this patch, sent by mistake in the regmap series.
I will send this separately with proper commit message
Nikhil D
---
configs/arm64/k3-j721e-evm-linux-demo.c | 16
Hi Jan,
Can you let us know when the next version of Jailhouse is planned to be
released/tagged?
TI plans to migrate to a stable version as part of the LTS kernel migration.
Regards,
Nikhil D
--
You received this message because you are subscribed to the Google Groups
"Jailhouse" group.
To
On 13/01/20 7:07 pm, Jan Kiszka wrote:
From: Nikhil Devshatwar
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
* Integrate with the arm iommu support such that
On 13/01/20 6:08 pm, Jan Kiszka wrote:
On 13.01.20 11:46, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address
translation.
J721e has 3 instances of PVU and all the DMA traffic
ping
Nikhil D
On 08/01/20 4:48 pm, nikhil...@ti.com wrote:
From: Nikhil Devshatwar
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address translation.
J721e has 3 instances of PVU and all the DMA traffic can be routed via PVU
when
On 06/01/20 5:35 pm, Jan Kiszka wrote:
On 06.01.20 12:57, Nikhil Devshatwar wrote:
On 06/01/20 4:14 pm, Jan Kiszka wrote:
On 06.01.20 11:10, Nikhil Devshatwar wrote:
On 06/01/20 2:52 pm, Jan Kiszka wrote:
On 06.01.20 09:12, Nikhil Devshatwar wrote:
+{
+ /*
+ * dummy unmap for
On 06/01/20 4:14 pm, Jan Kiszka wrote:
On 06.01.20 11:10, Nikhil Devshatwar wrote:
On 06/01/20 2:52 pm, Jan Kiszka wrote:
On 06.01.20 09:12, Nikhil Devshatwar wrote:
+{
+ /*
+ * dummy unmap for now
+ * PVU does not support dynamic unmap
+ * Works well for static
On 06/01/20 2:52 pm, Jan Kiszka wrote:
On 06.01.20 09:12, Nikhil Devshatwar wrote:
+{
+ /*
+ * dummy unmap for now
+ * PVU does not support dynamic unmap
+ * Works well for static partitioning
Huh!? But this breaks cell create/destroy cycles, without any user
notice, no? And
and
send directly.
will check why the from: line is missing
On 30.12.19 14:24, 'Nikhil Devshatwar' via Jailhouse wrote:
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
*
Add stream_ids for peripherals which are behind IOMMU instances.
PVU and SMMU-V3 sets up memory mapping for all of these contexts
for correct 2nd stage translation.
Signed-off-by: Nikhil Devshatwar
---
configs/arm64/k3-j721e-evm-linux-demo.c | 7 +++
configs/arm64/k3-j721e-evm.c
Add support for Texas Instrument's Peripheral Virtualization Unit
* Define a new IOMMU type and extra fields in the platform_data
* Add new cofig option CONFIG_IOMMU_TI_PVU
* Integrate with the arm iommu support such that multiple types
of IOMMU can be supported.
Signed-off-by: Nikhil
This series adds support for TI PVU as an iommu unit.
PVU is a 2nd stage only IOMMU which provides realtime address translation.
J721e has 3 instances of PVU and all the DMA traffic can be routed via PVU
when running inside a virtual machine.
Nikhil Devshatwar (4):
arm64: ti-pvu: Add support
J721e device has 3 instance of PVU which can be used as IOMMU.
Each PVU has a config region and a TLB region where the memory
mapping information is stored.
Describe these as part of the root cell's platform_data.
Signed-off-by: Nikhil Devshatwar
---
configs/arm64/k3-j721e-evm.c | 24
arm_smmuv3_cell_init and arm_smmuv3_cell_exit calls iterate over all
iommu_units to process the ones with SMMUV3 type.
After the loop, it unconditionally issues commands with first element
of smmu. This causes Unhandled HYP exception while enabling jailhouse.
Fix this by issuing the sync
For K3-J721e devices, gpio virtualization is achieved by
replicating copies of GPIO controller.
Each cell gets a dedicated GPIO controller. However, there is
additional field in the pinctrl to select the GPIO group.
Add the mem_regions for main_gpio2 and main_gpio3
Program gpio_group in the
On 24/12/19 9:42 am, Lokesh Vutla wrote:
On 23/12/19 8:43 PM, Nikhil Devshatwar wrote:
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the 2 Linux cells.
This will be updated as support for more devices get added.
Signed-off-by:
This series adds support for the Texas Instrument's j721e-evm board.
The J721E SoC belongs to the K3 Multicore SoC architecture platform
for automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
Verified with the 5.5
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet ports, SD and eMMC interfaces for
storage and many other connectivity, graphics, multimedia
UART is disabled by default on TI platforms and must be enabled
via the MDR register.
Add a new flag in the jailhouse_console and apply the quirk
as part of uart_init for 8250 driver when this flag is present.
Signed-off-by: Lokesh Vutla
Signed-off-by: Nikhil Devshatwar
---
Notes:
Changes
Add GIC and UART demo cell configs for j721e-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo and uart-demo.
Signed-off-by: Lokesh Vutla
Signed-off-by: Nikhil Devshatwar
---
Notes:
Changes from v1:
* Remove pio_bitmap_size references
On 27/11/19 4:34 PM, Jan Kiszka wrote:
On 27.11.19 11:44, Nikhil Devshatwar wrote:
On 27/11/19 3:30 PM, Jan Kiszka wrote:
On 27.11.19 10:53, Nikhil Devshatwar wrote:
On 19/11/19 12:14 AM, Jan Kiszka wrote:
Hi Nikhil,
On 18.11.19 14:26, Devshatwar, Nikhil wrote:
HI Jan,
Current
On 27/11/19 3:30 PM, Jan Kiszka wrote:
On 27.11.19 10:53, Nikhil Devshatwar wrote:
On 19/11/19 12:14 AM, Jan Kiszka wrote:
Hi Nikhil,
On 18.11.19 14:26, Devshatwar, Nikhil wrote:
HI Jan,
Current Jailhouse implementation has support for partitioning the
SPI interrupts on a GICv3.
On 19/11/19 12:14 AM, Jan Kiszka wrote:
Hi Nikhil,
On 18.11.19 14:26, Devshatwar, Nikhil wrote:
HI Jan,
Current Jailhouse implementation has support for partitioning the SPI
interrupts on a GICv3.
However, the LPI interrupts managed by the GIC ITS cannot be
partitioned.
Is this
On 04/09/19 7:11 PM, Lokesh Vutla wrote:
On 04/09/19 5:52 PM, Nikhil Devshatwar wrote:
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the 2
On 04/09/19 7:06 PM, Lokesh Vutla wrote:
On 04/09/19 5:52 PM, Nikhil Devshatwar wrote:
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet
This series adds support for the Texas Instrument's j721e-evm board.
The J721E SoC belongs to the K3 Multicore SoC architecture platform
for automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
Nikhil Devshatwar (4):
Add GIC and UART demo cell configs for j721e-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo and uart-demo.
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
Changes from v1:
* Remove pio_bitmap_size references
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the 2 Linux cells.
This will be updated as support for more devices get added.
Signed-off-by:
UART is disabled by default on TI platforms and must be enabled
via the MDR register.
Add a new flag in the jailhouse_console and apply the quirk
as part of uart_init for 8250 driver when this flag is present.
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
Changes from v2:
*
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet ports, SD and eMMC interfaces for
storage and many other connectivity, graphics, multimedia
On 19/08/19 10:20 PM, Lokesh Vutla wrote:
On 19/08/19 7:56 PM, Nikhil Devshatwar wrote:
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet
On 19/08/19 10:43 PM, Jan Kiszka wrote:
On 19.08.19 19:10, Lokesh Vutla wrote:
On 19/08/19 10:29 PM, Jan Kiszka wrote:
On 19.08.19 18:50, Lokesh Vutla wrote:
On 19/08/19 7:56 PM, Nikhil Devshatwar wrote:
Add the linux demo cell config for j721e-evm board.
Also add the required device
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the 2 Linux cells.
This will be updated as support for more devices get added.
Signed-off-by:
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet ports, SD and eMMC interfaces for
storage and many other connectivity, graphics, multimedia
Add GIC and UART demo cell configs for j721e-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo and uart-demo.
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
Changes from v1:
* Remove pio_bitmap_size references
UART is disabled by default on TI platforms and must be enabled
via the MDR register.
Add a new flag in the jailhouse_console and apply the quirk
as part of uart_init for 8250 driver when this flag is present.
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
Changes from v1:
*
This series adds support for the Texas Instrument's j721e-evm board.
The J721E SoC belongs to the K3 Multicore SoC architecture platform
for automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
Nikhil Devshatwar (4):
On 12/06/19 9:30 PM, Ralf Ramsauer wrote:
On 6/12/19 5:48 PM, Nikhil Devshatwar wrote:
On 24/05/19 4:15 AM, Ralf Ramsauer wrote:
Hi Lokesh,
On 5/23/19 11:16 PM, 'Nikhil Devshatwar' via Jailhouse wrote:
UART is disabled by default on TI platforms and must be enabled
on some platforms via
On 24/05/19 4:15 AM, Ralf Ramsauer wrote:
Hi Lokesh,
On 5/23/19 11:16 PM, 'Nikhil Devshatwar' via Jailhouse wrote:
UART is disabled by default on TI platforms and must be enabled
on some platforms via the MDR register.
Do this as part of uart_init for 8250 driver
Signed-off-by: Nikhil
On 24/05/19 7:37 AM, Jan Kiszka wrote:
On 23.05.19 23:16, 'Nikhil Devshatwar' via Jailhouse wrote:
From: Lokesh Vutla
Before building jailhouse for TI's K3 platforms,
ci/jailhouse-config-k3.h needs to be copied to
include/jailhouse/config.h
Signed-off-by: Lokesh Vutla
---
ci/jailhouse
k3-j721e-evm is the new evaluation module from Texas Instruments
which has the j721e SoC. (aka DRA829) It has a dual core
ARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports,
6x UART ports, 5x ethernet ports, SD and eMMC interfaces for
storage and many other connectivity, graphics, multimedia
From: Lokesh Vutla
Before building jailhouse for TI's K3 platforms,
ci/jailhouse-config-k3.h needs to be copied to
include/jailhouse/config.h
Signed-off-by: Lokesh Vutla
---
ci/jailhouse-config-k3.h | 2 ++
1 file changed, 2 insertions(+)
create mode 100644 ci/jailhouse-config-k3.h
diff
Add GIC and UART demo cell configs for j721e-evm board.
This can be used to run the standard jaiilhouse baremetal
inmate demos like gic-demo and uart-demo.
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
configs/arm64/k3-j721e-evm-gic-demo.c | 72 ++
UART is disabled by default on TI platforms and must be enabled
on some platforms via the MDR register.
Do this as part of uart_init for 8250 driver
Signed-off-by: Nikhil Devshatwar
Signed-off-by: Lokesh Vutla
---
inmates/lib/uart-8250.c | 4
1 file changed, 4 insertions(+)
diff --git
This series adds support for the Texas Instrument's j721e-evm board.
The J721E SoC belongs to the K3 Multicore SoC architecture platform
for automotive applications such as infotainment, cluster, premium
Audio, Gateway, industrial and a range of broad market applications.
Lokesh Vutla (1):
ci,
Add the linux demo cell config for j721e-evm board.
Also add the required device tree for booting Linux kernel
in the inmate cell.
This cell config acts as a reference for partitioning
devices across the 2 Linux cells.
This will be updated as support for more devices get added.
Signed-off-by:
On Monday 02 April 2018 11:16 AM, Qiu Shui wrote:
On Monday, April 2, 2018 at 11:12:12 AM UTC+8, Qiu Shui wrote:
On Thursday, March 29, 2018 at 1:09:46 PM UTC+8, Jan Kiszka wrote:
On 2018-03-29 06:36, Qiu Shui wrote:
I build the armbian with these two patches to the kernel:
[1]
On Monday 05 March 2018 12:21 PM, Jan Kiszka wrote:
From: Jan Kiszka
Jailhouse only supports hypercalls with the immediate code 0x4a48. Avoid
interpreting calls with other codes as ours.
Signed-off-by: Jan Kiszka
---
Hi Jan/Ralf,
Do you have any opinion on the following?
Regards,
Nikhil D
On Wednesday 13 December 2017 11:52 AM, Devshatwar, Nikhil wrote:
Hello all,
I am profiling the impact of reloading a cell on the root cell.
My observation is that the hypercall for cell_load and cell_start ends
up
On Monday 25 September 2017 05:23 PM, Ralf Ramsauer wrote:
ARM inmates make use of hypervisor's sysregs accessors and helpers. In
order to entirely decouple the hypervisor code from inmate code, let's
duplicate accessors.
And that's it, we just need to define accessors, compiler makes the
rest.
On Sunday 23 July 2017 03:56 PM, Nikhil Devshatwar wrote:
On Sunday 23 July 2017 03:48 PM, Jan Kiszka wrote:
Hi Nikhil,
On 2017-07-23 12:15, GitHub wrote:
Branch: refs/heads/wip/gicv3-rework
FYI, this is my current staging branch for the ESPRESSObin. Works in
UP-mode so far. Will explode
On Sunday 23 July 2017 03:48 PM, Jan Kiszka wrote:
Hi Nikhil,
On 2017-07-23 12:15, GitHub wrote:
Branch: refs/heads/wip/gicv3-rework
FYI, this is my current staging branch for the ESPRESSObin. Works in
UP-mode so far. Will explode in a minute in Travis CI when building
GICv3 on 32-bit
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