Re: Share memory among cells on arm64

Hi Giovani! I'm facing the same challenge with a ZCU104. May you please share your test code? Thank you! MS Il giorno lunedì 24 dicembre 2018 alle 07:02:06 UTC+1 JJZhu ha scritto: > 在 2018年4月10日星期二 UTC+8下午10:39:18，Giovani Gracioli写道： > > Updating: > > > > I added > > > > .num_msix_vectors =

Re: Share memory among cells on arm64

在 2018年4月10日星期二 UTC+8下午10:39:18，Giovani Gracioli写道： > Updating: > > I added > > .num_msix_vectors = 1, > .iommu = 1, > > to the root cell .pci_devices config, wrote a simple linux program to write > to the shared memory (0x80050) and a simple inmate cell code to read from > the shared

Re: Share memory among cells on arm64

On 2018-08-09 21:58, Giovani Gracioli wrote: Not sure the situation of this, but I created a patch that provides PCI support for arm (Jailhouse version 0.9.1). It is attached. It is based on the Evidence's code. I tested it on the ultrascale+ (arm64). It may be useful for some people. To

Re: Share memory among cells on arm64

Not sure the situation of this, but I created a patch that provides PCI support for arm (Jailhouse version 0.9.1). It is attached. It is based on the Evidence's code. I tested it on the ultrascale+ (arm64). It may be useful for some people. Best Giovani > On 2018-04-18 21:52, Giovani Gracioli

Re: Share memory among cells on arm64

On 2018-04-18 21:52, Giovani Gracioli wrote: > Thanks Jan. > > It is working now. the irqchip in the non-root cell was missing. Good to hear! > > I added the following to the non-root cell: > > struct jailhouse_irqchip irqchips[1]; > ... > .vpci_irq_base = 140-32 > ... > > .irqchips = { >

Re: Share memory among cells on arm64

I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the non-root cell config. After adding it to the non-root cell config and created the cell, I got the following: irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3 irqchip_set_pending()->

Re: Share memory among cells on arm64

I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the non-root cell config. After adding it to the non-root cell config and created the cell, I got the following: irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3 irqchip_set_pending()->

Re: Share memory among cells on arm64

I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the non-root cell config. When I added it to the cell config and created the cell, I got the following: jailhouse cell create zynqmp-zcu102-gic-demo-i irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3

Re: Share memory among cells on arm64

Thanks Jan. So what I should do is to have a different IRQ for the root and non-root cells? The root cell config has the following: ... .vpci_irq_base = 136-32 ... .irqchips = { /* GIC */ { .address = 0xf901, .pin_base = 32,

Re: Share memory among cells on arm64

On 2018-04-17 15:17, Giovani Gracioli wrote: > It is not completely the same configurations, one is the root-cell and > another one is a bare-metal cell based on the gic-demo. I attached both here. > > I believe the Linux program is correct, because I can see the number of > interrupts

Re: Share memory among cells on arm64

It is not completely the same configurations, one is the root-cell and another one is a bare-metal cell based on the gic-demo. I attached both here. I believe the Linux program is correct, because I can see the number of interrupts increasing by outputting /proc/interrupts. It basically maps

Re: Share memory among cells on arm64

On 2018-04-16 23:53, Giovani Gracioli wrote: > I instrumented the code with several prints. > > When I start the bare-metal cell, I can see that an interrupt from CPU 3 is > issued and handled by CPU 0: > > Started cell "gic-demo-ivshmem" > ivshmem_register_mmio() mmio->address = 8,

Re: Share memory among cells on arm64

I instrumented the code with several prints. When I start the bare-metal cell, I can see that an interrupt from CPU 3 is issued and handled by CPU 0: Started cell "gic-demo-ivshmem" ivshmem_register_mmio() mmio->address = 8, mmio->is_write = 0, current cpu = 3 ivshmem_register_mmio()

Re: Share memory among cells on arm64

On 2018-04-16 20:35, Giovani Gracioli wrote: > I added .vpci_irq_base = 136-32 to the bare-metal cell config (.cell) and now > I can see the interrupts generated by uio_send through the output of cat > /proc/interrupts: > >CPU0 CPU1 CPU2 > 38: 38 0

Re: Share memory among cells on arm64

I added .vpci_irq_base = 136-32 to the bare-metal cell config (.cell) and now I can see the interrupts generated by uio_send through the output of cat /proc/interrupts: CPU0 CPU1 CPU2 38: 38 0 0 GICv2 136 Edge uio_ivshmem, uio_ivshmem

Re: Share memory among cells on arm64

On 2018-04-16 17:58, Giovani Gracioli wrote: > Hello guys, > > Now I am trying to send an interrupt from the root-cell (Linux) to the > bare-metal cell. The other way around, from the bare-metal to Linux, is > working. Whenever I start the bare-metal cell, I can see that an interrupt > has

Re: Share memory among cells on arm64

Hello guys, Now I am trying to send an interrupt from the root-cell (Linux) to the bare-metal cell. The other way around, from the bare-metal to Linux, is working. Whenever I start the bare-metal cell, I can see that an interrupt has arrived by checking the /proc/interrupts (number 38 is the

Re: Share memory among cells on arm64

I found the error. It was missing a config parameter in the non-root cell: .num_pci_devices = 2 (in the .cell struct) After inserting this, I got the correct output: Shared memory connection established: "gic-demo-ivshmem" <--> "ZynqMP-ZCU102" Thanks for the help. > Yes, this is strange and

Re: Share memory among cells on arm64

Yes, this is strange and it is not happening. I added some prints in the pci_cell_init function (hypervisor/pci.c) and ivhsmem_init function (hypervisor/arm-common/ivhsmem.c). When I enable the root cell, I got the following: pci_cell_init - cell ZynqMP-ZCU102, id = 0, num_pci_devices 2

Re: Share memory among cells on arm64

Hi, at a first look the configuration looks ok for me. Il giorno giovedì 12 aprile 2018 19:49:09 UTC+2, Giovani Gracioli ha scritto: > Hello, > > Thank you for the answers. > > My comments are below. > > 1) The root config is defined as follows (copied only the relevant parts): > >

Re: Share memory among cells on arm64

Hi I found out that the ivhsmem regions are not being correctly handled by the ivshmem_init. I added some prints in the ibhsmem_init function, comparing dev_info (from the *device argument) and iv (from the ivhsmem_list). The print was placed in the for loop that iterates over the

Re: Share memory among cells on arm64

Hello, Thank you for the answers. My comments are below. 1) The root config is defined as follows (copied only the relevant parts): .platform_info = { .pci_mmconfig_base = 0xfc00, .pci_mmconfig_end_bus = 0,

Re: Share memory among cells on arm64

On 2018-04-12 08:51, Claudio Scordino wrote: > BTW, we plan to have a version of the PCI stuff rebased upstream in a > couple of weeks. > We'll post it on the ML once ready. Great! Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You

Re: Share memory among cells on arm64

Il giorno giovedì 12 aprile 2018 08:51:39 UTC+2, Claudio Scordino ha scritto: > Hi Giovani, > > > > > 2018-04-12 8:01 GMT+02:00 Jan Kiszka : > On 2018-04-11 19:40, Giovani Gracioli wrote: > > > Here is the output of the unhandled data read: > > > > > > Unhandled data

Re: Share memory among cells on arm64

Hi Giovani, 2018-04-12 8:01 GMT+02:00 Jan Kiszka : > On 2018-04-11 19:40, Giovani Gracioli wrote: > > Here is the output of the unhandled data read: > > > > Unhandled data read at 0xfc10(2) > > > > FATAL: unhandled trap (exception class 0x24) > > Cell state before

Re: Share memory among cells on arm64

On 2018-04-11 19:40, Giovani Gracioli wrote: > Here is the output of the unhandled data read: > > Unhandled data read at 0xfc10(2) > > FATAL: unhandled trap (exception class 0x24) > Cell state before exception: > pc: 1828 lr: 15f0 spsr: 6005 EL1 > sp:

Re: Share memory among cells on arm64

Here is the output of the unhandled data read: Unhandled data read at 0xfc10(2) FATAL: unhandled trap (exception class 0x24) Cell state before exception: pc: 1828 lr: 15f0 spsr: 6005 EL1 sp: 3f30 esr: 24 1 146 x0: fc10 x1:

Re: Share memory among cells on arm64

Hi Jan, Thanks for the reply. I am using the uio driver and when I load it, the pci devices become enabled. I suppose this part is ok: lspci -v after the driver is loaded: 00:00.0 Unassigned class [ff00]: Red Hat, Inc Inter-VM shared memory Subsystem: Red Hat, Inc Inter-VM shared

Re: Share memory among cells on arm64

On 2018-04-10 16:39, Giovani Gracioli wrote: > Updating: > > I added > > .num_msix_vectors = 1, > .iommu = 1, > > to the root cell .pci_devices config, wrote a simple linux program to write > to the shared memory (0x80050) and a simple inmate cell code to read from > the shared memory.

Re: Share memory among cells on arm64

Updating: I added .num_msix_vectors = 1, .iommu = 1, to the root cell .pci_devices config, wrote a simple linux program to write to the shared memory (0x80050) and a simple inmate cell code to read from the shared memory. It was able to read the values that were written. The next step

Re: Share memory among cells on arm64

Thanks for the answers. So, I have changed the config. In the root cell I have the following now: /* IVSHMEM shared memory region for 00:00.0 */ { .phys_start = 0x80040, .virt_start = 0x80040, .size = 0x10,

Re: Share memory among cells on arm64

Hi, what you see there are the registers of the ivshmem device, not the payload memory region. You will have to map the paddr you have in your cell-config. That paddr can be found in the config space as well, is just not a regular PCI BAR. I would suggest to write a uio driver and base it on

Re: Share memory among cells on arm64

On 2018-04-03 19:39, Giovani Gracioli wrote: > Hello, > > I would like to share buffers among cells on arm64 (Xilinx ultrascale+). The > documentation suggests the use of the ivshmem. > > In order to use ivshmem, I changed the root cell config as follows (it is > based on the zynqmp-zcu102.c

Re: Share memory among cells on arm64

Just another info, after enabling the root cell, I can see the virtual pci devices with lspci -v: 00:00.0 Unassigned class [ff01]: Red Hat, Inc Inter-VM shared memory Subsystem: Red Hat, Inc Inter-VM shared memory Flags: fast devsel Memory at fc10 (64-bit,

Share memory among cells on arm64

Hello, I would like to share buffers among cells on arm64 (Xilinx ultrascale+). The documentation suggests the use of the ivshmem. In order to use ivshmem, I changed the root cell config as follows (it is based on the zynqmp-zcu102.c original file): - In the .mem_regions: /* IVSHMEM shared