My 2c
"As Designed" should be the only answer. Bug is subjective. If the
user thinks the designed behaviour is
broken then they will always think of it as a bug. Invalid is worse,
because yes it tells the user they are an idiot.
Even if the program is working "As Designed" it does not
Hello Ian,
I can see your point, and it has merit. But its a design choice. As is
the design choice to lay out the schematic by function. For complex
MCU's (and lets face it, these days all MCU's are complex with regard to
functionality). I think that really they should just be defined as
Hello Ajith,
I admit i skimmed your proposal, but i think it looks like it has merit,
and that work can be done to improve symbols and pin mapping.
I always struggle with multi use pins like on MCUs. Its tedious to keep
drawing boxes with pins, just to support a layout of pins that suits
Presumably the hotkey file is textual. I would prefer Full also, but a
way to have both the benefits of both Sparse and FULL files is to list
everything, but comment out the entries which are still the default. So
the file shows exactly whats been changed, AND what all the
possibilities are.
Hi Simon,
Thast was it. GLXInfo crashed also. I rebooted and it all came good.
Not sure what the problem was with OpenGL.
Thanks for the help.
Steven
On 31/10/18 9:11 pm, Simon Richter wrote:
Hi,
On 31.10.2018 14:42, Strontium wrote:
The error was 'BadValue (integer parameter out
to component, PCB calculator and Page layout editor all seem fine.
On 31/10/18 20:42, Strontium wrote:
I was on the js-reynaud legacy nightly ppa (Ubuntu 18.04), and things
were fine a few days ago. But i just tried to run kicad and it was
crashing.
So, i uninstalled everything from legacy nightly
I was on the js-reynaud legacy nightly ppa (Ubuntu 18.04), and things
were fine a few days ago. But i just tried to run kicad and it was
crashing.
So, i uninstalled everything from legacy nightly and installed the ppa
js-reynaud/kicad-5 but for some reason if i try and open a schematic OR
a
I honestly think each major revision of KiCad should be considered a NEW
program, installs to a new place has its configuration and libraries all
in a new location. Only Incremental updates 5.0 -> 5.1 should be
considered upgrades.
Kicad configuration isn't complex or onerous so if a user
So,
I tried to use the PCB Jumpers from the standard library, specifically a
NC jumper. Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm
These seem to be new with the V5 library, because i don't remember them
with V4.
And it causes DRC errors. Firstly it generates "Track near Pad"
Hello Everyone,
I like the patch, and hope it makes it in.
Clemens, I don't think anything that is being discussed is in any way
going to constrain b) or c). But I think there is a third group, not just
1. Big Manufacturers
2. Hobbyist/Student
but
3. Small Scale Professional
+1
On 19/05/18 01:27, Seth Hillbrand wrote:
I'll second Tom's suggestion here. Distros are free to package KiCad
how they like, but we can create an AppImage[1] with GTK2 and
wxpython that users can download from the website. This would
provide a way for all users to run KiCad even if
Wayne,
I think it is an acceptable solution for V5 because this shouldn't get
in the way of a V5 release.
For V6, would it be feasible to define 0.01/0.1% to be a special
value (like zero) which means "effectively zero" and then the pad gui
can be updated with this special knowledge
On 28/04/18 18:51, jp charras wrote:
Le 28/04/2018 à 10:08, Eeli Kaikkonen a écrit :
It still looks to me that the original problem wasn't understood, and I wasn't
able to make it
clear. A Solder Mask Defined footprint means that the solder mask opening is
smaller than the
underlying copper
Hi Wayne,
I have no personal problem with your patch, but from a standards point
of view I want to raise this.
As per:
https://standards.freedesktop.org/basedir-spec/basedir-spec-latest.html
|"$XDG_CONFIG_HOME| defines the base directory relative to which user
specific configuration files
icad but you can not
change the name of the kicad subdirectory itself.
Steven
Le 12/04/2018 à 15:29, Strontium a écrit :
kicad5
kicad6
etc etc works for me. I am not wedded to my suggestion, it was
illustrative only.
For backward compatibility, "kicad" would be for kicad4 because that
table configuration might help: $ kicad -c projectconfig.cfg)
Regards,
Clemens
On 2018-04-12 09:33, Strontium wrote:
After considering my patch, what about the following proposal:
Just change the hard coded string in common.cpp (at around line 243) from:
cfgpath.AppendDir( wxT( "kica
and a Nightly all on the same machine
and configurations won't conflict.
Anything more exotic can be deferred to V6 development.
Steven
On 08/04/18 13:33, Carsten Schoenert wrote:
Am 07.04.18 um 17:34 schrieb Strontium:
Attached is a patch for discussion only.
Its the minimum change I c
On a practical note, the bigger the profile of KiCad gets, the more
likely some a-hole tries to trademark kicad out from under the project
for their own perceived benefit (Or just simply to be an a-hole). It
happens.
So it's probably a good idea to get the trademark just to protect the
Hell Carsten,
On 08/04/18 13:33, Carsten Schoenert wrote:
Am 07.04.18 um 17:34 schrieb Strontium:
Attached is a patch for discussion only.
Its the minimum change I could come up with to implement a unique
version specific config directory.
Nick mentioned changing XDG_CONFIG_HOME
Attached is a patch for discussion only.
Its the minimum change I could come up with to implement a unique
version specific config directory.
Nick mentioned changing XDG_CONFIG_HOME, that will not work on Windows
or Mac.
And on Linux, etc it will change from "~/.config/kicad" to
Hi Wayne,
I agree with you about scope creep, however I do see issues for users.
From an end user perspective V5 is a big change. I noticed big changes
just from missing nightly updates for 2 months. There may be an
extended period of time when a user will want to run both versions, for
On 04/04/18 18:52, Jean-Samuel Reynaud wrote:
So my questions are:
- Is it usefull ?
Having both versions be able to be installed side by side is immensely
valuable for an end user, and the development of kicad, in my opinion.
The users can "USE" the stable version for their work. They can
On 07/03/18 18:25, Tomasz Wlostowski wrote:
On 07/03/18 06:34, Strontium wrote:
My second "show stopper" bug for me, using V5 RC2
I also reported this in the bug tracker, again sorry for the double up.
I was trying to layout a board, but Kicad is refusing to let me lay
tracks or via
My second "show stopper" bug for me, using V5 RC2
I also reported this in the bug tracker, again sorry for the double up.
I was trying to layout a board, but Kicad is refusing to let me lay
tracks or vias in close proximity to the board edge. Its highlighting
the edge, and ignoring any
Sorry for posting this, AND also posting a bug report, but i know you
guys are close to releasing a V5 and i have been testing RC2 from
nightly PPA and have hit two bugs which would be show stoppers for me,
and make me want to go back to V4.
First one is a problem with Zone refills using DRC.
My 2c, something like this would be useful for fanout of chips,
especially BGA. You could have a standard fan out, which included the
main chip, all its fan out vias, tracks and bypass capacitors. It would
then be imported as a module, the schematic represents everything in
that module. Its
+1 also
It allows a company to start with the libraries at some point and keep
them consistent (by forking) and they can easily cherry pick changes or
do wholesale merges with their changed libraries, as they desire. And
for a casual user who just uses things, "as is" it will just work.
On
why the Linux distributions should follow suit.
Steven
On 22/09/17 10:01, Adam Wolf wrote:
Strontium,
I assume you are talking about linux based on the word PPA, but mostly
for other people on the list, you can do this with the MacOS KiCad.
Adam
On Thu, Sep 21, 2017 at 8:59 PM, Strontium
report?
Your message is already drowning in the mailing list traffic, but a bug
report will stay in the tracker until it is resolved.
Regards,
Orson
On 09/13/2017 05:53 AM, Strontium wrote:
His second criticism is with the via tool.
What he did is lay two tracks on his board, one on either side
This is a question for the distribution maintainers,
Is it possible to change the distribution PPA's (etc) so that one can
install the nightly and the stable version of kicad, simultaneously?
When things like file format versions change then people have to make a
choice, do I run nightly and
On 13/09/17 13:24, Nick Østergaard wrote:
What version of kicad did he test?
Application: kicad
Version: no-vcs-found-8182369~60~ubuntu16.04.1, release build
Libraries:
wxWidgets 3.0.2
libcurl/7.47.0 OpenSSL/1.0.2g zlib/1.2.8 libidn/1.32 librtmp/2.3
Platform: Linux 4.4.0-93-generic
His third criticism is with net connectivity.
What he did was he has a component with 4 GND pads in a row. He ran a
track across them (in the middle) and finished it at the last pad. The
Track clearly crosses all pads, however the DRC shows them as
"unconnected" when they are really
His second criticism is with the via tool.
What he did is lay two tracks on his board, one on either side. (Both
had the same net)
He then pressed the via tool, and dropped vias into the intersections.
The vias created design violations because they are assigned No Net.
Doing DRC does not
Hi all,
Background: My father is a hardware engineer, he has been doing it since
the early 70s learning in the RAAF, laying boards using tape, so he has
a lot of experience. He is retired, but still likes to design boards,
and I have convinced him to give KiCAD a go. He has been using old
Hello Wayne and Greg,
Can I suggest just adopting PEP8 for Python code formatting. Its clean,
well documented, and there are plenty of linters to check conformance.
And if there is anything in PEP8 that is annoying for KiCad development
(cant imagine what) just specify an exclusion or
I agree with this decision as well but for different reasons.
The more I get into small scale self manufacturing, the more I am
persuaded by the argument that you want to keep as little BoM
information in the Kicad schematic fields as reasonably possible. It
becomes a maintenance nightmare,
Hi Oliver,
On 06/05/17 12:13, Oliver Walters wrote:
And it just so happens that in this schematic NO components have
been edited to include these default fields/values, so, they don't
show up in the component table.
I have a patch to fix this now - if a field is empty and a
TSHEET / VALUE) are preesnt to be edited in
the table...
On Fri, May 5, 2017 at 10:51 PM, Strontium <strnty...@gmail.com
<mailto:strnty...@gmail.com>> wrote:
Hi Oliver,
Just had a chance to check out your component table viewer, its
nice. Great work.
Is it on your roadmap to
Hi Oliver,
Just had a chance to check out your component table viewer, its nice.
Great work.
Is it on your roadmap to be able to view/edit a components custom fields?
Regards,
Steven
On 03/05/17 05:35, Oliver Walters wrote:
Wayne,
Thanks for merging!
I will address those points at some
I Agree,
Minimum clearance from an edge is not the same thing as minimum
clearance from a trace. Would like to see this also.
The idea to have the zone clearances optionally come from the Design
Rules is also good.
Steven
On 01/05/17 08:28, José Ignacio wrote:
While changing the format
just a BOM tool.
On Tue, Feb 14, 2017 at 9:00 PM, Strontium <strnty...@gmail.com
<mailto:strnty...@gmail.com>> wrote:
This looks really nice, this would be awesome if it allowed you to
edit the BOM as well, for example, your line 3, change 0.1uf to
1uf and C1, C7, C8, C9,
This looks really nice, this would be awesome if it allowed you to edit
the BOM as well, for example, your line 3, change 0.1uf to 1uf and C1,
C7, C8, C9, C10 and C16 all change their value in the schematic to
match. Obviously there are things you wouldnt be able to edit, such as
Reference
Can I make the suggestion, for CPU/MCU/FPGA type parts that have lots of
configurable pins, drawing an actual component is tedious and somewhat
pointless as its just a box (or multiple boxes, one for each subunit)
with pins.
Some CPU's have so many functional units and pins that fitting it
My 2c for what its worth,
The properties we are talking about are just KEY:Value pairs, and i
don't think its wise to change from that. Its simple and easily handles
most possibilities.
What I think would be useful however is a customisable "set" of standard
"keys", So when you go into the
Hello Heikki,
Can you explain the logic you are using to determine the net of the vias
during DRC reconnect? It looks like you are only considering the top
and bottom layer, but stitching vias may be stitching internal layers?
Steven
On 23/10/16 21:48, Heikki Pulkkinen wrote:
Hi Wayne
On 18/10/16 01:47, Wayne Stambaugh wrote:
I created a new entry in the version 5 road map[1] to address this
issue. Please take a look at it when you get a chance to make sure I
didn't miss anything.
Cheers,
Wayne
[1]:
On 13/10/16 22:21, Wayne Stambaugh wrote:
I'm going to keep this brief, please respond in kind. I'm going to
create a new entry in the version 5 road map over the weekend with the
pertinent requirements so this will be my last comments on this subject.
The horse is dead.
Noted.
Why the
On 11/10/16 23:35, Wayne Stambaugh wrote:
On 10/11/2016 12:18 AM, Strontium wrote:
On 11/10/16 09:27, Wayne Stambaugh wrote:
I've thought about this for a while and I'm going to try a different
approach. Please bear with me, this is going to be lengthy but in the
interest of resolving
On 11/10/16 09:27, Wayne Stambaugh wrote:
I've thought about this for a while and I'm going to try a different
approach. Please bear with me, this is going to be lengthy but in the
interest of resolving the via stitching issue properly, I think it needs
to be done. I'm going to expand on JP's
On 10/10/16 23:36, Wayne Stambaugh wrote:
On 10/10/2016 1:25 AM, Strontium wrote:
On 09/10/16 23:11, Wayne Stambaugh wrote:
On 10/8/2016 1:20 PM, Nox wrote:
There is nothing here that has not been discussed before. The reason
that freely assigning nets to vias has not been implemented
On 10/10/16 19:59, Tomasz Wlostowski wrote:
Hi all,
There's been another long thread on stitching vias/net propagation. Let
me add my 3 cents.
The whole subject is more complex, as Wayne and JP already mentioned
many times.
I disagree, I think the issue is portrayed to be far more difficult
Hello Torsten,
I can clearly understand why you went down this road.
The patch I proposed handles all kinds of vias, blind, buried and
through. And doesn’t require a special component. The problem I had
with the "special component" which I did try, possibly after reading one
of your posts,
On 10/10/16 19:43, Tomasz Wlostowski wrote:
On 10.10.2016 07:25, Strontium wrote:
On 09/10/16 23:11, Wayne Stambaugh wrote:
On 10/8/2016 1:20 PM, Nox wrote:
There is nothing here that has not been discussed before. The reason
that freely assigning nets to vias has not been implemented
On 09/10/16 23:11, Wayne Stambaugh wrote:
On 10/8/2016 1:20 PM, Nox wrote:
There is nothing here that has not been discussed before. The reason
that freely assigning nets to vias has not been implemented is that
every implementation is a compromise. If we allow random net naming of
vias, all
ing regular expressions.
They are really powerful but only a small number of users (typically
developers) will actually know how to use them effectively.
On 5/3/2016 7:13 PM, Strontium wrote:
My 2c.
One of the fantastically useful features of eeschema is components have
an "arbitrary"
My 2c.
One of the fantastically useful features of eeschema is components have
an "arbitrary" list of key:value pairs (fields) attached to them as
attributes.
Can I suggest that such a feature attached to objects on the PCB would
be even more powerful/useful.
It would mean that changes
As far as i know wxPython, which kicad requires for python scripting,
does not support py3k.
There is https://github.com/wxWidgets/Phoenix but i'm not sure how
compatible that is with wxPython, or if it is compatible with py2k.
Steven
On 11/01/16 16:46, Nick Østergaard wrote:
Ohh yeah, I
Hi Clemens,
I have been looking at your problem.
And I believe you are either running Arch, or there is possibly
something wrong with your python install.
PEP-0394 http://legacy.python.org/dev/peps/pep-0394/ says that the
"python" command should run the python2 interpreter installed on your
Hi Cirilo,
It can be purged it doesn’t do anything any more.
I wasn't sure what the procedure was to do that.
Steven
On 10/01/16 09:02, Cirilo Bernardo wrote:
In somewhat recent changes to pcbnew/pcbframe.cpp the file
scripting/python_console_frame.h has become orphaned. Can the
file be
I am building with this:
$ cmake ../kicad-source-mirror -DKICAD_SKIP_BOOST=ON
-DCMAKE_INSTALL_PREFIX=/opt/kicad-build
-DDEFAULT_INSTALL_PATH=/opt/kicad-build -DKICAD_SCRIPTING=ON
-DKICAD_SCRIPTING_MODULES=ON -DKICAD_SCRIPTING_WXPYTHON=ON
$ make all
$ make install
That installs pcbnew.py in :
Hi Piers,
On 20/12/15 00:24, Piers Titus van der Torren wrote:
Hi Wayne,
If I can add my thoughts, I think Steven has a fair point that
tracking zones in the DRC is non trivial, so a 'real' solution in that
direction is not around the corner, and will never be perfect either.
Yes, I think
your path changes didn't break anything. Any of you heavy Python
users have any thoughts on this patch since it impacts you the most?
On 12/17/2015 12:10 AM, Strontium wrote:
Hi Wayne,
Thanks for testing this on windows, I really appreciate it a lot.
I moved the offending comments from being
spaces before and after parenthesis )
that need to fixed.
On 12/16/2015 5:58 AM, Strontium wrote:
Hello List,
I believe I have cleaned up my patch and made the enhanced shell do
everything it should.
It has a tabbed interface, with simple text editing capabilities.
Its GUI can be used
dy well
for it and a free via is for manufacturing the same as having a
through hole pad. Just a start/stop layer needs to be added for
burried/blind vias.
Thanks,
Torsten
*Gesendet:* Mittwoch, 16. Dezember 2015 um 02:49 Uhr
*Von:* Strontium <strnty...@gmail.com>
*An:* kicad-developers@lists
Hello List,
I believe I have cleaned up my patch and made the enhanced shell do
everything it should.
It has a tabbed interface, with simple text editing capabilities.
Its GUI can be used to introspect the full internal state of pcbnew, as
exposed by the python interface.
The editor can
a
macro like in FreeCAD, choosing from a list?
https://bugs.launchpad.net/kicad/+bug/1526064
"Ability to assign shortcuts to run a specific script or adding
toolbar buttons would be great!"
thank you for your improvements
Maurice
On 15/12/2015 09.03, Strontium wrote:
I attach an enha
I attach an enhanced patch to the python shell.
This one is a bigger change than the previous patch. But it moves the
code to the point where the whole shell is contained as an external
python file, which makes it a lot easier to develop and enhance.
Explanation of the changes:
- I created
Hi Wayne, Everyone,
This is the process now. If you have a fill zone, and you start to lay
a track within it, KiCad will assign that track/via to the net of the
zone of the layer you are on. AND, as a board Designer, that's exactly
what you would expect. But then, following this design
s GND."
On 14/12/15 21:21, Tomasz Wlostowski wrote:
On 12.12.2015 02:41, Strontium wrote:
This change should not break or modify any current behaviour, EXCEPT to
retain the nets of tracks/vias which Kicad is otherwise incapable of
determining automatically.
Hi Steven,
Thanks for the patc
Attached is a patch for the enhanced python shell.
This is what it looks like for me: http://i.imgur.com/je6yv8g.png
The assertions I was getting occur in a debug build and appear to be
normal behaviour of wxpython, and not actual errors.
See:
On 13/12/15 01:20, Wayne Stambaugh wrote:
I just tried this. Nice! This is definitely nicer than the Python
shell we are using. I'm with Nick, where's the patch?
On 12/12/2015 10:00 AM
Attached is A ROUGH PATCH, but its not correct yet. I am posting it for
comments, and maybe someone can
will post it once I test it.
Strontium (Steven J)
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ur, EXCEPT to
retain the nets of tracks/vias which Kicad is otherwise incapable of
determining automatically.
Strontium (Steven J)
=== modified file 'pcbnew/connect.cpp'
--- pcbnew/connect.cpp 2015-06-26 13:41:56 +
+++ pcbnew/connect.cpp 2015-12-11 06:36:01 +
@@ -855,14 +855,32 @@
* segme
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