From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the ones mentioned in pl180
datasheet
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds write delay parameter required after each write to controller
registers on some of the SOCs like Qualcomm ones. The delay parameter will
provide information on how many clock cycle delay required after each write.
Signed
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK going to card bus is directly driven by the clock controller, so the
driver has to set the required rates depending on the state of the card. This
bit of support is very much similar to bypass mode but there is no such thing
called
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch adds new setup and makes it specific to Qcom hw designer.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some bits which control Command Path State Machine (CPSM) are new in Qcom
integration, so this patch adds support to those bits.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |4
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |2 +-
1 file changed, 1
Thanks Felipe,
On 21/04/14 23:08, Felipe Balbi wrote:
+ if (var-reg_write_delay host-mclk)
+ udelay(1 + ((var-reg_write_delay * USEC_PER_SEC)/host-mclk));
looks like this should be quirk flag instead of a write delay... No
strong feelings though, but it looks like the
Hi Christopher,
On 22/04/14 13:58, Christopher Covington wrote:
Hi Srini,
On 04/21/2014 05:43 PM, srinivas.kandaga...@linaro.org wrote:
This patches are tested in PIO mode on IFC8064 board with both eMMC and
external SD card. I would appreciate any feedback/suggestions on the overall
On 22/04/14 10:20, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
Move memory, regulators, clocks and irq allocation to
devm_* variants. Properly check for valid clk handles.
-module_platform_driver_probe(msm_otg_driver, msm_otg_probe);
On 22/04/14 10:20, Ivan T. Ivanov wrote:
@@ -79,8 +78,7 @@ static int msm_hsusb_init_vddcx(struct msm_otg *motg, int
init)
ret = regulator_set_voltage(motg-vddcx, 0,
USB_PHY_VDD_DIG_VOL_MAX);
if (ret)
-
Hi Ivan,
On 22/04/14 10:20, Ivan T. Ivanov wrote:
From: Ivan T. Ivanoviiva...@mm-sol.com
Allows MSM OTG controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanoviiva...@mm-sol.com
---
.../devicetree/bindings/usb/msm-hsusb.txt | 67 +
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts and offsets are different to the ones mentioned in pl180
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
include/linux/amba/bus.h |1 +
1 file changed, 1 insertion(+)
diff --git
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have passed.
This patch adds a 3 clock cycle delay required after writing
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some bits which control Command Path State Machine (CPSM) are new in Qcom
integration, so this patch adds support to those bits.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |4
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCICLK register layout is bit different to the standard pl180 register layout.
Qcom SDCC controller some setup in MCICLK register to get it going. So this
patch adds new setup and makes it specific to Qcom hw designer.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch moves some of the ST specific register extensions access under
condition, so that other SOCs like Qualcomm or ARM would not a side effect of
writing to those reserved/different purpose bits.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c |2 +-
1 file changed, 1
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit postion datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Thanks Bjorn for testing it on msm8960 SOC.
On 09/05/14 10:56, Bjorn Andersson wrote:
On Tue, Apr 29, 2014 at 1:18 AM, srinivas.kandaga...@linaro.org wrote:
[...]
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to SD card controller using generic pl180 mmci driver.
This patch also adds temporary fixed regulator to get it going till the actual
regulator is mainlined.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga
On 09/05/14 12:21, Kumar Gala wrote:
There are only 4 SDCs on APQ8064
You are right.. Will fix it in next version.
thanks,
srini
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From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds clocks necessary for SD card controller on apq8064 SOC.
Without this patch the clocks are visible to the sdcc driver.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/clk/qcom/gcc-msm8960.c | 8
Thanks Linus W.
On 13/05/14 08:17, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180
On 13/05/14 08:20, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed
Thanks Linus W for reviewing the patches.
On 13/05/14 08:29, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:20 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
On 13/05/14 09:08, Linus Walleij wrote:
/* Keep ST Micro busy mode if enabled */
- datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
+ if (host-hw_designer == AMBA_VENDOR_ST)
+ datactrl |= host-datactrl_reg MCI_ST_DPSM_BUSYMODE;
Do not hard-check the
Thanks Linus W,
On 13/05/14 09:28, Linus Walleij wrote:
code is conditioned on hw designer.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
(...)
+ if (host-hw_designer == AMBA_VENDOR_QCOM) {
+ host-cclk = host-mclk
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm amba vendor Id to the list. This ID is used in mmci
driver.
Signed-off
On 13/05/14 11:04, Ulf Hansson wrote:
On 29 April 2014 10:18, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Hi Russell,
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit
On 13/05/14 23:13, Stephen Boyd wrote:
On 05/13, Srinivas Kandagatla wrote:
Thanks Linus W,
On 13/05/14 08:16, Linus Walleij wrote:
On Tue, Apr 29, 2014 at 10:19 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds Qualcomm
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Reviewed-by: Linus Walleij linus.wall...@linaro.org
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Qcom SD card controller, cclk is mclk and mclk should be directly
controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control and cclk_is_mclk flags in variant structure
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to fbclk that is used to latch data and
cmd on some controllers like SD Card controller in Qcom SOC.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.c | 5 +
1 file
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with wrong ddrmode mask on non
ST
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Most of the Qcomm SD card controller registers must be updated to the MCLK
domain so subsequent writes to registers will be ignored until 3 clock cycles
have passed.
This patch adds a 3 clock cycle delay required after writing
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.h | 208
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Reviewed
Hi Kumar,
On 15/05/14 15:31, Kumar Gala wrote:
I’d rather have the driver have the select of ARM_AMBA and not the core
support. We clearly don’t need to build ARM_AMBA in to function.
Shouldn’t driver depend on it rather than selecting it?
Suggested approach will end up changing the way
Hi Andy,
On 15/05/14 18:32, Andy Gross wrote:
On Fri, May 02, 2014 at 01:08:27PM -0500, Andy Gross wrote:
On Fri, May 02, 2014 at 09:58:41PM +0530, Vinod Koul wrote:
On Thu, Apr 17, 2014 at 05:04:02PM -0500, Andy Gross wrote:
This patch adds APIs that allow for BAM hardware flags to be set
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Qualcomm APQ8064 SOCs, SD card controller has an additional glue
called DML (Data Mover Local/Lite) to do dma transfers between
Controller and DMA engine. This hardware needs to be setup before any
dma transfer is requested.
This patch
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds dma support in both sdcc1 and sdcc3 device node.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 26 ++
1 file changed, 26 insertions
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
DML hardware is a glue in between SD Card Controller and DMA engine,
this hardware needs to be setup before and during any dma transfers.
This patchset adds DML support to the mmci driver.
This patchset is a very early version of adding
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch fixes the range of iomemory for sdcc controller, it is now
set to 0x2000 so that the mmci driver could talk to dml hardware as well.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
arch/arm/boot/dts/qcom
Thanks Bjorn for testing this series.
On 19/05/14 23:08, Bjorn Andersson wrote:
On Mon, Apr 21, 2014 at 2:43 PM,srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatlasrinivas.kandaga...@linaro.org
[snip]
This patches are tested in PIO mode on IFC8064 board with both eMMC and
On 22/05/14 16:09, Andy Gross wrote:
On Thu, May 22, 2014 at 11:40:49AM +0530, Vinod Koul wrote:
snip
I have 3 different IRQs that can be asserted based on the bit I set in the
hardware descriptor. The normal IRQ is the INT bit. However, in some cases the
peripheral protocol requires the
On 22/05/14 16:32, Andy Gross wrote:
On Thu, May 22, 2014 at 04:27:05PM +0100, Srinivas Kandagatla wrote:
snip
The EOT is not used for every transaction. It is part of a handshaking
protocol with the attached peripheral, much like the NWD (notify when done). As
near as I can tell today
On 23/05/14 08:50, Ulf Hansson wrote:
On 23 May 2014 09:13, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Ulf,
I like to get this patches for v3.16, any chance of considering these
patches to v3.16 ?
I promise to have them properly reviewed early next week, sorry for
taking
Thanks Linus W.
On 23/05/14 10:09, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer
On 23/05/14 10:12, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:37 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds support to fbclk that is used to latch data and
cmd on some controllers like SD Card controller in Qcom
On 23/05/14 10:31, Linus Walleij wrote:
On Thu, May 15, 2014 at 11:38 AM, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register
Hi Linus W,
On 23/05/14 10:31, Linus Walleij wrote:
static int mmci_qcom_pio_read(struct mmci_host *host, char *buffer,
unsigned int remain)
{
u32 *ptr = (u32*) buffer;
unsigned int count = 0;
unsigned int words;
unsigned int fifo_size =
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Thankyou Linus W and everyone for reviewing RFC to v3 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.h | 208
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different datactrl register
layout.
Without this patch datactrl register is updated with wrong ddrmode mask on non
ST
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
MCIFIFOCNT register behaviour on Qcom chips is very different than the other
pl180 integrations. MCIFIFOCNT register contains the number of
words that are still waiting to be transferred through the FIFO. It keeps
decrementing once the host
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control and cclk_is_mclk flags
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Reviewed
Hi Ulf,
On 26/05/14 10:10, Ulf Hansson wrote:
Hi Srinivas,
+static struct variant_data variant_qcom = {
+ .fifosize = 16 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .datalength_bits= 24,
+
I am not sure I like this approach. For each and every writel
(including pio_writes) you will add a few cpu cycles, since you need
to check for mclk_delayed_writes no matter of variant.
How about, adding a new function pointer in the struct mmci_host, for
writel operations which you could
On 26/05/14 10:53, Ulf Hansson wrote:
On 23 May 2014 14:51, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds ddrmode mask to variant structure giving more flexibility
to the driver to support more SOCs which have different
On 26/05/14 15:34, Ulf Hansson wrote:
This is hot path.
As I suggested for the readl and writel wrapper functions, I think it
would be better to use a function pointer in the struct mmci host,
which you set up in the probe phase. That means the variant data don't
need to be checked each an
Hi Ulf,
Thanks for the comments.
On 26/05/14 14:05, Ulf Hansson wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also
Hi Ulf,
Thankyou for the comments.
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled
On 27/05/14 10:32, Ulf Hansson wrote:
On 27 May 2014 00:39, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
Hi Ulf,
Thankyou for the comments.
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
From: Srinivas Kandagatla
On 26/05/14 18:00, Srinivas Kandagatla wrote:
Hi Ulf,
On 26/05/14 10:10, Ulf Hansson wrote:
Hi Srinivas,
+static struct variant_data variant_qcom = {
+ .fifosize = 16 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE
On 27/05/14 15:07, Ulf Hansson wrote:
Hmm. Looking a bit deeper into this, we have some additional related
code to fixup. :-)
In -probe(), we do clk_set_rate(100MHz), if the mclk 100MHz. That's
due to the current variants don't support higher frequency than this.
It seems like the Qcom
Hi Linus W,
On 26/05/14 11:07, Ulf Hansson wrote:
unsigned intfifosize;
unsigned intfifohalfsize;
@@ -116,6 +118,7 @@ static struct variant_data variant_u300 = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
On 28/05/14 09:02, Linus Walleij wrote:
On Tue, May 27, 2014 at 12:39 AM, Srinivas Kandagatla
srinivas.kandaga...@linaro.org wrote:
On 26/05/14 15:21, Ulf Hansson wrote:
On 23 May 2014 14:52, srinivas.kandaga...@linaro.org wrote:
+ boolexplicit_mclk_control
On 28/05/14 09:08, Linus Walleij wrote:
On Fri, May 23, 2014 at 2:53 PM, srinivas.kandaga...@linaro.org wrote:
+ if (unlikely(bytes)) {
+ unsigned char buf[4];
(...)
Please think twice about this.
http://lwn.net/Articles/70473/
http://lwn.net/Articles/420019/
Hi Ulf,
On 26/05/14 22:38, Srinivas Kandagatla wrote:
2 files changed, 28 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 17e7f6a..6434f5b1 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -185,6 +185,10 @@ static struct variant_data
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Thankyou Linus W, Ulf H and everyone for reviewing RFC to v3 patches.
This patch series adds Qualcomm SD Card Controller support in pl180 mmci
driver. QCom SDCC is basically a pl180, but bit more customized, some of the
register layouts
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch replaces a constant used in calculating timeout with a proper
macro. This is make code more readable.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Reviewed-by: Linus Walleij linus.wall...@linaro.org
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl
register. Bit position datactrl[16:4] hold the true block size instead of power
of 2.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Reviewed
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On Controllers like Qcom SD card controller where cclk is mclk and mclk should
be directly controlled by the driver.
This patch adds support to control mclk directly in the driver, and also
adds explicit_mclk_control flag in variant
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
Some of the controller have maximum supported frequency, This patch adds
support in variant data structure to specify such restrictions. This
gives more flexibility in calculating the f_max before passing it to
mmc-core.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds edge support for data and command out to variant structure
giving more flexibility to the driver to support more SOCs which have
different clock register layout.
Without this patch other new SOCs like Qcom will have to add
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds specifics of clk and datactrl register on Qualcomm SD
Card controller. This patch also populates the Qcom variant data with
these new values specific to Qualcomm SD Card Controller.
Signed-off-by: Srinivas Kandagatla
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
On some SOCs like Qcom there are explicit bits in the command register
to specify if its a data transfer command or not. So this patch adds
support to such bits in variant data, giving more flexibility to the
driver.
Signed-off
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds 8bit bus enable to variant structure giving more flexibility
to the driver to support more SOCs which have different clock register layout.
Without this patch other new SOCs like Qcom will have to add more code
to special
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch adds a fake Qualcomm ID 0x00051180 to the amba_ids, as Qualcomm
SDCC controller is pl180, but amba id registers read 0x0's.
The plan is to remove SDCC driver totally and use mmci as the main SD
controller driver for Qualcomm SOCs
From: Srinivas Kandagatla srinivas.kandaga...@linaro.org
This patch converts the register bits in the header file to use BIT(()
macro, which looks much neater.
No functional changes done.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@linaro.org
---
drivers/mmc/host/mmci.h | 208
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