Re: [PATCH v4 6/7] DMA: sun6i: Add driver for the Allwinner A31 DMA controller
On Mon, Mar 10, 2014 at 06:57:00PM +0100, Arnd Bergmann wrote: On Monday 10 March 2014 17:51:56 Maxime Ripard wrote: Neither pll6 nor ahb1_mux are listed in the DT binding. Also, why is it the driver's business to set the parent? Those are global clocks, so it's not really part pof the driver binding itself. But I can add them. No better don't then. Can you change the clk_get() call to pass NULL as the device pointer to clarify this in the source though? Ok. About the reparenting itself, other devices are actually fine having any parent they want, only the DMA is picky about it (at least, from what we know), so it made sense to me to put it into the driver itself. Where would you put it? Maybe Mike Turquette has an idea. We have in the past discussed about cases where you want the default clock setting to be part of the clock provider in some property. Could that work here? You mean in the DT? I guess it would yes. -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v4 6/7] DMA: sun6i: Add driver for the Allwinner A31 DMA controller
Hi,
On Tue, Mar 11, 2014 at 09:52:55AM +, Shevchenko, Andriy wrote:
On Mon, 2014-03-10 at 15:41 +0100, Maxime Ripard wrote:
The Allwinner A31 has a 16 channels DMA controller that it shares with the
newer A23. Although sharing some similarities with the DMA controller of the
older Allwinner SoCs, it's significantly different, I don't expect it to be
possible to share the driver for these two.
The A31 Controller is able to memory-to-memory or memory-to-device
transfers on
the 16 channels in parallel.
Since it's going to be next cycle of review, I add few more nitpicks
below.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/dma/sun6i-dma.txt | 45 +
drivers/dma/Kconfig| 8 +
drivers/dma/Makefile | 1 +
drivers/dma/sun6i-dma.c| 986
+
4 files changed, 1040 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/sun6i-dma.txt
create mode 100644 drivers/dma/sun6i-dma.c
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
new file mode 100644
index ..5d7c86d52665
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -0,0 +1,45 @@
+Allwinner A31 DMA Controller
+
+This driver follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+
+- compatible: Must be allwinner,sun6i-a31-dma
+- reg: Should contain the registers base address and length
+- interrupts: Should contain a reference to the interrupt used by
this device
+- clocks: Should contain a reference to the parent AHB clock
+- resets: Should contain a reference to the reset controller asserting
+ this device in reset
+- #dma-cells : Should be 1, a single cell holding a line request number
+
+Example:
+ dma: dma-controller@01c02000 {
+ compatible = allwinner,sun6i-a31-dma;
+ reg = 0x01c02000 0x1000;
+ interrupts = 0 50 4;
+ clocks = ahb1_gates 6;
+ resets = ahb1_rst 6;
+ #dma-cells = 1;
+ };
+
+Clients:
+
+DMA clients connected to the A31 DMA controller must use the format
+described in the dma.txt file, using a two-cell specifier for each
+channel: a phandle plus one integer cells.
+The two cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. The port ID as specified in the datasheet
+
+Example:
+spi2: spi@01c6a000 {
+ compatible = allwinner,sun6i-a31-spi;
+ reg = 0x01c6a000 0x1000;
+ interrupts = 0 67 4;
+ clocks = ahb1_gates 22, spi2_clk;
+ clock-names = ahb, mod;
+ dmas = dma 25, dma 25;
+ dma-names = rx, tx;
+ resets = ahb1_rst 22;
+};
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016bcea4..7923697eaa2e 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -351,6 +351,14 @@ config MOXART_DMA
help
Enable support for the MOXA ART SoC DMA controller.
+config DMA_SUN6I
+ tristate Allwinner A31 SoCs DMA support
+ depends on ARCH_SUNXI
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support for the DMA engine for Allwinner A31 SoCs.
+
config DMA_ENGINE
bool
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a029d0f4a1be..18cdbad1927c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_K3_DMA) += k3dma.o
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
+obj-$(CONFIG_DMA_SUN6I) += sun6i-dma.o
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
new file mode 100644
index ..a11040633b30
--- /dev/null
+++ b/drivers/dma/sun6i-dma.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd
+ * Author: Sugar sh...@allwinnertech.com
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/dmaengine.h
+#include linux/dmapool.h
+#include linux/interrupt.h
+#include linux/module.h
+#include linux/of_dma.h
+#include linux/platform_device.h
+#include linux/reset.h
+#include linux/slab.h
+#include linux/types.h
+
+#include virt-dma.h
+
+/*
+ * There's 16 physical channels that can work in parallel.
+ *
+ * However we have 30 different endpoints for our requests
[PATCH] spi: core: Fix Oops in spi_pump_messages error path
When the generic implementation of the transfer_one_message callback was called
by the spi_pump_messages function, if that transfer was to fail, the
spi_finalize_current_message was called twice, once in
spi_transfer_one_message, and one in spi_pump_messages.
This was causing a null pointer dereference in the second call, because the
first one set the -cur_msg field to NULL.
Since the SPI framework expect the transfer_one_message callback to call
spi_finalize_current_message, we can remove it from spi_pump_messages, together
with any dereference of the -cur_msg pointer.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Cc: sta...@vger.kernel.org
---
drivers/spi/spi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 23756b0..39f12be 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -756,8 +756,6 @@ static void spi_pump_messages(struct kthread_work *work)
if (ret) {
dev_err(master-dev,
failed to transfer one message from queue: %d\n, ret);
- master-cur_msg-status = ret;
- spi_finalize_current_message(master);
return;
}
}
--
1.8.4.2
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Re: [PATCH] spi: core: Fix Oops in spi_pump_messages error path
Hi Geert, On Mon, Feb 17, 2014 at 07:02:09PM +0100, Geert Uytterhoeven wrote: On Mon, Feb 17, 2014 at 6:20 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: When the generic implementation of the transfer_one_message callback was called by the spi_pump_messages function, if that transfer was to fail, the spi_finalize_current_message was called twice, once in spi_transfer_one_message, and one in spi_pump_messages. This was causing a null pointer dereference in the second call, because the first one set the -cur_msg field to NULL. Since the SPI framework expect the transfer_one_message callback to call spi_finalize_current_message, we can remove it from spi_pump_messages, together with any dereference of the -cur_msg pointer. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com Cc: sta...@vger.kernel.org Already fixed in v3.14-rc3 in 1f802f8249a0da536877842c43c7204064c4de8b (spi: Fix crash with double message finalisation on error handling). There's no need to inform stable, as the problem was introduced in v3.14-rc1. Oops, totally missed that. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v7 1/8] clk: sunxi: factors: automatic reparenting support
On Mon, Feb 17, 2014 at 11:02:15AM +0100, David Lanzendörfer wrote: From: Emilio López emi...@elopez.com.ar This commit implements .determine_rate, so that our factor clocks can be reparented when needed. Signed-off-by: Emilio López emi...@elopez.com.ar Your signed-off-by is missing here. Once you added it, you can add my Acked-by Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v7 3/8] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote: From: Hans de Goede hdego...@redhat.com Signed-off-by: Hans de Goede hdego...@redhat.com Again, your SoB is missing, and that can be squashed with the previous patch. -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v7 2/8] clk: sunxi: Implement MMC phase control
Hi, On Mon, Feb 17, 2014 at 11:02:21AM +0100, David Lanzendörfer wrote: From: Emilio López emi...@elopez.com.ar Signed-off-by: Emilio López emi...@elopez.com.ar You're missing your Signed-off-by here too. Remember, for every patch you send, your Signed-off-by must be there, regardless wether you're the author or not. A commit log would be very much welcome too. Now, down to the patch itself, I remember Mike saying that he would prefer adding a function in the framework instead of hardcoding it. Mike, what's your feeling on this? Would merging this seem reasonnable to you as is, or do you want to take this to the framework? --- drivers/clk/sunxi/clk-sunxi.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..33b9977 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, /** + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control + */ If you don't go the framework road, some documentation on what are the arguments it takes and what it's supposed to return would be great. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v7 5/8] ARM: dts: sun7i: Add support for mmc
;
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c11000 0x1000;
+ clocks = ahb_gates 10, mmc2_clk;
+ clock-names = ahb, mod;
+ interrupts = 0 34 4;
+ bus-width = 4;
+ status = disabled;
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c12000 0x1000;
+ clocks = ahb_gates 11, mmc3_clk;
+ clock-names = ahb, mod;
+ interrupts = 0 35 4;
+ bus-width = 4;
+ status = disabled;
+ };
+
pio: pinctrl@01c20800 {
compatible = allwinner,sun7i-a20-pinctrl;
reg = 0x01c20800 0x400;
@@ -432,6 +472,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins =
PF0,PF1,PF2,PF3,PF4,PF5;
+ allwinner,function = mmc0;
+ allwinner,drive = 3;
+ allwinner,pull = 0;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = PH1;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins =
PI4,PI5,PI6,PI7,PI8,PI9;
+ allwinner,function = mmc3;
+ allwinner,drive = 3;
+ allwinner,pull = 0;
+ };
};
timer@01c20c00 {
Looks good otherwise.
Thanks!
Maxime
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Re: [PATCH v7 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
4
+#define MMC_CLK_100M5
+#define MMC_CLK_200M6
+#define MMC_CLK_MOD_NUM 7
Wouldn't an enum be better here?
+
+struct sunxi_mmc_clk_dly {
+ u32 mode;
+ u32 oclk_dly;
+ u32 sclk_dly;
+};
Comments here would be great too.
Thanks for working on this!
Maxime
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Re: [PATCH v7 8/8] ARM: sunxi: Add documentation for driver for SD/MMC hosts found on Allwinner sunxi SoCs
On Mon, Feb 17, 2014 at 11:03:02AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
---
.../devicetree/bindings/mmc/sunxi-mmc.txt | 32
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
new file mode 100644
index 000..5ce8c5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -0,0 +1,32 @@
+* Allwinner sunxi MMC controller
+
+The highspeed MMC host controller on Allwinner SoCs provides an interface
+for MMC, SD and SDIO types of memory cards.
+
+Supported maximum speeds are the ones of the eMMC standard 4.5 as well
+as the speed of SD standard 3.0.
+Absolute maximum transfer rate is 200MB/s
+
+Required properties:
+- compatible: Should be allwinner,revision-chip-mmc.
+ The supported chips include a10, a10s, 13, a20 and a31.
Please use the real compatibles here. It's much easier to search
for. Plus, your driver doesn't support all the SoCs you're mentionning here.
+- base registers are 0x1000 appart, so the base of mmc1
+ would be 0x01c0f000+0x1000=0x01c1(see example)
+ and so on.
Please provide the real property name to use. No need for an example
here, you have a full-fledged one in a few lines.
+- clocks requires the reference at the ahb clock gate
+ with the correct index (mmc0 - 8, mmc1 - 9, and so on)
+ as well as the reference to the correct mod0 clock.
Ditto. Plus, this is not a mod0 clock.
+- interrupts requires the correct IRQ line
+ (mmc0 - 32, mmc1 - 33, and so on)
Ditto.
+
+Examples:
+
+mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mod;
You never talked about the clock-names property, and which clocks were
supposed to be provided.
+ interrupts = 0 32 4;
+ bus-width = 4;
And you never talked about bus-width either.
+ status = disabled;
+};
Isn't the cd-gpios property requested too?
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Re: [PATCH v7 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
Hi Hans,
On Tue, Feb 18, 2014 at 09:49:21PM +0100, Hans de Goede wrote:
Hi,
On 02/18/2014 04:37 PM, Maxime Ripard wrote:
snip
+
+ for (i = 0; i data-sg_len; i++) {
+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
+SDXC_IDMAC_DES0_DIC;
+
+ if (data-sg[i].length == max_len)
+ pdes[i].buf_size = 0; /* 0 == max_len */
+ else
+ pdes[i].buf_size = data-sg[i].length;
+
+ pdes[i].buf_addr_ptr1 = sg_dma_address(data-sg[i]);
+ pdes[i].buf_addr_ptr2 = (u32)pdes_pa[i + 1];
+ }
+
+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
+
+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
wmb ensure the proper ordering of the instructions, not flushing the
caches like what your comment implies.
Since I put that comment there, allow me to explain. A modern ARM
cpu core has 2 or more units handling stores. One for regular
memory stores, and one for io-mem stores. Regular mem stores can
be re-ordered, io stores cannot. Normally there is no syncing
between the 2 store units. Cache flushing is not an issue here
since the memory holding the descriptors for the idma controller
is allocated cache coherent, which on arm means it is not cached.
What is an issue here is the io-store starting the idmac hitting
the io-mem before the descriptors hit the main-mem, the wmb()
ensures this does not happen.
To expand a bit, my point was not that it was functionnally
wrong. Since you put a barrier in there, and that it resides in a
cache coherent section, we're fine.
My point was that the comment itself was misleading.
+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
+struct mmc_data *data)
+{
+ u32 dma_len;
+ u32 i;
+ u32 temp;
+ struct scatterlist *sg;
+
+ dma_len = dma_map_sg(mmc_dev(smc_host-mmc), data-sg, data-sg_len,
+sunxi_mmc_get_dma_dir(data));
+ if (dma_len == 0) {
+ dev_err(mmc_dev(smc_host-mmc), dma_map_sg failed\n);
+ return -ENOMEM;
+ }
+
+ for_each_sg(data-sg, sg, data-sg_len, i) {
+ if (sg-offset 3 || sg-length 3) {
+ dev_err(mmc_dev(smc_host-mmc),
+ unaligned scatterlist: os %x length %d\n,
+ sg-offset, sg-length);
+ return -EINVAL;
+ }
+ }
+
+ sunxi_mmc_init_idma_des(smc_host, data);
+
+ temp = mci_readl(smc_host, REG_GCTRL);
+ temp |= SDXC_DMA_ENABLE_BIT;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ temp |= SDXC_DMA_RESET;
+ mci_writel(smc_host, REG_GCTRL, temp);
Does it really need to be done in two steps?
We don't know, so this is probably best left as is.
Ok.
(Newline)
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
+
+ if (!(data-flags MMC_DATA_WRITE))
+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
+
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST |
SDXC_IDMAC_IDMA_ON);
+
+ return 0;
+}
+
+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
+ struct mmc_request *req)
+{
+ u32 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | SDXC_STOP_ABORT_CMD
+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
+ u32 ri = 0;
+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
+
+ mci_writel(host, REG_CARG, 0);
+ mci_writel(host, REG_CMDR, cmd_val);
+
+ do {
+ ri = mci_readl(host, REG_RINTR);
+ } while (!(ri (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT))
+time_before(jiffies, expire));
+
+ if (ri SDXC_INTERRUPT_ERROR_BIT) {
+ dev_err(mmc_dev(host-mmc), send stop command failed\n);
+ if (req-stop)
+ req-stop-resp[0] = -ETIMEDOUT;
+ } else {
+ if (req-stop)
+ req-stop-resp[0] = mci_readl(host, REG_RESP0);
+ }
+
+ mci_writel(host, REG_RINTR, 0x);
+}
+
+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
+{
+ struct mmc_command *cmd = smc_host-mrq-cmd;
+ struct mmc_data *data = smc_host-mrq-data;
+
+ /* For some cmds timeout is normal with sd/mmc cards */
+ if ((smc_host-int_sum SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESP_TIMEOUT
+ (cmd-opcode == SD_IO_SEND_OP_COND || cmd-opcode ==
SD_IO_RW_DIRECT))
+ return;
+
+ dev_err(mmc_dev(smc_host-mmc),
I'd rather put it at a debug loglevel.
Erm, this only happens if something is seriously wrong.
Still. Something would be seriously wrong in the MMC
driver/controller. You don't want to bloat the whole kernel logs with
the dump of your registers just because the MMC is failing. This is of
no interest to anyone but someone that would
Re: [PATCHv2 1/8] ARM: at91: Add at91sam9rl DT SoC support
Hi Mark,
On Wed, Feb 19, 2014 at 05:00:20PM +, Mark Rutland wrote:
+ adc0: adc@fffd {
+ compatible = atmel,at91sam9260-adc;
+ reg = 0xfffd 0x100;
+ interrupts = 20 IRQ_TYPE_LEVEL_HIGH 0;
+ atmel,adc-use-external-triggers;
+ atmel,adc-channels-used = 0xf;
+ atmel,adc-vref = 3300;
+ atmel,adc-num-channels = 4;
+ atmel,adc-startup-time = 15;
+ atmel,adc-channel-base = 0x30;
+ atmel,adc-drdy-mask = 0x1;
+ atmel,adc-status-register = 0x1c;
+ atmel,adc-trigger-register = 0x04;
+ atmel,adc-res = 8 10;
+ atmel,adc-res-names = lowres, highres;
+ atmel,adc-use-res = highres;
+
+ trigger@0 {
+ trigger-name = timer-counter-0;
+ trigger-value = 0x1;
+ };
A unit-address should go with a reg value. Either this needs a reg and
the parent node needs #address-cells and #size-cells, or the
unit-address should go, and the names made unique through other means.
What do you suggest to make the name unique then?
The ePAPR is pretty clear that the above is the way to go, so I'm
unclear on what you have in mind here.
Plus, I haven't seen anywhere that reg was actually mandatory.
Thanks!
Maxime
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Re: [PATCH v3 2/2] i2c: New bus driver for the Qualcomm QUP I2C controller
Hi Bjorn,
On Thu, Feb 20, 2014 at 04:38:10PM -0800, Bjorn Andersson wrote:
+static int qup_i2c_probe(struct platform_device *pdev)
+{
[ snip ]
+
+ qup_i2c_enable_clocks(qup);
+
[ snip ]
+
+ pm_runtime_set_autosuspend_delay(qup-dev, MSEC_PER_SEC);
+ pm_runtime_use_autosuspend(qup-dev);
+ pm_runtime_enable(qup-dev);
Since the device is already woken up, you probably need to call
pm_runtime_set_active here.
Maxime
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Re: [PATCH v7 5/8] ARM: dts: sun7i: Add support for mmc
On Tue, Feb 18, 2014 at 04:10:38PM +0100, Hans de Goede wrote:
Hi,
On 02/18/2014 03:22 PM, Maxime Ripard wrote:
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +
arch/arm/boot/dts/sun7i-a20.dtsi| 61
+++
4 files changed, 100 insertions(+)
I'd prefer to have three patches here:
- One that add the controllers
- One that add the pin muxing options
- One that enable the controllers on the various boards.
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..ae800b6 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -34,6 +34,14 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default, default;
+ pinctrl-0 = mmc0_pins_a;
+ pinctrl-1 = mmc0_cd_pin_reference_design;
This can be made a single pinctrl group, you don't need the pinctrl-1
stuff, it only complicates the node.
Then how do we deal with boards which use a different gpio for card-detect ?
In that case we don't want to change the mux setting of the reference
design cd pin. IOW I believe that having 2 separate pinctrl settings for
this is the rigt thing todo. I would prefer using just mmc0_cd_pin_a instead
of _reference_design though.
Oh wait, you're probably talking about using:
pinctrl-0 = mmc0_pins_a,
mmc0_cd_pin_reference_design;
Yes that would be better.
Yep, exactly :)
+ cd-gpios = pio 7 1 0; /* PH1 */
+ status = okay;
+ };
+
pinctrl@01c20800 {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = PH20, PH21;
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..370cef84 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -19,6 +19,14 @@
compatible = cubietech,cubietruck, allwinner,sun7i-a20;
soc@01c0 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default, default;
+ pinctrl-0 = mmc0_pins_a;
+ pinctrl-1 = mmc0_cd_pin_reference_design;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ status = okay;
+ };
+
pinctrl@01c20800 {
led_pins_cubietruck: led_pins@0 {
allwinner,pins = PH7, PH11, PH20, PH21;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..685ec06 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -34,7 +34,30 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = default, default;
+ pinctrl-0 = mmc0_pins_a;
+ pinctrl-1 = mmc0_cd_pin_reference_design;
+ cd-gpios = pio 7 1 0; /* PH1 */
+ status = okay;
+ };
+
+ mmc3: mmc@01c12000 {
+ pinctrl-names = default, default;
+ pinctrl-0 = mmc3_pins_a;
+ pinctrl-1 = mmc3_cd_pin_olinuxinom;
+ cd-gpios = pio 7 11 0; /* PH11 */
+ status = okay;
+ };
+
pinctrl@01c20800 {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
+ allwinner,pins = PH11;
+ allwinner,function = gpio_in;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = PH2;
allwinner,function = gpio_out;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff0948..5b55414 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -355,6 +355,46 @@
#size-cells = 0;
};
+ mmc0: mmc@01c0f000 {
+ compatible = allwinner,sun5i-a13-mmc;
+ reg = 0x01c0f000 0x1000;
+ clocks = ahb_gates 8, mmc0_clk;
+ clock-names = ahb, mod;
+ interrupts = 0 32 4;
+ bus-width = 4
Re: [PATCH v4 1/8] clk: sunxi: Add Allwinner A20/A31 GMAC clock unit
On Mon, Feb 10, 2014 at 06:35:47PM +0800, Chen-Yu Tsai wrote: The Allwinner A20/A31 clock module controls the transmit clock source and interface type of the GMAC ethernet controller. Model this as a single clock for GMAC drivers to use. Signed-off-by: Chen-Yu Tsai w...@csie.org Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH v4 0/8] Add Allwinner A20 GMAC ethernet support
Hi Chen-Yu, On Mon, Feb 10, 2014 at 06:35:46PM +0800, Chen-Yu Tsai wrote: Hi, This is the v4 of the remaining Allwinner A20 GMAC glue layer patches. The stmmac driver changes have been merged through net-next. The remaining bits are clock and DT patches. The patches should be applied over my clock renaming patches. The Allwinner A20 SoC integrates an early version of dwmac IP from Synopsys. On top of that is a hardware glue layer. This layer needs to be configured before the dwmac can be used. Part of the glue layer is a clock mux, which controls the source and direction of the TX clock used by GMAC. Just merged patches 2-8. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH] pinctrl: sunxi: use chained_irq_{enter, exit} for GIC compatibility
On Tue, Feb 11, 2014 at 12:22:37AM +0800, Chen-Yu Tsai wrote:
On tha Allwinner A20 SoC, the external interrupts on the pin controller
device are connected to the GIC. Without chained_irq_{enter, exit},
external GPIO interrupts, such as used by mmc core card detect, cause
the system to hang.
Cc: sta...@vger.kernel.org
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Description: Digital signature
Re: [PATCH] i2c: mv64xxx: Fix compilation breakage
On Fri, Mar 21, 2014 at 11:49:59AM -0400, Paul Gortmaker wrote: On Mon, Mar 10, 2014 at 7:29 AM, Russell King - ARM Linux li...@arm.linux.org.uk wrote: On Mon, Mar 10, 2014 at 11:58:08AM +0100, Maxime Ripard wrote: On Fri, Mar 07, 2014 at 04:08:36PM +, Russell King - ARM Linux wrote: On Fri, Mar 07, 2014 at 03:59:30PM +0100, Maxime Ripard wrote: @@ -900,7 +902,8 @@ mv64xxx_i2c_probe(struct platform_device *pd) exit_free_irq: free_irq(drv_data-irq, drv_data); exit_reset: - if (pd-dev.of_node !IS_ERR(drv_data-rstc)) + if (pd-dev.of_node IS_ENABLED(CONFIG_RESET_CONTROLLER) + !IS_ERR(drv_data-rstc)) reset_control_assert(drv_data-rstc); Another question is... why do we need to check pd-dev.of_node here? If CONFIG_RESET_CONTROLLER is set, we always try to get the reset controller node, so drv_data-rstc is either going to be a valid pointer, or it's going to be an error pointer - neither reset_control_get() nor devm_reset_control_get return NULL. Following back on this as I was doing the patch, actually, drv_data-rstc will be NULL if we're not probed by DT, and hence never call reset_control_get, that would set an error pointer. But then, we can use IS_ERR_OR_NULL on drv_data-rstc. I think you can also move the devm_reset_control_get() into the main probe function: you're only checking for -EPROBE_DEFER from it to fail, allowing other errors to continue with the driver init. This means that on non-OF, devm_reset_control_get() will fail with -ENOENT. Looping linux-next into the CC since this is the cause of the failure in orion5x_defconfig there, and no point in anyone else re-doing the same bisect. I sent a fix for this that hasn't been picked up yet: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-March/239069.html IIRC, Wolfram's away until Monday, so I guess it will be merged some time next week. -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCH 2/2] ARM: dts: mvebu: Add the i2c-bridge capability to the mv64xxx-i2c
Hi Greg, On Fri, Jun 07, 2013 at 05:42:23PM +0200, Gregory CLEMENT wrote: The mv64xxx-i2c embedded in the Armada XP have a new feature called i2c-bridge. This commit split the i2c information into armada-370.dtsi and armada-xp.dtsi. Most of the data remains the same and stay in the common file Armada-370-xp.dtsi. With this new feature the size of the registers are bigger for Armada XP and for this SoCs we add a new flag for the i2c-bridge capability. The Device Tree binding documentation is updated accordingly. Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com --- Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt | 6 ++ arch/arm/boot/dts/armada-370-xp.dtsi | 2 -- arch/arm/boot/dts/armada-370.dtsi | 8 arch/arm/boot/dts/armada-xp.dtsi | 10 ++ 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt index f46d928..8ede3e7 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt @@ -8,6 +8,12 @@ Required properties : - interrupts : The interrupt number - clock-frequency : Desired I2C bus clock frequency in Hz. +Optional properties : + +- i2c,i2c-bridge : This flag indicate that the i2c controller have the + Transaction Generator support and we want to use it. Not all the + mv64xxx controller have this feature. Why not using a different compatible string here then? Maxime -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Arm-netbook] getting allwinner SoC support upstream (was Re: Uploading linux (3.9.4-1))
On Fri, Jun 07, 2013 at 07:26:49PM +0100, luke.leighton wrote: maxime: we need to talk :) please tell me in 4 or 5 sentences what you've managed to do so far, expanding a little on what thomas says below, more specifically what it achieves and/or allows rather than technically what it does (suitable for managers and directors in other words), and what plans you'd like to see happen. You mean something like http://linux-sunxi.org/Linux_mainlining_effort ? You should really do a bit of research before starting a thread like this one. This webpage has been around for like 9 monthes now on the wiki of a community you pretend to represent (even though I fail to get how you can pretend such thing, but that's another topic). is the maintainer of the mainline Allwinner sunxi effort. It already supports a number of boards, has a pinctrl driver, a GPIO driver, serial port is working, network is working, I2C is working. All in mainline, completely Device Tree based. great. which version did it first hit, i.e. what will the first signs of this be when allwinner begin doing git pulls? 3.8, as shown in the wiki page and which boards. bear in mind that one of those boards should really be the total range of products available across hundreds of chinese tablet clone manufacturers. specific question: is one of the boards the one that tom cubie submitted, which covers virtually every android tablet product manufactured in the millions by chinese tablet clone manufacturers? Again, wiki. So isn't this entire discussion completely moot? no because it's totally in isolation from allwinner. i need to give them a heads-up, and get them involved, giving them specific incentives [which nobody's yet given!!] for following a particular path [or paths] yet to be recommended. The mainline support for sunxi has already started since 6 months or so, and has been Device Tree based from day one. to clarify: the *community-driven* mainline support for sunxi. ok - which chips? sun3i (ARM9), sun4i (Cortex A8), sun5i, sun6i and sun7i (Dual-Core Cortex A7)? which ones are in? A10, A13 for the moment. I just received hardware with A10s, A20 and A31 that I need to work on, but support should come quite soon. I already have some patches pending to be tested on an A31 board, but didn't have as much time as I wanted lately to actually set a proper environment to test them. Maxime -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/4] Add external interrupt support for Allwinner SoCs
Hi everyone, This patch adds the support for the external interrupt sources found in the PIO IP of the Allwinner SoCs. This IP handles up to 32 external interrupt source, that are exposed through a particular pin function on some pins handled by the PIO. We thus need to change the muxing to enable these interrupts, which leads to some additional logic. Thanks, Maxime Maxime Ripard (4): pinctrl: sunxi: Search the description array by pin id pinctrl: sunxi: Add external interrupts support pinctrl: sunxi: Add external interrupt functions ARM: sunxi: dt: Register the pio node as interrupt controller arch/arm/boot/dts/sun4i-a10.dtsi | 2 + arch/arm/boot/dts/sun5i-a13.dtsi | 2 + drivers/pinctrl/pinctrl-sunxi.c | 307 +-- drivers/pinctrl/pinctrl-sunxi.h | 68 + 4 files changed, 331 insertions(+), 48 deletions(-) -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/4] ARM: sunxi: dt: Register the pio node as interrupt controller
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 2 ++
arch/arm/boot/dts/sun5i-a13.dtsi | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..9b3c99c 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -173,8 +173,10 @@
pio: pinctrl@01c20800 {
compatible = allwinner,sun4i-a10-pinctrl;
reg = 0x01c20800 0x400;
+ interrupts = 28;
clocks = apb0_gates 5;
gpio-controller;
+ interrupt-controller;
#address-cells = 1;
#size-cells = 0;
#gpio-cells = 3;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..f34db19 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -163,8 +163,10 @@
pio: pinctrl@01c20800 {
compatible = allwinner,sun5i-a13-pinctrl;
reg = 0x01c20800 0x400;
+ interrupts = 28;
clocks = apb0_gates 5;
gpio-controller;
+ interrupt-controller;
#address-cells = 1;
#size-cells = 0;
#gpio-cells = 3;
--
1.8.3
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[PATCH 1/4] pinctrl: sunxi: Search the description array by pin id
Avoid to use expensive string manipulation functions and search by pin
id when possible.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 50 -
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index c52fc2c..0e7961c 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -1399,6 +1399,31 @@ sunxi_pinctrl_desc_find_function_by_name(struct
sunxi_pinctrl *pctl,
return NULL;
}
+static struct sunxi_desc_function *
+sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
+ const u16 pin_num,
+ const char *func_name)
+{
+ int i;
+
+ for (i = 0; i pctl-desc-npins; i++) {
+ const struct sunxi_desc_pin *pin = pctl-desc-pins + i;
+
+ if (pin-pin.number == pin_num) {
+ struct sunxi_desc_function *func = pin-functions;
+
+ while (func-name) {
+ if (!strcmp(func-name, func_name))
+ return func;
+
+ func++;
+ }
+ }
+ }
+
+ return NULL;
+}
+
static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@@ -1680,37 +1705,20 @@ sunxi_pmx_gpio_set_direction(struct pinctrl_dev
*pctldev,
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_desc_function *desc;
- char pin_name[SUNXI_PIN_NAME_MAX_LEN];
const char *func;
- u8 bank, pin;
- int ret;
-
- bank = (offset) / PINS_PER_BANK;
- pin = (offset) % PINS_PER_BANK;
-
- ret = sprintf(pin_name, P%c%d, 'A' + bank, pin);
- if (!ret)
- goto error;
if (input)
func = gpio_in;
else
func = gpio_out;
- desc = sunxi_pinctrl_desc_find_function_by_name(pctl,
- pin_name,
- func);
- if (!desc) {
- ret = -EINVAL;
- goto error;
- }
+ desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
+ if (!desc)
+ return -EINVAL;
sunxi_pmx_set(pctldev, offset, desc-muxval);
- ret = 0;
-
-error:
- return ret;
+ return 0;
}
static const struct pinmux_ops sunxi_pmx_ops = {
--
1.8.3
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[PATCH 3/4] pinctrl: sunxi: Add external interrupt functions
The A10 and A13 has a few pins that can be muxed into a particular
function that can be used as an interrupt source. Add the available
pins for such functions to the A10 and A13 description array.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 99 ++---
1 file changed, 73 insertions(+), 26 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 47c7f43..3bf941f 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -675,6 +675,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D0 */
SUNXI_FUNCTION(0x3, pata),/* ATAA0 */
SUNXI_FUNCTION(0x4, uart3), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
SUNXI_FUNCTION(0x7, csi1)), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -682,6 +683,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D1 */
SUNXI_FUNCTION(0x3, pata),/* ATAA1 */
SUNXI_FUNCTION(0x4, uart3), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
SUNXI_FUNCTION(0x7, csi1)), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -689,6 +691,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D2 */
SUNXI_FUNCTION(0x3, pata),/* ATAA2 */
SUNXI_FUNCTION(0x4, uart3), /* RTS */
+ SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
SUNXI_FUNCTION(0x7, csi1)), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -696,6 +699,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D3 */
SUNXI_FUNCTION(0x3, pata),/* ATAIRQ */
SUNXI_FUNCTION(0x4, uart3), /* CTS */
+ SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
SUNXI_FUNCTION(0x7, csi1)), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -703,6 +707,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D4 */
SUNXI_FUNCTION(0x3, pata),/* ATAD0 */
SUNXI_FUNCTION(0x4, uart4), /* TX */
+ SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
SUNXI_FUNCTION(0x7, csi1)), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -710,6 +715,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, lcd1),/* D5 */
SUNXI_FUNCTION(0x3, pata),/* ATAD1 */
SUNXI_FUNCTION(0x4, uart4), /* RX */
+ SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
SUNXI_FUNCTION(0x7, csi1)), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -718,6 +724,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, pata),/* ATAD2 */
SUNXI_FUNCTION(0x4, uart5), /* TX */
SUNXI_FUNCTION(0x5, ms), /* BS */
+ SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
SUNXI_FUNCTION(0x7, csi1)), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -726,6 +733,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, pata),/* ATAD3 */
SUNXI_FUNCTION(0x4, uart5), /* RX */
SUNXI_FUNCTION(0x5, ms), /* CLK */
+ SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
SUNXI_FUNCTION(0x7, csi1)), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -734,6 +742,7 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, pata),/* ATAD4 */
SUNXI_FUNCTION(0x4, keypad), /* IN0 */
SUNXI_FUNCTION(0x5, ms), /* D0 */
+ SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
SUNXI_FUNCTION(0x7, csi1)), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -742,6 +751,7 @@ static const
[PATCH 2/4] pinctrl: sunxi: Add external interrupts support
The port controller IP found in the Allwinner A10 and A13 can use few of
the pins it manage as an interrupt source, called external interrupts in
the datasheet.
The number of these external interrupts are SoCs specific, but the
current upper limit is 32. In order to work, the external interrupts'
pins have to be muxed to a specific function to generate an interrupt.
This patch adds the irqchip and the needed logic to use the PIO
controller as an interrupt controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 158 +++-
drivers/pinctrl/pinctrl-sunxi.h | 68 +
2 files changed, 225 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 0e7961c..47c7f43 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -13,10 +13,12 @@
#include linux/io.h
#include linux/clk.h
#include linux/gpio.h
+#include linux/irqdomain.h
#include linux/module.h
#include linux/of.h
#include linux/of_address.h
#include linux/of_device.h
+#include linux/of_irq.h
#include linux/pinctrl/consumer.h
#include linux/pinctrl/machine.h
#include linux/pinctrl/pinctrl.h
@@ -1796,6 +1798,26 @@ static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip
*gc,
return pin;
}
+static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct sunxi_pinctrl *pctl = dev_get_drvdata(chip-dev);
+ struct sunxi_desc_function *desc;
+
+ if (offset chip-ngpio)
+ return -ENXIO;
+
+ desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, irq);
+ if (!desc)
+ return -EINVAL;
+
+ pctl-irq_array[desc-irqnum] = offset;
+
+ dev_dbg(chip-dev, %s: request IRQ for GPIO %d, return %d\n,
+ chip-label, offset + chip-base, desc-irqnum);
+
+ return irq_find_mapping(pctl-domain, desc-irqnum);
+}
+
static struct gpio_chip sunxi_pinctrl_gpio_chip = {
.owner = THIS_MODULE,
.request= sunxi_pinctrl_gpio_request,
@@ -1805,10 +1827,118 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip = {
.get= sunxi_pinctrl_gpio_get,
.set= sunxi_pinctrl_gpio_set,
.of_xlate = sunxi_pinctrl_gpio_of_xlate,
+ .to_irq = sunxi_pinctrl_gpio_to_irq,
.of_gpio_n_cells= 3,
.can_sleep = 0,
};
+static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
+ unsigned int type)
+{
+ struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ u32 reg = sunxi_irq_cfg_reg(d-hwirq);
+ u8 index = sunxi_irq_cfg_offset(d-hwirq);
+ u8 mode;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ mode = IRQ_EDGE_RISING;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ mode = IRQ_EDGE_FALLING;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ mode = IRQ_EDGE_BOTH;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ mode = IRQ_LEVEL_HIGH;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ mode = IRQ_LEVEL_LOW;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel((mode IRQ_CFG_IRQ_MASK) index, pctl-membase + reg);
+
+ return 0;
+}
+
+static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
+{
+ struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ u32 ctrl_reg = sunxi_irq_ctrl_reg(d-hwirq);
+ u8 ctrl_idx = sunxi_irq_ctrl_offset(d-hwirq);
+ u32 status_reg = sunxi_irq_status_reg(d-hwirq);
+ u8 status_idx = sunxi_irq_status_offset(d-hwirq);
+ u32 val;
+
+ /* Mask the IRQ */
+ val = readl(pctl-membase + ctrl_reg);
+ writel(val ~(1 ctrl_idx), pctl-membase + ctrl_reg);
+
+ /* Clear the IRQ */
+ writel(1 status_idx, pctl-membase + status_reg);
+}
+
+static void sunxi_pinctrl_irq_mask(struct irq_data *d)
+{
+ struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ u32 reg = sunxi_irq_ctrl_reg(d-hwirq);
+ u8 idx = sunxi_irq_ctrl_offset(d-hwirq);
+ u32 val;
+
+ /* Mask the IRQ */
+ val = readl(pctl-membase + reg);
+ writel(val ~(1 idx), pctl-membase + reg);
+}
+
+static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
+{
+ struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ struct sunxi_desc_function *func;
+ u32 reg = sunxi_irq_ctrl_reg(d-hwirq);
+ u8 idx = sunxi_irq_ctrl_offset(d-hwirq);
+ u32 val;
+
+ func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
+
pctl-irq_array[d-hwirq],
+ irq);
+
+ /* Change
[PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 286 ++
1 file changed, 286 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm/boot/dts/sun5i-a10s.dtsi
new file mode 100644
index 000..2307ce8
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+ interrupt-parent = intc;
+
+ cpus {
+ cpu@0 {
+ compatible = arm,cortex-a8;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x2000;
+ };
+
+ clocks {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+
+ /*
+* This is a dummy clock, to be used as placeholder on
+* other mux clocks when a specific parent clock is not
+* yet implemented. It should be dropped when the driver
+* is complete.
+*/
+ dummy: dummy {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ };
+
+ osc24M: osc24M@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-osc-clk;
+ reg = 0x01c20050 0x4;
+ clock-frequency = 2400;
+ };
+
+ osc32k: osc32k {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 32768;
+ };
+
+ pll1: pll1@01c2 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-pll1-clk;
+ reg = 0x01c2 0x4;
+ clocks = osc24M;
+ };
+
+ /* dummy is 200M */
+ cpu: cpu@01c20054 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-cpu-clk;
+ reg = 0x01c20054 0x4;
+ clocks = osc32k, osc24M, pll1, dummy;
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-axi-clk;
+ reg = 0x01c20054 0x4;
+ clocks = cpu;
+ };
+
+ axi_gates: axi_gates@01c2005c {
+ #clock-cells = 1;
+ compatible = allwinner,sun4i-axi-gates-clk;
+ reg = 0x01c2005c 0x4;
+ clocks = axi;
+ clock-output-names = axi_dram;
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-ahb-clk;
+ reg = 0x01c20054 0x4;
+ clocks = axi;
+ };
+
+ ahb_gates: ahb_gates@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun4i-ahb-gates-clk;
+ reg = 0x01c20060 0x8;
+ clocks = ahb;
+ clock-output-names = ahb_usb0, ahb_ehci0,
+ ahb_ohci0, ahb_ehci1, ahb_ohci1, ahb_ss,
+ ahb_dma, ahb_bist, ahb_mmc0, ahb_mmc1,
+ ahb_mmc2, ahb_mmc3, ahb_ms, ahb_nand,
+ ahb_sdram, ahb_ace, ahb_emac, ahb_ts,
+ ahb_spi0, ahb_spi1, ahb_spi2, ahb_spi3,
+ ahb_pata, ahb_sata, ahb_gps, ahb_ve,
+ ahb_tvd, ahb_tve0, ahb_tve1, ahb_lcd0,
+ ahb_lcd1, ahb_csi0, ahb_csi1, ahb_hdmi,
+ ahb_de_be0, ahb_de_be1, ahb_de_fe0,
+ ahb_de_fe1, ahb_mp, ahb_mali400;
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = 0;
+ compatible = allwinner,sun4i-apb0-clk;
+ reg = 0x01c20054 0x4;
+ clocks = ahb;
+ };
+
+ apb0_gates: apb0_gates@01c20068 {
+ #clock-cells = 1;
+ compatible = allwinner,sun4i-apb0-gates-clk;
+ reg = 0x01c20068 0x4
[PATCH 1/6] ARM: sunxi: Add Allwinner A10s machine compatible
The A10s is a SoC member of the Allwinner sun5i family. It is basically
an A13 with an EMAC and an HDMI controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Documentation/arm/sunxi/README | 4
arch/arm/mach-sunxi/sunxi.c| 1 +
2 files changed, 5 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d9a372d..e3f93fb 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -17,6 +17,10 @@ SunXi family
+ User Manual
http://dl.linux-sunxi.org/A10/A10%20User%20Manual%20-%20v1.20%20%282012-04-09%2c%20DECRYPTED%29.pdf
+ - Allwinner A10s (sun5i)
++ Datasheet
+
http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
+
- Allwinner A13 (sun5i)
+ Datasheet
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 08937a3..a42d874 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -109,6 +109,7 @@ static void __init sunxi_dt_init(void)
static const char * const sunxi_board_dt_compat[] = {
allwinner,sun4i-a10,
+ allwinner,sun5i-a10s,
allwinner,sun5i-a13,
NULL,
};
--
1.8.3
--
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[PATCH 6/6] ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 2e67a27..4aa6401 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -31,10 +31,12 @@ CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y +CONFIG_SUN4I_EMAC=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y CONFIG_SERIO_AMBAKMI=y +CONFIG_MDIO_SUN4I=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/6] Add support for Allwinner A10s SoCs
Hi everyone, This patch serie reworks a bit the pinctrl driver and adds the necessary bits needed to support the Allwinner A10s SoC. This SoC is a bit in between the A10 and A13. Notable differences with the A13 is the addition of an HDMI controller and of the EMAC. For the time being (ie until we find a proper datasheet for this SoCs), the clock definition is taken from the A10 one. This patches depends on the Add external interrupt support for Allwinner SoCs patch serie. Thanks, Maxime Maxime Ripard (6): ARM: sunxi: Add Allwinner A10s machine compatible pinctrl: sunxi: Move the pins definitions to a separate header pinctrl: sunxi: Add Allwinner A10s pins ARM: sunxi: dt: Add Allwinner A10s DTSI ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree ARM: multi_v7: Enable Allwinner EMAC in multi_v7_defconfig Documentation/arm/sunxi/README |4 + arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75 + arch/arm/boot/dts/sun5i-a10s.dtsi| 286 +++ arch/arm/configs/multi_v7_defconfig |2 + arch/arm/mach-sunxi/sunxi.c |1 + drivers/pinctrl/pinctrl-sunxi-pins.h | 2023 ++ drivers/pinctrl/pinctrl-sunxi.c | 1362 +-- 7 files changed, 2393 insertions(+), 1360 deletions(-) create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi create mode 100644 drivers/pinctrl/pinctrl-sunxi-pins.h -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
new file mode 100644
index 000..73ad65e
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ sun5i-a10s.dtsi
+
+/ {
+ model = Olimex A10s-Olinuxino Micro;
+ compatible = olimex,a10s-olinuxino-micro, allwinner,sun5i-a10s;
+
+ soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy1;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
+
+ pinctrl@01c20800 {
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = PE3;
+ allwinner,function = gpio_out;
+ allwinner,drive = 1;
+ allwinner,pull = 0;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+
+ uart2: serial@01c28800 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_pins_a;
+ status = okay;
+ };
+
+ uart3: serial@01c28c00 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_pins_a;
+ status = okay;
+ };
+ };
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_olinuxino;
+
+ power {
+ gpios = pio 4 3 0;
+ default-state = on;
+ };
+ };
+};
--
1.8.3
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[PATCH 3/6] pinctrl: sunxi: Add Allwinner A10s pins
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi-pins.h | 645 +++
drivers/pinctrl/pinctrl-sunxi.c | 1 +
2 files changed, 646 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h
b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 92c6b14..2eeae0c 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -1004,6 +1004,646 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x4, hdmi)), /* HSDA */
};
+static const struct sunxi_desc_pin sun5i_a10s_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXD3 */
+ SUNXI_FUNCTION(0x3, ts0), /* CLK */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXD2 */
+ SUNXI_FUNCTION(0x3, ts0), /* ERR */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXD1 */
+ SUNXI_FUNCTION(0x3, ts0), /* SYNC */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXD0 */
+ SUNXI_FUNCTION(0x3, ts0), /* DLVD */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ETXD3 */
+ SUNXI_FUNCTION(0x3, ts0), /* D0 */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ETXD2 */
+ SUNXI_FUNCTION(0x3, ts0), /* D1 */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN5 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ETXD1 */
+ SUNXI_FUNCTION(0x3, ts0), /* D2 */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ETXD0 */
+ SUNXI_FUNCTION(0x3, ts0), /* D3 */
+ SUNXI_FUNCTION(0x5, keypad)), /* IN7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXCK */
+ SUNXI_FUNCTION(0x3, ts0), /* D4 */
+ SUNXI_FUNCTION(0x4, uart1), /* DTR */
+ SUNXI_FUNCTION(0x5, keypad)), /* OUT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXERR */
+ SUNXI_FUNCTION(0x3, ts0), /* D5 */
+ SUNXI_FUNCTION(0x4, uart1), /* DSR */
+ SUNXI_FUNCTION(0x5, keypad)), /* OUT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* ERXDV */
+ SUNXI_FUNCTION(0x3, ts0), /* D6 */
+ SUNXI_FUNCTION(0x4, uart1), /* DCD */
+ SUNXI_FUNCTION(0x5, keypad)), /* OUT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, emac), /* EMDC */
+ SUNXI_FUNCTION(0x3, ts0), /* D7 */
+ SUNXI_FUNCTION(0x4, uart1), /* RING */
+ SUNXI_FUNCTION(0x5, keypad)), /* OUT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
+ SUNXI_FUNCTION(0x0, gpio_in
Re: [PATCH 4/6] ARM: sunxi: dt: Add Allwinner A10s DTSI
Hi Arnd, On Sun, Jun 09, 2013 at 11:36:24PM +0200, Arnd Bergmann wrote: On Sunday 09 June 2013 18:36:05 Maxime Ripard wrote: Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- arch/arm/boot/dts/sun5i-a10s.dtsi | 286 ++ 1 file changed, 286 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a10s.dtsi Would it make sense to split out the parts that are common with A13 into a separate sun5i.dtsi file? I don't have the documentation at the moment, so I'm not exactly sure at which extent it's similar to the A13. Yet for the moment, the two dtsi are very different (different clock definitions, different muxings, etc.), so , I'm not quite sure about wether it would make stuff smaller. Of course, if we find they actually share a lot, we can definitely make a common sun5i DTSI later. But if you prefer to have it right now, I can always send a v2 :) Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 4/4] ARM: sunxi: dt: Register the pio node as interrupt controller
Hi Linus, On Mon, Jun 10, 2013 at 03:57:23PM +0200, Linus Walleij wrote: On Sat, Jun 8, 2013 at 12:05 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com Acked-by: Linus Walleij linus.wall...@linaro.org I guess this patch needs to go through the ARM SoC tree. Tell me if I can carry it in the pinctrl tree (read: there will be no conflicts agains changes from elsewhere) and I'll apply it. I'll carry this patch through my tree. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/4] ARM: mxs: dt: Add Crystalfontz CFA-10057 device tree
From: Brian Lilly br...@crystalfontz.com
The CFA-10057 is a breakout board for the CFA-10036 that has Ethernet,
USB and a 4.3 LCD screen on it.
Signed-off-by: Brian Lilly br...@crystalfontz.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx28-cfa10057.dts | 191 +++
arch/arm/mach-mxs/mach-mxs.c | 3 +-
3 files changed, 194 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imx28-cfa10057.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e26c504..1560a09 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-cfa10037.dtb \
imx28-cfa10049.dtb \
imx28-cfa10055.dtb \
+ imx28-cfa10057.dtb \
imx28-evk.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts
b/arch/arm/boot/dts/imx28-cfa10057.dts
new file mode 100644
index 000..2da713c
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ imx28-cfa10036.dts
+
+/ {
+ model = Crystalfontz CFA-10057 Board;
+ compatible = crystalfontz,cfa10057, crystalfontz,cfa10036,
fsl,imx28;
+
+ apb@8000 {
+ apbh@8000 {
+ pinctrl@80018000 {
+ pinctrl-names = default, default;
+ pinctrl-1 = hog_pins_cfa10057
+ hog_pins_cfa10057_pullup;
+
+ hog_pins_cfa10057: hog-10057@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x0073 /*
MX28_PAD_GPMI_D7__GPIO_0_7 */
+ 0x3053 /*
MX28_PAD_AUART1_TX__GPIO_3_5 */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 0;
+ };
+
+ hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x2133 /*
MX28_PAD_SSP2_D3__GPIO_2_19 */
+ 0x3183 /*
MX28_PAD_I2C0_SCL__GPIO_3_24 */
+ 0x3193 /*
MX28_PAD_I2C0_SDA__GPIO_3_25 */
+ 0x31a3 /*
MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
+ 0x31e3 /*
MX28_PAD_LCD_RESET__GPIO_3_30 */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 1;
+ };
+
+ lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x1000 /*
MX28_PAD_LCD_D00__LCD_D0 */
+ 0x1010 /*
MX28_PAD_LCD_D01__LCD_D1 */
+ 0x1020 /*
MX28_PAD_LCD_D02__LCD_D2 */
+ 0x1030 /*
MX28_PAD_LCD_D03__LCD_D3 */
+ 0x1040 /*
MX28_PAD_LCD_D04__LCD_D4 */
+ 0x1050 /*
MX28_PAD_LCD_D05__LCD_D5 */
+ 0x1060 /*
MX28_PAD_LCD_D06__LCD_D6 */
+ 0x1070 /*
MX28_PAD_LCD_D07__LCD_D7 */
+ 0x1080 /*
MX28_PAD_LCD_D08__LCD_D8 */
+ 0x1090 /*
MX28_PAD_LCD_D09__LCD_D9 */
+ 0x10a0 /*
MX28_PAD_LCD_D10__LCD_D10 */
+ 0x10b0 /*
MX28_PAD_LCD_D11__LCD_D11 */
+ 0x10c0 /*
MX28_PAD_LCD_D12__LCD_D12
[PATCH 3/4] ARM: mxs: dt: Add the Crystalfontz CFA-10055 device tree
From: Brian Lilly br...@crystalfontz.com
The CFA-10055 is yet another breakout board for the CFA-10036, and is
basically a CFA-10037, with the screen and LCD controller found on the
CFA-10049.
Signed-off-by: Brian Lilly br...@crystalfontz.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx28-cfa10055.dts | 179 +++
arch/arm/mach-mxs/mach-mxs.c | 15 +--
3 files changed, 185 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/boot/dts/imx28-cfa10055.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9f7121..e26c504 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -130,6 +130,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-cfa10036.dtb \
imx28-cfa10037.dtb \
imx28-cfa10049.dtb \
+ imx28-cfa10055.dtb \
imx28-evk.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts
b/arch/arm/boot/dts/imx28-cfa10055.dts
new file mode 100644
index 000..1581112
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10055 is an expansion board for the CFA-10036 module and
+ * CFA-10037, thus we need to include the CFA-10037 DTS.
+ */
+/include/ imx28-cfa10037.dts
+
+/ {
+ model = Crystalfontz CFA-10055 Board;
+ compatible = crystalfontz,cfa10055, crystalfontz,cfa10037,
crystalfontz,cfa10036, fsl,imx28;
+
+ apb@8000 {
+ apbh@8000 {
+ pinctrl@80018000 {
+ pinctrl-names = default, default;
+ pinctrl-1 = hog_pins_cfa10055
+ hog_pins_cfa10055_pullup;
+
+ hog_pins_cfa10055: hog-10055@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x3053 /*
MX28_PAD_AUART1_TX__GPIO_3_5 */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 0;
+ };
+
+ hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x31e3 /*
MX28_PAD_LCD_RESET__GPIO_3_30 */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 1;
+ };
+
+ spi2_pins_cfa10055: spi2-cfa10055@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x2103 /*
MX28_PAD_SSP2_SCK__GPIO_2_16 */
+ 0x2113 /*
MX28_PAD_SSP2_CMD__GPIO_2_17 */
+ 0x2123 /*
MX28_PAD_SSP2_D0__GPIO_2_18 */
+ ;
+ fsl,drive-strength = 1;
+ fsl,voltage = 1;
+ fsl,pull-up = 1;
+ };
+
+ lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x1000 /*
MX28_PAD_LCD_D00__LCD_D0 */
+ 0x1010 /*
MX28_PAD_LCD_D01__LCD_D1 */
+ 0x1020 /*
MX28_PAD_LCD_D02__LCD_D2 */
+ 0x1030 /*
MX28_PAD_LCD_D03__LCD_D3 */
+ 0x1040 /*
MX28_PAD_LCD_D04__LCD_D4 */
+ 0x1050 /*
MX28_PAD_LCD_D05__LCD_D5 */
+ 0x1060 /*
MX28_PAD_LCD_D06__LCD_D6 */
+ 0x1070 /*
MX28_PAD_LCD_D07__LCD_D7 */
+ 0x1080 /*
MX28_PAD_LCD_D08__LCD_D8
[PATCH 2/4] ARM: cfa10049: Switch the chip select pin of the LCD controller
From: Brian Lilly br...@crystalfontz.com The early prototypes had the chip select pin for the LCD controller wired on the GPIO 3-23, while the production run of the CFA-10049 have this chip select on the GPIO 3-5. Signed-off-by: Brian Lilly br...@crystalfontz.com Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- arch/arm/boot/dts/imx28-cfa10049.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 063e620..fa91af5 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -33,7 +33,7 @@ 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ - 0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */ + 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ ; fsl,drive-strength = 0; fsl,voltage = 1; @@ -265,7 +265,7 @@ gpio-sck = gpio2 16 0; gpio-mosi = gpio2 17 0; gpio-miso = gpio2 18 0; - cs-gpios = gpio3 23 0; + cs-gpios = gpio3 5 0; num-chipselects = 1; #address-cells = 1; #size-cells = 0; -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/4] ARM: mxs: Various Crystalfontz DT additions
Hi, Here is a patchset that adds support for two new Crystalfontz boards, add enable the USB port on the CFA-10036, and fix the chip select pin number for the 10049. Thanks, Maxime Brian Lilly (3): ARM: cfa10049: Switch the chip select pin of the LCD controller ARM: mxs: dt: Add the Crystalfontz CFA-10055 device tree ARM: mxs: dt: Add Crystalfontz CFA-10057 device tree Maxime Ripard (1): ARM: cfa10036: Add USB0 OTG port arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx28-cfa10036.dts | 23 + arch/arm/boot/dts/imx28-cfa10049.dts | 4 +- arch/arm/boot/dts/imx28-cfa10055.dts | 179 arch/arm/boot/dts/imx28-cfa10057.dts | 191 +++ arch/arm/mach-mxs/mach-mxs.c | 16 ++- 6 files changed, 403 insertions(+), 12 deletions(-) create mode 100644 arch/arm/boot/dts/imx28-cfa10055.dts create mode 100644 arch/arm/boot/dts/imx28-cfa10057.dts -- 1.8.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/4] ARM: cfa10036: Add USB0 OTG port
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/imx28-cfa10036.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts
b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1594694..eae9c97 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -45,6 +45,17 @@
fsl,voltage = 1;
fsl,pull-up = 0;
};
+
+ usb0_otg_cfa10036: otg-10036@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x0142 /*
MX28_PAD_GPMI_READY0__USB0_ID */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 0;
+ };
+
};
ssp0: ssp@8001 {
@@ -82,6 +93,18 @@
reset-gpios = gpio2 7 0;
};
};
+
+ usbphy0: usbphy@8007c000 {
+ status = okay;
+ };
+ };
+ };
+
+ ahb@8008 {
+ usb0: usb@8008 {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_otg_cfa10036;
+ status = okay;
};
};
--
1.8.3
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Re: [PATCH 1/4] ARM: cfa10036: Add USB0 OTG port
Hi Arnd,
On Fri, Jun 14, 2013 at 12:06:51AM +0200, Arnd Bergmann wrote:
On Thursday 13 June 2013 15:43:42 Maxime Ripard wrote:
+
+ ahb@8008 {
+ usb0: usb@8008 {
+ pinctrl-names = default;
+ pinctrl-0 = usb0_otg_cfa10036;
+ status = okay;
};
};
The patches all look good, just one trivial comment about the fragment above:
There is already a usb0 label in the imx28.dtsi file for the same
node. When you refer to the node from a board.dts file, either leave
out the redundant label, or use it to simplify the statements above
to the brief version:
usb0 {
pinctrl-names = default;
pinctrl-0 = usb0_otg_cfa10036;
status = okay;
};
Good to know, thanks!
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH 0/6] Add support for Allwinner A10s SoCs
Hi Linus, On Sun, Jun 09, 2013 at 06:36:01PM +0200, Maxime Ripard wrote: Hi everyone, This patch serie reworks a bit the pinctrl driver and adds the necessary bits needed to support the Allwinner A10s SoC. This SoC is a bit in between the A10 and A13. Notable differences with the A13 is the addition of an HDMI controller and of the EMAC. For the time being (ie until we find a proper datasheet for this SoCs), the clock definition is taken from the A10 one. This patches depends on the Add external interrupt support for Allwinner SoCs patch serie. Do you have any comments on the two patches on the pinctrl driver? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [linux-sunxi] [PATCH 5/6] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree
Hi Emilio,
On Fri, Jun 14, 2013 at 03:09:49PM -0300, Emilio López wrote:
Hi Maxime,
El 09/06/13 13:36, Maxime Ripard escribió:
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 75
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
Please add this on the sunxi target in arch/arm/boot/dts/Makefile so it
gets built on make dtbs.
(snip)
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_olinuxino;
+
+ power {
+ gpios = pio 4 3 0;
+ default-state = on;
+ };
Also, as discussed on IRC, I think it would be wise to change the name
on the LED node. The schematics have a 'power' led already that is
hard-wired to 3.3v, and this led node that you are declaring is referred
as 'led1' there. I suppose 'green' would be a suitable name to keep
consistency with other sunxi boards (namely cubieboard).
Other than that, my OLinuXino worked just fine after applying this
patchset, so
Tested-by: Emilio López emi...@elopez.com.ar
Thanks for your comments and the test.
I'll send a v2.
Maxime
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH 2/6] pinctrl: sunxi: Move the pins definitions to a separate header
Hi Linus, On Sun, Jun 16, 2013 at 01:03:09PM +0200, Linus Walleij wrote: On Sun, Jun 9, 2013 at 6:36 PM, Maxime Ripard maxime.rip...@free-electrons.com wrote: It will allow us to have a cleaner separation between the data needed by the driver to work, and the core logic of the driver in itself, and will allow having too much noise in the core driver in the future. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com Patch applied. Since you will anyway have to bring the ARM SoC branch on top of the pinctrl tree, I might as well apply this to my tree. Thanks for merging this. I applied the other patches except for the 5th one that Emilio commented on. If everything else fails, you'll have a nice development base in v3.11 with this in place, right? Yes, As far as I can see, we should have a pretty complete support for the GPIO/muxing/IRQ on the old allwinner SoCs (sun4i and sun5i) now. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv2] ARM: sunxi: Add Olimex A10s-Olinuxino-micro device tree
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Emilio López emi...@elopez.com.ar
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 76
2 files changed, 77 insertions(+)
create mode 100644 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c5..bae46c3 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-cubieboard.dtb \
sun4i-a10-mini-xplus.dtb \
sun4i-a10-hackberry.dtb \
+ sun5i-a10s-olinuxino-micro.dtb \
sun5i-a13-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
new file mode 100644
index 000..64dc0c4
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ sun5i-a10s.dtsi
+
+/ {
+ model = Olimex A10s-Olinuxino Micro;
+ compatible = olimex,a10s-olinuxino-micro, allwinner,sun5i-a10s;
+
+ soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy1;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
+
+ pinctrl@01c20800 {
+ led_pins_olinuxino: led_pins@0 {
+ allwinner,pins = PE3;
+ allwinner,function = gpio_out;
+ allwinner,drive = 1;
+ allwinner,pull = 0;
+ };
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+ };
+
+ uart2: serial@01c28800 {
+ pinctrl-names = default;
+ pinctrl-0 = uart2_pins_a;
+ status = okay;
+ };
+
+ uart3: serial@01c28c00 {
+ pinctrl-names = default;
+ pinctrl-0 = uart3_pins_a;
+ status = okay;
+ };
+ };
+
+ leds {
+ compatible = gpio-leds;
+ pinctrl-names = default;
+ pinctrl-0 = led_pins_olinuxino;
+
+ green {
+ label = a10s-olinuxino-micro:green:usr;
+ gpios = pio 4 3 0;
+ default-state = on;
+ };
+ };
+};
--
1.8.3.1
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Re: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
On Mon, Jun 17, 2013 at 12:36:47PM +0200, Oliver Schinagl wrote:
On 15-06-13 12:28, Tomasz Figa wrote:
+#define DRV_VERSION 1.0
What is this version thingy?
Is there a versioning scheme defined for this driver? Do you expect it to
be changed every modification of this driver?
I don't see any point of having such thing in a project with a version
control system, where you have all change history.
Well we export something to userspace, while trivial there is the
possibility it changes over time. Say A40 which outputs 256 bits
instead of the current 128 bits. That would validate a bump in
version number. It's purely so the user can be aware of differences
in the driver. So maybe DRV_A[BP]I_VERSION would be better?
Except that in that case, the userspace API won't change. You'll still
call read on the same file in sysfs. The only thing that will change
will be the number of bytes returned by your read function, which is
(or should be) totally fine.
+/* We read the entire key, but only return the requested byte. This is
of + * course slower then it could be and uses 4 times more reads as
needed but + * keeps code simpler.
I have no idea how often this is going to be read, but since the whole sid
is really small (16 bytes), maybe it would be better to simply read the ID
in probe to a buffer and then just memcpy from it in read().
The sid will be read once (well all 16 bytes) during probe and after
that only on user request. Right now we don't have a user (yet)
other then the sysfs entry.
In future, this key can be used to read the MAC (low reads) or AES
keys for example (also low reads).
Initially I had such an approach, but Maxime recommended against
having the value cached.
As I wrote to andy, the only 'more efficient' way would be to store
the previously read key and see on the next read if its the same, So
best case, we could save 4 reads. I think it makes the code
unnecessarily complex for something that is read so little.
I asked Oliver that because I felt like it could still be updated by the
user, and sysfs should report that.
And since it's not like it would be used extensively and very often,
it's not a big deal anyway.
+
+ if (offset = SID_SIZE)
+ goto exit;
return 0; ...
I did say in the changelog I opted for goto over return. But since
everybody keeps preferring returns (I personally like 'one single
exit point much more' I have already changed it all over to many
returns, who am I to argue :)
Yet, you don't have a single exit point neither, you have several of
them. You can say that you have a single return statement in your code,
which is true, yet you have several times a jump to this location, so we
can definitely say that you actually have several exit points. Please
also refer to the chapter 7 of the Documentation/CodingStyle file.
+ return (u8)sid_key;
Unnecessary casting.
Unnecessary because of the = 0xff above, or because you can put a
32bit int in an 8bit int without worries? (we only want the last
byte).
The latter. The 0xff only filter out non-relevant informations from
your 32-bits integer in that case, that's all, it doesn't do any
casting.
+ for (i = 0; i size; i++) {
+ if ((pos + i) = SID_SIZE || (pos 0))
+ break;
+ buf[i] = sunxi_sid_read_byte(sid_reg_base, pos + i);
+ }
This could be greatly simplified if you just read the whole sid to memory
in probe and memcpy from it here.
But can't because we don't want to cache it.
And we can't simply use memcpy, since we will need to do some endianness
conversions. The data stored in the SID are big-endian, while we're
running most likely in little endian mode.
+ if (!pdev-dev.of_node) {
+ dev_err(pdev-dev, No devicetree data available\n);
+ ret = -ENXIO;
+ goto exit;
+ }
What is this check for? You don't seem to need anything from dev.of_node
in this driver.
My understanding was, that when using the device tree, we check if
the device tree is atleast available. And we use
platform_get_resource, doesn't that get the data from the device
tree?
If there's no device tree, you won't be probed in the first place. And
resources get filled by the kernel from the device tree automatically at
boot, so you're safe to assume that the resources are there when you get
probed.
You need this check when you actually need some more informations from
the DT, the value of an additionnal property for example.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH] mxs: icoll: Add function to register an interrupt as FIQ source
MXS, unlike other ARM platforms, has no way to make a FIQ from an
interrupt from a driver, without poking directly into the icoll.
Add an exported function to do this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/mach-mxs/icoll.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 8fb23af..1bb16da 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -16,6 +16,7 @@
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
+#include linux/export.h
#include linux/kernel.h
#include linux/init.h
#include linux/irq.h
@@ -34,6 +35,7 @@
#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
#define BM_ICOLL_INTERRUPTn_ENABLE 0x0004
+#define BM_ICOLL_INTERRUPTn_FIQ_ENABLE 0x0010
#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
#define ICOLL_NUM_IRQS 128
@@ -41,6 +43,15 @@
static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
static struct irq_domain *icoll_domain;
+void mxs_icoll_set_irq_fiq(unsigned int irq)
+{
+ struct irq_data *d = irq_get_irq_data(irq);
+
+ __raw_writel(BM_ICOLL_INTERRUPTn_FIQ_ENABLE,
+icoll_base + HW_ICOLL_INTERRUPTn_SET(d-hwirq));
+}
+EXPORT_SYMBOL(mxs_icoll_set_irq_fiq);
+
static void icoll_ack_irq(struct irq_data *d)
{
/*
--
1.8.1.2
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[PATCH] gpio: mxs: Use set and clear capabilities of the gpio controller
The current driver doesn't use the set and clear registers found on the mxs gpio controller. This leads the generic gpio controller to be using some internal value to avoid looking up the value stored in the registers, making it behave pretty much like a cache. This raises some coherency problem when a gpio is not modified by the gpio controller, while it can easily be fixed by using the set and clear registers. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- drivers/gpio/gpio-mxs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-mxs.c b/drivers/gpio/gpio-mxs.c index 25000b0..f8e6af2 100644 --- a/drivers/gpio/gpio-mxs.c +++ b/drivers/gpio/gpio-mxs.c @@ -326,7 +326,8 @@ static int mxs_gpio_probe(struct platform_device *pdev) err = bgpio_init(port-bgc, pdev-dev, 4, port-base + PINCTRL_DIN(port), -port-base + PINCTRL_DOUT(port), NULL, +port-base + PINCTRL_DOUT(port) + MXS_SET, +port-base + PINCTRL_DOUT(port) + MXS_CLR, port-base + PINCTRL_DOE(port), NULL, 0); if (err) goto out_irqdesc_free; -- 1.8.1.2 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 6/6] ARM: sunxi: Add EMAC Controller to Hackberry dt
The Hackberry has a PHY that needs to be powered up through a GPIO, so
we need to use a fixed regulator here.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b9efac1..3514b37 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -23,10 +23,51 @@
};
soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy0;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ phy-supply = reg_emac_3v3;
+ status = okay;
+
+ phy0: ethernet-phy@0 {
+ reg = 0;
+ };
+ };
+
+ pio: pinctrl@01c20800 {
+ pinctrl-names = default;
+ pinctrl-0 = hackberry_hogs;
+
+ hackberry_hogs: hogs@0 {
+ allwinner,pins = PH19;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+ };
+
uart0: serial@01c28000 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_a;
status = okay;
};
};
+
+ regulators {
+ compatible = simple-bus;
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = regulator-fixed;
+ regulator-name = emac-3v3;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ enable-active-high;
+ gpio = pio 7 19 0;
+ };
+ };
};
--
1.8.1.2
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[PATCH 5/6] ARM: cubieboard: Enable ethernet (EMAC) support in dts
From: Stefan Roese s...@denx.de
Signed-off-by: Stefan Roese s...@denx.de
---
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..32d9b18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -27,6 +27,21 @@
};
soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy0;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ status = okay;
+
+ phy0: ethernet-phy@0 {
+ reg = 0;
+ };
+ };
+
pinctrl@01c20800 {
led_pins_cubieboard: led_pins@0 {
allwinner,pins = PH20, PH21;
--
1.8.1.2
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[PATCH 4/6] ARM: sunxi: Add EMAC controller node to sun4i DTSI
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ff1f41f..983da33 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -163,6 +163,22 @@
reg = 0x01c2 0x30;
ranges;
+ emac: ethernet@01c0b000 {
+ compatible = allwinner,sun4i-emac;
+ reg = 0x01c0b000 0x1000;
+ interrupts = 55;
+ clocks = ahb_gates 17;
+ status = disabled;
+ };
+
+ mdio@01c0b080 {
+ compatible = allwinner,sun4i-mdio;
+ reg = 0x01c0b080 0x14;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
intc: interrupt-controller@01c20400 {
compatible = allwinner,sun4i-ic;
reg = 0x01c20400 0x400;
--
1.8.1.2
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[PATCH 3/6] ARM: sun4i: Add muxing options for the ethernet controller
The EMAC only has one pinset available for muxing, so hopefully, we
cover all cases.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..ff1f41f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,17 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = PA0, PA1, PA2,
+ PA3, PA4, PA5, PA6,
+ PA7, PA8, PA9, PA10,
+ PA11, PA12, PA13, PA14,
+ PA15, PA16;
+ allwinner,function = emac;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
timer@01c20c00 {
--
1.8.1.2
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[PATCH 1/6] net: Add EMAC ethernet driver found on Allwinner A10 SoC's
From: Stefan Roese s...@denx.de
The Allwinner A10 has an ethernet controller that seem to be developped
internally by them.
The exact feature set of this controller is unknown, since there is no
public documentation for this IP, and this driver is mostly the one
published by Allwinner that has been heavily cleaned up.
Signed-off-by: Stefan Roese s...@denx.de
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../bindings/net/allwinner,sun4i-emac.txt | 22 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/allwinner/Kconfig | 36 +
drivers/net/ethernet/allwinner/Makefile| 5 +
drivers/net/ethernet/allwinner/sun4i-emac.c| 960 +
drivers/net/ethernet/allwinner/sun4i-emac.h| 108 +++
7 files changed, 1133 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
create mode 100644 drivers/net/ethernet/allwinner/Kconfig
create mode 100644 drivers/net/ethernet/allwinner/Makefile
create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
new file mode 100644
index 000..b90bfcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
@@ -0,0 +1,22 @@
+* Allwinner EMAC ethernet controller
+
+Required properties:
+- compatible: should be allwinner,sun4i-emac.
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+- phy: A phandle to a phy node defining the PHY address (as the reg
+ property, a single integer).
+- clocks: A phandle to the reference clock for this device
+
+Optional properties:
+- (local-)mac-address: mac address to be used by this driver
+
+Example:
+
+emac: ethernet@01c0b000 {
+ compatible = allwinner,sun4i-emac;
+ reg = 0x01c0b000 0x1000;
+ interrupts = 55;
+ clocks = ahb_gates 17;
+ phy = phy0;
+};
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index ed956e0..18fd6fb 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -20,6 +20,7 @@ config SUNGEM_PHY
source drivers/net/ethernet/3com/Kconfig
source drivers/net/ethernet/adaptec/Kconfig
source drivers/net/ethernet/aeroflex/Kconfig
+source drivers/net/ethernet/allwinner/Kconfig
source drivers/net/ethernet/alteon/Kconfig
source drivers/net/ethernet/amd/Kconfig
source drivers/net/ethernet/apple/Kconfig
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 8268d85..009da27 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/
obj-$(CONFIG_NET_VENDOR_8390) += 8390/
obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/
obj-$(CONFIG_GRETH) += aeroflex/
+obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
obj-$(CONFIG_NET_VENDOR_AMD) += amd/
obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
diff --git a/drivers/net/ethernet/allwinner/Kconfig
b/drivers/net/ethernet/allwinner/Kconfig
new file mode 100644
index 000..5d20fb0
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -0,0 +1,36 @@
+#
+# Allwinner device configuration
+#
+
+config NET_VENDOR_ALLWINNER
+ bool Allwinner devices
+ default y
+ depends on ARCH_SUNXI
+ ---help---
+ If you have a network (Ethernet) card belonging to this
+class, say Y and read the Ethernet-HOWTO, available from
+http://www.tldp.org/docs.html#howto.
+
+Note that the answer to this question doesn't directly
+affect the kernel: saying N will just cause the configurator
+to skip all the questions about Davicom cards. If you say Y,
+you will be asked for your specific card in the following
+questions.
+
+if NET_VENDOR_ALLWINNER
+
+config SUN4I_EMAC
+tristate Allwinner A10 EMAC support
+ depends on ARCH_SUNXI
+ depends on OF
+ select CRC32
+ select NET_CORE
+ select MII
+ select REGULATOR_FIXED_VOLTAGE
+---help---
+ Support for Allwinner A10 EMAC ethernet driver.
+
+ To compile this driver as a module, choose M here. The module
+ will be called sun4i-emac.
+
+endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile
b/drivers/net/ethernet/allwinner/Makefile
new file mode 100644
index 000..03129f7
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Allwinner device drivers.
+#
+
+obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c
b/drivers/net/ethernet/allwinner/sun4i-emac.c
new file mode 100644
index
[PATCH 2/6] net: Add MDIO bus driver for the Allwinner EMAC
This patch adds a separate driver for the MDIO interface of the
Allwinner ethernet controllers.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../bindings/net/allwinner,sun4i-mdio.txt | 26 +++
drivers/net/ethernet/allwinner/Kconfig | 8 +
drivers/net/ethernet/allwinner/Makefile| 1 +
drivers/net/ethernet/allwinner/sun4i-mdio.c| 191 +
4 files changed, 226 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
create mode 100644 drivers/net/ethernet/allwinner/sun4i-mdio.c
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
new file mode 100644
index 000..00b9f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
@@ -0,0 +1,26 @@
+* Allwinner A10 MDIO Ethernet Controller interface
+
+Required properties:
+- compatible: should be allwinner,sun4i-mdio.
+- reg: address and length of the register set for the device.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Example at the SoC level:
+mdio@01c0b080 {
+ compatible = allwinner,sun4i-mdio;
+ reg = 0x01c0b080 0x14;
+ #address-cells = 1;
+ #size-cells = 0;
+};
+
+And at the board level:
+
+mdio@01c0b080 {
+ phy-supply = reg_emac_3v3;
+
+ phy0: ethernet-phy@0 {
+ reg = 0;
+ };
+};
diff --git a/drivers/net/ethernet/allwinner/Kconfig
b/drivers/net/ethernet/allwinner/Kconfig
index 5d20fb0..7bbd500 100644
--- a/drivers/net/ethernet/allwinner/Kconfig
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -27,10 +27,18 @@ config SUN4I_EMAC
select NET_CORE
select MII
select REGULATOR_FIXED_VOLTAGE
+ select PHYLIB
---help---
Support for Allwinner A10 EMAC ethernet driver.
To compile this driver as a module, choose M here. The module
will be called sun4i-emac.
+config SUN4I_MDIO
+ tristate Allwinner sun4i MDIO interface support
+ ---help---
+ This driver supports the MDIO interface found in the network
+ interface units of the Allwinner SoC that have an EMAC (A10,
+ A12, A10s, etc.)
+
endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile
b/drivers/net/ethernet/allwinner/Makefile
index 03129f7..95eaa31 100644
--- a/drivers/net/ethernet/allwinner/Makefile
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
+obj-$(CONFIG_SUN4I_MDIO) += sun4i-mdio.o
\ No newline at end of file
diff --git a/drivers/net/ethernet/allwinner/sun4i-mdio.c
b/drivers/net/ethernet/allwinner/sun4i-mdio.c
new file mode 100644
index 000..00e432c
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/sun4i-mdio.c
@@ -0,0 +1,191 @@
+/*
+ * Allwinner EMAC MDIO interface driver
+ *
+ * Copyright 2012-2013 Stefan Roese s...@denx.de
+ * Copyright 2013 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997 Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/delay.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of_address.h
+#include linux/of_mdio.h
+#include linux/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+
+#define EMAC_MAC_MCMD_REG (0x00)
+#define EMAC_MAC_MADR_REG (0x04)
+#define EMAC_MAC_MWTD_REG (0x08)
+#define EMAC_MAC_MRDD_REG (0x0c)
+#define EMAC_MAC_MIND_REG (0x10)
+#define EMAC_MAC_SSRR_REG (0x14)
+
+#define MDIO_TIMEOUT (msecs_to_jiffies(100))
+
+struct sun4i_mdio_data {
+ void __iomem*membase;
+ struct regulator*regulator;
+};
+
+static int sun4i_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct sun4i_mdio_data *data = bus-priv;
+ unsigned long start_jiffies;
+ int value;
+
+ /* issue the phy address and reg */
+ writel((mii_id 8) | regnum, data-membase + EMAC_MAC_MADR_REG);
+ /* pull up the phy io line */
+ writel(0x1, data-membase + EMAC_MAC_MCMD_REG);
+
+ /* Wait read complete */
+ start_jiffies = jiffies;
+ while (readl(data-membase + EMAC_MAC_MIND_REG) 0x1) {
+ if (time_after(start_jiffies,
+ start_jiffies + MDIO_TIMEOUT))
+ return -ETIMEDOUT;
+ msleep(1);
+ }
+
+ /* push down the phy io line */
+ writel(0x0, data-membase + EMAC_MAC_MCMD_REG);
+ /* and read data */
+ value = readl(data-membase + EMAC_MAC_MRDD_REG);
+
+ return value;
+}
+
+static int
[PATCH] ARM: sunxi: Fix Mini X-plus device tree build
Commit b00adbe0 (ARM: sunxi: Rename uart nodes to serial) changed the
node names in the DTSI, changes that were not accordingly made to the
Mini X-Plus device tree. This breakage slipped through because it was
not properly declared in the Makefile.
Fix both issues.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
This is 3.10-rc* material.
arch/arm/boot/dts/Makefile | 4 +++-
arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 4 ++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c62558..6d774d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -147,7 +147,9 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
-dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
+dtb-$(CONFIG_ARCH_SUNXI) += \
+ sun4i-a10-cubieboard.dtb \
+ sun4i-a10-mini-xplus.dtb \
sun4i-a10-hackberry.dtb \
sun5i-a13-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 4a7c35d..078ed7f 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -22,8 +22,8 @@
bootargs = earlyprintk console=ttyS0,115200;
};
- soc {
- uart0: uart@01c28000 {
+ soc@01c2 {
+ uart0: serial@01c28000 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_a;
status = okay;
--
1.8.1.2
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[PATCH 1/2] clk: sun5i: Add compatibles for Allwinner A13
The A13 has a lot less clocks than the one found in the Allwinner A10.
Add these stripped down clocks to the clock driver and in the
documentation.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Documentation/devicetree/bindings/clock/sunxi.txt | 117 +++--
.../bindings/clock/sunxi/sun4i-a10-gates.txt | 93
.../bindings/clock/sunxi/sun5i-a13-gates.txt | 58 ++
drivers/clk/sunxi/clk-sunxi.c | 31 --
4 files changed, 187 insertions(+), 112 deletions(-)
create mode 100644
Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
create mode 100644
Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 729f524..d495521 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -12,22 +12,30 @@ Required properties:
allwinner,sun4i-axi-clk - for the AXI clock
allwinner,sun4i-axi-gates-clk - for the AXI gates
allwinner,sun4i-ahb-clk - for the AHB clock
- allwinner,sun4i-ahb-gates-clk - for the AHB gates
+ allwinner,sun4i-ahb-gates-clk - for the AHB gates on A10
+ allwinner,sun5i-a13-ahb-gates-clk - for the AHB gates on A13
allwinner,sun4i-apb0-clk - for the APB0 clock
- allwinner,sun4i-apb0-gates-clk - for the APB0 gates
+ allwinner,sun4i-apb0-gates-clk - for the APB0 gates on A10
+ allwinner,sun5i-a13-apb0-gates-clk - for the APB0 gates on A13
allwinner,sun4i-apb1-clk - for the APB1 clock
allwinner,sun4i-apb1-mux-clk - for the APB1 clock muxing
- allwinner,sun4i-apb1-gates-clk - for the APB1 gates
+ allwinner,sun4i-apb1-gates-clk - for the APB1 gates on A10
+ allwinner,sun5i-a13-apb1-gates-clk - for the APB1 gates on A13
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
- allwinner,sun4i-*-gates-clk where it shall be set to 1
+ allwinner,*-gates-clk where it shall be set to 1
-Additionally, allwinner,sun4i-*-gates-clk clocks require:
+Additionally, allwinner,*-gates-clk clocks require:
- clock-output-names : the corresponding gate names that the clock controls
+Clock consumers should specify the desired clocks they use with a
+clocks phandle cell. Consumers that are using a gated clock should
+provide an additional ID in their clock property. The values of this
+ID are documented in sunxi/soc-gates.txt.
+
For example:
osc24M: osc24M@01c20050 {
@@ -50,102 +58,3 @@ cpu: cpu@01c20054 {
reg = 0x01c20054 0x4;
clocks = osc32k, osc24M, pll1;
};
-
-
-
-Gate clock outputs
-
-The allwinner,sun4i-*-gates-clk clocks provide several gatable outputs;
-their corresponding offsets as present on sun4i are listed below. Note that
-some of these gates are not present on sun5i.
-
- * AXI gates (allwinner,sun4i-axi-gates-clk)
-
-DRAM0
-
- * AHB gates (allwinner,sun4i-ahb-gates-clk)
-
-USB00
-EHCI0 1
-OHCI0 2*
-EHCI1 3
-OHCI1 4*
-SS 5
-DMA 6
-BIST7
-MMC08
-MMC19
-MMC210
-MMC311
-MS 12**
-NAND13
-SDRAM 14
-
-ACE 16
-EMAC17
-TS 18
-
-SPI020
-SPI121
-SPI222
-SPI323
[PATCH 2/2] ARM: sun5i: Update the clock compatible strings
The Allwinner A13 has a smaller clock set than the one found in the A10.
Fix the A13 device tree and documentation to reflect this.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a13.dtsi | 35 ---
1 file changed, 12 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f..8ba65c1 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -95,20 +95,15 @@
ahb_gates: ahb_gates@01c20060 {
#clock-cells = 1;
- compatible = allwinner,sun4i-ahb-gates-clk;
+ compatible = allwinner,sun5i-a13-ahb-gates-clk;
reg = 0x01c20060 0x8;
clocks = ahb;
- clock-output-names = ahb_usb0, ahb_ehci0,
- ahb_ohci0, ahb_ehci1, ahb_ohci1, ahb_ss,
- ahb_dma, ahb_bist, ahb_mmc0, ahb_mmc1,
- ahb_mmc2, ahb_mmc3, ahb_ms, ahb_nand,
- ahb_sdram, ahb_ace, ahb_emac, ahb_ts,
- ahb_spi0, ahb_spi1, ahb_spi2, ahb_spi3,
- ahb_pata, ahb_sata, ahb_gps, ahb_ve,
- ahb_tvd, ahb_tve0, ahb_tve1, ahb_lcd0,
- ahb_lcd1, ahb_csi0, ahb_csi1, ahb_hdmi,
- ahb_de_be0, ahb_de_be1, ahb_de_fe0,
- ahb_de_fe1, ahb_mp, ahb_mali400;
+ clock-output-names = ahb_usbotg, ahb_ehci,
ahb_ohci,
+ ahb_ss, ahb_dma, ahb_bist, ahb_mmc0,
+ ahb_mmc1, ahb_mmc2, ahb_nand, ahb_sdram,
+ ahb_spi0, ahb_spi1, ahb_spi2,
ahb_stimer,
+ ahb_ve, ahb_lcd, ahb_csi, ahb_de_be,
+ ahb_de_fe, ahb_iep, ahb_mali400;
};
apb0: apb0@01c20054 {
@@ -120,15 +115,13 @@
apb0_gates: apb0_gates@01c20068 {
#clock-cells = 1;
- compatible = allwinner,sun4i-apb0-gates-clk;
+ compatible = allwinner,sun5i-a13-apb0-gates-clk;
reg = 0x01c20068 0x4;
clocks = apb0;
- clock-output-names = apb0_codec, apb0_spdif,
- apb0_ac97, apb0_iis, apb0_pio, apb0_ir0,
- apb0_ir1, apb0_keypad;
+ clock-output-names = apb0_codec, apb0_pio,
apb0_ir;
};
- /* dummy is pll62 */
+ /* dummy is pll6 */
apb1_mux: apb1_mux@01c20058 {
#clock-cells = 0;
compatible = allwinner,sun4i-apb1-mux-clk;
@@ -145,15 +138,11 @@
apb1_gates: apb1_gates@01c2006c {
#clock-cells = 1;
- compatible = allwinner,sun4i-apb1-gates-clk;
+ compatible = allwinner,sun5i-a13-apb1-gates-clk;
reg = 0x01c2006c 0x4;
clocks = apb1;
clock-output-names = apb1_i2c0, apb1_i2c1,
- apb1_i2c2, apb1_can, apb1_scr,
- apb1_ps20, apb1_ps21, apb1_uart0,
- apb1_uart1, apb1_uart2, apb1_uart3,
- apb1_uart4, apb1_uart5, apb1_uart6,
- apb1_uart7;
+ apb1_i2c2, apb1_uart1, apb1_uart3;
};
};
--
1.8.1.2
--
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Re: [PATCH] mxs: icoll: Add function to register an interrupt as FIQ source
Hi Shawn, Le 02/05/2013 04:39, Shawn Guo a écrit : On Mon, Apr 29, 2013 at 03:58:37PM +0200, Maxime Ripard wrote: MXS, unlike other ARM platforms, How are other ARM platforms handling that? Just like that. You can look at mxc_set_irq_fiq in arch/arm/mach-imx/irq-common.c or s3c24xx_set_fiq in arch/arm/mach-s3c24xx/irq.c I've also thought about declaring a IRQ type and using the .irq_set_type to register an interrupt as a FIQ source, but since FIQ are ARM-specific, it's probably a bad idea. has no way to make a FIQ from an interrupt from a driver, without poking directly into the icoll. Add an exported function to do this. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- arch/arm/mach-mxs/icoll.c | 11 +++ This will become drivers/irqchip/irq-mxs.c after the merge window. Ok, I'll rebase and repost then. Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 5/5] ARM: sun5i: olinuxino: Enable the i2c controllers
The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
pinctrl-0 = uart1_pins_b;
status = okay;
};
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+ };
+
+ i2c1: i2c@01c2b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+ };
+
+ i2c2: i2c@01c2b400 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins_a;
+ status = okay;
+ };
};
leds {
--
1.8.1.2
--
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[PATCH 4/5] ARM: sun5i: dt: Add i2c muxing options
The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a13.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = PB0, PB1;
+ allwinner,function = i2c0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = PB15, PB16;
+ allwinner,function = i2c1;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = PB17, PB18;
+ allwinner,function = i2c2;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
};
timer@01c20c00 {
--
1.8.1.2
--
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[PATCH 2/5] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++
arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
clocks = apb1_gates 23;
status = disabled;
};
+
+ i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b000 0x400;
+ interrupts = 8;
+ clocks = apb1_gates 1;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b400 0x400;
+ interrupts = 9;
+ clocks = apb1_gates 2;
+ clock-frequency = 10;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
clocks = apb1_gates 19;
status = disabled;
};
+
+ i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b000 0x400;
+ interrupts = 8;
+ clocks = apb1_gates 1;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b400 0x400;
+ interrupts = 9;
+ clocks = apb1_gates 2;
+ clock-frequency = 10;
+ status = disabled;
+ };
};
};
--
1.8.1.2
--
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[PATCH 3/5] ARM: sun4i: dt: Add i2c muxing options
The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = PB0, PB1;
+ allwinner,function = i2c0;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = PB18, PB19;
+ allwinner,function = i2c1;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = PB20, PB21;
+ allwinner,function = i2c2;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
};
timer@01c20c00 {
--
1.8.1.2
--
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[PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.
Notable missing feature is 10-bit addressing.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/i2c/i2c-sunxi.txt | 19 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-sunxi.c | 441 +
4 files changed, 471 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
create mode 100644 drivers/i2c/busses/i2c-sunxi.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be allwinner,sun4i-i2c.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..327a49b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
This driver can also be built as a module. If so, the module
will be called i2c-stu300.
+config I2C_SUNXI
+ tristate Allwinner A1X I2C controller
+ depends on ARCH_SUNXI
+ help
+ If you say yes to this option, support will be included for the
+ I2C controller embedded in Allwinner A1X SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-sunxi.
+
config I2C_TEGRA
tristate NVIDIA Tegra internal I2C controller
depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)+= i2c-sunxi.o
obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o
obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 000..f9f8bd4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,441 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/completion.h
+#include linux/err.h
+#include linux/i2c.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of_address.h
+#include linux/of_irq.h
+#include linux/platform_device.h
+
+#define SUNXI_I2C_ADDR_REG (0x00)
+#define SUNXI_I2C_ADDR_ADDR(v) ((v 0x7f) 1)
+#define SUNXI_I2C_XADDR_REG(0x04)
+#define SUNXI_I2C_DATA_REG (0x08)
+#define SUNXI_I2C_CNTR_REG (0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAGBIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_STARTBIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE BIT(7)
+#define SUNXI_I2C_STA_REG (0x10)
+#define SUNXI_I2C_STA_BUS_ERROR(0x00)
+#define SUNXI_I2C_STA_START(0x08)
+#define SUNXI_I2C_STA_START_REPEAT (0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK (0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK (0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK (0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK (0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK (0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK (0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK (0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK (0x58)
+#define SUNXI_I2C_CCR_REG (0x14)
+#define SUNXI_I2C_CCR_DIV_N(val) (val 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val) ((val 0xf) 3
[PATCH 1/5] i2c: sunxi: Add Allwinner A1X i2c driver
This patch implements a basic driver for the I2C host driver found on
the Allwinner A10, A13 and A31 SoCs.
Notable missing feature is 10-bit addressing.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/i2c/i2c-sunxi.txt | 19 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-sunxi.c | 441 +
4 files changed, 471 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
create mode 100644 drivers/i2c/busses/i2c-sunxi.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
new file mode 100644
index 000..40c16d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-sunxi.txt
@@ -0,0 +1,19 @@
+Allwinner SoC I2C controller
+
+Required properties:
+- compatible : Should be allwinner,sun4i-i2c.
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks : The parent clock feeding the I2C controller.
+
+Recommended properties:
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Example:
+i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index adfee98..327a49b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -706,6 +706,16 @@ config I2C_STU300
This driver can also be built as a module. If so, the module
will be called i2c-stu300.
+config I2C_SUNXI
+ tristate Allwinner A1X I2C controller
+ depends on ARCH_SUNXI
+ help
+ If you say yes to this option, support will be included for the
+ I2C controller embedded in Allwinner A1X SoCs.
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-sunxi.
+
config I2C_TEGRA
tristate NVIDIA Tegra internal I2C controller
depends on ARCH_TEGRA
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..7225818 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
+obj-$(CONFIG_I2C_SUNXI)+= i2c-sunxi.o
obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o
obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o
obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
diff --git a/drivers/i2c/busses/i2c-sunxi.c b/drivers/i2c/busses/i2c-sunxi.c
new file mode 100644
index 000..f9f8bd4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sunxi.c
@@ -0,0 +1,441 @@
+/*
+ * Allwinner A1X SoCs i2c controller driver.
+ *
+ * Copyright (C) 2013 Maxime Ripard
+ *
+ * Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/clk.h
+#include linux/completion.h
+#include linux/err.h
+#include linux/i2c.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of_address.h
+#include linux/of_irq.h
+#include linux/platform_device.h
+
+#define SUNXI_I2C_ADDR_REG (0x00)
+#define SUNXI_I2C_ADDR_ADDR(v) ((v 0x7f) 1)
+#define SUNXI_I2C_XADDR_REG(0x04)
+#define SUNXI_I2C_DATA_REG (0x08)
+#define SUNXI_I2C_CNTR_REG (0x0c)
+#define SUNXI_I2C_CNTR_ASSERT_ACK BIT(2)
+#define SUNXI_I2C_CNTR_INT_FLAGBIT(3)
+#define SUNXI_I2C_CNTR_MASTER_STOP BIT(4)
+#define SUNXI_I2C_CNTR_MASTER_STARTBIT(5)
+#define SUNXI_I2C_CNTR_BUS_ENABLE BIT(6)
+#define SUNXI_I2C_CNTR_INT_ENABLE BIT(7)
+#define SUNXI_I2C_STA_REG (0x10)
+#define SUNXI_I2C_STA_BUS_ERROR(0x00)
+#define SUNXI_I2C_STA_START(0x08)
+#define SUNXI_I2C_STA_START_REPEAT (0x10)
+#define SUNXI_I2C_STA_MASTER_WADDR_ACK (0x18)
+#define SUNXI_I2C_STA_MASTER_WADDR_NAK (0x20)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_ACK (0x28)
+#define SUNXI_I2C_STA_MASTER_DATA_SENT_NAK (0x30)
+#define SUNXI_I2C_STA_MASTER_RADDR_ACK (0x40)
+#define SUNXI_I2C_STA_MASTER_RADDR_NAK (0x48)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_ACK (0x50)
+#define SUNXI_I2C_STA_MASTER_DATA_RECV_NAK (0x58)
+#define SUNXI_I2C_CCR_REG (0x14)
+#define SUNXI_I2C_CCR_DIV_N(val) (val 0x3)
+#define SUNXI_I2C_CCR_DIV_M(val) ((val 0xf) 3
[PATCH 3/5] ARM: sun4i: dt: Add i2c muxing options
The i2c controller found on the Allwinner A10 has only one muxing option
available for each controller. Add them to the dtsi
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 311dcd4..63f6716 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = PB0, PB1;
+ allwinner,function = i2c0;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = PB18, PB19;
+ allwinner,function = i2c1;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = PB20, PB21;
+ allwinner,function = i2c2;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
};
timer@01c20c00 {
--
1.8.1.2
--
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[PATCH 5/5] ARM: sun5i: olinuxino: Enable the i2c controllers
The A13-Olinuxino makes use of the 3 i2c controllers found on the Allwinner
A13. Enable them in the device tree.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca5506..80497e3 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
pinctrl-0 = uart1_pins_b;
status = okay;
};
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+ };
+
+ i2c1: i2c@01c2b000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+ };
+
+ i2c2: i2c@01c2b400 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins_a;
+ status = okay;
+ };
};
leds {
--
1.8.1.2
--
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[PATCH 4/5] ARM: sun5i: dt: Add i2c muxing options
The i2c controller found on the Allwinner A13 has only one muxing option
available for each controller. Add them to the dtsi
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun5i-a13.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 16df784..450b410 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -182,6 +182,27 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = PB0, PB1;
+ allwinner,function = i2c0;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = PB15, PB16;
+ allwinner,function = i2c1;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = PB17, PB18;
+ allwinner,function = i2c2;
+ allwinner,drive = 0;
+ allwinner,pull = 1;
+ };
};
timer@01c20c00 {
--
1.8.1.2
--
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[PATCH 2/5] ARM: sunxi: dt: Add i2c controller nodes to the DTSI
The Allwinner A10 and A13 both have 3 i2c controller embedded.
Add those to the common sunxi dtsi.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 27 +++
arch/arm/boot/dts/sun5i-a13.dtsi | 27 +++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..311dcd4 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -292,5 +292,32 @@
clocks = apb1_gates 23;
status = disabled;
};
+
+ i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b000 0x400;
+ interrupts = 8;
+ clocks = apb1_gates 1;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b400 0x400;
+ interrupts = 9;
+ clocks = apb1_gates 2;
+ clock-frequency = 10;
+ status = disabled;
+ };
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 8ba65c1..16df784 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -215,5 +215,32 @@
clocks = apb1_gates 19;
status = disabled;
};
+
+ i2c0: i2c@01c2ac00 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2ac00 0x400;
+ interrupts = 7;
+ clocks = apb1_gates 0;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b000 0x400;
+ interrupts = 8;
+ clocks = apb1_gates 1;
+ clock-frequency = 10;
+ status = disabled;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = allwinner,sun4i-i2c;
+ reg = 0x01c2b400 0x400;
+ interrupts = 9;
+ clocks = apb1_gates 2;
+ clock-frequency = 10;
+ status = disabled;
+ };
};
};
--
1.8.1.2
--
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Re: [PATCH] net: sun4i-emac: remove erroneous assignment
Hi Arnd, On Mon, Jun 03, 2013 at 11:36:50PM +0200, Arnd Bergmann wrote: The newly added sun4i-emac driver causes a build error when CONFIG_NET_POLL_CONTROLLER is set, because it attempts to assign a pointer to netdev-poll_controller, which has been replaced with ops-ndo_poll_controller in 2.6.31! The correct assignment is present as well, so we just need to remove the wrong one. Thanks for fixing this, Acked-by: Maxime Ripard maxime.rip...@anandra.org Maxime -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 10/10] arm: add basic support for Rockchip RK3066a boards
Hi Thomas, On Wed, Jun 05, 2013 at 09:11:19AM +0200, Thomas Petazzoni wrote: Dear Heiko Stübner, On Mon, 3 Jun 2013 01:02:20 +0200, Heiko Stübner wrote: index 000..a2d8c70 --- /dev/null +++ b/arch/arm/mach-rockchip/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-$(CONFIG_ARCH_ROCKCHIP) := 0x60408000 +params_phys-$(CONFIG_ARCH_ROCKCHIP):= 0x60088000 +initrd_phys-$(CONFIG_ARCH_ROCKCHIP):= 0x6080 Thanks to the AUTO_ZRELADDR thing that you're using as part of the MULTIPLATFORM support, this Makefile.boot file is no longer useful. See mach-socfpga, mach-mvebu, mach-bcm2835, mach-bcm, mach-highbank, etc. Cc'ing Maxime Ripard, since I see that mach-sunxi does have a Makefile.boot, even though I believe it is not needed. Yes, it is a left-over and should be removed obviously. Thanks for reminding it to me :) Maxime -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [Arm-netbook] getting allwinner SoC support upstream (was Re: Uploading linux (3.9.4-1))
Hi everyone, On Thu, Jun 06, 2013 at 09:00:00AM -0700, Olof Johansson wrote: On Thu, Jun 6, 2013 at 8:13 AM, jonsm...@gmail.com jonsm...@gmail.com wrote: On Wed, Jun 5, 2013 at 7:54 PM, luke.leighton luke.leigh...@gmail.com wrote: augh. ok. solutions. what are the solutions here? Luke if you really want to fix this a good solution is to have Allwinner join Linaro and provide an engineer to the Linaro effort. That engineer will get educated on the right way to do kernel development and he can pass that knowledge back to Allwinner each day as he learns it. There's no need for anybody to join Linaro to contribute upstream. That's a crazy notion. Listen, Allwinner isn't working in a vacuum, believe it or not. I've talked to them, so has Arnd and other people working on ARM, including Maxime Ripard, who's been reimplementing upstream support for their platform. Everybody is interested in the right things happening, it's just a matter of figuring out how to do it. The right people are already talking. I should also add that Allwinner not only talked to us already, but also expressed interest in doing actual modern kernel development (like using recently introduced kernel frameworks, like the clk framework). I've received patches from them already for private reviews, they began to show up on the kernel mailing lists, they asked to be CCed on the patches I send upstream, they're even the one that reached out to me when the early support for their chips was released. So, like Olof said, they aren't in a vacuum, they are very aware of the mainline kernel and speak a decent english. So yes, Allwinner has an evil vendor tree (c), with a solution similar yet inferior (because not generic enough) to the device tree, but they show interest on going down the mainline road. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
Hi Greg,
On Mon, Jun 17, 2013 at 03:58:47PM -0700, Greg KH wrote:
On Mon, Jun 17, 2013 at 10:59:37PM +0200, Oliver Schinagl wrote:
[..]
+static int __init sunxi_sid_probe(struct platform_device *pdev)
+{
+ u8 entropy[SID_SIZE];
+ unsigned int i;
+ struct resource *res;
+ void __iomem *sid_reg_base;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ sid_reg_base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(sid_reg_base))
+ return PTR_ERR(sid_reg_base);
+ platform_set_drvdata(pdev, sid_reg_base);
+
+ ret = device_create_bin_file(pdev-dev, sid_bin_attr);
+ if (ret)
+ return ret;
You just raced with userspace, having the file show up after the device
was announced to users that it was there. Please use the proper device
file api to add default attributes to prevent this from happening.
Sorry if the question looks dumb, but what kind of race can we generate
here?
The device_create_bin_file is the last call that we make (if we except
the entropy stuff, but it doesn't really matter here), so after we
created the file, we have everything properly initialised so that our
functions can be called, right?
And another dumb question for you, what is the proper device file API
you are referring to ? :)
Thanks!
Maxime
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Re: [PATCH 1/2] Initial support for Allwinner's Security ID fuses
On Mon, Jun 24, 2013 at 09:04:40AM -0700, Greg KH wrote:
On Mon, Jun 24, 2013 at 11:29:42AM +0200, Maxime Ripard wrote:
Hi Greg,
On Mon, Jun 17, 2013 at 03:58:47PM -0700, Greg KH wrote:
On Mon, Jun 17, 2013 at 10:59:37PM +0200, Oliver Schinagl wrote:
[..]
+static int __init sunxi_sid_probe(struct platform_device *pdev)
+{
+ u8 entropy[SID_SIZE];
+ unsigned int i;
+ struct resource *res;
+ void __iomem *sid_reg_base;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ sid_reg_base = devm_ioremap_resource(pdev-dev, res);
+ if (IS_ERR(sid_reg_base))
+ return PTR_ERR(sid_reg_base);
+ platform_set_drvdata(pdev, sid_reg_base);
+
+ ret = device_create_bin_file(pdev-dev, sid_bin_attr);
+ if (ret)
+ return ret;
You just raced with userspace, having the file show up after the device
was announced to users that it was there. Please use the proper device
file api to add default attributes to prevent this from happening.
Sorry if the question looks dumb, but what kind of race can we generate
here?
Userspace gets told about the device from the driver core, udev runs and
reads all of the attributes, then your probe function comes along and
adds a new attribute. Userspace will then not know about it at all.
Hmm, I see.
Thanks for the explanations!
Maxime
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Re: [PATCH 1/2] fb: backlight: HX8357: Make IM pins optionnal
Hi Jean Christophe,
On Mon, Jun 24, 2013 at 04:26:45PM +0200, Jean-Christophe PLAGNIOL-VILLARD
wrote:
On 20:27 Fri 21 Jun , Alexandre Belloni wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/video/backlight/hx8357.c | 53
+++-
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/drivers/video/backlight/hx8357.c
b/drivers/video/backlight/hx8357.c
index a0482b5..69f5672 100644
--- a/drivers/video/backlight/hx8357.c
+++ b/drivers/video/backlight/hx8357.c
@@ -76,6 +76,7 @@ struct hx8357_data {
unsignedreset;
struct spi_device *spi;
int state;
+ u8 use_im_pins;
boolean please
Ok.
};
static u8 hx8357_seq_power[] = {
@@ -250,9 +251,11 @@ static int hx8357_lcd_init(struct lcd_device *lcdev)
* Set the interface selection pins to SPI mode, with three
* wires
*/
- gpio_set_value_cansleep(lcd-im_pins[0], 1);
- gpio_set_value_cansleep(lcd-im_pins[1], 0);
- gpio_set_value_cansleep(lcd-im_pins[2], 1);
+ if (lcd-use_im_pins) {
+ gpio_set_value_cansleep(lcd-im_pins[0], 1);
+ gpio_set_value_cansleep(lcd-im_pins[1], 0);
+ gpio_set_value_cansleep(lcd-im_pins[2], 1);
+ }
base on the dt probe you may have gpios betwee 0 to HX8357_NUM_IM_PINS
so this look wrong
How so?
HX8357_NUM_IM_PINS is defined to 3, the probe checks to see if we
actually have HX8357_NUM_IM_PINS, otherwise returns an error, what is
wrong in setting these pins here?
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH 2/3] ARM: mxs: dt: Add Crystalfontz CFA-10056 device tree
;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ hx8369: hx8369@0 {
+ compatible = himax,hx8369a, himax,hx8369;
+ reg = 0;
+ spi-max-frequency = 10;
+ spi-cpol;
+ spi-cpha;
+ gpios-reset = gpio3 30 0;
+ };
+ };
+
+ fiq {
+ compatible = crystalfontz,cfa10049-fiq;
+ interrupts = 50;
+ };
+};
This code has never been merged, and even with the unmerged driver the
driver won't load. You should maybe remove it :)
Maxime
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Re: [PATCH 3/3] ARM: mxs: dt: Add Crystalfontz CFA-10058 device tree
*/
+ 0x1191 /*
MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+ 0x11a1 /*
MX28_PAD_LCD_RS__LCD_DOTCLK */
+ 0x11b1 /*
MX28_PAD_LCD_CS__LCD_ENABLE */
+ ;
+ fsl,drive-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 0;
+ };
+ };
+
+ lcdif@8003 {
+ pinctrl-names = default;
+ pinctrl-0 = lcdif_24bit_pins_a
+ lcdif_pins_cfa10058;
+ display = display;
+ status = okay;
+
+ display: display {
+ bits-per-pixel = 32;
+ bus-width = 24;
+
+ display-timings {
+ native-mode = timing0;
+ timing0: timing0 {
+ clock-frequency =
3000;
+ hactive = 800;
+ vactive = 480;
+ hback-porch = 40;
+ hfront-porch = 40;
+ vback-porch = 13;
+ vfront-porch = 29;
+ hsync-len = 8;
+ vsync-len = 8;
+ hsync-active = 0;
+ vsync-active = 0;
+ de-active = 1;
+ pixelclk-active = 1;
+ };
+ };
+ };
+ };
+ };
+
+ apbx@8004 {
+ lradc@8005 {
+ fsl,lradc-touchscreen-wires = 4;
+ status = okay;
+ };
+
+ pwm: pwm@80064000 {
+ pinctrl-names = default;
+ pinctrl-0 = pwm3_pins_b;
+ status = okay;
+ };
+
+ i2c1: i2c@8005a000 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+ };
Unused i2c bus on this board.
+ usbphy1: usbphy@8007e000 {
+ status = okay;
+ };
+ };
+ };
+
+ ahb@8008 {
+ usb1: usb@8009 {
+ vbus-supply = reg_usb1_vbus;
+ pinctrl-0 = usbphy1_pins_a;
+ pinctrl-names = default;
+ status = okay;
+ };
+ };
+
+ regulators {
+ compatible = simple-bus;
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = regulator-fixed;
+ regulator-name = usb1_vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gpio0 7 1;
+ };
+ };
+
+ ahb@8008 {
+ mac0: ethernet@800f {
+ phy-mode = rmii;
+ pinctrl-names = default;
+ pinctrl-0 = mac0_pins_a;
+ phy-reset-gpios = gpio2 21 0;
+ phy-reset-duration = 100;
+ status = okay;
+ };
+ };
+
+ backlight {
+ compatible = pwm-backlight;
+ pwms = pwm 3 500;
+ brightness-levels = 0 4 8 16 32 64 128 255;
+ default-brightness-level = 6;
+ };
+
+ fiq {
+ compatible = crystalfontz,cfa10049-fiq;
+ interrupts = 50;
+ };
Again, out-of-tree driver :)
Thanks,
Maxime
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Re: [PATCH 1/3] ARM: mxs: Simplify detection of CrystalFontz boards
On Wed, Jun 26, 2013 at 04:52:25PM +0200, Alexandre Belloni wrote: As all CrystalFontz boards are compatible with crystalfontz,cfa10036, make it easier to add future boards. Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com Acked-by: Maxime Ripard maxime.rip...@free-electrons.com -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCHv2 2/3] ARM: mxs: dt: Add Crystalfontz CFA-10056 device tree
-strength = 0;
+ fsl,voltage = 1;
+ fsl,pull-up = 0;
+ };
+ };
+
+ lcdif@8003 {
+ pinctrl-names = default;
+ pinctrl-0 = lcdif_24bit_pins_a
+ lcdif_pins_cfa10056;
+ display = display;
+ status = okay;
+
+ display: display {
+ bits-per-pixel = 32;
+ bus-width = 24;
+
+ display-timings {
+ native-mode = timing0;
+ timing0: timing0 {
+ clock-frequency =
3200;
+ hactive = 480;
+ vactive = 800;
+ hback-porch = 2;
+ hfront-porch = 2;
+ vback-porch = 2;
+ vfront-porch = 2;
+ hsync-len = 5;
+ vsync-len = 5;
+ hsync-active = 0;
+ vsync-active = 0;
+ de-active = 1;
+ pixelclk-active = 1;
+ };
+ };
+ };
+ };
+ };
+
+ apbx@8004 {
+ usbphy1: usbphy@8007e000 {
+ status = okay;
+ };
+ };
+ };
+
+ ahb@8008 {
+ usb1: usb@8009 {
+ vbus-supply = reg_usb1_vbus;
+ pinctrl-0 = usbphy1_pins_a;
+ pinctrl-names = default;
+ status = okay;
+ };
+ };
+
+ regulators {
+ compatible = simple-bus;
+
+ reg_usb1_vbus: usb1_vbus {
+ compatible = regulator-fixed;
+ regulator-name = usb1_vbus;
+ regulator-min-microvolt = 500;
+ regulator-max-microvolt = 500;
+ gpio = gpio0 7 1;
+ };
+ };
+
+ ahb@8008 {
+ mac0: ethernet@800f {
+ phy-mode = rmii;
+ pinctrl-names = default;
+ pinctrl-0 = mac0_pins_a;
+ phy-reset-gpios = gpio2 21 0;
+ phy-reset-duration = 100;
+ status = okay;
+ };
+ };
+
+ spi2 {
+ compatible = spi-gpio;
+ pinctrl-names = default;
+ pinctrl-0 = spi2_pins_cfa10056;
+ status = okay;
+ gpio-sck = gpio2 16 0;
+ gpio-mosi = gpio2 17 0;
+ gpio-miso = gpio2 18 0;
+ cs-gpios = gpio3 5 0;
+ num-chipselects = 1;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ hx8369: hx8369@0 {
+ compatible = himax,hx8369a, himax,hx8369;
+ reg = 0;
+ spi-max-frequency = 10;
+ spi-cpol;
+ spi-cpha;
+ gpios-reset = gpio3 30 0;
+ };
+ };
+};
--
1.8.1.2
--
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCHv2 3/3] ARM: mxs: dt: Add Crystalfontz CFA-10058 device tree
Hi Alexandre,
On Wed, Jun 26, 2013 at 05:40:32PM +0200, Alexandre Belloni wrote:
From: Brian Lilly br...@crystalfontz.com
The CFA-10057 is a breakout board for the CFA-10036 that has Ethernet, USB
and a
5 LCD screen on it.
Signed-off-by: Brian Lilly br...@crystalfontz.com
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx28-cfa10058.dts | 158
+++
2 files changed, 159 insertions(+)
create mode 100644 arch/arm/boot/dts/imx28-cfa10058.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d494f37..ddd6f32 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -133,6 +133,7 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-cfa10055.dtb \
imx28-cfa10056.dtb \
imx28-cfa10057.dtb \
+ imx28-cfa10058.dtb \
imx28-evk.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts
b/arch/arm/boot/dts/imx28-cfa10058.dts
new file mode 100644
index 000..99a21ac
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Copyright 2013 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10058 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ imx28-cfa10036.dts
+
+/ {
+ model = Crystalfontz CFA-10058 Board;
+ compatible = crystalfontz,cfa10058, crystalfontz,cfa10036,
fsl,imx28;
+
+ apb@8000 {
+ apbh@8000 {
+ pinctrl@80018000 {
+ pinctrl-names = default, default;
+ pinctrl-1 = hog_pins_cfa10058
+ hog_pins_cfa10058_pullup;
It doesn't compile, this node doesn't exist anymore.
+ hog_pins_cfa10058: hog-10058@0 {
+ reg = 0;
+ fsl,pinmux-ids =
+ 0x0073 /*
MX28_PAD_GPMI_D7__GPIO_0_7 */
+ 0x3053 /*
MX28_PAD_AUART1_TX__GPIO_3_5 */
Again, we should probably split out these two pins into two different
nodes that would be grabed by their respective drivers.
Thanks,
Maxime
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[PATCH 1/8] clocksource: sun4i: Use the BIT macros where possible
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- drivers/clocksource/sun4i_timer.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index d4674e7..bdf34d9 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -24,12 +24,12 @@ #include linux/of_irq.h #define TIMER_IRQ_EN_REG 0x00 -#define TIMER_IRQ_EN(val) (1 val) +#define TIMER_IRQ_EN(val) BIT(val) #define TIMER_IRQ_ST_REG 0x04 #define TIMER_CTL_REG(val) (0x10 * val + 0x10) -#define TIMER_CTL_ENABLE (1 0) -#define TIMER_CTL_AUTORELOAD (1 1) -#define TIMER_CTL_ONESHOT (1 7) +#define TIMER_CTL_ENABLE BIT(0) +#define TIMER_CTL_AUTORELOAD BIT(1) +#define TIMER_CTL_ONESHOT BIT(7) #define TIMER_INTVAL_REG(val) (0x10 * val + 0x14) #define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18) -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/8] clocksource: sun4i: Add clocksource and sched clock drivers
The A10 and the A13 has a 64 bits free running counter that we can use
as a clocksource and a sched clock, that were both not used yet on these
platforms.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clocksource/sun4i_timer.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/clocksource/sun4i_timer.c
b/drivers/clocksource/sun4i_timer.c
index bdf34d9..1d2eaa0 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -23,6 +23,8 @@
#include linux/of_address.h
#include linux/of_irq.h
+#include asm/sched_clock.h
+
#define TIMER_IRQ_EN_REG 0x00
#define TIMER_IRQ_EN(val) BIT(val)
#define TIMER_IRQ_ST_REG 0x04
@@ -34,6 +36,11 @@
#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
#define TIMER_SCAL 16
+#define TIMER_CNT64_CTL_REG0xa0
+#define TIMER_CNT64_CTL_CLRBIT(0)
+#define TIMER_CNT64_CTL_RL BIT(1)
+#define TIMER_CNT64_LOW_REG0xa4
+#define TIMER_CNT64_HIGH_REG 0xa8
static void __iomem *timer_base;
@@ -96,6 +103,20 @@ static struct irqaction sun4i_timer_irq = {
.dev_id = sun4i_clockevent,
};
+static u32 sun4i_timer_sched_read(void)
+{
+ u32 reg = readl(timer_base + TIMER_CNT64_CTL_REG);
+ writel(reg | TIMER_CNT64_CTL_RL, timer_base + TIMER_CNT64_CTL_REG);
+ while (readl(timer_base + TIMER_CNT64_CTL_REG) TIMER_CNT64_CTL_REG);
+
+ return readl(timer_base + TIMER_CNT64_LOW_REG);
+}
+
+static cycle_t sun4i_timer_clksrc_read(struct clocksource *c)
+{
+ return sun4i_timer_sched_read();
+}
+
static void __init sun4i_timer_init(struct device_node *node)
{
unsigned long rate = 0;
@@ -117,6 +138,12 @@ static void __init sun4i_timer_init(struct device_node
*node)
rate = clk_get_rate(clk);
+ writel(TIMER_CNT64_CTL_CLR, timer_base + TIMER_CNT64_CTL_REG);
+ setup_sched_clock(sun4i_timer_sched_read, 32, clk_get_rate(clk));
+ clocksource_mmio_init(timer_base + TIMER_CNT64_LOW_REG, node-name,
+ clk_get_rate(clk), 300, 32,
+ sun4i_timer_clksrc_read);
+
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER_INTVAL_REG(0));
--
1.8.3.1
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[PATCH 0/8] clocksource: sunxi: Timer fixes and cleanup
Hi everyone, The first timer code we merged when adding support for the A13 some time back was mostly a clean up from the source drop we had, without any documentation. This happened to work, but the code merged in turned out to be far from perfect, and had several flaws. This patchset hopefully fixes these flaws, and cleanup most of the driver as well, to end up in an almost complete rewrite of it (even though it's not that long). It also finally adds a clocksource from the free running counter found in the A10/A13 SoCs. These flaws have all been spotted when trying to add the A31 support, work that is still ongoing, but will hopefully benefit from this patchset as well. Thanks, Maxime Maxime Ripard (8): clocksource: sun4i: Use the BIT macros where possible clocksource: sun4i: Add clocksource and sched clock drivers clocksource: sun4i: Don't forget to enable the clock we use clocksource: sun4i: Fix the next event code clocksource: sun4i: Factor out some timer code clocksource: sun4i: Remove TIMER_SCAL variable clocksource: sun4i: Cleanup parent clock setup clocksource: sun4i: Fix bug when switching from periodic to oneshot modes drivers/clocksource/sun4i_timer.c | 107 ++ 1 file changed, 75 insertions(+), 32 deletions(-) -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/8] clocksource: sun4i: Don't forget to enable the clock we use
Even if in our case, this clock was non-gatable, used as a parent clock for several IPs, it still is a good idea to enable it. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- drivers/clocksource/sun4i_timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 1d2eaa0..8bd66df 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -135,6 +135,7 @@ static void __init sun4i_timer_init(struct device_node *node) clk = of_clk_get(node, 0); if (IS_ERR(clk)) panic(Can't get timer clock); + clk_prepare_enable(clk); rate = clk_get_rate(clk); -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 7/8] clocksource: sun4i: Cleanup parent clock setup
The current bring-up code for the timer was overly complicated. The only thing we need is actually which clock we want to use as source and that's pretty much all. Let's keep it that way. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- drivers/clocksource/sun4i_timer.c | 15 +-- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 912d3e0..98e38a6 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -32,6 +32,9 @@ #define TIMER_CTL_REG(val) (0x10 * val + 0x10) #define TIMER_CTL_ENABLE BIT(0) #define TIMER_CTL_AUTORELOAD BIT(1) +#define TIMER_CTL_CLK_SRC(val) (((val) 0x3) 2) +#define TIMER_CTL_CLK_SRC_OSC24M (1) +#define TIMER_CTL_CLK_PRES(val)(((val) 0x7) 4) #define TIMER_CTL_ONESHOT BIT(7) #define TIMER_INTVAL_REG(val) (0x10 * val + 0x14) #define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18) @@ -166,16 +169,8 @@ static void __init sun4i_timer_init(struct device_node *node) writel(clk_get_rate(clk) / HZ, timer_base + TIMER_INTVAL_REG(0)); - /* set clock source to HOSC, 16 pre-division */ - val = readl(timer_base + TIMER_CTL_REG(0)); - val = ~(0x07 4); - val = ~(0x03 2); - val |= (4 4) | (1 2); - writel(val, timer_base + TIMER_CTL_REG(0)); - - /* set mode to auto reload */ - val = readl(timer_base + TIMER_CTL_REG(0)); - writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0)); + writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_AUTORELOAD, + timer_base + TIMER_CTL_REG(0)); ret = setup_irq(irq, sun4i_timer_irq); if (ret) -- 1.8.3.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 8/8] clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
The interval was firing at was set up at probe time, and only changed in
the set_next_event, and never changed back, which is not really what is
expected.
When enabling the periodic mode, now set an interval to tick every
jiffy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clocksource/sun4i_timer.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c
b/drivers/clocksource/sun4i_timer.c
index 98e38a6..b7e1f9e 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -46,6 +46,7 @@
#define TIMER_CNT64_HIGH_REG 0xa8
static void __iomem *timer_base;
+static u32 ticks_per_jiffy;
static void sun4i_clkevt_time_stop(void)
{
@@ -68,7 +69,8 @@ static void sun4i_clkevt_time_start(bool periodic)
else
val |= TIMER_CTL_ONESHOT;
- writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
+ timer_base + TIMER_CTL_REG(0));
}
static void sun4i_clkevt_mode(enum clock_event_mode mode,
@@ -77,6 +79,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
sun4i_clkevt_time_stop();
+ sun4i_clkevt_time_setup(ticks_per_jiffy);
sun4i_clkevt_time_start(true);
break;
case CLOCK_EVT_MODE_ONESHOT:
@@ -166,10 +169,9 @@ static void __init sun4i_timer_init(struct device_node
*node)
clk_get_rate(clk), 300, 32,
sun4i_timer_clksrc_read);
- writel(clk_get_rate(clk) / HZ,
- timer_base + TIMER_INTVAL_REG(0));
+ ticks_per_jiffy = DIV_ROUND_UP(clk_get_rate(clk), HZ);
- writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) |
TIMER_CTL_AUTORELOAD,
+ writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
timer_base + TIMER_CTL_REG(0));
ret = setup_irq(irq, sun4i_timer_irq);
--
1.8.3.1
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[PATCH 4/8] clocksource: sun4i: Fix the next event code
The next_event logic was setting the next interval to fire in the
current timer value instead of the interval value register, which is
obviously wrong. Plus the logic to set the actual value was wrong as
well, so this code has always been broken.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clocksource/sun4i_timer.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c
b/drivers/clocksource/sun4i_timer.c
index 8bd66df..032e504 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -16,6 +16,7 @@
#include linux/clk.h
#include linux/clockchips.h
+#include linux/delay.h
#include linux/interrupt.h
#include linux/irq.h
#include linux/irqreturn.h
@@ -69,9 +70,14 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
static int sun4i_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
- u32 u = readl(timer_base + TIMER_CTL_REG(0));
- writel(evt, timer_base + TIMER_CNTVAL_REG(0));
- writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
+ u32 val = readl(timer_base + TIMER_CTL_REG(0));
+ writel(val ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+ udelay(1);
+
+ writel(evt, timer_base + TIMER_INTVAL_REG(0));
+
+ val = readl(timer_base + TIMER_CTL_REG(0));
+ writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
timer_base + TIMER_CTL_REG(0));
return 0;
--
1.8.3.1
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[PATCH 5/8] clocksource: sun4i: Factor out some timer code
The set_next_event and set_mode callbacks share a lot of common code we
can easily factor to avoid duplication and mistakes.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clocksource/sun4i_timer.c | 48 ++-
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c
b/drivers/clocksource/sun4i_timer.c
index 032e504..7f3b248 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -45,24 +45,46 @@
static void __iomem *timer_base;
+static void sun4i_clkevt_time_stop(void)
+{
+ u32 val = readl(timer_base + TIMER_CTL_REG(0));
+ writel(val ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+ udelay(1);
+}
+
+static void sun4i_clkevt_time_setup(unsigned long delay)
+{
+ writel(delay, timer_base + TIMER_INTVAL_REG(0));
+}
+
+static void sun4i_clkevt_time_start(bool periodic)
+{
+ u32 val = readl(timer_base + TIMER_CTL_REG(0));
+
+ if (periodic)
+ val = ~TIMER_CTL_ONESHOT;
+ else
+ val |= TIMER_CTL_ONESHOT;
+
+ writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+}
+
static void sun4i_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
- u32 u = readl(timer_base + TIMER_CTL_REG(0));
-
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- u = ~(TIMER_CTL_ONESHOT);
- writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+ sun4i_clkevt_time_stop();
+ sun4i_clkevt_time_start(true);
break;
-
case CLOCK_EVT_MODE_ONESHOT:
- writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
+ sun4i_clkevt_time_stop();
+ sun4i_clkevt_time_start(false);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
- writel(u ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
+ sun4i_clkevt_time_stop();
break;
}
}
@@ -70,15 +92,9 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode,
static int sun4i_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
- u32 val = readl(timer_base + TIMER_CTL_REG(0));
- writel(val ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
- udelay(1);
-
- writel(evt, timer_base + TIMER_INTVAL_REG(0));
-
- val = readl(timer_base + TIMER_CTL_REG(0));
- writel(val | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
- timer_base + TIMER_CTL_REG(0));
+ sun4i_clkevt_time_stop();
+ sun4i_clkevt_time_setup(evt);
+ sun4i_clkevt_time_start(false);
return 0;
}
--
1.8.3.1
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[PATCH 6/8] clocksource: sun4i: Remove TIMER_SCAL variable
The prescaler is only used when using the internal low frequency
oscillator (at 32kHz). Since we're using the higher frequency oscillator
at 24MHz, we can just remove it.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clocksource/sun4i_timer.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/clocksource/sun4i_timer.c
b/drivers/clocksource/sun4i_timer.c
index 7f3b248..912d3e0 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -36,7 +36,6 @@
#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
-#define TIMER_SCAL 16
#define TIMER_CNT64_CTL_REG0xa0
#define TIMER_CNT64_CTL_CLRBIT(0)
#define TIMER_CNT64_CTL_RL BIT(1)
@@ -141,7 +140,6 @@ static cycle_t sun4i_timer_clksrc_read(struct clocksource
*c)
static void __init sun4i_timer_init(struct device_node *node)
{
- unsigned long rate = 0;
struct clk *clk;
int ret, irq;
u32 val;
@@ -159,15 +157,13 @@ static void __init sun4i_timer_init(struct device_node
*node)
panic(Can't get timer clock);
clk_prepare_enable(clk);
- rate = clk_get_rate(clk);
-
writel(TIMER_CNT64_CTL_CLR, timer_base + TIMER_CNT64_CTL_REG);
setup_sched_clock(sun4i_timer_sched_read, 32, clk_get_rate(clk));
clocksource_mmio_init(timer_base + TIMER_CNT64_LOW_REG, node-name,
clk_get_rate(clk), 300, 32,
sun4i_timer_clksrc_read);
- writel(rate / (TIMER_SCAL * HZ),
+ writel(clk_get_rate(clk) / HZ,
timer_base + TIMER_INTVAL_REG(0));
/* set clock source to HOSC, 16 pre-division */
@@ -191,8 +187,8 @@ static void __init sun4i_timer_init(struct device_node
*node)
sun4i_clockevent.cpumask = cpumask_of(0);
- clockevents_config_and_register(sun4i_clockevent, rate / TIMER_SCAL,
- 0x1, 0xff);
+ clockevents_config_and_register(sun4i_clockevent, clk_get_rate(clk),
+ 0x1, 0x);
}
CLOCKSOURCE_OF_DECLARE(sun4i, allwinner,sun4i-timer,
sun4i_timer_init);
--
1.8.3.1
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RTL8192CU on ARM not working
Hi everyone, I'm currently trying to use a RTL8192CU on an ARM (Freescale imx28, armv5) platform, using 3.10-rc3. Trouble is, while the chip is correctly detected and you can use iw on it without any problem it seems, once you start an association to an access point, the association goes on, seems to associate, displaying a WARN() message [1] and then, after what looks like a random amount of time (could be right away, could be after a few minutes), deassociate [2]. During the time where it's associated, we never seem to transmit any packets, while iw reports packets being sent, I guess we can assume that they are actually never transmitted as well [3]. What seems odd to me as well is that the signal power reported for the access point is excessively high when using iw scan (10 dbm), and once connected, the signal strength is -64dbm, which makes quite a huge difference. Do you have any suggestions on how to solve this issue? Thanks, Maxime [1]: # iw wlan0 connect FreeWifi 2447 # [ 485.010858] wlan0: authenticate with f4:ca:e5:c9:f5:91 [ 485.065514] wlan0: send auth to f4:ca:e5:c9:f5:91 (try 1/3) [ 485.075963] wlan0: authenticated [ 485.088915] wlan0: associate with f4:ca:e5:c9:f5:91 (try 1/3) [ 485.117137] wlan0: RX AssocResp from f4:ca:e5:c9:f5:91 (capab=0x401 status=0 aid=1) [ 485.130607] wlan0: associated [ 486.917555] [ cut here ] [ 486.922277] WARNING: at kernel/workqueue.c:1365 __queue_work+0x1f0/0x2f4() [ 486.929175] Modules linked in: [ 486.932284] CPU: 0 PID: 615 Comm: kworker/0:2 Not tainted 3.10.0-rc3 #2 [ 486.938958] Workqueue: rtl92c_usb rtl_watchdog_wq_callback [ 486.944548] [c00147dc] (unwind_backtrace+0x0/0xf0) from [c00120a0] (show_stack+0x10/0x14) [ 486.953132] [c00120a0] (show_stack+0x10/0x14) from [c001d2ec] (warn_slowpath_common+0x4c/0x68) [ 486.962140] [c001d2ec] (warn_slowpath_common+0x4c/0x68) from [c001d324] (warn_slowpath_null+0x1c/0x24) [ 486.971844] [c001d324] (warn_slowpath_null+0x1c/0x24) from [c003769c] (__queue_work+0x1f0/0x2f4) [ 486.981025] [c003769c] (__queue_work+0x1f0/0x2f4) from [c0037830] (queue_work_on+0x80/0x88) [ 486.989777] [c0037830] (queue_work_on+0x80/0x88) from [c0267ca4] (rtl_watchdog_wq_callback+0x5dc/0x8bc) [ 486.999572] [c0267ca4] (rtl_watchdog_wq_callback+0x5dc/0x8bc) from [c0038cbc] (process_one_work+0x1c0/0x4c8) [ 487.009795] [c0038cbc] (process_one_work+0x1c0/0x4c8) from [c0039684] (worker_thread+0x140/0x3ac) [ 487.019065] [c0039684] (worker_thread+0x140/0x3ac) from [c003f914] (kthread+0xa4/0xb0) [ 487.027381] [c003f914] (kthread+0xa4/0xb0) from [c000f0c0] (ret_from_fork+0x14/0x34) [ 487.035498] ---[ end trace 93341a0c249e647e ]--- [2]: # [ 786.086127] wlan0: deauthenticated from f4:ca:e5:c9:f5:91 (Reason: 2) [ 786.126368] cfg80211: Calling CRDA to update world regulatory domain [3]: # iw wlan0 station dump Station f4:ca:e5:c9:f5:91 (on wlan0) inactive time: 55430 ms rx bytes: 77826 rx packets: 1026 tx packets: 2 tx retries: 0 tx failed: 0 signal: -64 dBm signal avg: -63 dBm tx bitrate: 1.0 MBit/s authorized: yes authenticated: yes preamble: long WMM/WME:yes MFP:no TDLS peer: no -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [PATCHv3 RESEND 0/6] ARM: sunxi: Add support for A10 Ethernet controller
Hi Richard,
On Wed, May 29, 2013 at 08:15:49PM +0200, Richard Genoud wrote:
2013/5/24 Maxime Ripard maxime.rip...@free-electrons.com:
I tested it successfully on cubieboard 1GB, on top of kernel 3.10-rc3,
nfsroot (debian wheezy)
I also added in sun4i-a10-cubieboard.dts
phy0: ethernet-phy@0 {
reg = 1;
},
like Emilio suggested.
running an iperf, there's some good perfs !
iperf -s
Server listening on TCP port 5001
TCP window size: 85.3 KByte (default)
[ 4] local 192.168.1.10 port 5001 connected with 192.168.1.232 port 38169
[ ID] Interval Transfer Bandwidth
[ 4] 0.0-10.0 sec 112 MBytes 94.1 Mbits/sec
That's great ! with this patchset, we can now run a server with a
vanilla kernel ( who needs more that a serial port and ethernet,
really ? ;) )
Tested-by: Richard Genoud richard.gen...@gmail.com
Thanks for testing this.
Did you look at the load while iperf was running? I guess we can expect
it to be pretty high since it runs without DMA.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCHv4 0/6] ARM: sunxi: Add support for A10 Ethernet controller
Hi, The Allwinner A10 SoC has an ethernet controller that seem to be specific to Allwinner. This IP has no public documentation, so exact details are quite sparse, and this code come from refactored Allwinner code. The rework to use NAPI is taking more time than expected, I'm still working on it, but it could probably be sent as a follow-up patch. Thanks, Maxime Changes from v3: - Moved the MDIO driver to drivers/net/phy - Add error checking in the mdio driver for regulator_enable, that also silences a warning - Fixed the phy address in the cubieboard device tree (From Emilio Lopez) - Fix broken builds by selecting CONFIG_REGULATOR (From Emilio Lopez) Changes from v2: - Split the MDIO controller to a separate driver and make use of standards device tree bindings - Fixed various minor things as suggested by Florian Fainelli - Added clock support now that we have a clock driver Changes from v1: - Use phylib for the phy-related functions - Use an optional regulator to power up the phy - Rename the driver from Davicom Wemac to Allwinner EMAC, since it's the name mentionned in the datasheet, and we have no strong evidence of a relationship with Davicom - Fix various small things around the driver: add defines for undocumented values, fix documentation name and compatible example, etc. Maxime Ripard (4): net: Add MDIO bus driver for the Allwinner EMAC ARM: sun4i: Add muxing options for the ethernet controller ARM: sunxi: Add EMAC controller node to sun4i DTSI ARM: sunxi: Add EMAC Controller to Hackberry dt Stefan Roese (2): net: Add EMAC ethernet driver found on Allwinner A10 SoC's ARM: cubieboard: Enable ethernet (EMAC) support in dts .../bindings/net/allwinner,sun4i-emac.txt | 22 + .../bindings/net/allwinner,sun4i-mdio.txt | 26 + arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 + arch/arm/boot/dts/sun4i-a10-hackberry.dts | 41 + arch/arm/boot/dts/sun4i-a10.dtsi | 27 + drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/allwinner/Kconfig | 36 + drivers/net/ethernet/allwinner/Makefile| 5 + drivers/net/ethernet/allwinner/sun4i-emac.c| 960 + drivers/net/ethernet/allwinner/sun4i-emac.h| 108 +++ drivers/net/phy/Kconfig| 10 + drivers/net/phy/Makefile | 1 + drivers/net/phy/mdio-sun4i.c | 194 + 14 files changed, 1447 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt create mode 100644 drivers/net/ethernet/allwinner/Kconfig create mode 100644 drivers/net/ethernet/allwinner/Makefile create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h create mode 100644 drivers/net/phy/mdio-sun4i.c -- 1.8.2.3 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCHv4 1/6] net: Add EMAC ethernet driver found on Allwinner A10 SoC's
From: Stefan Roese s...@denx.de
The Allwinner A10 has an ethernet controller that seem to be developped
internally by them.
The exact feature set of this controller is unknown, since there is no
public documentation for this IP, and this driver is mostly the one
published by Allwinner that has been heavily cleaned up.
Signed-off-by: Stefan Roese s...@denx.de
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
.../bindings/net/allwinner,sun4i-emac.txt | 22 +
drivers/net/ethernet/Kconfig | 1 +
drivers/net/ethernet/Makefile | 1 +
drivers/net/ethernet/allwinner/Kconfig | 36 +
drivers/net/ethernet/allwinner/Makefile| 5 +
drivers/net/ethernet/allwinner/sun4i-emac.c| 960 +
drivers/net/ethernet/allwinner/sun4i-emac.h| 108 +++
7 files changed, 1133 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
create mode 100644 drivers/net/ethernet/allwinner/Kconfig
create mode 100644 drivers/net/ethernet/allwinner/Makefile
create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.c
create mode 100644 drivers/net/ethernet/allwinner/sun4i-emac.h
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
new file mode 100644
index 000..b90bfcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
@@ -0,0 +1,22 @@
+* Allwinner EMAC ethernet controller
+
+Required properties:
+- compatible: should be allwinner,sun4i-emac.
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device
+- phy: A phandle to a phy node defining the PHY address (as the reg
+ property, a single integer).
+- clocks: A phandle to the reference clock for this device
+
+Optional properties:
+- (local-)mac-address: mac address to be used by this driver
+
+Example:
+
+emac: ethernet@01c0b000 {
+ compatible = allwinner,sun4i-emac;
+ reg = 0x01c0b000 0x1000;
+ interrupts = 55;
+ clocks = ahb_gates 17;
+ phy = phy0;
+};
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index ed956e0..18fd6fb 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -20,6 +20,7 @@ config SUNGEM_PHY
source drivers/net/ethernet/3com/Kconfig
source drivers/net/ethernet/adaptec/Kconfig
source drivers/net/ethernet/aeroflex/Kconfig
+source drivers/net/ethernet/allwinner/Kconfig
source drivers/net/ethernet/alteon/Kconfig
source drivers/net/ethernet/amd/Kconfig
source drivers/net/ethernet/apple/Kconfig
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index 8268d85..009da27 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_NET_VENDOR_3COM) += 3com/
obj-$(CONFIG_NET_VENDOR_8390) += 8390/
obj-$(CONFIG_NET_VENDOR_ADAPTEC) += adaptec/
obj-$(CONFIG_GRETH) += aeroflex/
+obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
obj-$(CONFIG_NET_VENDOR_AMD) += amd/
obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
diff --git a/drivers/net/ethernet/allwinner/Kconfig
b/drivers/net/ethernet/allwinner/Kconfig
new file mode 100644
index 000..66d3532
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Kconfig
@@ -0,0 +1,36 @@
+#
+# Allwinner device configuration
+#
+
+config NET_VENDOR_ALLWINNER
+ bool Allwinner devices
+ default y
+ depends on ARCH_SUNXI
+ ---help---
+ If you have a network (Ethernet) card belonging to this
+class, say Y and read the Ethernet-HOWTO, available from
+http://www.tldp.org/docs.html#howto.
+
+Note that the answer to this question doesn't directly
+affect the kernel: saying N will just cause the configurator
+to skip all the questions about Allwinner cards. If you say Y,
+you will be asked for your specific card in the following
+questions.
+
+if NET_VENDOR_ALLWINNER
+
+config SUN4I_EMAC
+tristate Allwinner A10 EMAC support
+ depends on ARCH_SUNXI
+ depends on OF
+ select CRC32
+ select NET_CORE
+ select MII
+ select PHYLIB
+---help---
+ Support for Allwinner A10 EMAC ethernet driver.
+
+ To compile this driver as a module, choose M here. The module
+ will be called sun4i-emac.
+
+endif # NET_VENDOR_ALLWINNER
diff --git a/drivers/net/ethernet/allwinner/Makefile
b/drivers/net/ethernet/allwinner/Makefile
new file mode 100644
index 000..03129f7
--- /dev/null
+++ b/drivers/net/ethernet/allwinner/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Allwinner device drivers.
+#
+
+obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
diff --git a/drivers/net/ethernet/allwinner/sun4i-emac.c
b/drivers/net/ethernet/allwinner/sun4i
[PATCHv4 2/6] net: Add MDIO bus driver for the Allwinner EMAC
This patch adds a separate driver for the MDIO interface of the
Allwinner ethernet controllers.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
.../bindings/net/allwinner,sun4i-mdio.txt | 26 +++
drivers/net/phy/Kconfig| 10 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/mdio-sun4i.c | 194 +
4 files changed, 231 insertions(+)
create mode 100644
Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
create mode 100644 drivers/net/phy/mdio-sun4i.c
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
new file mode 100644
index 000..00b9f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
@@ -0,0 +1,26 @@
+* Allwinner A10 MDIO Ethernet Controller interface
+
+Required properties:
+- compatible: should be allwinner,sun4i-mdio.
+- reg: address and length of the register set for the device.
+
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+
+Example at the SoC level:
+mdio@01c0b080 {
+ compatible = allwinner,sun4i-mdio;
+ reg = 0x01c0b080 0x14;
+ #address-cells = 1;
+ #size-cells = 0;
+};
+
+And at the board level:
+
+mdio@01c0b080 {
+ phy-supply = reg_emac_3v3;
+
+ phy0: ethernet-phy@0 {
+ reg = 0;
+ };
+};
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 1e11f2b..3a316b3 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -144,6 +144,16 @@ config MDIO_OCTEON
If in doubt, say Y.
+config MDIO_SUN4I
+ tristate Allwinner sun4i MDIO interface support
+ depends on ARCH_SUNXI
+ select REGULATOR
+ select REGULATOR_FIXED_VOLTAGE
+ help
+ This driver supports the MDIO interface found in the network
+ interface units of the Allwinner SoC that have an EMAC (A10,
+ A12, A10s, etc.)
+
config MDIO_BUS_MUX
tristate
depends on OF_MDIO
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9645e38..23a2ab2 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_AMD_PHY) += amd.o
obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO)+= mdio-mux-gpio.o
obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
diff --git a/drivers/net/phy/mdio-sun4i.c b/drivers/net/phy/mdio-sun4i.c
new file mode 100644
index 000..61d3f4e
--- /dev/null
+++ b/drivers/net/phy/mdio-sun4i.c
@@ -0,0 +1,194 @@
+/*
+ * Allwinner EMAC MDIO interface driver
+ *
+ * Copyright 2012-2013 Stefan Roese s...@denx.de
+ * Copyright 2013 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * Based on the Linux driver provided by Allwinner:
+ * Copyright (C) 1997 Sten Wang
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/delay.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/mutex.h
+#include linux/of_address.h
+#include linux/of_mdio.h
+#include linux/phy.h
+#include linux/platform_device.h
+#include linux/regulator/consumer.h
+
+#define EMAC_MAC_MCMD_REG (0x00)
+#define EMAC_MAC_MADR_REG (0x04)
+#define EMAC_MAC_MWTD_REG (0x08)
+#define EMAC_MAC_MRDD_REG (0x0c)
+#define EMAC_MAC_MIND_REG (0x10)
+#define EMAC_MAC_SSRR_REG (0x14)
+
+#define MDIO_TIMEOUT (msecs_to_jiffies(100))
+
+struct sun4i_mdio_data {
+ void __iomem*membase;
+ struct regulator*regulator;
+};
+
+static int sun4i_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
+{
+ struct sun4i_mdio_data *data = bus-priv;
+ unsigned long start_jiffies;
+ int value;
+
+ /* issue the phy address and reg */
+ writel((mii_id 8) | regnum, data-membase + EMAC_MAC_MADR_REG);
+ /* pull up the phy io line */
+ writel(0x1, data-membase + EMAC_MAC_MCMD_REG);
+
+ /* Wait read complete */
+ start_jiffies = jiffies;
+ while (readl(data-membase + EMAC_MAC_MIND_REG) 0x1) {
+ if (time_after(start_jiffies,
+ start_jiffies + MDIO_TIMEOUT))
+ return -ETIMEDOUT;
+ msleep(1);
+ }
+
+ /* push down the phy io line */
+ writel(0x0, data-membase + EMAC_MAC_MCMD_REG);
+ /* and read data */
+ value = readl(data-membase + EMAC_MAC_MRDD_REG);
+
+ return value;
+}
+
+static int sun4i_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
+ u16 value)
+{
+ struct sun4i_mdio_data
[PATCHv4 6/6] ARM: sunxi: Add EMAC Controller to Hackberry dt
The Hackberry has a PHY that needs to be powered up through a GPIO, so
we need to use a fixed regulator here.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 41 +++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b9efac1..3514b37 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -23,10 +23,51 @@
};
soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy0;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ phy-supply = reg_emac_3v3;
+ status = okay;
+
+ phy0: ethernet-phy@0 {
+ reg = 0;
+ };
+ };
+
+ pio: pinctrl@01c20800 {
+ pinctrl-names = default;
+ pinctrl-0 = hackberry_hogs;
+
+ hackberry_hogs: hogs@0 {
+ allwinner,pins = PH19;
+ allwinner,function = gpio_out;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
+ };
+
uart0: serial@01c28000 {
pinctrl-names = default;
pinctrl-0 = uart0_pins_a;
status = okay;
};
};
+
+ regulators {
+ compatible = simple-bus;
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = regulator-fixed;
+ regulator-name = emac-3v3;
+ regulator-min-microvolt = 330;
+ regulator-max-microvolt = 330;
+ enable-active-high;
+ gpio = pio 7 19 0;
+ };
+ };
};
--
1.8.2.3
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[PATCHv4 5/6] ARM: cubieboard: Enable ethernet (EMAC) support in dts
From: Stefan Roese s...@denx.de
Signed-off-by: Stefan Roese s...@denx.de
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0d..e752b57 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -27,6 +27,21 @@
};
soc@01c2 {
+ emac: ethernet@01c0b000 {
+ pinctrl-names = default;
+ pinctrl-0 = emac_pins_a;
+ phy = phy1;
+ status = okay;
+ };
+
+ mdio@01c0b080 {
+ status = okay;
+
+ phy1: ethernet-phy@1 {
+ reg = 1;
+ };
+ };
+
pinctrl@01c20800 {
led_pins_cubieboard: led_pins@0 {
allwinner,pins = PH20, PH21;
--
1.8.2.3
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[PATCHv4 4/6] ARM: sunxi: Add EMAC controller node to sun4i DTSI
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ff1f41f..983da33 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -163,6 +163,22 @@
reg = 0x01c2 0x30;
ranges;
+ emac: ethernet@01c0b000 {
+ compatible = allwinner,sun4i-emac;
+ reg = 0x01c0b000 0x1000;
+ interrupts = 55;
+ clocks = ahb_gates 17;
+ status = disabled;
+ };
+
+ mdio@01c0b080 {
+ compatible = allwinner,sun4i-mdio;
+ reg = 0x01c0b080 0x14;
+ status = disabled;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
intc: interrupt-controller@01c20400 {
compatible = allwinner,sun4i-ic;
reg = 0x01c20400 0x400;
--
1.8.2.3
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[PATCHv4 3/6] ARM: sun4i: Add muxing options for the ethernet controller
The EMAC only has one pinset available for muxing, so hopefully, we
cover all cases.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Richard Genoud richard.gen...@gmail.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619..ff1f41f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -199,6 +199,17 @@
allwinner,drive = 0;
allwinner,pull = 0;
};
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = PA0, PA1, PA2,
+ PA3, PA4, PA5, PA6,
+ PA7, PA8, PA9, PA10,
+ PA11, PA12, PA13, PA14,
+ PA15, PA16;
+ allwinner,function = emac;
+ allwinner,drive = 0;
+ allwinner,pull = 0;
+ };
};
timer@01c20c00 {
--
1.8.2.3
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Re: [PATCH 1/3] iio: Add Nuvoton NAU7802 ADC driver
Hi Alexandre,
Le 18/04/2013 17:38, Alexandre Belloni a écrit :
+ nau7802_i2c_write(st, NAU7802_REG_PUCTRL, data);
+ nau7802_i2c_write(st, NAU7802_REG_ADC_CTRL, 0x30);
+
+ if (tmp = 2400) {
+ data = NAU7802_CTRL1_VLDO((4500 - tmp) / 300);
+ nau7802_i2c_write(st, NAU7802_REG_CTRL1, data);
+ }
You should probably make a macro or inline function (with a comment) out
of that computation explaining why you are doing this.
+
+ st-min_conversions = 6;
I'd prefer to see this as a define.
+
+ /*
+ * The ADC fires continuously and we can't do anything about
+ * it. So we need to have the IRQ disabled by default, and we
+ * will enable them back when we will need them..
+ */
+ if (client-irq) {
+ irq_set_status_flags(client-irq, IRQ_NOAUTOEN);
+ ret = request_threaded_irq(client-irq,
+ NULL,
+ nau7802_eoc_trigger,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+ client-dev.driver-name,
+ idev);
+ if (ret) {
+ /*
+ * What may happen here is that our IRQ controller is
+ * not able to get level interrupt but this is required
+ * by this ADC as when going over 40 sample per second,
+ * the interrupt line may stay high between conversions.
+ * So, we continue no matter what but we switch to
+ * polling mode.
+ */
+ dev_info(client-dev,
+ Failed to allocate IRQ, using polling mode\n);
+ client-irq = 0;
+ /*
+ * We are polling, use the fastest sample rate by
+ * default
+ */
+ st-sample_rate = 0x7;
Ditto.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH] video: mxsfb: Fix colors display on lower color depth
Hi Shawn, Le 18/04/2013 16:48, Shawn Guo a écrit : Copy Sascha. Ah, yes, sorry, I somehow got confused and thought you were the one that wrote the driver. I'll resend the patch. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH RESEND] video: mxsfb: Fix colors display on lower color depth
The current code always registers as a 32 bits display, and uses the hardware to drop the MSB of each color to abjust to the interface width used by the panel. This results on 18 bits (and probably 16 bits display as well) in colors being displayed poorly, because the MSB are obviously the most important bits for each color definition. The default controller behaviour when using an interface width smaller than the color depth is to drop the LSBs of each color, which makes more sense because you lose the least important part of the color definition. So, to fix the colors display, just get back to the default controller behaviour. Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com --- - Copied Sascha drivers/video/mxsfb.c |5 - 1 file changed, 5 deletions(-) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 76c..2cfaf8b 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -424,11 +424,6 @@ static int mxsfb_set_par(struct fb_info *fb_info) return -EINVAL; case STMLCDIF_16BIT: case STMLCDIF_18BIT: - /* 24 bit to 18 bit mapping */ - ctrl |= CTRL_DF24; /* ignore the upper 2 bits in - * each colour component - */ - break; case STMLCDIF_24BIT: /* real 24 bit */ break; -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/2] video: ssd1307fb: Add support for SSD1306 OLED controller
The Solomon SSD1306 OLED controller is very similar to the SSD1307,
except for the fact that the power is given through an external PWM for
the 1307, and while the 1306 can generate its own power without any PWM.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../devicetree/bindings/video/ssd1307fb.txt| 10 +-
drivers/video/ssd1307fb.c | 273 +++-
2 files changed, 209 insertions(+), 74 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/ssd1307fb.txt
b/Documentation/devicetree/bindings/video/ssd1307fb.txt
index 3d0060c..7a12542 100644
--- a/Documentation/devicetree/bindings/video/ssd1307fb.txt
+++ b/Documentation/devicetree/bindings/video/ssd1307fb.txt
@@ -1,13 +1,17 @@
* Solomon SSD1307 Framebuffer Driver
Required properties:
- - compatible: Should be solomon,ssd1307fb-bus. The only supported bus for
-now is i2c.
+ - compatible: Should be solomon,chipfb-bus. The only supported bus for
+now is i2c, and the supported chips are ssd1306 and ssd1307.
- reg: Should contain address of the controller on the I2C bus. Most likely
0x3c or 0x3d
- pwm: Should contain the pwm to use according to the OF device tree PWM
- specification [0]
+ specification [0]. Only required for the ssd1307.
- reset-gpios: Should contain the GPIO used to reset the OLED display
+ - solomon,height: Height in pixel of the screen driven by the controller
+ - solomon,width: Width in pixel of the screen driven by the controller
+ - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
+mapped to.
Optional properties:
- reset-active-low: Is the reset gpio is active on physical low?
diff --git a/drivers/video/ssd1307fb.c b/drivers/video/ssd1307fb.c
index 395cb6a..5ab5281 100644
--- a/drivers/video/ssd1307fb.c
+++ b/drivers/video/ssd1307fb.c
@@ -16,24 +16,39 @@
#include linux/pwm.h
#include linux/delay.h
-#define SSD1307FB_WIDTH96
-#define SSD1307FB_HEIGHT 16
-
#define SSD1307FB_DATA 0x40
#define SSD1307FB_COMMAND 0x80
#define SSD1307FB_CONTRAST 0x81
+#defineSSD1307FB_CHARGE_PUMP 0x8d
#define SSD1307FB_SEG_REMAP_ON 0xa1
#define SSD1307FB_DISPLAY_OFF 0xae
+#define SSD1307FB_SET_MULTIPLEX_RATIO 0xa8
#define SSD1307FB_DISPLAY_ON 0xaf
#define SSD1307FB_START_PAGE_ADDRESS 0xb0
+#define SSD1307FB_SET_DISPLAY_OFFSET 0xd3
+#defineSSD1307FB_SET_CLOCK_FREQ0xd5
+#defineSSD1307FB_SET_PRECHARGE_PERIOD 0xd9
+#defineSSD1307FB_SET_COM_PINS_CONFIG 0xda
+#defineSSD1307FB_SET_VCOMH 0xdb
+
+struct ssd1307fb_par;
+
+struct ssd1307fb_ops {
+ int (*init)(struct ssd1307fb_par *);
+ int (*remove)(struct ssd1307fb_par *);
+};
struct ssd1307fb_par {
struct i2c_client *client;
+ u32 height;
struct fb_info *info;
+ struct ssd1307fb_ops *ops;
+ u32 page_offset;
struct pwm_device *pwm;
u32 pwm_period;
int reset;
+ u32 width;
};
static struct fb_fix_screeninfo ssd1307fb_fix = {
@@ -43,15 +58,10 @@ static struct fb_fix_screeninfo ssd1307fb_fix = {
.xpanstep = 0,
.ypanstep = 0,
.ywrapstep = 0,
- .line_length= SSD1307FB_WIDTH / 8,
.accel = FB_ACCEL_NONE,
};
static struct fb_var_screeninfo ssd1307fb_var = {
- .xres = SSD1307FB_WIDTH,
- .yres = SSD1307FB_HEIGHT,
- .xres_virtual = SSD1307FB_WIDTH,
- .yres_virtual = SSD1307FB_HEIGHT,
.bits_per_pixel = 1,
};
@@ -134,16 +144,17 @@ static void ssd1307fb_update_display(struct ssd1307fb_par
*par)
* (5) A4 B4 C4 D4 E4 F4 G4 H4
*/
- for (i = 0; i (SSD1307FB_HEIGHT / 8); i++) {
- ssd1307fb_write_cmd(par-client, SSD1307FB_START_PAGE_ADDRESS +
(i + 1));
+ for (i = 0; i (par-height / 8); i++) {
+ ssd1307fb_write_cmd(par-client,
+ SSD1307FB_START_PAGE_ADDRESS + i +
par-page_offset);
ssd1307fb_write_cmd(par-client, 0x00);
ssd1307fb_write_cmd(par-client, 0x10);
- for (j = 0; j SSD1307FB_WIDTH; j++) {
+ for (j = 0; j par-width; j++) {
u8 buf = 0;
for (k = 0; k 8; k++) {
- u32 page_length = SSD1307FB_WIDTH * i;
- u32 index = page_length + (SSD1307FB_WIDTH * k
+ j) / 8;
+ u32 page_length = par-width * i;
+ u32 index = page_length + (par-width * k + j)
/ 8;
u8 byte = *(vmem + index);
u8 bit = byte (1 (j % 8));
bit = bit (j % 8);
@@ -227,16 +238,147
[PATCH 2/2] ARM: dts: cfa10036: Change the OLED display to SSD1306
The SSD1307 was used in an early prototype that will never get
distributed. The final board now has a SSD1306 instead, that has its own
power generation unit and thus doesn't need any PWM. The panel attached
to it also changed.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/imx28-cfa10036.dts | 14 +-
arch/arm/boot/dts/imx28-cfa10049.dts |4 ++--
2 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts
b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1594694..40488f5a8 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -58,12 +58,6 @@
};
apbx@8004 {
- pwm: pwm@80064000 {
- pinctrl-names = default;
- pinctrl-0 = pwm4_pins_a;
- status = okay;
- };
-
duart: serial@80074000 {
pinctrl-names = default;
pinctrl-0 = duart_pins_b;
@@ -75,11 +69,13 @@
pinctrl-0 = i2c0_pins_b;
status = okay;
- ssd1307: oled@3c {
- compatible = solomon,ssd1307fb-i2c;
+ ssd1306: oled@3c {
+ compatible = solomon,ssd1306fb-i2c;
reg = 0x3c;
- pwms = pwm 4 3000;
reset-gpios = gpio2 7 0;
+ solomon,height = 32;
+ solomon,width = 128;
+ solomon,page-offset = 0;
};
};
};
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts
b/arch/arm/boot/dts/imx28-cfa10049.dts
index a0d3e9f..ded7784 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -132,8 +132,8 @@
apbx@8004 {
pwm: pwm@80064000 {
- pinctrl-names = default, default;
- pinctrl-1 = pwm3_pins_b;
+ pinctrl-names = default;
+ pinctrl-0 = pwm3_pins_b;
status = okay;
};
--
1.7.10.4
--
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