On 10/07/2013 05:15 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131004 08:42]:
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing stuff?
Well omap4 seems to work for me just fine, and omap3 in legacy
mode. But looks like omap3 device
Ticket Number: 7PWYZ2008
Ballot Number: BT:12052008/20
Draw:#1471
Special Notification to you,You are receiving this email because you have just
been picked for a total grand prize of One Million Dollars in the top 10
winners of the Coca-Cola Consumer`s Award for the year 2013: kindly send
Hi,
On Monday 16 September 2013 12:29 PM, Archit Taneja wrote:
Hi Hans, Laurent,
On Friday 06 September 2013 03:42 PM, Archit Taneja wrote:
VPE(Video Processing Engine) is an IP found on DRA7xx, this series
adds VPE as a
mem to mem v4l2 driver, and VPDMA as a helper library.
The first
On 09/06/2013 12:12 PM, Archit Taneja wrote:
The primary function of VPDMA is to move data between external memory and
internal processing modules(in our case, VPE) that source or sink data. VPDMA
is
capable of buffering this data and then delivering the data as demanded to the
modules as
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Acked-by:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm SoC's.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
From: Ivan T. Ivanov iiva...@mm-sol.com
Hi,
This is sixth version of MSM USB3 drivers patches.
Changes since v5:
* devicetree bindings descriptions fixes
* Fixed NULL pointer dereferences in dev_prink's
* Removed extra space in sleep clock name
Changes since v4:
* Substitute references to
Hi Archit,
I've got a few comments below...
On 09/06/2013 12:12 PM, Archit Taneja wrote:
VPE is a block which consists of a single memory to memory path which can
perform chrominance up/down sampling, de-interlacing, scaling, and color space
conversion of raster or tiled YUV420 coplanar,
On 09/06/2013 12:12 PM, Archit Taneja wrote:
Create functions which the VPE driver can use to create a VPDMA descriptor and
add it to a VPDMA descriptor list. These functions take a pointer to an
existing
list, and append the configuration/data/control descriptor header to the list.
In the
On 09/06/2013 12:12 PM, Archit Taneja wrote:
Add support for the de-interlacer block in VPE.
For de-interlacer to work, we need to enable 2 more sets of VPE input ports
which fetch data from the 'last' and 'last to last' fields of the interlaced
video. Apart from that, we need to enable the
Hi Felipe,
On Fri, 2013-10-04 at 09:31 -0500, Felipe Balbi wrote:
On Wed, Aug 21, 2013 at 04:29:44PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
MSM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration
On 10/04/2013 04:23 PM, Greg KH wrote:
On Fri, Oct 04, 2013 at 01:46:08PM +0300, Roger Quadros wrote:
Greg,
On 10/03/2013 06:41 PM, Greg KH wrote:
On Thu, Oct 03, 2013 at 05:54:14PM +0300, Roger Quadros wrote:
On 10/03/2013 03:29 PM, Felipe Balbi wrote:
Hi,
On Wed, Oct 02, 2013 at
On Tue, 10 Sep 2013, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer nodes
clocks. I just think the check in the clkoutx2_recalc is wrong, and should be
enhanced to actually check what is the target mode for the clock once it is
enabled. Maybe
Hi Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
On Mon, Oct 7, 2013 at 10:33 AM, Roger Quadros rog...@ti.com wrote:
Hi Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez
+devicetree
Javier,
On 10/07/2013 11:50 AM, Javier Martinez Canillas wrote:
On Mon, Oct 7, 2013 at 10:33 AM, Roger Quadros rog...@ti.com wrote:
Hi Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator
On Monday 07 October 2013 01:25 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few comments below...
On 09/06/2013 12:12 PM, Archit Taneja wrote:
VPE is a block which consists of a single memory to memory path which can
perform chrominance up/down sampling, de-interlacing, scaling, and color
Ticket Number: 7PWYZ2008
Ballot Number: BT:12052008/20
Draw:#1471
Special Notification to you,You are receiving this email because you have just
been picked for a total grand prize of One Million Dollars in the top 10
winners of the Coca-Cola Consumer`s Award for the year 2013: kindly send
Hi Ivan,
Few comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
Hi Ivan,
Minor comments below.
On 10/07/2013 10:44 AM, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of
On 10/07/2013 11:16 AM, Archit Taneja wrote:
On Monday 07 October 2013 01:25 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few comments below...
On 09/06/2013 12:12 PM, Archit Taneja wrote:
VPE is a block which consists of a single memory to memory path which can
perform chrominance
With the new omapdss device model. The user(omapdrm/omapfb) of a omap_dss_device
has to call connect() to use the device. A connect() call can request to defer
probe if the device(or the previous entities in the chain) have missing
resources like a regulator or an I2C bus.
We make omapdrm defer
omapdrm establishes connections for omap_dss_device devices when probed. It
should also be responsible to disconnect the devices. Keeping the devices
connected can prevent the panel driver modules from unloading, it also causes
issues when we try to remove or re-insert omapdrm module.
Before
Some omapdss panels are connected to outputs/encoders(HDMI/DSI/DPI) that require
regulators. The output's connect op tries to get a regulator which may not exist
yet because it might get registered later in the kernel boot.
omapdrm currently ignores those panels which return a non zero value when
Hi Benoit,
This series are some enhancements and cleanups for IGEP boards
that it would be great if can make it for v3.13.
This is a second version of the patch-set that addresses some issues
raised by Roger Quadros and is composed of the following patches:
[PATCH v2 1/3] ARM: dts: omap3-igep:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards)
added USB OTG support for most OMAP boards but some OMAP3 boards
such as IGEP boards were not updated. This patch adds an USB OTG
device node to these board.
Signed-off-by: Javier Martinez Canillas
Commit 840ef8b7 (ARM: dt: add header to define IRQ flags) added
constants for IRQ edge/level triggered types so use it instead of
a magic number to enhance the DT readability.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- None
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Enric Balletbo i Serra eballe...@gmail.com
---
Changes since v1:
- Add HST USB port 1
On 10/07/2013 12:55 PM, Javier Martinez Canillas wrote:
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Enric Balletbo i Serra
On Mon, Oct 7, 2013 at 11:13 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 10/07/2013 11:06 AM, Roger Quadros wrote:
Well that's a very good question indeed.
The thing is that the IGEP0030 is a Computer-on-Module [1] that is used in
conjunction with expansion boards
On Monday 07 October 2013 03:04 PM, Hans Verkuil wrote:
On 10/07/2013 11:16 AM, Archit Taneja wrote:
On Monday 07 October 2013 01:25 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few comments below...
On 09/06/2013 12:12 PM, Archit Taneja wrote:
VPE is a block which consists of a single
Kexec disables outer cache before jumping to reboot code, but it doesn't
flush it explicitly. Flush is done implicitly inside of l2x0_disable().
But some SoC's override default .disable handler and don't flush cache.
This may lead to a corrupted memory during Kexec reboot on these platforms.
This
Initially commit cb527ede1bf6ff2008a025606f25344b8ed7b4ac
i2c-omap: Double clear of ARDY status in IRQ handler
added a workaround for undocumented errata ProDB0017052.
But then commit 1d7afc95946487945cc7f5019b41255b72224b70
i2c: omap: ack IRQ in parts refactored code and missed
one of ARDY
Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+
boards)
added USB OTG support for most OMAP boards but some OMAP3 boards
such as the IGEPv2 were not updated. This patch adds an USB OTG
device node to this
On 10/07/2013 01:22 PM, Javier Martinez Canillas wrote:
On Mon, Oct 7, 2013 at 11:13 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 10/07/2013 11:06 AM, Roger Quadros wrote:
Well that's a very good question indeed.
The thing is that the IGEP0030 is a
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on beagle after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros rog...@ti.com
---
On Fri, Oct 04, 2013 at 08:49:43PM +0100, Pekon Gupta wrote:
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
- OMAP_ECC_HAMMING_CODE_HW
1-bit hamming ecc-code
On Fri, Oct 04, 2013 at 08:49:44PM +0100, Pekon Gupta wrote:
OMAP NAND driver support multiple ECC scheme, which can used in following
different flavours, depending on in-build Hardware engines supported by SoC.
+---+---+---+
| ECC
On Fri, Oct 04, 2013 at 08:49:47PM +0100, Pekon Gupta wrote:
DT property values for OMAP based gpmc-nand have been updated
to match changes in commit:
6faf096 ARM: OMAP2+: cleaned-up DT support of various ECC schemes
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Doesn't
Hi,
From: Mark Rutland [mailto:mark.rutl...@arm.com]
On Fri, Oct 04, 2013 at 08:49:43PM +0100, Pekon Gupta wrote:
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
ecc-scheme, like:
- OMAP_ECC_HAMMING_CODE_DEFAULT
1-bit hamming ecc code using software library
On 10/07/2013 12:42 PM, Roger Quadros wrote:
On 10/07/2013 01:22 PM, Javier Martinez Canillas wrote:
On Mon, Oct 7, 2013 at 11:13 AM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
On 10/07/2013 11:06 AM, Roger Quadros wrote:
Well that's a very good question indeed.
The
On 10/07/2013 12:43 PM, Roger Quadros wrote:
Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+
boards)
added USB OTG support for most OMAP boards but some OMAP3 boards
such as the IGEPv2 were not updated.
Hi Javier,
On 07/10/2013 13:54, Javier Martinez Canillas wrote:
On 10/07/2013 12:43 PM, Roger Quadros wrote:
Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+ boards)
added USB OTG support for most OMAP
On 10/07/2013 01:58 PM, Benoit Cousson wrote:
Hi Javier,
On 07/10/2013 13:54, Javier Martinez Canillas wrote:
On 10/07/2013 12:43 PM, Roger Quadros wrote:
Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to OMAP3+
On 07/10/2013 14:02, Javier Martinez Canillas wrote:
On 10/07/2013 01:58 PM, Benoit Cousson wrote:
Hi Javier,
On 07/10/2013 13:54, Javier Martinez Canillas wrote:
On 10/07/2013 12:43 PM, Roger Quadros wrote:
Javier,
On 10/05/2013 03:04 AM, Javier Martinez Canillas wrote:
Commit ad871c10b
From: Mark Rutland [mailto:mark.rutl...@arm.com]
On Fri, Oct 04, 2013 at 08:49:47PM +0100, Pekon Gupta wrote:
DT property values for OMAP based gpmc-nand have been updated
to match changes in commit:
6faf096 ARM: OMAP2+: cleaned-up DT support of various ECC
schemes
Refer:
From: Mark Rutland [mailto:mark.rutl...@arm.com]
On Fri, Oct 04, 2013 at 08:49:44PM +0100, Pekon Gupta wrote:
[snip]
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-
omap2/gpmc.c
index 1c45b72..5a607fa 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++
Hi,
USB OTG on these boards might be broken on Greg's usb-next branch [1]
after the Generic PHY framework and associated patches were merged.
This is a probable fix but I'm not able to test these boards. Please
give it a try and your Ack if it works. Thanks.
[1] -
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
merged in greg/usb-next. [1]
[1] - https://lkml.org/lkml/2013/9/27/581
Signed-off-by: Roger Quadros
On 10/07/2013 03:28 PM, Roger Quadros wrote:
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
merged in greg/usb-next. [1]
Would it be much pain (and do we
On 10/07/2013 04:40 PM, Sebastian Andrzej Siewior wrote:
On 10/07/2013 03:28 PM, Roger Quadros wrote:
The generic PHY framewrok expects different properties than the
old USB PHY framework. Supply those properties.
Fixes USB OTG port on GAT04 and N900 after the Generic PHY framework was
On 10/07/2013 12:22 PM, Archit Taneja wrote:
On Monday 07 October 2013 03:04 PM, Hans Verkuil wrote:
On 10/07/2013 11:16 AM, Archit Taneja wrote:
On Monday 07 October 2013 01:25 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few comments below...
On 09/06/2013 12:12 PM, Archit Taneja wrote:
On Monday 07 October 2013 07:32 PM, Hans Verkuil wrote:
On 10/07/2013 12:22 PM, Archit Taneja wrote:
On Monday 07 October 2013 03:04 PM, Hans Verkuil wrote:
On 10/07/2013 11:16 AM, Archit Taneja wrote:
On Monday 07 October 2013 01:25 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few
Add device nodes for the HS USB Host port 1, USB PHY and its
required regulator and also pin mux setup for HS USB1 pins.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Enric Balletbo i Serra eballe...@gmail.com
Acked-by: Roger Quadros rog...@ti.com
---
Changes
Hi Benoit,
This series are some enhancements and cleanups for IGEP boards
that it would be great if can make it for v3.13.
This is a third version of the patch-set that addresses some issues
raised by Roger Quadros and is composed of the following patches:
[PATCH v3 1/3] ARM: dts: omap3-igep:
Commit 840ef8b7 (ARM: dt: add header to define IRQ flags) added
constants for IRQ edge/level triggered types so use it instead of
a magic number to enhance the DT readability.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v2:
- None
Changes since v1:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to O
added USB OTG support for most OMAP boards but some OMAP3 boards
such as IGEP boards were not updated. This patch adds an USB OTG
device node to these board.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
* Tero Kristo t-kri...@ti.com [131006 23:43]:
On 10/07/2013 05:15 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131004 08:42]:
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing stuff?
Well omap4 seems to work for me just fine, and
On Mon, Oct 7, 2013 at 2:09 PM, Benoit Cousson bcous...@baylibre.com wrote:
On 07/10/2013 14:02, Javier Martinez Canillas wrote:
On 10/07/2013 01:58 PM, Benoit Cousson wrote:
Hi Javier,
On 07/10/2013 13:54, Javier Martinez Canillas wrote:
On 10/07/2013 12:43 PM, Roger Quadros wrote:
On 10/07/2013 10:41 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131006 23:43]:
On 10/07/2013 05:15 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131004 08:42]:
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing stuff?
Well
Add mmc1 dt node to dra7-evm board.
Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21)
on i2c1 bus. When dt support for gpio-pcf857x is available, input supply
will be modelled as cascaded regulator.
Signed-off-by: Balaji T K balaj...@ti.com
---
Rebase to for_3.13/dts
Add mmc2 dt node to dra7-evm board
and model eMMC vcc as fixed regulator.
Signed-off-by: Balaji T K balaj...@ti.com
---
Rebase to for_3.13/dts
and removed ti,non-removable
arch/arm/boot/dts/dra7-evm.dts | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git
On 10/06/2013 05:41 PM, Russell King - ARM Linux wrote:
On Sun, Oct 06, 2013 at 05:30:47PM -0500, Joel Fernandes wrote:
On receiving IRQ exception in SVC mode, all the SVC mode registers are saved
onto the stack very early on.
The stack frame allocation code for IRQ entry during SVC mode
beagle-xm currently would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. So add
compatiblity for 3630 to allow match
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/omap3-beagle-xm.dts |2 +-
1 file changed, 1 insertion(+), 1
This is a respin of [1] based on of Olof's comments to introduce a
generic SoC binding. This standardizes the binding definitions for
SoCs based on existing implied bindings and based on existing usage
in arch/arm/mach-omap2/soc.h. Eventually we should be able to get rid
of soc_is_xyz() functions
SoC family definitions at the moment are reactive to board needs
as a result, beagle-xm would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. Obviously, this is
the wrong behavior.
Eventually, we will have descriptors match only with SoC types and
should
On 10/07/2013 06:12 PM, Javier Martinez Canillas wrote:
Commit ad871c10b (ARM: dts: OMAP: Add usb_otg and glue data to O
added USB OTG support for most OMAP boards but some OMAP3 boards
such as IGEP boards were not updated. This patch adds an USB OTG
device node to these board.
Hi Linus W,
Any comments on the pinctrl patches 3 - 5 in this series?
These are badly needed to not break omap3 PM support when
we're moving to device tree based booting.
* Tony Lindgren t...@atomide.com [131002 22:50]:
Let's replace is_pinconf with flags and add struct pcs_soc_data
so we can
* Tony Lindgren t...@atomide.com [131007 08:49]:
* Tero Kristo t-kri...@ti.com [131006 23:43]:
On 10/07/2013 05:15 AM, Tony Lindgren wrote:
* Tero Kristo t-kri...@ti.com [131004 08:42]:
Hi,
Just a gentle reminder, anybody have any comments on this series or
should we start queuing
Hi,
Few comments below.
* Nishanth Menon n...@ti.com [131007 09:57]:
SoC family definitions at the moment are reactive to board needs
as a result, beagle-xm would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. Obviously, this is
the wrong behavior.
* Nishanth Menon n...@ti.com [131007 09:57]:
beagle-xm currently would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. So add
compatiblity for 3630 to allow match
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/boot/dts/omap3-beagle-xm.dts |
SoC family definitions at the moment are reactive to board needs
as a result, beagle-xm would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. Obviously, this is
the wrong behavior.
With clock node dts conversion, we get the following warnings as a
result
On 10/07/2013 03:30 PM, Nishanth Menon wrote:
[...]
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts
b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 0c514dc..02dd4a9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -11,7 +11,7 @@
/ {
SoC family definitions at the moment are reactive to board needs
as a result, beagle-xm would matchup with ti,omap3 which invokes
omap3430_init_early instead of omap3630_init_early. Obviously, this is
the wrong behavior.
With clock node dts conversion, we get the following warnings as a
result
On 10/03/2013 11:59 AM, Suman Anna wrote:
The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc configuration.
The module address space is being
Hello,
On Thu, Sep 26, 2013 at 08:18:28PM +0100, Jyri Sarha wrote:
This patch adds DMA register location to mcasp DT bindings. On am33xx
SoCs the McASP registers are mapped trough L4 interconnect, which is
not accessible by the DMA controller, so McASP data port is mapped
trough L3 to a
On Thu, Sep 26, 2013 at 08:18:29PM +0100, Jyri Sarha wrote:
Extract DMA channels directly from DT as they can not be found from
platform resources anymore. This is a work-around until davinci audio
driver is updated to use dmaengine.
How long will this conversion take?
Signed-off-by: Jyri
On Thu, Sep 26, 2013 at 08:18:30PM +0100, Jyri Sarha wrote:
Makes interrupts property optional as the interrupts are not currently
used by the driver and adds interrupt-names property to name listed
interrupts. Currently know interrupt names are tx and rx.
Signed-off-by: Jyri Sarha
On Thu, Sep 26, 2013 at 08:18:35PM +0100, Jyri Sarha wrote:
This patch adds an optional address range to reg property. The range
describes the register location for DMA controller on am33xx. The both
address ranges are named accordingly in the reg-names property.
Signed-off-by: Hebbar,
On Thu, Sep 26, 2013 at 08:18:36PM +0100, Jyri Sarha wrote:
From: Darren Etheridge detheri...@ti.com
Adds sound, tlv320aic3x, mcasp1, and am335x_evm_audio_pin nodes.
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Signed-off-by: Jyri
On 10/07/2013 04:19 PM, Nishanth Menon wrote:
On 10/03/2013 11:59 AM, Suman Anna wrote:
The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc
On Mon, Oct 07, 2013 at 03:43:49PM -0500, Nishanth Menon wrote:
diff --git a/arch/arm/mach-omap2/board-generic.c
b/arch/arm/mach-omap2/board-generic.c
index 39c7838..4fe5b9c 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -113,6 +113,7 @@
On Mon, Oct 07, 2013 at 10:47:18PM +0100, Mark Rutland wrote:
On Thu, Sep 26, 2013 at 08:18:28PM +0100, Jyri Sarha wrote:
- interrupts : Interrupt number for McASP
The device also seems to be able to generate multiple interrupts -- which
interrupt does this actually cover?
The driver
Quoting Paul Walmsley (2013-10-07 01:21:16)
On Tue, 10 Sep 2013, Tero Kristo wrote:
In theory, DPLLs can also be used in their bypass mode to feed customer
nodes
clocks. I just think the check in the clkoutx2_recalc is wrong, and should
be
enhanced to actually check what is the
Quoting Tero Kristo (2013-09-25 01:48:26)
+
+static const struct clk_ops apll_ck_ops = {
+ .enable = dra7_apll_enable,
+ .disable= dra7_apll_disable,
Looks like .is_enabled is missing?
Also have you thought about using .prepare or .unprepare for these PLLs
which
Quoting Tero Kristo (2013-09-25 01:48:06)
Hi all,
Version 7 contains following high level changes:
- Dropped support for basic bindings from Mike Turquette, instead using
vendor specific bindings for all clocks
- Mux clock + divider clock vendor specific bindings get rid of use
of the
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