[PATCH 1/1] Added sleep support to UART

UART usage (e.g. serial console) now denies sleep for 5 seconds. This makes it possible to use serial console when dynamic idle is enabled. Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this new implementation. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- ar

Dynamic idle support for UART

This hack will most importantly allow serial console usage when dynamic idle is enabled. Note! Functionality under 24xx configuration has not been verified! There may be some problems with CONFIG_PM_DEBUG flag enabled, most likely during the PM debug information dumps after / before

Second part for the UART hack (dependency)

This patch depends on the PM patch set sent by Jouni Hogander. Basically just a cosmetic modification to make fclk mask look more nice inside pm34xx.c. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at h

[PATCH 1/1] Added sleep support to UART

UART usage (e.g. serial console) now denies sleep for 5 seconds. This makes it possible to use serial console when dynamic idle is enabled. Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this new implementation. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- ar

[PATCH 1/1] omap3_fclks_active() now uses generic serial clock check

Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm34xx.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index ada87ba..2574586 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/ar

[PATCH] Added sleep support to UART

UART usage (e.g. serial console) now denies sleep for 5 seconds. This makes it possible to use serial console when dynamic idle is enabled. Also moved code from pm-debug.c to serial.c, and made pm24xx.c use this new implementation. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- ar

[PATCH 1/1] PM debug support for 34xx

) - PM register dumps with programmable save points This patch depends on the PM workaround set from Jouni Hogander. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clockdomain.c | 38 arch/arm/mach-omap2/pm-debug.c

34xx off-mode support fixes

Hi, This patch set contains some experimental fixes for the cpu-idle support from Rajendra Nayak. With this patch set, all power domains enter OFF mode and recover from it, at least while using suspend and/or dynamic idle. If you are using these patches, you should disable CPU_IDLE support from ke

[PATCH 1/3] OMAP34xx suspend + dynamic idle fixed for chip off-mode

With this patch OMAP34xx enters and resumes from off-mode successfully with suspend and dynamic idle. CPU idle is broken with this patch and should be fixed separately. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/cpuidle34xx.c | 15 ++--- arch/arm/mach

[PATCH 3/3] CPU-idle trial fix + PM debug expansion

CPU-idle has a possibility of working now, also added full PRCM register dump into pm-debug. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/cpuidle34xx.c | 30 - arch/arm/mach-omap2/pm-debug.c| 17 ++ arch/arm/mach

[PATCH 2/3] PM debug support for 34xx

) - PM register dumps with programmable save points This patch depends on the PM workaround set from Jouni Hogander. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clockdomain.c | 38 arch/arm/mach-omap2/pm-debug.c

[PATCH] OMAP3: Fixed crash bug with serial + suspend

It was possible for an unhandled interrupt to occur if there was incoming serial traffic during wakeup from suspend. This was caused by the code in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time, but not acking its interrupts. Applies on top of PM branch. Signed-off-by: Tero

[PATCH] OMAP3: Fixed crash bug with serial + suspend

It was possible for an unhandled interrupt to occur if there was incoming serial traffic during wakeup from suspend. This was caused by the code in arch-arm/mach-omap2/serial.c keeping interrupt enabled all the time, but not acking its interrupts. Applies on top of PM branch. Signed-off-by: Tero

[PATCH 0/2] OMAP3: GPIO off-mode fixes

Hi, These two patches add fixes to GPIO off-mode handling. First patch is more important as it fixes a HW bug, second one just optimizes off-mode code a bit by removing a couple of unnecessary registers from the context save. --Tero -- To unsubscribe from this list: send the line "unsubscribe l

[PATCH 1/2] OMAP3: PM: Fixed glitches in GPIO outputs during off-mode transitions

. Also, GPIO signals themselves must be set to INPUT mode before switching pad configuration to safe mode, otherwise this will generate a glitch also. See OMAP3 errata section 1.158 for more details. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm34xx.c |7 +- arch/arm/plat-omap

[PATCH 2/2] OMAP3: GPIO: Removed a couple of unneeded registers from context save/restore

setwkuena and setdataout are covered already by wake_en and dataout fields. Signed-off-by: Tero Kristo --- arch/arm/plat-omap/gpio.c | 10 -- 1 files changed, 0 insertions(+), 10 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 5d44dcf..10107e9

[PATCH 1/2] OMAP3: PM: Fixed glitches in GPIO outputs during off-mode transitions

. Also, GPIO signals themselves must be set to INPUT mode before switching pad configuration to safe mode, otherwise this will generate a glitch also. See OMAP3 errata section 1.158 for more details. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm34xx.c |7 +- arch/arm/plat-omap

Bug fix: reschedule check for omap3 PM

From: Tero Kristo Hi, This patch fixes a problem where an interrupt may cause scheduling inside idle loop, but which does not get served due to the decision that has already been done for the system to enter idle. This can cause nasty latencies in some cases. This would not need to be done if

[PATCH] OMAP3: PM: Added resched check into idle calls

From: Tero Kristo Fixes a bug where scheduling is delayed until next wakeup due to race condition (e.g. interrupt requests scheduling just before omap_sram_idle is entered.) Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/cpuidle34xx.c |2 +- arch/arm/mach-omap2/pm34xx.c |2

[PATCH] OMAP3: PM: Added resource refresh to OPP unlock requests

From: Tero Kristo This will set the correct OPP after a lock has been released from sysfs. Applies on PM branch. Signed-off-by: Tero Kristo Signed-off-by: Jouni Hogander --- arch/arm/mach-omap2/pm.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach

[PATCH] OMAP3: PM: Force USB to standby if not used

From: Tero Kristo This patch will allow device to enter sleep mode while a USB cable is connected and USB is either disabled or built as a module from kernel config. Applies on top of PM branch. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/usb-musb.c | 10 -- 1 files changed

[PATCH] OMAP: PM: Fixed omap_pm_set_min_bus_tput

From: Tero Kristo Parameter check for this function was bugged. Applies on top of PM branch. Signed-off-by: Tero Kristo Signed-off-by: Jouni Hogander --- arch/arm/plat-omap/omap-pm-noop.c |4 ++-- arch/arm/plat-omap/omap-pm-srf.c |4 ++-- 2 files changed, 4 insertions(+), 4

[PATCH] OMAP3: Re-program also chipselect 1 when changing SDRAM timing

From: Tero Kristo Previously only chipselect 0 was controlled, which would result in the chipselect 1 running on too low rate during low core OPPs. Applies on top of PM branch. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/sram34xx.S | 29 +++-- 1 files changed

[PATCH 02/04] PM debug: do not print out status for meta powerdomains (dpll*)

Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm-debug.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index c903c55..d21af83 100644 --- a/arch/arm/mach-omap2/pm-debug.c

[PATCH 00/04] PM OMAP3: Misc patches

Some misc PM related patches here. #1 and #3 are more important than others, #4 introduces the PRCM register dump capability to PM debug, #2 is a sort of cosmetic change. --Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED]

[PATCH 01/04] Fix cpuidle off-modes to be controlled via sysfs

Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/cpuidle34xx.c | 21 ++--- arch/arm/mach-omap2/pm.c |4 ++-- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle

[PATCH 03/04] PM counters: fix initialization race condition

Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clockdomain.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index b0b5885..b27afc0 100644 --- a/arch/arm/mach

[PATCH 04/04] PM debug: Add PRCM register dump support

ters/n Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm-debug.c | 208 arch/arm/mach-omap2/pm.h |4 + 2 files changed, 212 insertions(+), 0 deletions(-) mode change 100644 => 100755 arch/arm/mach-omap2/pm-debug

[PATCH] PM: OMAP3: Make sure clk_disable_unused() order is correct

: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index dbbc7c8..522ce6f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/c

[PATCH] PM: Changed secure RAM storage size from 0x8000 to 0x803F

Without this, causes some random crashes related to memory management. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm34xx.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c

[PATCH] PM: Fix a bug with noncore dpll rate calculation

Noncore dpll can enter autoidle state, in which case the rate calculation fails. Fixed by checking dpll mode instead of idle status. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock.c | 16 +++- arch/arm/mach-omap2/cm-regbits-34xx.h

[PATCH] PM: Added three PLL registers to the PRCM context save

These registers are now also saved: CM_CLKSEL4 CM_CLKEN CM_CLKEN2 Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/prcm.c | 14 ++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/prcm.c b/ar

[PATCH] OMAP3: Fixes for suspend / resume GPIO wake-up handling

Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/plat-omap/gpio.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index f4ec3af..62349fd 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/pla

[PATCH] PM: Added suspend target state control to debugfs for OMAP3

Target state can be read / programmed via files under: [debugfs]/pm_debug/[pwrdm]/suspend Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm-debug.c | 30 -- arch/arm/mach-omap2/pm.h |4 arch/arm/mach-omap2/pm34xx.c

[PATCH] OMAP3: GPIO fixes for off-mode

Off mode is now using the omap2 retention fix code for scanning GPIOs only during off-mode transitions. All the *non_wakeup_gpios variables are now used for off-mode transition tracking on OMAP3. This patch fixes cases where GPIO state changes are missed during off-mode. Signed-off-by: Tero

[PATCH] OMAP3: PM: Prevent PER from going OFF when CORE is going INA

OMAP3 can't generate wakeups in this state, thus it is not permitted. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm34xx.c | 15 --- 1 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm

Resending: OMAP3 GPIO fixes for off-mode

Resending this patch as the previous version breaks after the PER vs. CORE dependency patch. Any comments to this by the way? -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.or

[PATCH] OMAP3: GPIO fixes for off-mode

Off mode is now using the omap2 retention fix code for scanning GPIOs only during off-mode transitions. All the *non_wakeup_gpios variables are now used for off-mode transition tracking on OMAP3. This patch fixes cases where GPIO state changes are missed during off-mode. Signed-off-by: Tero

[PATCH] OMAP3: PM: MPU and CORE should stay awake if there is CAM domain ACTIVE

MPU and CORE should stay awake if there is CAM domain ACTIVE. This is because that module doesn't have wake-up capability. This should replace the patch that is currently in the PM branch. Signed-off-by: Jouni Hogander <[EMAIL PROTECTED]> Signed-off-by: Tero Kristo <[EMAIL PROTECT

[PATCH 02/23] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory

memory. Tero Kristo <[EMAIL PROTECTED]> caught a bug in an earlier version of this patch - thanks Tero. ... 1. ARMv7 ARM (DDI 0406A) pp. A3-30, A3-31, B3-32. 2. Private communication with Richard Woodruff <[EMAIL PROTECTED]> Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> Cc: Tero

[PATCH 03/23] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll

From: Paul Walmsley <[EMAIL PROTECTED]> Add more barriers in the SRAM CORE DPLL M2 divider change code. - Add a DSB SY after the function's entry point to flush all cached and buffered writes and wait for the interconnect to claim that they have completed[1]. The idea here is to force all de

[PATCH 01/23] ARM: MMU: add a Non-cacheable Normal executable memory type

From: Paul Walmsley <[EMAIL PROTECTED]> Add a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. This is needed for the OMAP3 SDRAM clock change code, which must run from SRAM. The SRAM must be marked as non-cacheable memory to avoid dirty cache line writebacks to SDRAM while

[PATCH 09/23] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz

From: Paul Walmsley <[EMAIL PROTECTED]> According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC sp

[PATCH 13/23] OMAP3 clock: add a short delay when lowering CORE clk rate

From: Paul Walmsley <[EMAIL PROTECTED]> When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time del

[PATCH 15/23] OMAP3 SRAM: add more comments on the SRAM code

From: Paul Walmsley <[EMAIL PROTECTED]> Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sram34xx.S | 45 +-- 1 files changed, 24 insertions(+), 21 deletions(-

[PATCH 14/23] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

From: Paul Walmsley <[EMAIL PROTECTED]> Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley <

[PATCH 11/23] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

From: Paul Walmsley <[EMAIL PROTECTED]> The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sram34xx.S |3 --- 1 file

[PATCH 08/23] OMAP3 SRAM: renumber registers to make space for argument passing

From: Paul Walmsley <[EMAIL PROTECTED]> Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sram34xx.S | 114 1 files chang

[PATCH 16/23] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers

From: Paul Walmsley <[EMAIL PROTECTED]> Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sram34xx.S | 53 --- 1 files changed, 38 insertions(+), 15 dele

[PATCH 17/23] OMAP3: PM: Fixed VDD2 control to work from both sysfs and SRF API

SRF API for setting throughput requirement attempted to use throughput values as parameter to set_opp() and sysfs was attempting to use OPP levels (1..3.) Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm.c |5 +- arch/arm/mach-omap

[PATCH 18/23] OMAP3: PM: Added DVFS OPP locking interface for VDD1 and VDD2

Added two new files under /sys/power for controlling OPP locks. vdd1_lock and vdd2_lock. You can write to these to select desired OPP level and it will be locked at that level. Lock can be cleared by writing 0 to the same file. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/ar

OMAP3: DVFS core patch set

This patch set provides DVFS support for OMAP3. First 16 patches contain clock framework modifications from Paul Walmsley, which are needed for VDD2 OPP clock control to work properly. Rest of the patches are misc fixes for DVFS control, providing locking interface for OPPs and providing support fo

[PATCH 20/23] OMAP3: Add support for DPLL3 divisor values higher than 2

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock34xx.c|9 +++-- arch/arm/mach-omap2/sram34xx.S |7 --- arch/arm/plat-omap/include/mach/sram.h

[PATCH 19/23] OMAP3: Fix rate calculation bug in omap3_select_table_rate

L3 divisor is not taken into account when trying to set DPLL3 clock. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock34xx.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock

[PATCH 04/23] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change

From: Paul Walmsley <[EMAIL PROTECTED]> Where necessary, add interconnect barriers to force posted writes to complete before continuing. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sram34xx.S |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --

[PATCH 21/23] OMAP3: PM: Prevented DVFS state switches when enabling off-mode

resource_refresh() call tried to refresh DVFS OPP levels also. This should eventually be fixed in a way that DVFS VDD2 level is actually governed by something. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm34xx.c |4 1 files changed, 4 insertions

[PATCH 05/23] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change

From: Paul Walmsley <[EMAIL PROTECTED]> Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh mode. This prevents the SDRC from attempting to power off the SDRAM, which can cause the system to hang. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sr

[PATCH 23/23] OMAP3: PM: Fix linker error without CONFIG_PM option

omap3_save_scratchpad_contents() is not available without CONFIG_PM. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock34xx.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock

[PATCH 22/23] OMAP3: PM: Enable VDD2 OPP1

VDD2 OPP1 works at least with minimal kernel setup, there are some corner cases where it fails though, like when you use USB. Board setup should make sure and enable only working OPPs. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/pm.c |2 +- 1 files chan

[PATCH 10/23] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code

From: Paul Walmsley <[EMAIL PROTECTED]> The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> ---

[PATCH 06/23] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard

From: Paul Walmsley <[EMAIL PROTECTED]> The BeagleBoard u-boot uses DPLL3 settings that result in 8300 / 16600 Hz clock rates for the SDRC, rather than the derated DPLL3 settings used by earlier bootloaders. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sdram-m

[PATCH 07/23] OMAP3 SDRC: initialize SDRC_POWER at boot

From: Paul Walmsley <[EMAIL PROTECTED]> Initialize SDRC_POWER to a known-good setting when the kernel boots. Necessary since some bootloaders don't initialize SDRC_POWER properly. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/sdrc.c | 19 ++- 1 files

[PATCH 12/23] OMAP3 clock: initialize SDRC timings at kernel start

From: Paul Walmsley <[EMAIL PROTECTED]> On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <[EMAIL PROTECTED]> --- arch/arm/m

[PATCH] OMAP3: Add support for DPLL3 divisor values higher than 2

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock34xx.c|9 +++-- arch/arm/mach-omap2/sram34xx.S |8 +--- arch/arm/plat-omap/include/mach/sram.h

[PATCH] PM OMAP3: Change omap3_save_secure_ram to be called only during init

. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm34xx.c | 19 ++- 1 files changed, 18 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 4223622..b8cf5f2 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach

[PATCH] OMAP3: GPIO fixes for off-mode

Off mode is now using the omap2 retention fix code for scanning GPIOs during off-mode transitions. All the *non_wakeup_gpios variables are now used for off-mode transition tracking on OMAP3. This patch fixes cases where GPIO state changes are missed during off-mode. Signed-off-by: Tero Kristo

[PATCH] PM: OMAP3: Refreshed DVFS VDD1 control against latest clock fw

New clock framework patches from Paul Walmsley broke the DVFS for OMAP3. This patch fixes the VDD1 part of it. Applies on top of latest PM branch (pm-next) in Kevin's tree. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c | 11 +-- arch/arm/mach-omap2/clock34xx.h |

[PATCH 05/17] OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change

From: Paul Walmsley Clear the SDRC_POWER.PWRENA bit before putting the SDRAM into self-refresh mode. This prevents the SDRC from attempting to power off the SDRAM, which can cause the system to hang. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S |7 --- 1 files chang

[PATCH 06/17] OMAP3 SDRC: Add 166MHz, 83MHz SDRC settings for the BeagleBoard

From: Paul Walmsley The BeagleBoard u-boot uses DPLL3 settings that result in 8300 / 16600 Hz clock rates for the SDRC, rather than the derated DPLL3 settings used by earlier bootloaders. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 22

[PATCH 01/17] ARM: MMU: add a Non-cacheable Normal executable memory type

From: Paul Walmsley Add a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. This is needed for the OMAP3 SDRAM clock change code, which must run from SRAM. The SRAM must be marked as non-cacheable memory to avoid dirty cache line writebacks to SDRAM while the SDRAM controlle

[PATCH 04/17] OMAP3 clock: add interconnect barriers to CORE DPLL M2 change

From: Paul Walmsley Where necessary, add interconnect barriers to force posted writes to complete before continuing. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S |9 ++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b

[PATCH 08/17] OMAP3 SRAM: renumber registers to make space for argument passing

From: Paul Walmsley Renumber registers in omap3_sram_configure_core_dpll() assembly code to make space for additional parameters. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 114 1 files changed, 57 insertions(+), 57 deletions(-)

[PATCH 02/17] OMAP3 SRAM: mark OCM RAM as Non-cacheable Normal memory

M2 divider reprogramming code, which must execute while the SDRC is idled. If the ARM attempts to write cache lines back to the while the SRAM code is running, the ARM will stall[2]. TI deals with this problem in the CDP kernel by marking the SRAM as Strongly-ordered memory. Tero Kristo caught a

[PATCH 14/17] OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change

From: Paul Walmsley Program the SDRC_MR_0 register as well during SDRC clock changes. This register allows selection of the memory CAS latency. Some SDRAM chips, such as the Qimonda HYB18M512160AF6, have a lower CAS latency at lower clock rates. Signed-off-by: Paul Walmsley --- arch/arm/mach-

[PATCH 07/17] OMAP3 SDRC: initialize SDRC_POWER at boot

From: Paul Walmsley Initialize SDRC_POWER to a known-good setting when the kernel boots. Necessary since some bootloaders don't initialize SDRC_POWER properly. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sdrc.c | 19 ++- 1 files changed, 18 insertions(+), 1 deletions

[PATCH 09/17] OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz

From: Paul Walmsley According to the 34xx TRM Rev. K section 11.2.4.4.11.1 "Purpose of the DLL/CDL Module," the SDRC delay-locked-loop can be locked at any SDRC clock frequency from 83MHz to 166MHz. CDP code unconditionally unlocked the DLL whenever shifting to a lower SDRC speed, but this seems

[PATCH 03/17] OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll

From: Paul Walmsley Add more barriers in the SRAM CORE DPLL M2 divider change code. - Add a DSB SY after the function's entry point to flush all cached and buffered writes and wait for the interconnect to claim that they have completed[1]. The idea here is to force all delayed write traff

[PATCH 13/17] OMAP3 clock: add a short delay when lowering CORE clk rate

From: Paul Walmsley When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on

[PATCH 17/17] OMAP3: Add support for DPLL3 divisor values higher than 2

Previously only 1 and 2 was supported. This is needed for DVFS VDD2 control. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c|9 +++-- arch/arm/mach-omap2/sram34xx.S |8 +--- arch/arm/plat-omap/include/mach/sram.h |6 -- arch/arm/plat-omap

[PATCH 11/17] OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize

From: Paul Walmsley The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S |3 --- 1 files changed, 0 insertions(+), 3 deletion

[PATCH 12/17] OMAP3 clock: initialize SDRC timings at kernel start

From: Paul Walmsley On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock34xx.c |3 --- arch

[PATCH 16/17] OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers

From: Paul Walmsley Convert omap3_sram_configure_core_dpll() to use macros rather than magic numbers. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 53 --- 1 files changed, 38 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-o

[PATCH 15/17] OMAP3 SRAM: add more comments on the SRAM code

From: Paul Walmsley Clean up comments and copyrights on the CORE DPLL3 M2 divider change code. Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/sram34xx.S | 45 +-- 1 files changed, 24 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-omap2/sr

[PATCH 00/17] OMAP3: Base support for VDD2 DVFS

Resending this set against the latest PM branch. This set provides base SDRC + SRAM + clock framework support for VDD2 DVFS control. Main reasoning for this set is that when VDD2 clock is changed, memory clocking changes also and you need to be rather careful when you are doing this. -- To unsubs

[PATCH 10/17] OMAP3 clock: use pr_debug() rather than pr_info() in some clock change code

From: Paul Walmsley The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 1

[PATCH 1/8] OMAP3: PM: Fixed VDD2 control to work from both sysfs and SRF API

SRF API for setting throughput requirement attempted to use throughput values as parameter to set_opp() and sysfs was attempting to use OPP levels (1..3.) Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm.c |8 +-- arch/arm/mach-omap2/pm.h |1

[PATCH 0/8] OMAP3: Misc VDD2 DVFS fixes

Applies on top of PM branch + base VDD2 DVFS support patches. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

[PATCH 2/8] OMAP3: PM: Added DVFS OPP locking interface for VDD1 and VDD2

Added two new files under /sys/power for controlling OPP locks. vdd1_lock and vdd2_lock. You can write to these to select desired OPP level and it will be locked at that level. Lock can be cleared by writing 0 to the same file. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm.c

[PATCH 6/8] OMAP3: PM: Fix linker error without CONFIG_PM option

omap3_save_scratchpad_contents() is not available without CONFIG_PM. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 8b375a9..6c5254c

[PATCH 5/8] OMAP3: PM: Enable VDD2 OPP1

VDD2 OPP1 works at least with minimal kernel setup, there are some corner cases where it fails though, like when you use USB. Board setup should make sure and enable only working OPPs. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm.c |2 +- 1 files changed, 1 insertions(+), 1

[PATCH 8/8] PM: OMAP3: Added support for possibly failing clk_set_rate to DVFS

clk_set_rate() can fail in a case where a driver denies frequency change, this can happen after Paul's clk notifier code has been applied. This patch makes DVFS VDD2 control handle this situation correctly. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c|5 - arc

[PATCH 3/8] OMAP3: Fix rate calculation bug in omap3_select_table_rate

L3 divisor is not taken into account when trying to set DPLL3 clock. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock34xx.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index b565ee6

[PATCH 7/8] PM: OMAP3: Removed a couple of unused variables from DVFS code

- freqs_notify is only used by CPU_FREQ => added compiler flags - req_l3_freq was a copy paste bug and was never used by this function => rm Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/resource34xx.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/ar

[PATCH 4/8] OMAP3: PM: Prevented DVFS state switches when enabling off-mode

resource_refresh() call tried to refresh DVFS OPP levels also. This should eventually be fixed in a way that DVFS VDD2 level is actually governed by something. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm34xx.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a

[PATCH] PM debug: Fix problems with PM timers

Camera sleep deny fix introduced a problem that broke MPU state timers, this is now fixed. Also removed DPLL* powerdomain timers from the status dumps. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pm-debug.c |3 ++- arch/arm/mach-omap2/pm34xx.c |3 +-- 2 files changed, 3

[PATCH 0/4] Misc PM patches for 34xx

Hi, Here are a few PM patches for omap34xx. First two are important to get dynamic idle and suspend to work in generic cases where we have enabled some gpio:s and/or UART:s. These patches add dynamic clock handling for these. Dynamic clock handling is enabled via sysfs entries under /sys/power/.

[PATCH 1/4] PM: Dynamic GPIO clock handling

From: ext Jouni Hogander <[EMAIL PROTECTED]> In omap3 gpios 2-6 are in per domain. Functional clocks for these should be disabled. GPIO modules in PER domain are not able to act as a wake up source if PER domain is in retention. PER domain sleep transition before MPU is prevented by leaving icks

[PATCH 2/4] Added sleep support to UART

om pm-debug.c to serial.c, and made pm24xx.c use this new implementation. Sleep deny timer can be configured by writing desired value (in ms) to /sys/devices/platform/serial8250.0/serial_awake_time (default 5000, i.e. 5 seconds.) Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/ma

[PATCH 3/4] PM debug support for 34xx

) - PM register dumps with programmable save points - Current power domain states - Interface to set_pwrdm_state() This patch depends on the PM workaround set from Jouni Hogander. Signed-off-by: Tero Kristo <[EMAIL PROTECTED]> --- arch/arm/mach-omap2/clock.c |2 + ar

[PATCH 4/4] Sysfs interface for controlling suspend states + set_pwrdm_state fix

Target states for each powerdomain can now be set via sysfs interface. E.g. "echo 0 > /sys/power/suspend/mpu_pwrdm" will program MPU suspend state to be OFF. Also, set_pwrdm_state() should now work when pwrdm is currently in power save state. Signed-off-by: Tero Kristo <

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